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Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 6
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
Which of the following statement(s) is/are true for timing-driven placement?
a. Minimizes the signal delays for the interconnection wires.
b. Minimizes the signal delays for placing the cells on the layout area.
c. Modifies gates and/or inserts buffers in interconnection wires.
d. None of these.
Correct Answer: b

Detailed Solution: In timing driven placement, the cells or blocks are placed in suitable
locations on the layout surface, such that the overall signal delays are minimized. It does
not aim to minimize the interconnection delays specifically, and also it is not related
modifying gates or inserting buffers. The correct option is (b).
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QUESTION 2:
As the clock frequency increases, which of the following delays shall be most dominant?
a. Clock delay.
b. Gate delay.
c. Jitter delay.
d. Interconnection delay.
Correct Answer: d

Detailed Solution: As the chip size reduces with advancements in fabrication technology,
the clock frequency increases. At the same time, delays of the interconnection lines start to
dominate as compared to the delays of the circuit blocks or clock. The correct option is (d).
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QUESTION 3:
The maximum clock frequency with which a circuit can operate depends on:
a. Gate delays.
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b. Clock skew.
c. Interconnect delays.
d. Number of transistors in the chip.
e. All of these.
Correct Answer: a, b, c

Detailed Solution: The maximum clock frequency with which a circuit can operate
correctly depends on a variety of factors. It depends on the clock skew, the interconnection
delays, and also the delays of the combinational blocks. However, it does not depend on the
number of transistors. Hence, the correct options are (a), (b) and (c).
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QUESTION 4:
Which of the following are instances of controlling values?

a. Logic 0 at the input of a NAND gate.

b. Logic 1 at the input of an AND gate.
c. Logic 0 at the input of an OR gate.
d. Logic 1 at the input of a XOR gate.

Correct Answer: a

Detailed Solution: The controlling values depend on the type of the gate. For AND and
NAND gates, the controlling value is 0. For OR and NOR gates, the controlling value is 1.
However, for XOR and XNOR gates, neither 0 nor 1 is a controlling value. Hence, the correct
option is (a).
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QUESTION 5:
The Boolean difference of a Boolean function X with respect to another function Y defines
the conditions where:
a. The logic values of X and Y are always different.
b. The logic values of X and Y are always same.
c. Any change in the logic value of X will also cause the logic value of Y to
change.
d. Any change in the logic value of Y will also cause the logic value of X to
change.
e. None of these.

Correct Answer: d
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Detailed Solution: The Boolean difference dX/dY specifies the condition where a change
in the logic value of Y will change the logic value of X. The correct option is (d).
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QUESTION 6:
When we want to sensitize a path from a primary input to one of the primary outputs, we
have to:
a. Apply controlling values to the side inputs of all gates in the path.
b. Apply controlling values to all the inputs of the gates in the path.
c. Ensure that there is no skew or jitter in the path.
d. None of these.

Correct Answer: d

Detailed Solution: One of the necessary conditions for sensitizing a path from a primary
input to a primary output is that non-controlling values must be applied to the side inputs
of all the gates that lie along the path. Hence, the correct option is (d).
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QUESTION 7:
A false path in a combinational circuit is defined as a path in which:
a. The final output line for the path evaluates to 0 for all input combinations.
b. The path is never sensitized corresponding to any input combination.
c. The delay of the path is the longest.
d. A signal transition in the input can cause a data hazard in the output.
e. None of these.

Correct Answer: b

Detailed Solution: In a combinational circuit, a false path is defined as a path from one of
the inputs to one of the outputs such that for none of the possible input combinations, the
path is sensitized. The correct option is (b).
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QUESTION 8:
If the RAT and AAT values for line x are RAT(x) = 20 and AAT(x) = 27, which of the
following is/are true?
a. The Slack value on line x is -7.
b. The Slack value on line x is +7.
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c. The timing constraint has been met.

d. There is violation of timing constraint.
Correct Answer: a, d

Detailed Solution: The Slack value on line x is given by 20 – 27 = -7. A positive value of
Slack indicates that the timing constraint has been met, while a negative value indicates
violation. The correct options are (a) and (d).
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QUESTION 9:
If the RAT and AAT values for line x are RAT(x) = 46 and AAT(x) = 25, which of the
following is/are true?
a. The Slack value on line x is +21.
b. The Slack value on line x is -21.
c. The timing constraint has been met.
d. None of these.
Correct Answer: a, c

Detailed Solution: The Slack value on line x is given by 46 – 25 = +21. A positive value of
Slack indicates that the timing constraint has been met. The correct options are (a) and (c).
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QUESTION 10:
Which of the following is/are false for the zero slack algorithm?
a. The slack values of some of the paths are evenly distributed across all the
nodes in the path by increasing their time budget values.
b. It starts by assuming that the slack on all the lines is zero.
c. Only the AAT values and the slacks are updated in the iterative steps.
d. The total delay in the circuit is reduced at the cost of increase in area.

Correct Answer: b, c, d

Detailed Solution: In the zero slack algorithm, the slack values of every path are evenly
distributed across all the nodes along the path by increasing their time budget values. Only
option (a) is true. Hence, the correct options are (b), (c) and (d).
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