....ed. bated indexed alld reilbvc MKd 1nouta '°°""'"I....,_ .

,
o r - . . . -- M,-,nl ....u... ,.,... DI.
([] 25 of 706 f t . . otftd
,.,.orunM, ...... n,_..,,..__,.,.,.,....t,._...tw

1.1., ,i.,Roei-
n, IOUJ#c, ,.,,"-~ - - - 1hr ,..-ore..., ...._ ... ALU. It MIO--- _..,
Wlt•"°9CfOIC .CPU ......... Dnuoflbt•1 tw1_,.. _ _........_iai lMc..,..,,

I .l ARCHITK TUU
I 16--WI
1k a«lmlc:CIIR o(IOM ,..:wides 1 ---'er of Mnf'Ovteht:I OVff IOH 1,cW1ec1wt. 11 MppOIU
AW. 1 Mi of 16--liok flfplrn ..d PIO"idt• wp,eaced ae-,. ...,__, cap!Mtlity, a rid1 ...,._.
9C1.,owe:ml inl,ffllPI~ . ktd111.t..., _bN..., - ~ ~iqaedu.e c--ctc. n.
- - . i Mock a,,_,..._ . Fi1,1.2.4Hc:ra.1 .,...,....,. ....... ordi,.,_ _. _... ..
....
T\t COM,... .-cluilK1wl o( 1016 cu~ divided .-0 two ..... (1) 8• l11tl'fllc1 UM (BlU)-, (')
EMMi,oa Ullil (EU). D. ._, ~ Wfit co,,"1/111111H ~w.llfo, "'1tWI 1dllrm cwhM._, • • •
,,,..._,., uu.... .,_..,. ,• .,.,. "1). T1w ... law6icc - ..... die ,y....·,..._..._. - ......
NlaWtb1a ltffllll_.... .,. . . . . .._a.~w... _.__..iap oMiWtb.
aaicaticww~ cnrra.,d,vkf l ad ,mphrralll iMW.,-- ,, wla . . "-•At • ..., ........ 86
..._.,, tcpnc.-d - - , . . n. «-pktc phylkal ~ wWdi ii 20-W.. IOftl d &tetnl4td ---••·
--udotTictN ptirn.cld ,....._....._,
F« ~ . , . . , . _.. ....,_ . _ ecMSllb:of!M ..-tworegillrn. . . c:onkalofa . , , . . . qilw
almc.a.d• w,-......_if _...ltlll:Wl •wiacb..._ ._,_,._..,. ..,~of•ol& d:q_,.
..Oa.lltd•ot& ct....._iisNd ld.tDprodluc c:120-Wl,a. )'Sical_...u. F«cua,k,lr6 ew,-...._
..... ii IOOJill Md . . olhrt ii SSSSH, dlca c:hc ..,_,kal addrua i, ~ .. bdow:

s,__....._ -+HI01H
Oflwt.,.__ --+JJJiSH
Sc,-....,_ -+ 100,11-+ OOOIIOOtlOOO0I0I
~ftcd lly <f .,_ ,.,.._ --1> 0001 0000 0000 0101 0000

---
oo.. - . -+ 010101010101 1101
-+ 0001 0ltl 0101 10100101
I J J A J

_ _ __,___ u - r~=---- ~

-
_..,_
1.2.2 Plqll.......
8086 bu• 1<>-bit llaa reaislcrwhicb is divided iDeo two pe,11. viz.(•) cotwlidot, co«or111111ujl,,g1 and (b)
-«AiMC01ttroljl,,g1. n.. ...........,..,..._islhe lowttbyteoflhe l(>.bitllaareaiswralODawith
1he ovaflowJl,,g. nil llag is iclclllical IO 1he IOIS llaa regilttr, with an additional over9ow llaa. which is -
, . . _ in IOIS. This port oflhe llaa reaiswr of 8086 reflem 1he resulu oflhe opencions perbmed by ALU.
The COtttro/jl,,g ,.,lllff' is 1he hiahttbyte oflhe llaa regileerofl086. I t - • thRc a..., viz. dir«tioll
flog (D). l1t1an,p1jl,,g (I) and tropjl,,g (T).
The complete bit configintion of 8016 fla1 reai- i1 shown in Fig. 1.•.

15 14 13 12 11 10 9 I 7 8 5 4 0

Jxjxjxjxjo lol ii Tis lz lxlAclxlPlxleyl

0-0-..log
0-0lr-.log
1--...,Clog
T-Traplog
S-Signlo9
Z- l.orolog
Ac-,._,,...-,log
P-Pwtylog
Cy-Ca,,ylo9
X-Nal-
fll. 1A ,,.., lfefl_o,-.
The clacriptioo, ofeach llag bit i1 u follows:

S.-., Flis This fla1 is oet whea 1he result ohay computation is aeptive. For liped eompalOlioal.
1he lip llaa equals the MSB of the result.

Z-Z- Flis Thi, llaa is IOI if 1he mull of 1he ~ o r _ . . perbmed by 1he previous
imlNdiowinatnat- is Zffl),

1'-l'utty F... Thi, llaa is IOI IO I if1he lower byte of1he result contains even mnber of I1.

c-c:.ny Flis Thi, llaa is oet whea 1here is• cony out ofMSB in cue ohcldition or• bonow in cue of
subtnclion. For eumple, whea two mnbcn - added.• cony may be 1eaeraled out ofdie moot lipi6caat
bit position. The carry llaa. in lhil cue, will be IOI 10 •I'. In cue, no carry is ....,..i. it will be •o·. Some
other inllnlctiont abo allect or- lhil llaa and will be diocuued later in this ...L

T-T.... Flis If this llag is aet. lhe procesM>< .-n lhe 1iagJe 1tep uecutioa mode. la other wonk,•
tnp iaemupt is aeaeraled after uecutioa of each imtructioa. The procesM>< u......, lhe current imwotion
and 1he • - I is tnftllm-e<i IO 1he Trap inwmopt oervice routine.

. . . - . F... If this 11aa is oeL the mubble U11em1pU - recopised by 1he CPU, otherwise lhey
are ignored.

O . D ~ F... Thi, is Ul<d by llrin1 manipulation inllnlctiont. lfthis llaa bit is 'O', 1he IViDg is
p,ocelNd beaialnina rr- 1he lowest acldreu to 1he hia),est addreu. i.e. ••lol11<:1Y-1i"1 aode. Otherwise.
1he IViDg is pn,c:esaecl r.- lhe hi....11 acldreu -ank 1he lowest addreu. i.e. • • ~ l i 1 1 g aode. We
will clacribe llrina m•ipoil..._ ...., in chopltr 2 in more detail.

A C ~ Cany Flis This is IOI iflhere i1 • carry r.- lhe lowest nibble. i.e. bit tbrec, duriaa
aclditioe or bonow for 1he lowest Dil,blc, i.e. bit-· duriaa IUbcnctioe.

0.0..,.• Flis Thi, ftaa is IOI if ID overflow occun, i.e. if 1he mull of• lipod opention is lorp
_,,i, IO be accommodaeod in • clnliaotion resistor. For eumple. in cue of die addition of two Iipod ..,._
ben. iflhe .....it overflows inlO 1he lip bit. i.e. die result is of more - 7-bita in size in caoe of8-bitlipod
openlions and moR than IS-bill in size in caoe of l(>.bit signed opefllliom. then 1he overflow llag will be KL
processed bcgmnang trom the towc.st addrcU to the htghcit addrcu. 1.e. au1omcremen1,ng mode. VtherwlSC,
lhe l1ring is proccaed fiom lhe hipesc adclreu towards lhe lowest address, i.e. outod«-,,ti,,g ...ode. We
will dncribe l1ring manipulatiom laser in chapter 2 in ....- detail.

A C ~ Cany F... This is ,et iflhere ia a cany fiom d,e lowelC nibble, i.e. bi1 lbree, during
acldilion or bonow for lhe lowesc nibble, i.e. bit lhree, during IUbcnction.

o.o-fto• Ros This flag is ,et if., overllow occun, i.e. if dw raull of a aipod openoon is larJ<
moup IO be ~ l e d in a destiaalion register. For example, in cue ofd,e addilion oflwo sipod num•
bera, if dw result overllow, into dw sip bil, i.e. dw ......i, is of more - 7-bita in size in cue of 8-bil sipod
openciomand DIOR - 15-bita in size incaK of l6-bi1sipodopenciom. lben lhe overllow flag will be ,et.

I .J SIGNAL DESCRIPTIONS OF ION

The micropn,cessoc 8086 is a 16-bit CPU available in lhree cloclt mes, i.e. 5, 8 and 10 MHz. packaged in a
40 pin CERDIP or plasric package. The 8086 operaics in single processor or multiprocessor oonfiguntions
to achieve high performance. The p i n ~ is shown in Fig. 1.5. Some oflhe pins aerve a particular
function in minim- mode (single pn,ce,-mode) and Olhen function in maximum mode (multiproceuor
mode) conllguralion.
The 8016 signals can be categoriaed in lbree groupo. The lint are d,e signals having - functions in
minimum u well u maximum mode, d,e oecond are lhe signals which t.ve opecial functions for minimum
mode and d,e lhird are lhe signals having opecial functions for maximum mode.

GNO
AO,. 2
-- --
40
39
vcc
AO,s
AO,, 38 A,.i5,
AO,z 37 A,,IS.
AO,, 5 36 A,o/St
AO,o 6 35 A,A
AOt 1 34 BiEls,
AOt 8 33 lfiiix
AO, 9 32 lffi
AOt
AOt
AO•
10
11
12
31
30
29
~.
iicworo

Cl5a<
(HOlD)
(HI.DA)
(WA)
AO, 13 28 ~ (M/IO)

ADz 14 27 s; (OT/II)
AO, 15 26 So (OEN)

-
AOo

NTR
aJ(

GNO
16
17
18
19
20
25
24
23
22

21
0So
OS,
Tm'
R£ADY

RESET
(ALE)
(INTA)

f1C. LS Pin 0>nfltutallon al ll()N

The following signal descriptions are - for bod, dw minimum and maximum modea.
AD 1,-AD1 These are lhe lime multiplexed memory l/0 adclreu and data lines. Addn:u remains on lhe
lines during T1 - • while lhe data is available on dw da1a bus during T,,T,.T. and T4 . Here T1,T,,T,.T4 and

T• aft the clock stues ofa machine cycle. T• is a wait state. These lines aft active high and float to a tristate
during intcnupt acknowledge and local bus bold acknowledge cycles.

A 1,,IS.,A1,.rs..A 1.,IS• A 1.,S, These are d,e lime multiplexed address and slalul lines. During T 1,
lhese are lhe - significant adclreu lines for memory operations. During 1/0 operations, lhese lines are
low. During memory or l/0 operations, llalul information is available on lhoK line, for T,.T,,T• and T4 .
The llatUI ofdw inlenupt enable flag bil(displayed on s,) i, updated a1 dw beginning of uch cloclt cycle.
The S4 and s, togelher indicale which segment regisier is presently being used for memory acceues, u
. ..... .. . . ...... .. ,. . ,....., .
currently -d.

BHE

0 Whole word (2 bytes)

I[] 31 of 706 Upper byte from or., odd-._

ltD . -
O

-
Lower byte from or to ~wn addras

Read signal, when low, indicales lhe peripherals - lhe pcoc:essor is perbmiag a memory
or l/0 read.,,...-_ RD is active low and lllows lhe ICal< for T,. T,, T• of any read cycle. The signal re•
maim lrislaled during lhe 'hold acknowledge'.

READY This is lhe acknowledgement &om lhe slow devices or memory dual !hey have completed lhe
data .,_i.,,_ The signal made available by lhe devices is synd1rooized by lhe 8284A clock gmeralor., pro-
vide ready input to lhe 8086. The signal is active hip.

I N ~ . . . . - This is a level triggered input. This is - l e d during lhe last clock cycle of
each inslNc:tioo to determine lhe availability oflhe reqll<IL lfany inlemlpC request is pending. lhe processor
mien lhe ia11cnupt acknowledge cycle. This can be inlemally masked by resetting lhe inlenupt enable Sag.
This signal is active hip and i....,,,.Uy sync:brooized.

TEIT This input is examined by a 'WAIT' inllnlctioo. If lhe TEST input goes low, uecucioo will
conli...,., else, !he pn,cellOf remains ia ., idle llal<. The input is synchrooiud intemally during each clock
cycle on leading edge of clock.

NMI-NcNH, I t la lnt.rn,pt This is an edge-triggered input which ca_, a Type2 inl<mlpl. The
NMI is - .nubble inlemally by SGftware. A transilioo &om low IO hip initiate, .... inlenupt .apome al
lhe md of lhe cun-ml inllnlclioo. This input is internally syncbrooized.

IIIIESET This input ca111<1 lhe pcoc:ellOI' to terminate lhe CUlffDI activity and stan uecucioo &om
FFFFOH. The signal is active hip and must be active for at least fow clock cycles. II reswts uecucioo when
lhe RESET mums low. RESET is also inkmally synchronised.

CLK-Clodr Input The clock input provides lhe buic timing for pcoc:e...,, operalioo and bus conlrol
activity. It's an asymmetric square wave with 33% duty cycle. The ,..ge of &equmc:y for diffanl 8086
versions is &om SMHz to 10MHz.

V« +SV power supply for lhe operation oflhe intemal cin:uiL

GND .,,,...ct for lhe internal cin:uiL

MNIMX The logic level al Ibis pin decides whether lhe processor is to operate in either minimum (single
processor) or maximum (multiprocessor) .mde.
TIM ,......,..111-. an ltr 1111 •l■I••• ... .,...-.orM4:
M/1/O -"-'yllO This is a - line logically equivalent IO S, in lhe maximwn .mde. When ii is
low, it indicaln lheCPU is having an l/0 operation. and when it is high. it indicates dual the CPU is having a
memory opentioa. This line becomes active in lhe previous T4 and remains active till final T4 of lhe current
cycle. II is tristated during local bus "hold acknowledge".

INTA~Ad.nowladp This signal is used ua readscrobe forin1enuptacknowledge cycles.

In ocher words, when it goes low, ii - - lhe pcoc:<IIGI' bu accepoed lhe intem,pt. It is active low during
T,. T, and T. of each intemipt acknowledge cycle.

ALE....._ Latch IEn■lole This output signal indicates lhe availability of lhe valid addreu on lhe
addreu/dola li11<1, and is conneel<d to lasch enable input of latches. This signal is active hip and is never
lristal<d.

DT/R-Dala T.....,,ltl!IMeM This output is used to decide lhe di.ec1ion of data llow tbroup lhe
transreceiven (bidirecliooal buffen). When lhe pcoc:euor sends out data, this signsl is high and when lhe
processor is receiving data, this signal is low. Logically, this isequivakntto S1 in maximum .mde. Its timing
is lhe same u M/ 1/0. This is lristased during 'hold acknowledge'.

DEN -Dala Enable This signal indicates lhe availability of valid dola over lhe addreu/dola lion. It is IIIOd
to enable the__,;..,. (bidiroctioaal bullon) to ,epome the dola &om the multiplexed addreu/dola signal. It
is active &om the middle ofT2 umil the middle ofT4• DEN is trislalocl durina 'hold acknowledge' cycle.
 ·-
• -· -·-·-----··· ···---··
Until now, we have detcribed the architcdUre and pin conftauratioa or 1016. In the DUI ooction, we will
acudy _,,. operational lcaturn or 1016 bued ~ -

1.4 ..HYSICAL MIMOllY OllGANISATION

In an 1016 bucd 1y11&m, the IMbytea me~ ia phyaically orpniacd u an odd bank and an cvcD bank.
each or 512 Kbytea. addnued in ponllel by die - - · Byte data with an CVCD - .. is -l'emd
on 0 7 -000 while the byte data with III odd addrHa ia -remd oe 0,.-01 buu linea. The proccuor pro-
vidu two enable aignala, BHE and Ao ror aclcctioe oreither CVCD or odd or boch the ....... The iDllnlcOoa

11ram is retched &om me~ u wonla and ia addrHacd inwmally by die procuaor u DCttua,y. la odlcr
worda, irdie proccuor rc1ehc1 a word (conooclllivc two byl&a) &om memory, there arc different possibili•
tica. like:
I. Bods the byte, - y be data opcnoda
2. Bods die bytea may coataiD opcode l>ill
3. One or the bytea may be opcode while die odier -y be data
All the above possibilitica arc taken ..,. or by the inacmal dccodn circuit or die microproc:uaor. The
opcode• and opcnnda ue identified by the inlemal dccodn circuit wbicll ""1hcr dcrivn die aip,ala lhoac act
u i1lput 1o die limina and con1rol UDit. The limina md . - 1 unit thCD dcrivn all die aipla required ror
executioa or the imtruction..
While .ere.ring to word data, the BIU requirca oec or two memory cycln, dcpCDdiDg upoe whether die
awtina byte ia localed Ill an even or odd addnu. It is alway• better lo locale the word Ill• even addnu.
data

To read or write a complete word fiomllo memory, ir it ia located at., even addnu, oely oec read or write
cycle is required. Ir the word ia located at• odd addnu. the lint read or write cycle is required r o r - -
ing the lower byte while the oocoed ODC ia required (or acccuma die upper byte. Thul, two bus cycln -
requited, ir a word is locawd 111111 odd addreu. It .-id be kcpc in mind that while iaitialiaina the llnlCtllrcl
like scaek they lhollld be initialiaed III an even addreu ror cfll<icat opcnboe.
1086 i, a 16-bit microproc:uaor md hence can accna two byl&a or in oec memory or l/0 read or
data

writ& opcraboe. But the commercially availal>le memory chipa ue oely byte aize, i.e. they can IIOrC oely oec
byte in a me~ location. ()l,yioualy, to IIOre 16-l,;t data, two aucceuive memory loclllioea - med and
the lower byte or 16-bit data can be IIOrCd in die lint memory location while die oocoed byte ia IIOrCd in the
DUI location. In a aixlem bit read or write opcratioD boch or theac bylea will be read or wrillcn in a ainalc
machine cycle.
A map or an 1086 memory 1yatem 1Wt1 at OOOOOH and enda at FFFFFH. 1086 beina a 16-bit pro«uor
ia upcctcd lo acccaa 16-bit data lo / &om I-bit ....-rically availal>le - ~ chipa in parallel, u shown
below in Fig. 1.7.

eoee
s~ ~
-
Odd-
BHE •O

Do(pO,
e-,

@
Do-

o,-Du
Do-D,
rt=- l
Thus, bill 0.,-07 or a 16-bit data will be -remd over 0 0-07 (lower byte) or 16-bit data bua

to/ &om &-bit me~ (2) and bit DrDo, or die 16-bit data will be tnmremd over DrO,. (hipcr byte)
or the 16-bit data bua or the microproc:euor, 10 / 6-1-bit me~ (I). Thul ID achieve 16-bit data -fer
111ina I-bit mcmorin, in panlle~ die mop or c-'"'" ayatem byte memory addreuea will obvioualy be
die

divided iDID die two memory bonkau lhowD in Fia. 1.7.

4 bytes for IIOriag it in tho moonupt vector tabl•. llonco, 2S6 type• ofrntcmipt r<qwrc Z>6 l: 4: UJHl1
(UC.byte) locatiom for tho complde inrnrupc vector cablo.

1.5 GENBAL BUS OPERATION

The IOl6 hu •combined-., and dllla • commonly rcfened 10 u • lime mullipl..od adcnu and elm
bus. The maia rcaooa behiDd multiploxiq adcns1 and elm over d,c ...,. pim is d,c maximum llliliAbOD
or ...-uor pim and ii facii.., d,c,... or 40 pin ltandlnl DIP pacb... Thc • CUI be demullipl..od ...
iq • few latchn and .,.__ivon, wbcaover required. In lhe followiq sex~ wo will discuu • ........ bus
opentioacyclo.
Baically,all lhc proceuorMcyclHcomistoh11o aat fourclockcyclH. Thcte- referrod10•T1, T,_T,
and T,. The adcnss is lnullmilled by lhe proceuordurina T 1. II is rre-oa lhc M only foroao cyclo. During
T,, i.o. lhc ...., cyclo, lhe bus is tristaled l'or chanaiaa lhe dircclioa of• for lhc followina dllla rad cyclo.
The dllla .,_._. lake, place during T, and T,. In UK, m adcnuod device is slow and shows 'NOT READY'
- lhe wait - T. arc imencd belweea T, and T,. Thcte clock - durina wait period arc called ldk
slola (T1). _,, Slota (T.) or i110cti~ slllta. The proceuor _. - cyclH for i - i bouoebepina. The
Addrea Laedi Eaable (ALE) lipal is.,,,_ during T 1 by lhe proceuor (minimum mode) or lhe M coatrol-
ler (-.iimum mode) depeDcliDg _ lhe _ ofdie MN/MX input. The negativeedpofdlisALE pulse is
IIIOd 10 sei-- die adcnss and lhe elm o , - infonnaoon. In maximum mode, die - lines So, 51and S,
arc lllOd 10 indicale lhc type oropenlioa .. discuued in lhc ,ipal deacripbon _.;c,aorthis chopler. S - bits
S, 10 S, arc multiplexed with hiper order adcnss bits and die BHE lipal. Addrea is valid durina T I while
die - s,
bits 10 S, arc valid during T, duoup T,. Figure 1.8 show, • gmenl • openlioa cycle or IOl6.

18

1---Mamo,y-cyda
T, I T,I T,I Twl T,
I T, I
Mamo,y-q,do --::-i
T,I T, I Tw I T,

Cl.I(

7~--~a~V \ w- c:=-
1A,.-A,. S,-S, A11-A11 S,-S,

fi
o. ... D,s-llo <D11-Do

-
"-Olly "-Olly

~"'-
READY
I \lli._J
DTIII
~~-----"-- I \..__
i5lN
!
~Mamo,y---:
\ V \ r--
wil

U l/0 ADDIIESSING CAl'AIILITY

The 80l6/1088 - - CUI adcnss up 10 64K l/0 byte rcgislen o, 32K word rcgislen. The limitalioa is
-lhc adcnu ofan 1/0clevicc -DOI be grcalerlhan 16 bits insitt, this me-that a maximum 11111111,er
16
of 2 • i.e. 64Kbyte IJO devices r b 1L $ CZ I D JP f1:eu appears oa the address lines
trh,,,,,t ncino thf. A I F cional TM 11nnoH -.,1,t,...n lin#'c
 llLJ 41 Of ] Q 6 II- LU 8ull'Mlf Dom Bua o f _ .

I.a MINIMUM MODE ION SYSTEM AND TIMINGS

In a minim..., mode 8086 1y1tcm. tbe microproc:eu« 8086 i, operaoed in minimum mode by ■trapping ill
MN/ MX pin ro lo8ic I. In Ibis mode, all tbe control sipals an 8iven out by the microproc:eu« chip i11elr.
There is• single microproc:cuor in the minimum mode system. The remaining compoaeDII ill the syatem
are latches. lnnlRCeiven, clock 8enerator, memory and 1/0 device,. Some type of chip ■election loaic
may be required f0< oelcc:lina memory 0< l/0 device■, depending.._ the adclre11 map oftbe system.

20

lffi MRO Mwii

1111<5 v,
MAO
WIii
3:8 v,
MWR ~
WR C(LS8)
IOWR
Rii B v,
ioilo
IORO
MIIO A(MS8) v,

The latches .,. generally bufrcted output D-type ftip-llopo. like, 74LS373 or 8282. They .,. -.I for
oeporaling the valid adclre11 from die multiplexed acldml/dlla signals and IR controlled by tbe ALE signal
aenero■ed by 8086. T,--iven an the bidiffl:lional buffers and oometimea they.-. called data amplifien.
They .,. required IO ..,_.,. the valid data from tbe time multiplexed adclreuldata signal They .,. con•
trolled by two signals. namely, DEN and OT/ R. The DEN signal indicates 1hal the valid data ii available
on the dlla bus. while OT/ R indicalel the direction ofdala. i.e. from/ IO the p,ocasor. The l)'llffll COCllains
memory lor the monitor and _,. program ,rorage. UIIUally, EPROMS are -.1 lor ,,_;a ........ while
RAM, lor _,.. proa,am IIOrage. A syltcm may c-.ia l/0 device, for commW1icalion with the p,oc:eu«
u well u _,,. special pwpooe l/0 devices. The clock.........,. (IC8284) ..nerates the clock from the crya•
!al oocillaaor and then obapel it to make it more precise so 1hal it can be -.1 u., accuntc limina ~feffnce
for the sysoem. The clock ...,._ also 1ynchtonizc1 _,,. extemal 1ipals with the 1y1tcm clock. The gen•
oral system orpnisation i1 shown in Fig. 1.13. Since it has 20 adclre11 line1 and 16 data lines. the 8086 CPU
requires - octal adclreu latches and two octal data buffers lor the complete adclre11 and data oeporalion.
The working of the minim..,. mode confi"""lion sysoem can be belier described in oerms of the liming
diagrams ratba than qualitatively describing the operations. The opcode fetch and read cycles an similar.
Hence. the timing diapam can be categorized in two puts. the 6nt is the liming diagram lor rw,d cyck and
the second is the limina diagram for wrl,e cyck.
The read cycle begins in T 1 with the-rlion of the Addreu Latch Enable (ALE) signal and M/ io sipal.
During the neptive going edp of this sip~ the valid addreu ii i...:bed on the local bus. The BHE and A0
signals adclreu low, high or both bylel. From T I ro T4 , the Mlio signal indicalel a memory or l/0 operation.
At T,. the adclreu ii - e d &om the local bus and is - to the output. The bus ii then ~ - The Read
( RD ) coatrol signal is also aclivaaed in T 2. Thia signal - . the adchued device to enable ia dlla bus driv-
en. After RD ,oa low, the valid data ii available on the data bus. The adchued device will drive the READY
line high. When the proceuor - the read signal to high love~ tbe ackhllOd device will again lnltllle its
bus driven. CS logic indicalel chip •lect logic and 'e' ..i ·o· oufixn indicate even and odd adclreu memory
bonb.
A wrilecyclealao beginlwitbthe-.lionofALEMMI theemilaionofthe adclreu. The wio signal ilapin
UIOrlOd to indicale a memory or l/0 operation. In T,. after ■-line the addreu in T ,. the pr--, sendo the
data to be writlm to the ackhllOd locaoon. The data remeiao on the bus until the middle ofT4 - · The WR
becomes active a the beginnioit ofT, (unlike RD ii - h a l delayed in T2 to provide time lor ftoolina).
The BHE and A0 1ipals . . ,-cl to ■elect the proper byte or bylel of memory or l/0 wonl IO be read or
writlea aa mady diocuued in the signal description aeclion of Ibis chapter.
The M/ io, RD and WR signals indicate the types of data tramfcr u specified in Table I.S.
""IHU.:11 .&:> •Ul;.-U)' UIM.UltKU Ill UN,; :.1~1. .1 ui,;:.,i,;11puun Ki.llUfl UI uu:. 1.1wp1.,;1.

The M/ K>, RD one! WR signals indicMe the types of data tnmfcr u apecified in Table 1.5.

,_u
1,1/jjj RD DEN T,-J,,Typ,
0 0 I IJOrad
0 0 IJO wrilt
0 Mnnory,. .d

-
0 Mc-,,writo

ROY
C•GEN.
8284 =
I
R- c• ROY

R - CII< Ready
MNIMX M/10
RD DMUX
v,.
WR
~ RAM
&088 BHE i:;_aoRAM
,·················; '-~~:r-► ~ ~g~
ALE STB '-'----_;_:="---------------
74373
AOo-AD,~ D1 Latchn 01
A11/S1-
20<3
A,A ..
cs
OTIR
cs. CSo

a a cs a
r...-.
' - - - ~ - i G 74245 ~ oe
Rt
l/0

DIR YI RDWR:

MRO MWR MRO

D9-D1s
1'11,1.U _ _ _ S)'Alffl

Figure l.l4(1) lhow1 the read cycle while Fig. 1.14(1,) lhow1 die write cycle.

I.I.I HOLD lle9p0nM s.qu-ce

The HOLD pin ii checked at the md of each bus cycle. If it ii received active by the p,occu« bclorc T, of
the pR•ious cycle 0< during T 1 ..... of the cunmt cycle, the CPU activ■tn HLDA in the next clock cycle
and f0< the 1UCCeeding bus cycles, the bus will be given IO another requesting muter. The coauol of die bus ii
1104 regained by the p,oce110< until the requesting muler does 1104 dlOp the HOLD pin low. When the requell

ii dlOpped by the reque1tiag - . the HLDA ii dlOpped by the p,occu« It the tniling edge of the next
clock. 11 lhown in Fig. 1.14 (c). The other coaditiom have already been dilCUl■ed in the 1igaal deacripcioa
ICC1ion b the HOLD and HLDA signals.

T, I r, I r, I Twl T, I

~J7
AOOISTAT\JS=x H. A,.-A,.x S,-S,
C
NJOIOATA
--
liorct.a.ein D,s-Do ---------
 'II- UA(c) Bua R,oquest-Bua Granl Tlm/nf1 In llflnlnNMn - ~

1.9 MAXIMUM MODE 1086 SYSTEM AND TIMINGS

In the maxiDn mode. the 8086js OJ.>CIW<l_by ltnlppiDg the MN/ MX pink> ground. In dlis mode, the pro-
cessor derives the - ,i.,..b S,. S1 ond S.. Aaochcr chip called bus comn,ller derives the coallOI sipb
using this Sla111S infonnation. In the maximum mode, there may be IDOff d w , - m ~ in the sys•
tem configumion. The ocher componenu in the system are the same u in the minimtan mode sy,tem. In Ibis
section. we wiU IIIUdy the bus conuoller chip ond ib functions in brief. The functions of all the pin, having
special functions in maximum mode have almldy bccD discussed in the pin diagram KC1ioD oflhis chapter.

-
f:I
INTA
-Clk
~
So
ROY if, ~
8288
- O k ROY ~
-s, Bus
~ lowe
ALE
-Ok OEN OT/ft CS.RAM
,.. CSoRAM
~ROM
CS.,ROM
ll086 __,.._C§ IO
r--------- : L.__ _

5TB
ADo-A01s,
A,e/5,- Oi~Qi
A19fSt
74373

MNIMX

The buic fuDctiom oftbe bus conllOller chip IC8288, is to derive CODIIOI signals like RD and WR
(for memory ond l/0 devices). DEN. OT/ R, ALE. etc. using the i n f ~ ~ available by Che
processor OD the stabaS lines. The bus eonllOller chip bas input lines S,- S 1 and S 0 and CLK. which
are driven by the CPU. It derives the ouq,uts ALE, DEN, DTIR, MRDC, MWTC. AMWC. IORC,
IOWC and AIOWC. The AEN • 108 and CEN pins are specially useful for multiprocessor systems.
AEN and 108 are gencnlly grounded. CEN pin is usually tied to +SV. The significanc:c oftbe MCE/
PDEN output depends upon the stabaS of the 108 pin. lfl08 is grounded, it acts u muter cucade en•
able to conllOI cucaded 82S9A, else it acts u peripheral data enable used in the multiple bus configura-
tions. INTA pin is vsed to iu..ae two intenupt eckDowledae pubes to the intcnupt controller or to an
intenuptin1 device.
IORC. IOWC are l/0 rHd command ond l/0 write command signab respectively. These sipb enable
an 10 iDlerface k> read or write the clala from or k> the addressed port. The MRDC. MWTC ore memory
rHd command ond memory write command llignab respectively ond may be med u memory read md write
sipb. All these command llipb iDstnic1 the memory to accept or send clala k> or from the bas. For bolh
of these write command signals. the adv.-d llipb nunely AIOWC ond AMWTC ore available. They
abo serve the 1UDC . , . . _ , but are IICtivMed one clock cycle earlier dwi the IOWC ond MWTC sipb,
respectively. The maximum mode system is shown ia Fig. I. IS.
The maxim..., mode system liming diagram• are also divided in two portion, u read (input) ond write
(output) liming diagrams. The addreu/data ond adclreu/status timings are similar to the minimum mode.
ALE is uscrted in T 1• just like minim1m1 mode. The only difference lica in the status 1ignal1 used and
1M available conllOI ond advanced command signab. Fi1ure 1.16 (a) shows the maximum mode limin1•
for the read operation while the Fig. 1.16 (b) shows the same for the write operation. The CS Logic block
represents chip select logic ond the 'e' ond ·o· suffixes indicate even ond odd addreu memory bank.
100 .,..... "- ••- - - - ""~ •- activlt<d - clock cycle earlier lhan the IOWC IDd MWTC signals.
n:spc, ([] 45 f 706 iom iuhown in Fia. I.IS.
n : 0 a diasruns are also divided in two portions u read (input) IDd write
(ouq>ul/ umma a11gnn11. I DC -ss/clMa u,d addrus/SlalllS liminas are similar IO die minimmn mode.
ALE is utencd in T 1,j1111 like minim- mode. The only difference lies in the llalllS sipals med ud
the availallle CODlrOI u,d advanced commud sipals. Fi,- 1.16 (a) shows die muimum mode liminas
for die n:adopenlioD while die Fia. 1.16 (h) shows die.._ for die write openlioD. The CS Loaic block
n:pn:scnts chip seleet loaic ud die 'e' and ·o• suflxu indicate even ud odd addn:u -mory bult.

I r, I r, I r, I r, I r, I

CU(
- - - Ono bus cyda - -

ALE

AOOISTAruQ-< IIHE, A,o-A,o Xs, - s, }-- - - - - •

N:IOIOATA - - ~ - - - - -
AD11-Allo

T, I r, I r, I T, I

CU(

, - --_-_-_-_-... Ono bul cyda - - -

ALE

_,,.
s.-s. ______ v-;,;;;,_--,r-
__,1'... - - - - --,'\..__
Aool
s,-s,

N:IOIOATA DATA OUT D,. - Do

AD,s-ADo
NI/WC«
ii(1li(;

OTIR

OEN
( MICROPROCESSOR-AND-INTERFACI... ,
-------- ---- ---

57 Of 706
r,r-, --.plndlogra mundlmlng. .._cl_andwr llt
l:LJ '"'11 ... - ..... _ . ...- - . - ~
'II • - - N I . F""°', • tow ~andhquonl r
_ _ _ and..,.,..._ . . _ _ _ Thuo. . ~-•blcl9ou ndtr
. _ , . , . , . . . , . _ _ , . ._ _._A,.._c l _ _ _ _ t r ~ " " '
---cl--llig llly-.,.... _and_,., ... _ _ _ cl _ _ ..,
-p,lnciplN. Thi - and~ - hor9 n - .., 11ASM ( M - MACRO
ASS~ER).

2, I MACHINI LANGUAGE INSTIIUCTION POIIMATS

A SMC!.int -,-,C ~ format hu one or more numllcr or llclda utoeialcd wilh it. Tht ftnt IWd it
callcd u opnodott tOlk jwU or opco« field, which indicalel the typt or the operattOO IO be performed by
lhe CPU. T\c imtrudioa format alto cont1i111 other Kida known u optrondfi•l4h. ne CPU cxccUICs lhc:
iMwctMNI -..inl lM in'--'"- which N•ide in .... AeW..
There aft six aenmJ formats of imtnKtt()M in 8016 ~ M l . T h e leasth ofNI instnacboa may 1/&I)'
from o. l,yte to six bytt,. The instrvction fonnats an dtKrilJod • follow-.:
I. One 1tJ1e INCNctletl This format is only oac l,ytc loat and may haw the i,..licd dlla or reai11er
ope,.... The le•t tipifk• l•bittoflhe o,codc ut mtd for1pccifl,-in1 dtere1i11eropcrand. if any. Q1h.
•rwiM, ■II CM t-lth1 form an opcode and tM ~ -. implMd.

1, . . _ . _ , . llepOer Th• - M! bylc. loaa- Tho ftm b)tc of !ho code ,peciftu fie opcmioo
Nkit and width ofthe- operud 1peci&ed l,y • M;_ The MeoM ltyw ofdw C'odt thow• dlot reaitter openack
- , RIM lleld, u thowo below.
D, D, D, D706 DSD4D3 02 DI DO
I OPCODE w I II REG I RIM I

Th4I Nt..tff n-pn"•Nd.,. the REG Mid is one o(thc operud,. Tho RIM field 1,-ci&., anothcf' n1i.ter
or memory locatioa. i.e. CM ochn-opctand.
J . ....-.,-tolfNm Memerywtlh no D ~ This (OftUI is alto 2 l,yttt k>ftaandsimilarto
the naistrr ao rc1is1tt rom.. .x«-p1 for 1M MOD 6dd as ahown.

D, D, Du Dl D6 DS D4Dl D2 DI DO
I OPCODE w I MOD REG RIM

Th< MOO kid ol,owt !ho - of - • I · 11w MOD, RIM, REG Uld Ille W llelcb "' de<iclod in
T•1e2.2.
4. "-lhtar talfrwn Memory with D ~ This type of insnction rcnnat coruinl OM or
two addicioaal bytes for di1plac:cmca1 aloq wich 2-byt.c lhe bmal or the rcailt.cr to/from mc11.ory wifM>ul
d t a p ~ TM fOffMI i1MlhowaNtow.

D, D, _.:D:..:7.:06:::...____:D:::S:..:D4=D:..:3~.::D.:.2.::D.:..1.:.DO:.... D,
I OP CODE jj MOD I REG RIM j I
.
Lowa-_ Byte of
D1sp. .
I
D, D, D,
Hi&hcr Byte or
D1tp.

I. - Opo,and ,_ ~ lo lhM ro.m.t, lllc llnl..,,. u well u die J.bitt fn>m lho N<OOd
byte which art UICd ror REG Acid ie CaM of resister IO rc1i11er fonMI arc .eel for opcode. It also C01Uin1
one or iwo ll)'w:• v(lffllnCdi.ac dale. Tbc wmplclc im&nllclion "--- ii .. ahu,w• bcktw.

D, D, D7 06 DS D4 DJ D2 DI DO D, D, D, Do
I OPCODE 11 II IOP-CODE I RIM 11 ~ZT~ I llipcr Byte DATA

6. - Opo,andto Memerywlth l._.lt Dl1,l1t1me11C nil type ofinstructioll format re•

qun,s.,, 1,y1,, ,-.,,-.,. The fin<2 by,c.,-..,lho .-,...,,....,i.,oP COOE, MOO,tnd RIM
ftcldl. n. 1n111lftl. . 4 i,yw, coacaiD 2 byltsordispllc:Cffld l-.d 2 byee:s ofda&a as lllown.
D, D, D7 06 Dl D4 D3 D2 DI DO 0,
I OP CODE 11 MOD I OP-CODE I RIM I
D,
u"" u,,n,. _ d""'..,. ''"'iuu ...u. '"'"''" ,., .,.., Y"J"''"'_, ............ ~ ..,, .,_ .., ..,,,.,,., ,.._____ .... -~ ,.~.,~---~ v .., . -

ration between che segmnl areas. They may or may DOC overlap with each odle:r. Chaplet 3 on 'Aucmbty
t..1uaae Progroaunm1' c,plaim the codi"' ......- of the imlnlctiofts with suiloblc cumpln.

2.2 ADOltESSING ..OOU OP ION

Addftssia& . - indicalcs a way of localing - oc .,.....i.. Depending upoa the - l)'pCI ....i mthe
inmuction and 1hc memot')' addrcuin1 modes, uy illlllnactioe may bclona so one or mote addraliaa mode,,
oc _,. imlN<tioll may aoc belon1 to aoy of the addmsin1 . - , . Thus the addrcaing . - . cletcribe
cbc types of opcrudt ud lbc way they arc IICCflMd for executing an mlnletioa. Hue, we will pnseat the
addrcaing . - , of the malN<tioftsdepending upoatheil'l)'pCI. Acconling to the low ofiaalNctioa uccu-
tioa, the inotnN:liofts may be -,oriscd u (i) Sequeatial _,,.,I flow ioa1Nc1iono MNI (ii) Comol tram'°'
imwctioftl.
~ t ial colflroljlow i,utrvctk,111 an IM l,utrvcdo,u w•k• aftn- ex«vlkHt, 1n1,ufareo11trol lO IM lfUt
i,utrvcdo,e appnri,eg i•#fltdiawly aft,, It (i,e tit, •«fW'J«) ;,, IM progra•. for example, 1he ll'idmetic,
losical, data tnnsfcr and .,..,...... _,,.,I imlnlctiolla _, ,equenlial -.ol low ioauuctiolla. l"lw C011trol
trt,,ufer l,utruclio,u, <M tit, OIMr' lulttd, tra,ufer co,,trol lO ,a-, prwlefiMd addnu or ti¥ tuldn:n SCHHltow
1p«/fid I• tit, ;.,tnK:tio,, afwr tlt,/r,x«wtio,. Foe example, INT, CALL. RET Md JVMP iaalNctioaa fall
uadcr lhit ca&elO')'.
The addreuina modu b _,.,ial and comol tram'°' inllNctiofts .,. uplamecl .. follows:

I. Immediate In this type ofaddrcuing, immediMc data ll a pal1 of inllnletioo. and appean in the form
of sueceaivc byte or bytes.

Eumple2.1
HOV AX, 0005H
HOV BL. 06H
In llo - oumplN OOOSH end 0eH _ . . _ - • - · T h e - - mey be M>I
oc 18-bl In aize.

2. - In the cliroct addrcaina mode, a 16-l>it memory addms (olfld) oc aa 10 addml io directly
spcci6cd in che instructioe u a pal1 of it

Eumplel.2
HOV AX, I 5000H J
IN BOH
He,., - lffidN In a memory location In the - aeg,nent, wi-. - - . . mey be
_.,tedualng- uthe--aa-conlenlolOSu~addrMa.The-
- ... he,., lo 10H"OS+-. In the-.d-..ctlon 80H lo l0-aa.

l . ......,. In the rcglACr addressina mode, cbc er.ca ii IIOffll in a rcaillcr ...t it is rcfen-ed using the
par1ic111ar regislcr. All the regioscn, except IP, may be uocd ia this.-.

Eumple2.3
HOV BX, AX.
AOC AL. BL
The - - In theH lnalructlona.,. pt<Nided In ,-gillera BX, AA - AL. BL reopeclMly.
4, ......., . , _ Sometimes, the addreas of the -mocy locatioll wbicll _ _ , . - oc opcnnd is
dctmniacd in an indirect way, usilta thc offset rcgiltcn. This mode of addressing is bowa u rcaisltr indi-
rect mode. In lhi1 addreuing mode, the of&d addrcu ofelm is in either BX or SI or DI rcaisler. The defauh
tcpncnl is cithcr OS or ES. The data i1 supposed IO be available at thc acldrca poiak,d IO by the CODlffl( of
aay of the above re1ioscn ill the default data .._ . . .
Eumplel.f
HOV AX, (BX]
He,., - lo ~ - In a memory location In OS wi-e ollHI - a a lo In BX. The - ao-
dreaa ol llo - • giwr, u 10H"0Si{BX).

S. _,,... In this addreasing . - , olfMI of the opcnnd is IIOrcd • - ofthe iedcx regioscn. OS is the
dcfauk acpnc111 b index re1ioscn SI and 01. In,- oflllriftl ioauuctiolla OS and ES ace dcfauh a c - for
SI aad Ol re,pcc1ivcly. Thio 1M« io a special cue of the above discuued re1illcr illdired adclmlio,s IM«.
Eumple2.5
HOV AX, (SI]
HOV ex, (Oil
He.-, - • - • - - - - - I n SI In OS. T h e - - In thia c:ue, lo
_.,iec1 u 10H"OS,+{SIJ. The-o1-.10H-os.is11 will b e - no ,-gialef ex.

6 . . . . . . .r llelMwe la Ibis addreuiQg mode, the data ii available al an effective address t"onnecl try
- • • I-bit or 16-bitdi,placcmcnl with the-ofaoy-ofthc regisscn BX, BP, SI MNI DI ill the
A,,.f'.,..h , .. :,"--.. nc ,.... r::c\ ......- .., Tl... ..,.,..,_.......:........ i....1 .............1.. : ... ,1o.:. -,,,A,,.
 • · · '"'O'"..,.' _ ..,.,,.,.,..,e .,,.,....,, -- - - - __,,.,... .., • '"'e-• - - u ,,. ,.,.,.,.u_ -•"t, .. _
porticular ,.,...,, All lhe ,.,_,., except JP, may be -.I ia lhi1 mode.

waple:U
HOY BX, AX.
ADC Al, Bl
Tho - - I n - lnowction1.,. ptOllid.cl In l9gillen BX, AX and Al. B L ~ -

I[] 61 of 706 ..... lhe-..oflhe--,, Jocotionwhit~ ..-....-.. openndis

or-...., is bowa 01 ....... - ·
... 1M 011',ct .., ...... This moclt
rect mode. lo lhis-...., moclt, Ilic 011',ct-., ofdala is • - B X or SJ or DJ,.,;.., Tl,odeWt
oeamcm is eilher OS or ES. 11,e - is s_.J., be available al lhe-., poiolod., by Ilic-.. of
•y of the above reaiaers ia lhe dtfaull dalla Mpnnt.

Examplo:U
HOY AX, (BX)
...._, - l o p,e..-.t in •mamory-in o s - . - -.. ii In BX. T h o - •
chaa al the- ii gi.., u 10H'DS+{BXJ.

S. - . . i la dais-.,.,. mode, 011',ct oflho open,od i s - . . ! • -oflhe iadex ,.,_,., OS is lhe

d e - , . _ for iadex ,.,_,. SI and DI. la c:ae ofllri"l inllNctiom OS and ES.,. default,._,.. for
SJ ud DI rapeclively. This moclt is a speeial - of. . above disc--',.,..., - - . . . , mode.

Examplo:U
MOY AX. (Sil
MOV ex. (DI)
...._, - • - l l a n _ _ _ ln 81 JnDS. Tho---lnll, locuo, is
- - a a 10H'DS+{SI]. Tho-al-10H -OS+{S1Jw abe_.., Ngioll<CX.

6 ........... - • la !his-...., mode, lhe clala is available a l • ,Oeclive-., ro.-d by

acJdioa• l•IHlor 1 6 - b i l d ~ wilh lhe _,,.of...,_oflh o "tiloon BX, BP, SI and DI ia lhe
de"""1 (<idler OS or ES),........ The • - l e aiveo below e,q,J.aiu lhi1 moclt.

Example2.6
HOV AX. SDH[BXJ
MOV IOH[SI J. DX
...... t h e -... - i s gi.., u 10H-OS+60H+{BX) and 10Ho0S+101ff{SI) ~

7. - lnduad The ellec1ive oddress ofclala is formed. ia !his -ulng mode, by addiag _,,.
oh bue ,.giller (any - ofBX or BP)., lhe c:oaloal ofan index ,..iller (any- of SJ or DJ). 11,e default
,._,,. ,.tiller may be ES or OS.

waple2.7
MOV AX, [BX) [SI)
M0V [BX) [DI]. AX
Here, BX ii 1ha - ragiste< and SI is lhe irMm register. The - - .. is COfl1)Uled u
10H'DS+(BX)+{SI~

8. - - .,_... The ellec1ive-.. is ......t by oddina • I o r • - ..............

with the sum of coaltatl of anyone of the NIC ~aislcn (BX Of BP)Md M)'OOt of the index rcatlllttl. in a
defouhscamcoc.

EumploU
HOV AX.S0H (BX)(SJ)
ADD S0H [BX) [SI). BP
...._, $0H i s a n - ~ BX ilabaM ragiolerandSI ilan irMm ragioler.
The - _ , ... a l - i i "°'"""'ad aa 10H•DS+(BX)+{Sl)+60H. The - , d inllruction addl
oonlenl al B wi111 memory - al wllid\ ollNt ii gi.., by ~ 50H al content al BX and SI.
Tho ..... ii - - In lhe memory location.
forlhe<OlllrOl,,_ re,_111<-...,.mo c1esclepead,.... wMlhorlhedetliao lioolocalioo
is wilhio lhe - • -or ia a d i - - · h alao depads...,. lhe aodlocl ofpouiag lhe delblloboa
addrtu to oho...--. Buically,....,. are two-uiaa moclts fo, Ilic <OlllrOI ,._re, iaalnlctioM, viz.
inemepnen<and _ _,._...,. _ _
If tM /ocatiott to w/,k:A tM co,,tro/ t, to I>, tratufe,r,d Ila i• a diff,-1 ,,,_,,, odt,r tltt,• tltt, ,.,,...,
°""• 1M lftotk U ca/Id l11Nneglltfflt '1fOllc. J/tlw dad1t0llolt loc•tiolt llu 111 tlw #•,_ #f#Wltl, 11M -,t:k II
called i11tnueg,w,tl "'°"'·

__
Fi,-2.J thowslhemoclta for<OlllrOI . . .rer-..:tioas.

---- {-{=
-- -{
,.._2.1
::.
_....,_,o ,_r_ _
--
t. Jn11-wot _ M_ Jo this moclt, lhe _ , , to which the .-ol is., be . . .rer..d Jie,
in the a.amc ac,-ent U1 which 1be: eo1111rol tnmfcr imtruction lies aad appears directly in die UlltnletKNI • an
-.,.d.-,,iva lue. lalhis-....,moc Je,llic~iscoep uoodftlalivelO lho_,,.
oflhe iaalnlctioo poiaocr JP.