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MPMC

The document provides an overview of the Intel 8255A Programmable Peripheral Interface, detailing its architecture, modes of operation, and internal components such as data bus buffers and control logic. It also describes the 8051 microcontroller's architecture, including its CPU, memory structure, general-purpose registers, and interrupt sources. Key features of both devices are highlighted, focusing on their functionalities and operational modes.

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0% found this document useful (0 votes)
9 views6 pages

MPMC

The document provides an overview of the Intel 8255A Programmable Peripheral Interface, detailing its architecture, modes of operation, and internal components such as data bus buffers and control logic. It also describes the 8051 microcontroller's architecture, including its CPU, memory structure, general-purpose registers, and interrupt sources. Key features of both devices are highlighted, focusing on their functionalities and operational modes.

Uploaded by

Rahul Epuru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1.

INTEL 8255: (Programmable Peripheral Interface)

The 8255A is a general purpose programmable I/O device designed for use with Intel
microprocessors. It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be
configured to meet different system I/O needs. The three ports are PORT A, PORT B &
PORT C.
Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as
PORT A or PORT B. However, PORT C can be split into two parts PORT C lower (PC0-
PC3) and PORT C upper (PC7-PC4) by the control word. The three ports are divided in two
groups Group A (PORT A and upper PORT C) Group B (PORT B and lower PORT C).
The two groups can be programmed in three different modes. In the first mode (mode 0),
each group may be programmed in either input mode or output mode (PORT A, PORT B,
PORT C lower, PORT C upper). In mode 1, the second’s mode, each group may be
programmed to have 8-lines of input or output (PORT A or PORT B) of the remaining 4-lines
(PORT C lower or PORT C upper) 3-lines are used for hand shaking and interrupt control
signals. The third mode of operation (mode 2) is a bidirectional bus mode which uses 8-line
(PORT A only for a bidirectional bus and five lines (PORT C upper 4 lines and borrowing
one from other group) for handshaking.

Data Bus Buffer: It is a tri-state 8-bit buffer used to interface the chip to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by
the CPU. Control words and status information are also transferred through the data bus
buffer. The data lines are connected to BDB of p.
Read/Write and logic control: The function of this block is to control the internal operation
of the device and to control the transfer of data and control or status words. It accepts inputs
from the CPU address and control buses and in turn issues command to both the control
groups.
Chip Select: A low on this input selects the chip and enables the communication between the
8255 A & the CPU. It is connected to the output of address decode circuitry to select the
device when it (Read). A low on this input enables the 8255 to send the data or status
information to the CPU on the data bus. (Write): A low on this input pin enables the CPU to
write data or control words into the 8255 A.
A1, A0 port select: These input signals, in conjunction with the and inputs, control the
selection of one of the three ports or the control word registers. They are normally connected
to the least significant bits of the address bus (A0 and A1).

RESET: A high on this input pin clears the control register and all ports (A, B & C) are
initialized to input mode. This is connected to RESET OUT of 8255. This is done to prevent
destruction of circuitry connected to port lines. If port lines are initialized as output after a
power up or reset, the port might try to output into the output of a device connected to same
inputs might destroy one or both of them

Modes of operation
The two modes in which 8255 can be programmed are as follows:
Bit set/reset mode
The bits of port C gets set or reset in the BSR mode.
When port C is utilized for control or status operation, then by sending an OUT instruction,
each individual bit of port C can be set or reset.

I/O mode
The I/O mode is further classified into:
Mode 0: Simple input/output
Mode 1: Input output with handshaking
Mode 2: Bidirectional I/O with handshaking
Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function
or simple output function. In this mode there is no interrupt handling capacity.

Mode 1 – Handshake I/O mode or strobed I/O mode.

In this mode either port A or port B can work as simple input port or simple output port,
and port C bits are used for handshake signals before actual data transmission. It has
interrupt handling capacity and input and output are latched. Example: A CPU wants to
transfer data to a printer. In this case since speed of processor is very fast as compared to
relatively slow printer, so before actual data transfer it will send handshake signals to the
printer for synchronization of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode.


In this mode, Port A and Port B are configured as bidirectional I/O ports, while Port C is
configured as a control port for setting various operational modes.
Port A uses five signals from Port C as handshake signals for data transfer.
Port B uses the remaining three signals from Port C as handshake.
Port B either in Mode 0 or Mode 1. When Port B in mode 1, the lower bits of port C are
used for handshaking signals.

2. Internal Architecture of 8051 Microcontroller


The 8051 microcontroller architecture is shown below

CPU (Central Processor Unit):


The Central Processor Unit or CPU is the mind of any processing machine. It
scrutinizes and manages all processes that are carried out in the Microcontroller. The
user has no power over the functioning of the CPU. It interprets the program printed
in storage space (ROM) and carries out all of them and does the projected duty. CPU
manages different types of registers in the 8051 microcontrollers.

Bus
Fundamentally Bus is a group of wires which function as a communication canal or
means for the transfer of Data. These buses comprise 8, 16, or more cables. As a
result, a bus can bear 8 bits, 16 bits altogether. There are two types of buses:
1. Address Bus: Microcontroller 8051 consists of a 16-bit address bus. It is brought
into play to address memory positions. It is also utilized to transmit the address from
the Central Processing Unit to Memory.
2. Data Bus: Microcontroller 8051 comprise of 8 bits data bus. It is employed to cart
data.
Program Memory
Program memory in the 8051 is read-only, while the data memory is considered to be
read/write accessible. When stored on EEPROM or Flash, the program memory can
be rewritten when the microcontroller is in the special programmer circuit. The 8051
starts executing program instructions from address 0000 in the program memory.

Data Memory
The 8051 has 256 bytes of internal addressable RAM, although only the first 128
bytes are available for general use by the programmer. The first 128 bytes of RAM
(from 0x00 to 0x7F) are called the Direct Memory, and can be used to store data.

Special Function Register

The SFRs are at the directly addressable space special registers. These can be
accessed by their names or by their addresses. The SFRs have addresses between
80H and FFH. These addresses are above 80H, since the addresses 00 to 7FH are
addresses of RAM memory inside the 8051.Not all the address space of 80 to FF is
used by the SFR. The unused locations 80H to FFH are reserved and must not be
used by the 8051 programmer. The meaning of each symbol is enlisted in Table
below.
General Purpose Registers
The 8051 has 4 selectable banks of 8 addressable 8-bit registers, R0 to R7. This
means that there are essentially 32 available general purpose registers, although
only 8 (one bank) can be directly accessed at a time. To access the other banks, we
need to change the current bank number in the flag status register.

A and B Registers
The A register is located in the SFR memory location 0xE0. The A register works
in a similar fashion to the AX register of x86 processors. The A register is called
the accumulator, and by default it receives the result of all arithmetic operations.
The B register is used in a similar manner, except that it can receive the extended
answers from the multiply and divide operations. When not being used for
multiplication and Division, the B register is available as an extra general-purpose
register.

Oscillator
As we all make out the Microcontroller is a digital circuit piece of equipment, thus it
needs a timer for its function. For this function, Microcontroller 8051 consists of an
on-chip oscillator that toils as a time source for the CPU (Central Processing Unit). As
the productivity thumps of the oscillator are steady as a result, it facilitates
harmonized employment of all pieces of the 8051 Microcontroller. Input/Output Port:
As we are acquainted with that Microcontroller is employed in embedded systems to
manage the functions of devices.

Timer and Control Unit


The main function of a timer is to make a delay otherwise time gap among two
events. This microcontroller includes two timers where each timer is 16-bit where the
system can generate two delays concurrently to produce the suitable delay. Generally,
every microcontroller uses hardware delays where a physical device can be used
through the processor to generate the particular delay which is called a timer.
The delay can be generated through the timer based on the requirement of the
processor & transmits the signal to the processor whenever the particular delay gets
generated.

Types of Interrupts
The interrupts of the 8051 microcontrollers have the following sources
 TF0 (Timer 0 Overflow Interrupt)
 TF1 (Timer 1 Overflow Interrupt)
 INT0 (External Hardware Interrupt)
 INT1 (External Hardware Interrupt)
 RI/TI (Serial Communication Interrupt)

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