CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241
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Things to Remember
Presentations will be uploaded on CMS in PDF format.

Lectures will be roughly 45 Min and Q&A 5 Min

Keep your mobiles Switched off or in Silent

Notices and Lecture Material - LMS/Google Classroom

Saturday: 10-11 AM
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One BIG Question

Why learn this subject ?

3
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I Say
Basic Subject
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A I Say s
Basic Subject
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A I Say s
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Operating
Systems
Computer
Arch. Compiler
Design

MPI
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Handout-Course Overview
Peripheral
Devices
I/O, Memory
Interfacing,
interrupts

Architecture and
Programming
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Handout-Text Books
Textbooks:

T1: Barry B. Brey, The Intel Microprocessors: Architecture,

Programming and Interfacing, Pearson, 8th Edition, 2009.

Reference books

R1: D. V. Hall, Microprocessor and Interfacing, Tata McGraw Hill, 2nd

Edition.
R2: L. B. Das, The x86 Microprocessors, 2nd Edition, Pearson
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Handout-Evaluation
Sl. Weightag Date & Nature of
Component Duration Marks
No. e (%) Time Component
1. Mid-Term Examination 90 mins. 25% 75 Closed Book
2. Quizzes TBA 10% 30 TBA Open Book
120 mins. / As per
3. Regular Lab Evaluations 15% 45 Open Book
week timetable
4. Lab Exam TBA 10% 30 TBA Closed Book
Comprehensive
5. 3 hours 40% 120 Closed Book
Examination

How would be Quizzes conducted? – would be

communicated with in next two classes

Details of Lab exam will be communicated by Mid-Sem

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Important Announcements

The Practical sessions will be starting from 17th January

The Tutorial sessions will be starting from 21st January

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Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 1: Introduction
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Microprocessor-Overview

X=A+B
Y=C+D
F=X+Y
where A, B, C and D are n-bit binary numbers
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Microprocessor-Overview
X=A+B
Y=C+D
F=X+Y
A
B + X

C
Y
+ F

D +
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Microprocessor-Overview
X=A+B
Y=C+D
Sequential Architecture F=X+Y

A
B
Mux
+ Reg 0
C
Clk
D

Control
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Microprocessor-Overview
X=A+B
Y=C+D
Sequential Architecture F=X+Y

A
B
Mux
+
ALU
A
A+B Reg
A
0 A+B
C
Clk
D
X=A+B
Control Y=C*D
F=X-Y
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Microprocessor-Overview

Data Memory Universal Architecture

Micro
A A small chip whichALU
B Registers
Processor
Mux
+
has computing i.e. data
processing capabilities Reg

C
Clk
D
Stored Program Computer
X=A+B
Who invented this? Y=C*D
Instruction Control
F=X-Y
Memory
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A General Computer
Mouse
Keyboard
Bus Input Devices

Memory Bus CPU

8086/ARM
ROM/RAM Bus Output Devices
SSD Display
Datapath
Cache
Control
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Evolution of 8086 Family
Name Date Transistors Clock Data
speed width
8086 1978 29,000 5MHz 16 bits
80286 1982 134,000 6MHz 16 bits
80386 1985 275,000 16MHz 32 bits
80486 1989 1,200,000 25MHz 32 bits
Pentium 1993 3,100,000 60MHz 32 bits
64-bit bus
Pentium II 1997 7,500,000 233MHz 32 bits
64-bit bus
Pentium III 1999 9,500,000 450 MHz 32 bits
64-bit bus
Pentium 4 2000 42,000,000 1.5 GHz 32 bits
64-bit bus
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Thank You
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Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 2: Processor and Memory

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Microprocessor-Overview
Data Memory Universal Architecture

Micro
A A small chip whichALU
B Registers
Processor
Mux
+
has computing i.e. data
processing capabilities Reg

C
Clk
D
Stored Program Computer

Instruction Control
Memory
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A General Computer
Mouse
Keyboard
Bus Input Devices

Memory Bus CPU

8086/ARM
ROM/RAM Bus Output Devices
SSD Display
Datapath
Cache
Control
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A General Computer
What happens when you turn ON your computer

Input Devices
Disk DRAM
Memory CPU
ROM
BIOS Output Devices

BIOS-Basic input Output System

Secondary Memory
Load computer’s Operating system from disk (Magnetic Disk/SDD) to
DRAM
Primary Memory

What is BIOS and OS?? Programs- Set of instructions to executed by

the processor
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Processor
What steps will the Microprocessor follow to execute a program??

1. Fetches Instruction
Control Unit
Memory
DRAM µP 2. Decodes Instruction
ROM
BIOS Datapath
and ALU 3. Executes Instruction

How does this interaction happen?

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Processor-Memory Interaction

Address Address
Bus Send
Bus
Addr.

µP Data Bus
Receive
Data Bus
Memory
Data

Control Send Control

Bus Ctrl. Bus
Send
Read Signal
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Memory

Address
Receive
Bus
Memory
Addr. 8x3
011 0 1 1 0
1 1 0 0
2 0 0 1
3 1 0 1
Send 4 0 1 0
Data Bus
Data 5 0 0 0
6 0 1 0
(Read =1) 1 7 0 1 1
Receive Control
Ctrl. Bus
(Read Signal)
Read
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Memory

Address
Receive
Bus
Memory
Addr.
011 0 1 1 0
1 1 0 0
2 0 0 1
1 1 0 3 1 10 1
0
Receive 4 0 1 0
Data Bus
Data 5 0 0 0
6 0 1 0
(Write =0) 0 7 0 1 1
Receive Control
Ctrl. Bus
(Write Signal)
Write
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Memory

Address
Bus
Memory
8x3
N lines 0 1 1 0
1 1 0 0
2 0 0 1
M lines 3 1 0 1 2N
4 0 1 0
Data Bus
5 0 0 0
6 0 1 0
7 0 1 1
Control M
Bus
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Memory
Speed Cost Size
Register Very Very Smallest
Address High High Bytes
Bus
Memory
8x3
ns
8x3
0 1 1 0 SRAM
1 1 0 0
2 0 0 1
3 1 0 1
4 0 1 0
Data Bus
5 0 0 0 DRAM
6 0 1 0
7 0 1 1
Control Flash
Bus

Magnetic Disk Very

Very Largest
Low
ms Low Terra Bytes
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Memory
Register
Address
Bus
Memory
8x3
Volatile
8x3
0 1 1 0 SRAM Data is lost when
1 1 0 0 powered off
2 0 0 1
3 1 0 1
4 0 1 0
Data Bus
5 0 0 0 DRAM
6 0 1 0
7 0 1 1
Non-Volatile
Control Flash
Bus Data is retained even
when the power is off
Magnetic Disk
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Memory
General
Register Purpose Store Temp. Data
Address Registers
Bus
Memory
8x38x3
0 1 1 0 SRAM Cache Store Recently
1 1 0 0 used Data
2 0 0 1
3 1 0 1
4 0 1 0 Store Current
Data Bus
5 0 0 0 DRAM Primary
6 0 1 0
Memory Application’s Data
7 0 1 1
Control Flash
Bus
Secondary
Store All the Data
Memory
Magnetic Disk
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Memory
General
Register Purpose
GPRs
Address Registers
Bus
Memory
8x38x3
0 1 1 0 SRAM Cache
1
2
1 0 0
0 0 1 µP
3 1 0 1
4 0 1 0
Data Bus
5 0 0 0 DRAM Primary
Primary
Memory
Memory
6 0 1 0
7 0 1 1
Control Flash
Bus
Secondary
Memory
Magnetic Disk
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Processor
What is an Instruction??

1. Fetches Instruction
Control Unit
Memory
DRAM µP 2. Decodes Instruction
ROM
BIOS Datapath
and ALU 3. Executes Instruction
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Processor-Instruction
What is an Instruction??

Control Unit Tell the processor what

Instruction is a action to perform
group of bits
ALU Operation
µP
Read from I/O Device
Datapath or Memory
and ALU
Write to memory
Reset
Stop/Halt
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Processor
Instruction Set Architecture
Execution Model
Processor registers
Address and Data formats

Microarchitecture
Interconnection of elements
µP ALU
Data path
Control Path
Physical Realization
Technology (e.g 10nm, 4nm)
Packaging
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Thank You
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Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 3: Instruction Set Architecture

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Memory
Register
Address
Bus
Memory
8x38x3
0 1 1 0 SRAM
1 1 0 0
2 0 0 1
3 1 0 1
4 0 1 0
Data Bus
5 0 0 0 DRAM
6 0 1 0
7 0 1 1
Control Flash
Bus

Magnetic Disk
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Processor
What is an Instruction??

1. Fetches Instruction
Control Unit
Memory
DRAM µP 2. Decodes Instruction
ROM
BIOS Datapath
and ALU 3. Executes Instruction
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Processor-Instruction
What is an Instruction??

Control Unit Tell the processor what

Instruction is a action to perform
group of bits
ALU Operation
µP
Read from I/O Device
Datapath or Memory
and ALU
Write to memory
Reset
Stop/Halt
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Processor

Instruction Set
Architecture

µP Microarchitecture

Physical Realization
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Instruction Set Architecture

Software

Hardware
ISA

Serves as an interface between software and hardware.

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Instruction Set Architecture

Description of ISA will have the following
What instructions are available?

For example:
C code
C=A+B
8086 ARM

add R1, R2 add R1, R2, R3

R1 + R2  R1 R1 + R2  R3
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Instruction Set Architecture

Description of ISA will have the following
How many and what kind of registers are available?

For example:

8086 ARM

4 general purpose registers 31 general purpose registers

16-bit 32-bit
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Instruction Set Architecture

Description of ISA will have the following
What addressing modes are available?
Method of specifying the operand

For example:

8086 ARM
One of the operands can be memory Operands can only be in registers

add R1, [Address] add R1, R2, R3

And Many more details??

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Processor
Classification of processor based in ISA

CISC Architecture RISC Architecture

Intel 8086, x86 ARM, RISC-V

Register-Memory Architecture Load-Store Architecture

Large number of instructions Fewer fixed length instructions

with varied lengths

Fewer Registers More Registers

Reading Assignment
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Processor
Instruction Set Architecture
Execution Model
Processor registers
Address and Data formats

Microarchitecture
Interconnection of elements
µP ALU (e.g. What type of adder?)
Data path
Control Path
Physical Realization
Technology (e.g 10nm, 4nm)
Packaging
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Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 3: 8086 Microprocessor

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8086 MicroProcessor
BIU (Bus Interface Unit)
8086
Generates memory and I/O addresses
BIU
For transfer of data between processor
Registers and outside world (Memory and I/O)

ALU
EU (Execution Unit)
EU
Control and Receives program instruction codes and
Timing data from BIU
Executes the instructions

Stores the results

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8086 Microprocessor Overview

8086

Address Bus (20 bits)

BIU
Registers I/O
ROM RAM I/O
Ports Devices
ALU
EU Data Bus (16 bits)
Control and Control Bus
Timing
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8086 Buses

8086

BIU Address Bus

AA1919-A
-A160
Registers
A15-A0 Shared lines for
AD15-AD0 Address and Data
ALU
EU D15-D0
Control and ___
RD
___
Timing WR__
M/IO
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8086 Buses

8086

BIU Address Bus

AA1919-A
-A160
Registers
Latch A15-A0
AD15-AD0
ALU
EU Address Latch Enable
Control and ___
D15-D0
RD
___
Timing WR__
M/IO
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Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 4: 8086 Microprocessor Architecture

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Processor

Instruction Set
Architecture

µP Microarchitecture

Physical Realization
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Instruction Set Architecture

Description of ISA will have the following
What instructions are available?
For example:
C code
C=A+B
8086 ARM

add R1, R2 add R1, R2, R3

R1 + R2  R1 R3 + R2  R1

How many and what kind of registers are available?

What addressing modes are available?

Method of specifying the operand
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Processor
Instruction Set Architecture
Execution Model
Processor registers
Address and Data formats

Microarchitecture
Interconnection of elements
µP ALU (e.g. What type of adder?)
Data path
Control Path
Physical Realization
Technology (e.g 10nm, 4nm)
Packaging
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8086 Microprocessor Overview

8086

Address Bus (20 bits)

BIU
Registers I/O
ROM RAM I/O
Ports Devices
ALU
EU Data Bus (16 bits)
Control and Control Bus
Timing
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8086 Buses

8086

BIU Address Bus

AA1919-A
-A160
Registers
Latch A15-A0
AD15-AD0
ALU
EU Address Latch Enable (ALE)
Control and ___
D15-D0
RD
___
Timing WR__
___M/IO
BHE
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8086 Internal Block Diagram

15 87 0
AX AH AX AL Accumulator
General Purpose
BX BH BX BL Base Index
registers
CX CH CX CL Counter
DX DH DX DL Data
SP Stack pointer
BP Base pointer
SI Source Index
DI Destination Index
EU ALU Data Bus
(16bits)

ALU
EU
Control
Flag register
Eg: Carry, Overflow
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8086 Internal Block Diagram

15 87 0
AX AH AX AL Accumulator Set/Reset by programmer
BX BH BX BL Base Index Control Flags
CX CH CX CL Counter IF: Interrupt enable flag
DX DH DX DL Data
DF: Direction Flag
SP Stack pointer TF: Trap Flag
BP Base pointer
15 0
SI Source Index
DI Destination Index - - - - OF DF IF TF SF ZF AF PF - CF

EU ALU Data Bus

Status Flags
(16bits)
CF: Carry Flag
PF: Parity Flag
ALU AF: Auxiliary Carry Flag
ZF: Zero Flag Set/Reset by
EU processor
SF: Sign Flag
Control
Flag register OF: Overflow Flag
Eg: Carry, Overflow
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8086 Internal Block Diagram

Address bus 20 bits
15 87 0
AX Address Bus
AH AX AL
General Purpose (20 bits)
BX BH BX BL
CX CH CX CL
registers BIU ෍
Data Bus
DX DH DX DL (16 bits)
SP Code Segment Reg CS
BP Data Segment Reg DS
SI Stack Segment Reg SS
DI Extra Segment Reg ES
EU ALU Data Bus Instruction
IP
(16bits) Pointer Reg

Bus
ALU Instruction Queue
Control
EU
Control
Flag register 6 Instructions
Eg: Carry, Overflow
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8086 Internal Block Diagram

Address bus 20 bits
20-bit
15 87 0
AX Address Bus
AH AX AL
General Purpose (20 bits)
BX BH BX BL
CX CH CX CL
registers BIU ෍
Data Bus
DX DH DX DL (16 bits)
SP CS
BP 16-bit DS
SI SS
DI ES
EU 16-bit
ALU Data Bus
IP
(16bits)

Bus
ALU Instruction Queue
Control
EU
Control
Flag register 6 Instructions
Eg: Carry, Overflow
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8086 Internal Block Diagram

20-bit
Address Bus
How do you generate 20 bit (20 bits)
address from 16-bit registers?? ෍
Data Bus
(16 bits)
For Example:
CS
16-bit
CS = 2000H and IP = 3000H

2000H : 3000H Logical Representation IP

Segment Base Address
Physical Address Calculation Starting Address
20000H of the Segment
2000H * 16 + 3000H 3000H Offset
23000H
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Concept of Segmentation
Memory
00000
8086 can address a memory of 1MB

8086 communicates with memory

using the Concept of Segmentation
220
What is segmentation?

8086 considers memory to be divided FFFFF

into segments 8 bits
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Thank You
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Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 5: 8086 Microprocessor Architecture

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8086 Internal Block Diagram

15 87 0
AX AH AX AL Accumulator Set/Reset by programmer
BX BH BX BL Base Index Control Flags
CX CH CX CL Counter IF: Interrupt enable flag
DX DH DX DL Data
DF: Direction Flag
SP Stack pointer TF: Trap Flag
BP Base pointer
15 0
SI Source Index
DI Destination Index - - - - OF DF IF TF SF ZF AF PF - CF

EU ALU Data Bus

Status Flags
(16bits)
CF: Carry Flag
PF: Parity Flag
ALU AF: Auxiliary Carry Flag
ZF: Zero Flag Set/Reset by
EU processor
SF: Sign Flag
Control
Flag register OF: Overflow Flag
Eg: Carry, Overflow
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8086 Internal Block Diagram

15 87 0
AX Address Bus
AH AX AL
General Purpose (20 bits)
BX BH BX BL
CX CH CX CL
registers BIU ෍
Data Bus
DX DH DX DL (16 bits)
SP Code Segment Reg CS
BP Data Segment Reg DS
SI Stack Segment Reg SS
DI Extra Segment Reg ES
EU ALU Data Bus Instruction
IP
(16bits) Pointer Reg

Bus
ALU Instruction Queue
Control
EU
Control
Flag register 6 Instructions
Eg: Carry, Overflow
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8086 Internal Block Diagram

20-bit
15 87 0
AX Address Bus
AH AX AL
General Purpose (20 bits)
BX BH BX BL
CX CH CX CL
registers BIU ෍
Data Bus
DX DH DX DL (16 bits)
SP CS
BP 16-bit DS
SI SS
DI ES
EU 16-bit
ALU Data Bus
IP
(16bits)

Bus
ALU Instruction Queue
Control
EU
Control
Flag register 6 Instructions
Eg: Carry, Overflow
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8086 Internal Block Diagram

20-bit
Address Bus
Instruction
How do you generate 20 bit address from (20 bits)
Address
16-bit registers?? ෍
Data Bus
(16 bits)
Physical Address computation unit
CS
Value in Code Value in Instruction
Segment Register
* 16 +
Pointer Register
10H
Offset Address IP

Segment base Address

For example if CS = 2000H and IP = 3000H

Logical address = 2000:3000 20000H
3000H
Physical Address = 2000H * 10H + 3000H
23000H
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Concept of Segmentation
Memory
00000
8086 can address a memory of 1MB

8086 communicates with memory

using the Concept of Segmentation
220
What is segmentation?

8086 considers memory to be divided

into segments
FFFFF
8 bits
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Concept of Segmentation
Memory
The code segment is the area of the 00000
memory where code is stored
Code Segment

Any location within code segment can be

accessed using Code Segment and
Instruction Pointer Registers

FFFFF
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Concept of Segmentation
Memory
00000
Starting Address of Code
(CS) * 10H Segment
+ 0000H
64KB
Code Segment
Ending Address of Code
(CS) * 10H Segment
+ FFFFH

Segment base
Address
Multiply
CS
Value in CS
by 10H +
Register Offset
IP Address

Value in Code 0000H

Segment Register * 10H +
FFFFH FFFFF
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Concept of Segmentation
Memory
The Data segment is the area of the 00000
memory where data required for
executing the instructions is stored

Data Segment
e.g. Operands for Arithmetic and Logical
operations

Any location within data segment can be

accessed using Data Segment and Index
Registers (BX/SI/DI)
FFFFF
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Concept of Segmentation
Memory
00000

Multiply
DS
Value in DS
by 10H + Data Segment

Register BX
Depends on SI
Instruction
DI
Offset Address

FFFFF
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Concept of Segmentation
Memory
The Stack segment is the area of the 00000
memory used for storing address and data
temporarily.

Stack is mostly used during function calls

Stack Segment
Any location within Stack segment can be
accessed using Stack Segment and Stack
Pointer/Base Pointer Registers

FFFFF
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Concept of Segmentation
Memory
00000

Multiply
SS
Value in SS
by 10H + Stack Segment

Register BP
SP

FFFFF
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Concept of Segmentation
Memory
The Extra segment is the area of the 00000
memory where data required for
executing the string instructions is stored

Multiply
ES
Value in ES
by 10H +
Register DI

Extra Segment

FFFFF
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Concept of Segmentation
Default 16-bit segment and offset combinations

CS IP Instruction Address

DS BX Data Address
DI
SI

SS SP Stack Address
BP

ES DI String Dest. Address

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Concept of Segmentation
Memory Memory
Non
Code Segment
overlapping
segments Code Segment
Data Segment

Data Segment
Stack Segment

When all segment

Extra Segment
registers have the Stack Segment
same value
Overlapping
Segments Extra Segment

Can all Segments fully overlap?

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Practice Problem
Memory
Calculate the address range for Code, 00000
Data, Stack and Extra Segment, given Code Segment
0FFFF
CS register has 0000H 10000
Data Segment
DS register has 1000H
1FFFF
SS register has 2400H
24000 Stack Segment
ES register has 3100H 31000
33FFF
Extra Segment
40FFF

FFFFF
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Practice Problem
Calculate the Physical address for the following logical
addresses

0000:0100

0001:00F0

0010:0000
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Memory Organization
Memory
00000
00001
?????
2 bytes
1byte

D15-D0

µP 220

FFFFF
8 bits
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 6: 8086 Microprocessor Architecture

 CKV

Concept of Segmentation
Memory
Default 16-bit segment and offset combinations

CS IP Instruction Address Code Segment

DS BX Data Address
DI Data Segment
SI

Stack Segment
SS SP Stack Address
BP
Extra Segment
ES DI String Dest. Address
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Memory Organization
Memory
00000
00001
1byte
Latch A19-A0 50000
12 50000
2 bytes D15-D8 34 50001
56 50003
µP D15-D0 D7-D0 78 50004

MSB at Lower Address

LSB at Higher Address
This type of ordering in memory is called

Big-Endian
8 bits
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Memory Organization
Memory
Accessing Memory twice – Not optimal 00000
00001
1byte
Latch A19-A0 50000
12 50000
2 bytes D15-D8 34 50001
56 50002
µP D15-D0 D7-D0 78 50003

MSB at Higher Address

LSB at Lower Address
This type of ordering in memory is called
8086 Uses Little-Endian
8 bits
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Memory Organization
Memory Even Bank Odd Bank
50000 12
50001 34
50002 56
50003 78

512KB 512KB

1MB

8 bits
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Memory Organization
Aligned
Read Even Bank Odd Bank
word

A19-A0 50000 50000 12 50001 34

50002 56 50003 78
2 bytes D15-D8

µ D15-D0 D7-D0
A0 used to
enable Even
BHE used to
enable Odd
Bank Bank
P ALE
___
A0=0 BHE=0
RD
___
WR__ Even Bank Odd Bank
M/IO Enabled Enabled
___
BHE Both Banks enabled at once

When processor requests access for a word

(16-bit) data at an even address
1 Memory Bus Cycle
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Memory Organization
Write Even Bank Odd Bank

A19-A0 50000 50000 12 50001 34

50002 56 50003 78
2 bytes D15-D8

µ D15-D0
90
D7-D0
A0=0
Even Bank
BHE=0
Odd Bank
P ALE
___
2F Enabled Enabled

RD
___
WR__
M/IO
___
BHE Both Banks enabled at once

When processor wants to write a word (16-

bit) data at an even address
1 Memory Bus Cycle
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Memory Organization
Read Even Bank Odd Bank

A19-A0 50000 50000 12 50001 34

50002 56 50003 78
D15-D8

µ D15-D0 D7-D0
A0 = 0 BHE =1
P ALE
___ Even Bank Odd Bank
RD
___ Enabled Disabled
WR
M/IO
___
BHE Even bank enabled

When processor requests access for a byte (8-bit)

data at an even address
1 Memory Bus Cycle
 CKV

Memory Organization
Write Even Bank Odd Bank

A19-A0 50000 50000 12 50001 34

50002 56 50003 78
D15-D8

µ D15-D0 D7-D0
A0 = 0 BHE =1
P ALE
___
2F
Even Bank Odd Bank
RD
___ Enabled Disabled
WR
M/IO
___
BHE Even bank enabled

When processor wants to write a byte (8-bit)

data at an even address
1 Memory Bus Cycle
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Memory Organization
Read Even Bank Odd Bank

A19-A0 50003 50000 12 50001 34

50002 56 50003 78
D15-D8

µ D15-D0 D7-D0
A0 =1 BHE = 0
P ALE
___ Even Bank Odd Bank
RD
___ Disabled Enabled
WR
M/IO
___
BHE Odd bank enabled

When processor requests access for a byte (8-bit)

data at an odd address
1 Memory Bus Cycle
Similarly for Write
 CKV

Memory Organization
Misaligned
Read Even Bank Odd Bank
word

A19-A0 50001 50000 12 50001 34

50002 56 50003 78
2 bytes D15-D8
A0 = 1 BHE = 0
µ D15-D0 D7-D0
Even Bank
Disabled
Odd Bank
Enabled
P ALE
___
A0 = 0
Even Bank
BHE = 1
Odd Bank
RD
___
WR Enabled Disabled
M/IO
___
BHE Odd enabled first Even Bank enabled Next

When processor requests access for a word

(16-bit) data at an odd address
2 Memory Bus Cycles
Similarly for Write
 CKV

Memory Organization

𝐁𝐇𝐄 𝐀𝟎 Selection
0 0 Word (16-bits)
0 1 8-bits from Odd Bank
1 0 8-bits from Even Bank
1 1 No Selection
 CKV

Next Class

8086 Microprocessor Instruction Set and Addressing Modes

 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 7: 8086 Microprocessor Instruction Set and

Addressing Modes
 CKV

Memory Organization

Big-Endian 8086 Uses Little-Endian

 CKV

Memory Organization

8086 Uses Little-Endian

Read/Write 16-bit value @ Even Address
Even Bank Odd Bank

A19-A0 50000 50000 12 50001 34

50002 56 50003 78

D15-D8

D7-D0

Read/Write 8-bit value @ Even Address

Read/Write 8-bit value @ Odd Address
Read/Write 16-bit value @ Odd Address
 CKV

Types of Instructions

Data Transfer Instructions

Arithmetic and Logical Instructions

Arithmetic Instructions

Logical Instructions

Branch and Program Control Instructions

 CKV

Data Transfer Instructions

MOV [Destination], [Source]

Operation
Source: Register, Memory, Immediate value

Destination: Register, Memory

Size

Flags
 CKV

Addressing Modes

When processor executes an instruction

It performs the specified function on Data
These data also called Operands

May be part May reside in internal May reside in

of instruction registers of the memory
processor
 CKV

Register Addressing
During
Before Exec.
After Exec.
MOV AH, BL
AH 12 56 AL
BH 89 32 BL

MOV BX, CX During

Before Exec.
After Exec.
BX 1256
CX 8932
 CKV

Immediate Addressing
After
BeforeExec.
Exec.
MOV AL, 30h
56
30 AL

After
BeforeExec.
Exec.
MOV BX, 1390h
1956
1390 BX
 CKV

Direct Addressing

MOV AL, [3000h]

After
BeforeExec.
Exec.
Even Bank DS:3000 12
XX
12 AL Odd Bank DS:3001 34
Even Bank DS:3002 56
Odd Bank DS:3003 78
 CKV

Direct Addressing

MOV BX, [3000h]

After
BeforeExec.
Exec.
DS:3000 12
3412 BX
XXXX DS:3001 34
DS:3003 56
DS:3004 78
 CKV

Direct Addressing

MOV [3000h], AL
After
BeforeExec.
Exec.
DS:3000 7F
12
7F AL DS:3001 34
DS:3002 56
DS:3003 78
 CKV

Direct Addressing

MOV [3002h], BX
After
BeforeExec.
Exec.
DS:3000 7F
FFAD BX DS:3001 34
DS:3002 AD
56
DS:3003 FF
78
 CKV

Register Indirect Addressing

MOV AL, [BX]

MOV BX, [SI]

 CKV

Register Indirect Addressing

MOV [BX], AL

MOV [SI], BX
 CKV

Base-Plus-index Addressing

MOV AL, [BX+SI] Effective address is formed as the

sum of a base register (BP or BX) and
an index register (DI or SI)

MOV CX, [BP+SI]

 CKV

Register-Relative Addressing

MOV AL, [BX+40]

MOV CX, [BX+40]

 CKV

Base Relative-plus-indexed Addressing

MOV AL, [BX+SI+40]

MOV AX, [BX+SI+40]

 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 8: 8086 Microprocessor Instruction Code format

 CKV

Addressing Modes
Register Addressing

Immediate Addressing

Direct Addressing

Register Indirect Addressing

Base-Plus-Index Addressing

Register Relative Addressing

Base relative-plus-indexed Addressing

 CKV

Addressing Modes
Register Addressing Instruction Code
format

Direct Addressing

Register Indirect Addressing

Base-Plus-Index Addressing

Register Relative Addressing

Base relative-plus-indexed Addressing

 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP HIGH DISP
OPCODE D W MOD REG R/M

OR

Direct Address Direct Address

Low Byte High Byte
 CKV

Instruction Code Format

BYTE 1
1 0 0 0 1 0

OPCODE D W

Operation Code
Specifies data width
e.g. 100010 is
W=0 (Data-byte)
opcode for MOV
instruction W=1 (Data-word)

Specifies direction to or from register (REG field)

D=0 (Direction from Register i.e. Register is Source)
D=1 (Direction to Register i.e. Register is Destination)
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

REG W=0 (8-bit) W=1 (16-bit)

000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
Direct Addressing 110 d16 [BP+d8] [BP+d16] DH SI
Mode
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
Register Indirect 101 [DI] [DI+d8] [DI+d16] CH BP
Addressing mode 110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
Base plus index 001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
Addressing Mode
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
Register-relative 101 [DI] [DI+d8] [DI+d16] CH BP
addressing mode 110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
Base Relative plus
index addressing 010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
mode 011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP HIGH DISP
OPCODE D W MOD REG R/M

OR

Direct Address Direct Address

Low Byte High Byte

d8
d16
 CKV

Exercise Problems
Find the instruction codes for the following cases

MOV AX, BX

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP HIGH DISP
OPCODE D W MOD REG R/M

OR

Direct Address Direct Address

Low Byte High Byte
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV AX, BX
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1

OPCODE D W MOD REG R/M

AX BX
8B C3
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV BX, [2067h]
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0
Direct Address Direct Address
OPCODE D W MOD REG R/M Low Byte High Byte

BX [d16]
8B 1E 67 20
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV [BX+SI], AX
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0

OPCODE D W MOD REG R/M

AX [BX+SI]
89 00
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV DL, [BX+DI+95h]
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1

OPCODE D W MOD REG R/M LOW DISP

DL [BX+DI+d8]
8A 51 95
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV [BP+6745h],CX
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0

OPCODE D W MOD REG R/M LOW DISP HIGH DISP

CX [BP+d16]
89 8E 45 67
 CKV

Thank You
 CKV

Instruction Code Format: REG

REG W=0 (8-bit) W=1 (16-bit)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
Go Back
100 AH SP
MOV AX, BX 101 CH BP
110 DH SI
MOV BX, [2067h] 111 BH DI

MOV [BX+SI], AX

MOV DL, [BX+DI+95h]

MOV [BP+6745h],CX
 CKV

Instruction Code Format: MOV

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
Go Back 011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
MOV AX, BX
101 [DI] [DI+d8] [DI+d16] CH BP
110 d16 [BP+d8] [BP+d16] DH SI
MOV BX, [2067h]
111 [BX] [BX+d8] [BX+d16] BH DI
MOV [BX+SI], AX

MOV DL, [BX+DI+95h]

MOV [BP+6745h],CX
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 9: Instruction Codes, 8086 Instructions and Assembly

Programming
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP OR HIGH DISP
OPCODE D W MOD REG R/M
Direct Address Direct Address
Low Byte High Byte
REG W=0 (8-bit) W=1 (16-bit)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
Direct Address Direct Address
Low Byte High Byte
OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
Direct Addressing 110 d16 [BP+d8] [BP+d16] DH SI
Mode
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
Register Indirect 101 [DI] [DI+d8] [DI+d16] CH BP
Addressing mode 110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
Base plus index 001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
Addressing Mode
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP HIGH DISP
OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
Register-relative 101 [DI] [DI+d8] [DI+d16] CH BP
addressing mode 110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Instruction Code Format: MOV

BYTE 1 BYTE 2 BYTE 3 BYTE 4

1 0 0 0 1 0
LOW DISP HIGH DISP
OPCODE D W MOD REG R/M

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
Base Relative plus
index addressing 010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
mode 011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP
110 d16 [BP+d8] [BP+d16] DH SI
111 [BX] [BX+d8] [BX+d16] BH DI
 CKV

Exercise Problems
Find the instruction codes for the following cases

MOV AX, BX

BYTE 1 BYTE 2
1 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1

OPCODE D W MOD REG R/M

AX BX
8B C3
 CKV

Exercise Problems
Find the instruction codes for the following cases

MOV BX, [2067h]

BYTE 1 BYTE 2
1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0
Direct Address Direct Address
OPCODE D W MOD REG R/M Low Byte High Byte

BX [d16]
8B 1E 67 20
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV [BX+SI], AX
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M

1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0

89 00
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV DL, [BX+DI+95h]
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M LOW DISP

1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1

8A 51 95
 CKV

Exercise Problems
Find the instruction codes for the following cases
MOD-R/M Table
MOV [BP+6745h],CX
REG Table

BYTE 1 BYTE 2
1 0 0 0 1 0

OPCODE D W MOD REG R/M LOW DISP HIGH DISP

1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0

89 8E 45 67
 CKV

Instruction Code Format: MOV

MOV BX, 1459h
Used only if W=1
Immediate Addressing
REG Table
BYTE 1 BYTE 2 BYTE 3
1 0 1 1
Lower Byte Higher Byte
OPCODE W REG

1 0 1 1 1 0 1 1

BB 59 14
 CKV

Example Assembly Program

Write 8086 Assembly Language Program (ALP) to swap a word at
memory location 64000h with 65000h
Program Data Segment
MOV AX, 6000h
MOV DS, AX
64000h
MOV BX, [4000h] 64001h
MOV DX, [5000h]
MOV [5000h], BX
MOV [4000h], DX
BX DX

65000h
65001h
 CKV

Example Assembly Program

Write 8086 Assembly Language Program (ALP) to swap a word at
memory location 64000h with 65000h
Program Data Segment
MOV AX, 6000h
MOV DS, AX
MOV SI, 4000h SI 64000h
MOV DI, 5000h 64001h
MOV BX, [SI]
MOV DX, [DI]
MOV [DI], BX BX DX
MOV [SI], DX

DI 65000h
65001h
 CKV

Data Transfer Instructions

XCHG operand1, operand2

Exchanges the contents

Both operands can be registers

One of the operand can be a register and the other can

be a memory

Both operands cannot be Memory

 CKV

Example Assembly Program

Write 8086 Assembly Language Program (ALP) to swap a word at
memory location 64000h with 65000h
Program
Data Segment
MOV AX, 6000h
MOV DS, AX
MOV SI, 4000h 64000h
MOV DI, 5000h 64001h
MOV BX, [SI]
XCHG BX, [DI]
MOV [SI], BX BX

65000h
65001h
 CKV

Data Transfer Instructions

LEA – Load effective Address (during lab)

PUSH, POP – data transfer to/from stack

LAHF, SAHF – data transfer to/from Flag register from/to AH

 CKV

Data Transfer Instructions

PUSHF, POPF – data transfer to/from stack from/to Flag
register

XLAT – Translate (equivalent to DA:(BX+AL)AL)

 CKV

Thank You
 CKV

Instruction Code Format: REG

REG W=0 (8-bit) W=1 (16-bit)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
Go Back 111 BH DI

MOV [BX+SI], AX

MOV DL, [BX+DI+95h]

MOV [BP+6745h],CX
MOV BX,1459h
 CKV

Instruction Code Format: MOV

MOD 00 01 10 11 (R)
(M) (M) (M) W=0 W=1
R/M
000 [BX+SI] [BX+SI+d8] [BX+SI+d16] AL AX
001 [BX+DI] [BX+DI+d8] [BX+DI+d16] CL CX
010 [BP+SI] [BP+SI+d8] [BP+SI+d16] DL DX
011 [BP+DI] [BP+DI+d8] [BP+DI+d16] BL BX
100 [SI] [SI+d8] [SI+d16] AH SP
101 [DI] [DI+d8] [DI+d16] CH BP

Go Back 110 d16 [BP+d8] [BP+d16] DH SI

111 [BX] [BX+d8] [BX+d16] BH DI
MOV [BX+SI], AX

MOV DL, [BX+DI+95h]

MOV [BP+6745h],CX
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 10: 8086 Instructions and Assembly Programming

 CKV

Data Transfer Instructions

MOV – Move data from source to destination

XCHG – Exchange contents

 CKV

Data Transfer Instructions

LEA – Load effective Address (during lab)

PUSH, POP – data transfer to/from stack (Stack)

IN, OUT – data transfer to/from IO Ports (I/O Interfacing)

 CKV

Data Transfer Instructions

LAHF, SAHF – data transfer to/from Flag register from/to AH

PUSHF, POPF – data transfer to/from stack from/to Flag

register

XLAT – Translate (equivalent to DS:(BX+AL)AL)

 CKV

Arithmetic Instructions

ADD (Destination), (Source)

Operation: (Destination) (Destination)+(Source)
Source: Register, Memory, Immediate value
Destination: Register, Memory
Size
Flags
Similar addressing modes as MOV
 CKV

Arithmetic Instructions
SUB – Subtract

SUB Destination, Source

Destination  Destination – Source

Borrow based subtraction

 CKV

Instruction Code Format: ADD

BYTE 1 BYTE 2 BYTE 3 BYTE 4

0 0 0 0 0 0
LOW DISP OR HIGH DISP
OPCODE D W MOD REG R/M
Direct Address Direct Address
Low Byte High Byte
 CKV

Arithmetic Instructions

MUL– Unsigned Multiplication instruction (Exp 2)

DIV – Unsigned Division Instruction (Exp 2)

IMUL– Signed Multiplication instruction

IDIV – Signed Division Instruction

 CKV

Arithmetic Instructions

INC – Increment operation

Register
INC Operand
Memory

Flags: AF, OF, PF, SF, ZF affected, CF not affected

INC BL ; 8-bit

INC BX ; 16-bit
 CKV

Arithmetic Instructions

INC [2000h]

Increment Byte or Word? DS:2000h FF

00
DS:2001h 06
05

FFh + 1 OR 05FFh+1

INC BYTE PTR [2000h] INC WORD PTR [2000h]

Memory location can be specified in 24 ways

 CKV

Arithmetic Instructions

DEC – Decrement operation

Register
DEC Operand
Memory

Flags: AF, OF, PF, SF, ZF affected, CF not affected

DEC BL ; 8-bit

DEC BX ; 16-bit
 CKV

Arithmetic Instructions

ADC – Add with carry

ADC Destination, Source

Destination  Destination + Source + CF (Carry Flag)

Used for multi-byte/word addition

 CKV

Arithmetic Instructions
Can you add two 32-bit numbers in 8086?
1
126AB9B0h B9B0 AX
26797B31h 7B31 BX

MOV AX, B9B0h 1 34E1 AX

MOV BX, 7B31h CF
ADD AX, BX
 CKV

Arithmetic Instructions
Can you add two 32-bit numbers in 8086?
11 1
126AB9B0h 126A DX B9B0 AX
26797B31h 2679 CX 7B31 BX

MOV AX, B9B0h 0 38E4 DX 1 34E1 AX

MOV BX, 7B31h CF
ADD AX, BX
MOV DX, 126Ah 38E4 DX 34E1 AX
MOV CX, 2679h
ADC DX, CX
 CKV

Arithmetic Instructions
SBB – Subtract with Borrow

SBB Destination, Source

Destination  Destination – Source – CF (Carry Flag)

 CKV

ALP Example
Write an ALP to copy a block of data (e.g. 20 bytes) from one
memory area to another memory area i.e. from 32000H to
34000H Data Segment
MOV AX, 3000h
MOV DS, AX 32000h
MOV AL, [2000h] 32001h
MOV [4000h], AL
MOV AL, [2001h]
MOV [4001h], AL
AL

34000h
34001h
Will you do it for 20 times??
 CKV

ALP Example
Write an ALP to copy a block of data (e.g. 20 bytes) from one
memory area to another memory area i.e. from 32000H to
34000H Data Segment

MOV AX, 3000h

MOV DS, AX SI 32000h
MOV SI, 2000h 32001h
MOV DI, 4000h
MOV AL, [SI]
MOV [DI], AL Repeating AL
INC SI Sequence
INC DI
MOV AL, [SI] DI 34000h
MOV [DI], AL 34001h
INC SI
INC DI
 CKV

ALP Example
Write an ALP to copy a block of data (e.g. 20 bytes) from one
memory area to another memory area i.e. from 32000H to
34000H Data Segment
MOV CX, 0014h
MOV AX, 3000h
MOV DS, AX 32000h
MOV SI, 2000h SI 32001h
MOV DI, 4000h
AGAIN: MOV AL, [SI]
MOV [DI], AL Repeats but
how many AL
INC SI
INC DI times??
LOOP AGAIN
34000h
As specified DI 34001h
in CX Register
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 11: 8086 Instructions and Assembly Programming

 CKV

Arithmetic Instructions

ADD INC ADC MUL IMUL

SUB DEC SBB DIV IDIV

 CKV

ALP Example
Write an ALP to copy a block of data (e.g. 20 bytes) from one
memory area to another memory area i.e. from 32000H to
34000H Data Segment
MOV CX, 0014h
MOV AX, 3000h
MOV DS, AX SI 32000h
MOV SI, 2000h 32001h
MOV DI, 4000h
AGAIN: MOV AL, [SI]
MOV [DI], AL AL
INC SI
INC DI
LOOP AGAIN DI 34000h
34001h
 CKV

Logical Instructions
AND Destination, Source Bitwise Operations
Flags
CF and OF become zero
OR Destination, Source
PF, SF and ZF get effected
as per the result

XOR Destination, Source AF Undefined

e.g.: AL= 6Eh and BL=83h 0 1 1 0 1 1 1 0 AL

AND AL, BL
1 0 0 0 0 0 1 1 BL
OR AL, BL
XOR AL, BL 0 0 0 0 0 0 1 0 AL
 CKV

Logical Instructions
AND Destination, Source Bitwise Operations
Flags
CF and OF become zero
OR Destination, Source
PF, SF and ZF get effected
as per the result

XOR Destination, Source AF Undefined

e.g.: AL= 6Eh and BL=83h 0 1 1 0 1 1 1 0 AL

AND AL, BL
1 0 0 0 0 0 1 1 BL
OR AL, BL
XOR AL, BL 1 1 1 0 1 1 1 1 AL
 CKV

Logical Instructions
AND Destination, Source Bitwise Operations
Flags
CF and OF become zero
OR Destination, Source
PF, SF and ZF get effected
as per the result

XOR Destination, Source AF Undefined

e.g.: AL= 6Eh and BL=83h 0 1 1 0 1 1 1 0 AL

AND AL, BL
1 0 0 0 0 0 1 1 BL
OR AL, BL
XOR AL, BL 1 1 1 0 1 1 0 1 AL
 CKV

Logical Instructions

CMP Operand 1, Operand 2

CMP AX, BX

Subtracts BX from AX (i.e. AX – BX) and updates the flags

Flags: CF, AF, OF, PF, SF, ZF affected

The contents of AX and BX remain unchanged

 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
ROL Destination, Count ROL BL, 4 ROL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
0 0 1 1 0 0 1 0 1
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
ROL Destination, Count ROL BL, 4 ROL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
0 1 1 0 0 1 0 1 0
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
ROL Destination, Count ROL BL, 4 ROL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
1 1 0 0 1 0 1 0 1
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
ROL Destination, Count ROL BL, 4 ROL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
1 0 0 1 0 1 0 1 1
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
ROL Destination, Count ROL BL, 4 ROL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
0 0 1 0 1 0 1 1 0 After Execution

ROL – ROtate Left

 CKV

Logical Instructions

Rotate Operations

ROR Destination, Count

8-bit/16-bit Immediate
register or value or CL
Memory
Rotate Right Register/Memory CF

ROR – ROtate Right

 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
RCL Destination, Count RCL BL, 4 RCL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
0 0 1 1 0 0 1 0 1
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
RCL Destination, Count RCL BL, 4 RCL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
0 1 1 0 0 1 0 1 0
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
RCL Destination, Count RCL BL, 4 RCL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
1 1 0 0 1 0 1 0 0
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
RCL Destination, Count RCL BL, 4 RCL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
1 0 0 1 0 1 0 0 1
 CKV

Logical Instructions

Rotate Operations
MOV CL, 04h
RCL Destination, Count RCL BL, 4 RCL BL, CL

8-bit/16-bit Immediate CF BL
register or value or CL 0 01100101
Memory Before Execution
Rotate left CF BL
1 0 1 0 1 0 0 1 1 After Execution

RCL – Rotate through Carry Left

 CKV

Logical Instructions

Rotate Operations

RCR Destination, Count

8-bit/16-bit Immediate
register or value or CL
Memory
Rotate Right Register/Memory CF

RCR – Rotate through Carry Right

 CKV

Logical Instructions

Shift Operations

SAL-Shift Left Arithmetic/SHL-Shift Left Logical

SAL Destination , Count / SHL Destination, Count

SAL BL, 2 / SHL BL, 2 (or Count in CL)

BL CF BL
0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 01
Before Execution
 CKV

Logical Instructions

Shift Operations

SAL-Shift Left Arithmetic/SHL-Shift Left Logical

SAL Destination , Count / SHL Destination Count

SAL BL, 2 / SHL BL, 2 (or Count in CL)

BL CF BL
0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0
Before Execution After Execution
 CKV

Logical Instructions

Shift Operations

SAR-Shift Right Arithmetic

SAR Destination , Count

SAR BL, 2 (or count in CL)

BL BL CF
1 0 0 0 1 1 0 1 1 10 0 0 1 1 0 1
Before Execution
 CKV

Logical Instructions

Shift Operations

SAR-Shift Right Arithmetic

SAR Destination , Count

SAR BL, 2 (or count in CL)

BL BL CF
1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1
Before Execution After Execution
 CKV

Logical Instructions

Shift Operations

SHR-Shift Right Logical

SHR Destination , Count

SHR BL, 2 (or count in CL)

BL BL CF
1 0 0 0 1 1 0 1 10 0 0 0 1 1 0 1
Before Execution
 CKV

Logical Instructions

Shift Operations

SHR-Shift Right Logical

SHR Destination , Count

SHR BL, 2 (or count in CL)

BL BL CF
1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1
Before Execution After Execution
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 12: 8086 Instructions and Assembly Programming

 CKV

Logical Instructions
AND CMP ROL SAL/SHL
If Dst > Src
OR CF=0 and ZF=0
ROR SAR
If Dst < Src
XOR CF=1 and ZF=0
RCL SHR
If Dst = Src
CF=0 and ZF=1 RCR
TEST (bitwise AND, affects flags but does not change destination)

NOT (invert bits, e.g. NOT AL, NOT AX, NOT BYTE PTR [BX] etc)

NEG (2’s complement, e.g. NEG AL, NEG AX, NEG WORD PTR [BX] etc)
 CKV

Branch Instructions

JMP (jump to the specified instruction location)

THERE: MOV AL, 03 Unconditional Jump
ADD BL, AL
Backward
……
… Near or Short Jump
JMP THERE - Intra-segment jump
Forward …
…
THERE: ADD CL, AL Far Jump
- inter-segment jump
 CKV

Branch Instructions

SHORT JUMP (jump with 8-bit displacement)

Addr. Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 EB 08 JMP SHORT THERE JMP 000E
CS:IP 1000:0006 …….
+8 How far? …….
1000:000E B2 02 THERE: MOV DL, 02
1000:0010 B5 02 MOV CH, 02
1000:0012 EB XX EC JMP SHORT BEGIN
1000:0014
-14h
New IP = Current IP + 8-bit Displacement

The jump destination can be -128 to +127 away from current IP

 CKV

Branch Instructions
If the jump destination is beyond -128 to +127

NEAR JUMP (jump with 16-bit displacement)

Addr. Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 E9 07 01 JMP NEAR THERE JMP 010E
CS:IP 1000:0007 …….
+107H How far? …….
1000:010E B2 02 THERE: MOV DL, 02
1000:0110 B5 02 MOV CH, 02
New IP = Current IP + 16-bit Displacement

The jump destination can be -32768 to +32767 away from current IP

 CKV

Branch Instructions

SHORT JUMP (jump with 8-bit displacement)

NEAR JUMP (jump with 16-bit displacement)

“Relative” intra-segment jump instructions

Jump with in the same segment relative to IP

Direct Addressing Mode – Destination address can be

calculated from the instruction code
 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP reg16 (e.g. JMP BX)

BX 3412
CS: IP Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 FF E3 JMP BX
CS:IP 1000:0006
…..
…
1000:3412 New IP = BX
 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP [reg16] (e.g. JMP [BX])
DS:3412h FF
BX 3412
05
DS:3413h
CS: IP Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 FF 27 JMP [BX]
CS:IP 1000:0006
…..
…
New IP = Contents of memory location whose offset
1000:05FF address is stored in the register
 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP reg16 (e.g. JMP BX)

JMP [reg16] (e.g. JMP [BX])

Indirect Addressing Mode – Destination address is either

in register or memory

Destination address is not relative to the IP

 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 13: 8086 Instructions and Assembly Programming

 CKV

Branch Instructions

JMP (jump to the specified instruction location)

THERE: MOV AL, 03 Unconditional Jump
ADD BL, AL
Backward
……
… Near or Short Jump
JMP THERE - Intra-segment jump
Forward …
…
THERE: ADD CL, AL Far Jump
- inter-segment jump
 CKV

Branch Instructions

SHORT JUMP (jump with 8-bit displacement)

Addr. Inst Code
CS:IP 1000:0000 B1 03 BEGIN: MOV CL, 03
CS:IP 1000:0002 8A D1 MOV DL, CL
CS:IP 1000:0004 EB 08 JMP SHORT THERE JMP 000E
CS:IP 1000:0006 …….
+8 How far? …….
CS:IP 1000:000E B2 02 THERE: MOV DL, 02
CS:IP 1000:0010 B5 02 MOV CH, 02
CS:IP 1000:0012 EB XXEC JMP SHORT BEGIN JMP 0000
CS:IP 1000:0014
-14h
New IP = Current IP + 8-bit Displacement

The jump destination can be -128 to +127 away from current IP

 CKV

Branch Instructions
If the jump destination is beyond -128 to +127
NEAR JUMP (jump with 16-bit displacement)
Addr. Inst Code
CS:IP 1000:0000 B1 03 BEGIN: MOV CL, 03
CS:IP 1000:0002 8A D1 MOV DL, CL
CS:IP 1000:0004 E9 07 01 JMP NEAR THERE JMP 010E
CS:IP 1000:0007 …….
+107 How far? …….
CS:IP 1000:010E B2 02 THERE: MOV DL, 02
CS:IP 1000:0110 B5 02 MOV CH, 02
CS:IP 1000:0112
New IP = Current IP + 16-bit Displacement

The jump destination can be -32768 to +32767 away from current IP

 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP reg16 (e.g. JMP BX)

BX 3412
CS: IP Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 FF E3 JMP BX
CS:IP 1000:0006
…..
…
1000:3412 New IP = BX
 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP [reg16] (e.g. JMP WORD PTR[BX])
DS:3412h FF
BX 3412
05
DS:3413h
CS: IP Inst Code
1000:0000 B1 03 BEGIN: MOV CL, 03
1000:0002 8A D1 MOV DL, CL
1000:0004 FF 27 JMP WORD PTR [BX]
CS:IP 1000:0006
…..
…
New IP = Contents of memory location whose offset
1000:05FF address is stored in the register
 CKV

Branch Instructions

Other intra-segment unconditional Jump instructions

JMP reg16 (e.g. JMP BX)

JMP [reg16] (e.g. JMP WORD PTR [BX])

Indirect Addressing Mode – Destination address is either

in register or memory

Destination address is not relative to the IP

 CKV

Branch Instructions

Conditional JUMP Instructions

All conditional Jump instructions are short jump type

Jump to destination only if some condition is met

Conditional instructions check the flags

MOV DL, 04 Flags get affected

MOV AL, 01
BEGIN: ADD AL, 01
DEC DL
Checks Zero Flag
JNZ BEGIN
 CKV

Branch Instructions

Conditional JUMP Instructions

All conditional Jump instructions are short jump type

Jump to destination only if some condition is met

Conditional instructions check the flags

MOV DL, 04 Flags get affected

MOV AL, 01
BEGIN: ADD AL, 01
CMP AL DL
Checks Zero Flag
JNE BEGIN
 CKV

Branch Instructions

Conditional JUMP Instructions

Instruction Normally used after Condition Checked
JA/JNBE CMP CF=0 and ZF=0
JAE/JNB CMP CF=0
JB/JNAE CMP CF=1
JBE/JNA CMP CF=1 or ZF =1
JE/JZ CMP/DEC ZF =1
JNE/JNZ CMP/DEC ZF =0
 CKV

Branch Instructions

Conditional JUMP Instructions

JC CF=1
JNC CF=0
JP/JPE PF=1
JNP/JPO PF=0

JCXZ (Jump if CX=0)

 CKV

Branch Instructions

FAR JUMP
Destination not in current segment

Not enough to change IP.

Both CS and IP needs to be changed

JUMP FAR PTR AGAIN

 CKV

Branch Instructions

FAR JUMP

Addr. Inst Code

CS:IP 1000:0000 B1 03 BEGIN: MOV CL, 03
CS:IP 1000:0002 8A D1 MOV DL, CL
CS:IP 1000:0004 EA 0E 01 00 20 JMP FAR PTR THERE JMP 2000:010E
CS:IP 1000:0009 …….
How far? …….
CS:IP 2000:010E B2 02 THERE: MOV DL, 02
CS:IP 2000:0110
 CKV

Branch Instructions

Other intersegment far Jump instructions

JMP [reg16] (e.g. JMP DWORD PTR[BX])
DS:3412h 00
BX 3412
10
DS:3413h
DS:3414h 10
DS:3415h 70

Jumps to 7010h:1000h
 CKV

Branch Instructions

LOOP Instruction (LOOP <Label>)

Jump to a specified label if CX not equal to Zero after

auto decrement
Short Jump MOV CX, 06h
L1: ……………………
Flags don't get affected CX≠0
……………………
LOOP L1
CX=0
MOV DL, 02
Can LOOP be replaced with
equivalent instruction of
Sequence of instructions??
 CKV

Branch Instructions

Conditional LOOP instructions

LOOPNE/LOOPNZ

LOOPE/LOOPZ

These instructions check CX as well as Zero flag

Repeat execution till CX becomes 0 and the flag
condition is true
 CKV

ALP Example

MOV CX, 05 MOV CX, 04

MOV DL, 04 MOV DL, 05
MOV BL, 01 MOV BL, 01
MOV AL, 0 MOV AL, 0
L1: ADD AL, BL L1: ADD AL, BL
DEC DL DEC DL
LOOPNZ L1 LOOPNZ L1

What will be the AL value in the above programs?

 CKV

ALP Example
Write a program that counts the number of 1’s in a byte
stored at data memory location whose offset is 5000h and
stores the count in BL
MOV BL, 00
MOV DL, 08
MOV AL, [5000h]
L1: ROL AL, 1
JNC L2
INC BL
L2: DEC DL
JNZ L1
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 14: 8086 Instructions and Assembly Programming

 CKV

Branch Instructions

SHORT JUMP JA/JNBE LOOP

JAE/JNB LOOPZ
NEAR JUMP JB/JNAE LOOPNZ
JBE/JNA
FAR JUMP JE/JZ
JNE/JNZ
JC
JNC
JP/JPE
JNP/JPO
JCXZ
 CKV

String Instructions
The x86 processor architectures are equipped with
Special Instructions to handle string operations

String: A series of data words (or bytes) that reside in

consecutive memory locations

Operations:
Move

Scan

Compare
 CKV

String Instructions
Data Segment
MOVSB/MOVSW
Copies a byte or a word from a
location in data segment to a
location in extra segment

Extra Segment
 CKV

String Instructions
Data Segment
MOVSB/MOVSW
Offset address of Source byte or DS:SI
word (in data segment) must be in
SI Register

Offset address if destination byte

or word (in Extra Segment) must Extra Segment
be in DI register ES:DI
 CKV

String Instructions
Data Segment
MOVSB/MOVSW
SI and DI will increment/decrement DS:SI
Lower Address
DS:SI
by 1 (for Byte transfer) or 2 (for
Word transfer) automatically
Higher Address

Increment if Direction Flag (DF) = 0

Extra Segment

Instruction to Reset/Clear DF ES:DI Lower Address

ES:DI
CLD
Higher Address
 CKV

String Instructions
Data Segment
MOVSB/MOVSW DS:SI
SI and DI will increment/decrement DS:SI
Lower Address

by 1 (for Byte transfer) or 2 (for

Word transfer) automatically
Higher Address

Decrement if Direction Flag (DF) = 1

ES:DI Extra Segment

Instruction to Set DF ES:DI Lower Address

STD
Higher Address
 CKV

String Instructions
Data Segment
MOVSB
DS:SI
If DF = 0 DS:SI
12
Move byte from DS:SI to ES:DI
SI = SI + 1
DI = DI + 1
Extra Segment
ES:DI
ES:DI 45
 CKV

String Instructions
Data Segment
MOVSB DS:SI
DS:SI
If DF = 1
12
Move byte from DS:SI to ES:DI
SI = SI – 1
DI = DI – 1
ES:DI Extra Segment
ES:DI
45
 CKV

String Instructions
Data Segment
MOVSW
DS:SI
If DF = 0
12
DS:SI 89
Move word from DS:SI to ES:DI
SI = SI + 2
DI = DI + 2
Extra Segment
If DF = 1
ES:DI
Move word from DS:SI to ES:DI 45
SI = SI – 2 ES:DI 56
DI = DI – 2
 CKV

String Instructions
String Instructions often used with REP instruction

Example :

REP MOVSB

Repeats MOVSB instruction, But how many times?

The count specified in CX register

 CKV

String Instructions
Write ALP to move 5 bytes of data from one array whose starting
address is 5000h:1000h to another array whose starting address
is 5000h:2000h using string instructions

MOV AX, 5000h

MOV DS, AX
MOV ES, AX

MOV SI, 1000h

MOV DI, 2000h
MOV CX, 05h

CLD
REP MOVSB
 CKV

String Instructions
Write ALP to move 5 bytes of data from one array
(ARRAY1) to the other (ARRAY2)
.model small
.data
ARRAY1 db 11h, 22h, 33h, 44h, 55h
ARRAY2 db 0, 0, 0, 0, 0 MOV AX, DS
.code MOV ES, AX
.startup LEA SI, ARRAY1
; code here
MOV DI, Offset ARRAY2
MOV CX, 05h
.exit CLD
end REP MOVSB
 CKV

String Instructions
SCASB

Compares AL with the byte data in the memory

location whose logical address is ES:DI

AL or the contents of memory will not change

Flags get affected

DI gets auto-incremented/auto-decremented by 1
depending on the value of DF
 CKV

String Instructions
Data Segment
SCASB If DF = 0
Lower Address

AL 85
Higher Address
Compare

ES:DI Extra Segment

ES:DI Lower32
Address
45
67
79
Higher Address
 CKV

String Instructions
SCASW

Compares AX with the word data in the memory

location whose logical address is ES:DI

AL or the contents of memory will not change

Flags get affected

DI gets auto-incremented/auto-decremented by 2
depending on the value of DF
 CKV

String Instructions
Data Segment
SCASW If DF = 0
Lower Address

AX 1485
Higher Address
Compare

ES:DI Extra Segment

Lower32
Address
ES:DI 45
67
79
Higher Address
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 15: 8086 Instructions and Assembly Programming

 CKV

String Instructions

MOVSB/MOVSW
CLD
STD
REP
SCASB/SCASW
 CKV

String Instructions
Data Segment
MOVSB
DS:SI
If DF = 0 DS:SI
12
Move byte from DS:SI to ES:DI
SI = SI + 1
DI = DI + 1
Extra Segment
ES:DI
ES:DI 45
 CKV

String Instructions
Data Segment
MOVSB DS:SI
DS:SI
If DF = 1
12
Move byte from DS:SI to ES:DI
SI = SI – 1
DI = DI – 1
ES:DI Extra Segment
ES:DI
45
 CKV

String Instructions
Data Segment
MOVSW
DS:SI
If DF = 0
12
DS:SI 89
Move word from DS:SI to ES:DI
SI = SI + 2
DI = DI + 2
Extra Segment
If DF = 1
ES:DI
Move word from DS:SI to ES:DI 45
SI = SI – 2 ES:DI 56
DI = DI – 2
 CKV

String Instructions
SCASB/SCASW

Compares AL/AX with the byte/Word data in the

memory location whose logical address is ES:DI

AL/AX or the contents of memory will not change

Flags get affected

DI gets auto-incremented/auto-decremented by 1/2

depending on the value of DF
 CKV

String Instructions
Data Segment
SCASB If DF = 0
Lower Address

AL 85
Higher Address
Compare

ES:DI Extra Segment

ES:DI Lower32
Address
45
67
79
Higher Address
 CKV

String Instructions
Data Segment
SCASW If DF = 0
Lower Address

AX 1485
Higher Address
Compare

ES:DI Extra Segment

Lower32
Address
ES:DI 45
67
79
Higher Address
 CKV

ALP Example
Write ALP to search for a byte 35h in a given string of 50 bytes
with starting address of the string as 5000h:0000h. At the end
of the program BL should be equal to 1 if the key is found and 0
if key not found
MOV AX, 5000h
MOV ES, AX
MOV DI, 0000h
MOV CX, 32h ; 50 in hexadecimal is 32h
MOV BL, 0
CLD
MOV AL, 35h
REPNE SCASB
JNE EXIT
MOV BL, 1
EXIT: .EXIT
 CKV

String Instructions
LODSB/LODSW

Loads AL or AX with the data stored in the data

segment with offset address in SI register

No flags get affected

SI gets auto-incremented/auto-decremented by 1 (for

byte) or 2(for word) depending on the value of DF
 CKV

String Instructions
Data Segment
LODSB If DF = 0 DS:SI Extra Segment
DS:SI Lower Address
Lower32
Address

AL 85
32 45
67
79
Higher Address

Extra Segment

Higher Address
 CKV

String Instructions
Data Segment
LODSW If DF = 0 DS:SI
Lower Address
Lower32
Address
DS:SI 45
AX 1485
4532
67
Higher79
Address

Extra Segment

Higher Address
 CKV

String Instructions
STOSB/STOSW

Stores contents of AL or AX into the extra segment with

offset address in DI register

No flags get affected

DI gets auto-incremented/auto-decremented by 1 (for

byte) or 2(for word) depending on the value of DF
 CKV

String Instructions
Data Segment
STOSB If DF = 0

AL 85

Extra Segment
ES:DI Lower Address
ES:DI Lower32
85
Address
45
67
HigherAddress
Address
Higher79
 CKV

String Instructions
Data Segment
STOSW If DF = 0

AX 1485
Higher
HigherAddress
Address

Extra Segment
ES:DI
Lower Address
Lower32
85
Address
ES:DI 45
14
67
79
 CKV

String Instructions
Data Segment
STOSW If DF = 1

AX 1485
Higher
HigherAddress
Address

Extra Segment
ES:DI
Lower
LowerAddress
Address
67
ES:DI 79
32
85
45
14
 CKV

String Instructions
CMPSB/CMPSW

Compares byte/word in one string with byte/word on

another string

Flags get affected

DI gets auto-incremented/auto-decremented by 1 (for

byte) or 2(for word) depending on the value of DF
 CKV

String Instructions
Data Segment
CMPSB If DF = 0 DS:SI
DS:SI 32
45
67
Compare 79

Extra Segment
ES:DI Lower Address
ES:DI Lower32
Address
45
67
HigherAddress
Address
Higher85
 CKV

String Instructions
Data Segment
CMPSW If DF = 0 DS:SI
32
DS:SI 45
67
Compare 79

Extra Segment
ES:DI Lower Address
Lower32
Address
ES:DI 45
67
HigherAddress
Address
Higher85
 CKV

ALP Example
Write ALP to check if the string (of 20 bytes) stored at location
5000h:0000h is same as the string stored at 6000h:0000h. Store 1
in BL if strings are equal else store 0 in BL
MOV AX, 5000h
MOV DS, AX
MOV AX, 6000h
MOV ES, AX
MOV SI, 0000h
MOV DI, 0000h
MOV CX, 14h
MOV BL, 0
CLD
REPE CMPSB
JNE EXIT
MOV BL, 1
EXIT: .EXIT
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 16: 8086 Instructions and Assembly Programming

 CKV

String Instructions

MOVSB/MOVSW
CLD
STD
SCASB/SCASW
REP
REPE
LODSB/LODSW
REPNE
STOSB/STOSW

CMPSB/CMPSW
 CKV

String Instructions
Data Segment
DS:SI Extra Segment
LODSB If DF = 0 DS:SI Lower Address
Lower32
Address
45
AL 85
32 67
79
Higher Address
Loads AL with the data stored in the
data segment with offset address in SI
Extra Segment
register and increment SI

Equivalent to
MOV AL, [SI] Higher Address
INC SI
Except for changes in Flags
 CKV

String Instructions
Data Segment

STOSB If DF = 0

AL 85
Stores contents of AL into
the extra segment with
Extra Segment
offset address in DI
ES:DI
register ES:DI
Lower Address
Lower32
85
Address
Almost Equivalent to 45
MOV ES:[DI], AL 67
MOV [DI], AL Higher
Higher79Address
Address
INC DI INC DI
Segment Override
 CKV

Segment Override
Allows for the use of a different segment
register than the default

MOV AL, [BX+SI] ; by default Data Segment is

accessed
However you can instruct the processor to use
another segment e.g. Stack segment instead

MOV AL, SS:[BX+SI] Accesses Stack segment

 CKV

Segment Override
Allows for the use of a different segment
register than the default

MOV AL, [BP+SI] ; by default Stack Segment is

accessed

MOV AL, DS:[BP+SI] ; Accesses the Data segment

 CKV

Segment Override
What will be the effect on instruction codes?

How will you indicate the segment override in

the instruction code?

Instruction Instruction Code

MOV AL, [BX+SI] 8A 00

MOV AL, SS:[BX+SI] 36 8A 00

Segment Override Prefix

 CKV

Segment Override
Segment Override Prefix
0 0 1 1 1 0
SEG
MOV AL, [BX+SI] 8A 00
ES 0 0 MOV AL, SS:[BX+SI] 36 8A 00
CS 0 1
MOV AL, ES:[BX+SI] ?? 8A 00
SS 1 0
DS 1 1
 CKV

Other Instructions
Most of the instructions discussed till now will
exist in some or the other form in most of the
processors

There are some special instructions in 8086

 CKV

Special Instructions
DAA
Decimal Adjust AL after Addition

Used after addition to adjust the value in AL to

BCD value

BCD Representation:
25d Binary: 0001 1001 19h
25d BCD: 0010 0101
 CKV

Special Instructions
DAA
Decimal Addition BCD Addition
23 0010 0011
27 0010 0111
50 0100 1010 ADD
Expected Result 0000 0110 DAA
0101 0000
 CKV

Special Instructions
DAA Categorized as Arithmetic Instruction

Add 6 to the lower nibble (lower 4-bits) of AL

If lower nibble is > 9 or AF = 1

Add 6 to the higher nibble (higher 4-bits) of AL

If higher nibble is > 9 or CF = 1

 CKV

Special Instructions
DAS
Decimal Adjust AL after Subtraction

Sub 6 to the lower nibble (lower 4-bits) of AL

If lower nibble is > 9 or AF = 1

Sub 6 to the higher nibble (higher 4-bits) of AL

If higher nibble is > 9 or CF = 1

 CKV

Special Instructions
XLAT

Moves contents of memory location in data

segment whose offset address is BX+AL

AL [BX+AL]
 CKV

Special Instructions
XLAT Number ASCII
0 30h
Used for table lookup
1 31h
2 32h
3 33h
4 34h
5 35h
6 36h
7 37h
8 38h
9 39h
 CKV

Special Instructions
XLAT DS:BX
2000h:1000h 30h
Used for table lookup
31h
MOV AX, 2000h 32h
MOV DS, AX 33h
+8
MOV BX, 1000h 34h
MOV AL, 8 35h
AL=38 36h
XLAT
37h
38h
39h
 CKV

Special Instructions
LAHF

Moves lower byte of flag register into AH register

Flag register
7 0
- - - - OF DF IF TF SF ZF - AF - PF - CF
U U U
0 0 1

AH
 CKV

Special Instructions
SAHF

Moves AH register contents into lower byte of

Flag register
Flag register
7 0
- - - - OF DF IF TF SF ZF - AF - PF - CF
U U U
0 0 1

AH
 CKV

Special Instructions
Try this in emu8086
MOV AH, 0F0h
SAHF
LAHF

AH=??
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 17: 8086 Instructions and Assembly Programming

 CKV

Special Instructions

Segment Override DAA

DAS

XLAT

LAHF

SAHF
 CKV

Special Instructions
Write an ALP to add two BCD numbers
MOV AL, 64h ;AL = 0110 0100 BCD
MOV BL, 29h ;BL = 0010 1001 BCD
ADD AL, BL ;AL = 1000 1101 (AF=0) (CF=0)
DAA ;AL = 1001 0011
 CKV

Stack Instructions
What is a Stack?

Stack is an area of the memory

Data is generally pushed to and popped out of

the stack (only 16-bit data in 8086)

The stack is Last-In-First-Out (LIFO)

Last data that was pushed in will be the first one

that will be popped out
 CKV

Stack Instructions
PUSH

Stores data on to the Stack Anywhere in Stack??

Register e.g. PUSH AX, PUSH BX, PUSH SI

Memory e.g. PUSH WORD PTR[BX]
Flag Register PUSHF
 CKV

Stack Instructions
Stack Segment
PUSH Lower Address
Stack grows in
negative direction

If you want to store new Higher Address

data on to the stack,
where do you store it?
17
32
45
SS:SP will point to most SS:SP 19
recently pushed data 21
83
Top of Stack 83
 CKV

Stack Instructions
Stack Segment
PUSH Lower Address
Stack grows in
PUSH AX negative direction

AX 1367 Higher Address

Lower Byte to memory

location pointed by SS: SP-2 17
SS:SP 32
67
Higher Byte to memory 45
13
location pointed by SS: SP-1 SS:SP 19
21
Contents of SP register 83
decremented by 2 83
 CKV

Stack Instructions
POP

Loads data from the Stack to

Register/Memory/Flag register
e.g. POP AX, POP BX, POP SI

e.g. POP WORD PTR[BX]

POPF
 CKV

Stack Instructions
Stack Segment
POP Lower Address

POP BX Last in First Out

BX 1543
1367 Higher Address

Lower Byte from memory

location pointed by SS: SP 17
SS:SP 67
Higher Byte from memory 13
location pointed by SS: SP+1 SS:SP 19
21
Contents of SP register 83
incremented by 2 83
 CKV

Stack Instructions
What is the use of Stack Instructions?

Example:

AX has some value

PUSH AX

AX gets changed
POP AX
Original AX value needed
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions
Stack Segment
AX 1367 Lower Address

BX 2389
Higher Address

17
PUSH AX 12
15
SS:SP 19
67
21
13
SS:SP 83
83
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions
Stack Segment
AX 1367 Lower Address

BX 2389
Higher Address

17
PUSH AX SS:SP 12
89
15
23
PUSH BX 67
SS:SP
13
83
83
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions
Stack Segment
AX 2389
1367 Lower Address

BX 1367
2389
Higher Address

17
PUSH AX SS:SP 89
23
PUSH BX SS:SP 67
POP AX 13
POP BX SS:SP 83
83
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions (Show SS and SP after each inst)
Stack Segment
AX 1367 Lower Address

BX 2389
Higher Address

17
PUSH AX 12
15
1000:2FFE 19
67
21
13
Assume SS = 1000h 1000:3000 83
SP = 3000h initially 83
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions
Stack Segment
AX 1367 Lower Address

BX 2389
Higher Address

17
PUSH AX 1000:2FFC 12
89
15
23
PUSH BX 67
1000:2FFE
13
83
83
 CKV

Stack Instructions
Write an ALP to exchange contents of AX and BX registers
using stack instructions
Stack Segment
AX 2389
1367 Lower Address

BX 1367
2389
Higher Address

17
PUSH AX 1000:2FFC 89
23
PUSH BX 1000:2FFE 67
POP AX 13
POP BX 1000:3000 83
83
 CKV

Stack Instructions
PUSHF
Stores 16-bit flag register to the top of Stack

POPF
Transfers 16-bit data from top of the Stack to
the Flag register
 CKV

Stack Instructions
LODSB If DF = 0

Equivalent to
MOV AL, [SI]
INC SI

Except for changes in Flags

LODSB Equivalent to PUSHF

MOV AL, [SI]
INC SI
POPF
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 18: 8086 Instructions and Assembly Programming

 CKV

Special Instructions

PUSH

POP

PUSHF

POPF
 CKV

Correction in FAR Jump Instruction

 CKV

Branch Instructions

FAR JUMP

Addr. Inst Code

CS:IP 1000:0000 B1 03 BEGIN: MOV CL, 03
CS:IP 1000:0002 8A D1 MOV DL, CL
CS:IP 1000:0004 EA 0E 01 00 20 JMP FAR PTR THERE JMP 2000:010E
CS:IP 1000:0009 …….
How far? …….
CS:IP 2000:010E B2 02 THERE: MOV DL, 02
CS:IP 2000:0110
 CKV

Branch Instructions

Other intersegment far Jump instructions

JMP [reg16] (e.g. JMP DWORD PTR[BX])
DS:3412h 00
BX 3412
10
DS:3413h
DS:3414h 10
DS:3415h 70

Jumps to 7010h:1000h
 CKV

Procedures
CALL
‘CALL’ instruction in the program

-Gives the execution control to the

procedure/function which is called (callee)

-Changes IP (Intrasegment) or IP and CS

(Intersegment)

-Stores the Return Address on to the stack (i.e. IP

(or IP and CS) of the instruction which is next to
‘CALL’ in the main program)
 CKV

Procedures
RET
‘RET’ instruction in the program

-Gives the execution control back to the Caller

-Changes IP (Intrasegment) or IP and CS

(Intersegment) by retrieving the return address
from stack
 CKV

Procedures

Main Program
FUNC PROC NEAR
Normal Execution

CALL FUNC
MOV AL, 12

RET
ENDP
 CKV

Procedures

Main Program
FUNC2 PROC NEAR
FUNC PROC NEAR
Normal Execution

CALL FUNC2
CALL FUNC
ADD AL, 12
MOV AL, 12
RET
RET
ENDP
ENDP
 CKV

Procedures
CALL and RET
Stack Segment
Near CALL (intrasegment) Direct Call Lower Address

Addr.
CS:IP 1000:0000 BEGIN: MOV CL, 03
CS:IP 1000:0002 MOV DL, CL Higher Address
CS:IP 1000:0004 E8 07 01 CALL FUNC
CS:IP 1000:0007 MOV AL, 12 17
+107 How far?
……. SS:SP 07
32
FUNC PROC NEAR 00
45
CS:IP 1000:010E MOV DL, 02 19
SS:SP
CS:IP 1000:0110 MOV CH, 02 21
CS:IP 1000:0112 RET 83
CS:IP ENDP 83
 CKV

Procedures
CALL
Near CALL (intrasegment) Indirect Call

CALL reg16 e.g CALL BX

CALL [reg16] e.g CALL WORD PTR[BX]

 CKV

Procedures
CALL
Stack Segment
FAR CALL (intersegment) Direct Call
Addr. Inst Code
1000:0000
CS:IP B1 03 BEGIN: MOV CL, 03
CS:IP
1000:0002 8A D1 MOV DL, CL
CS:IP
1000:0004 9A 0E 01 00 20 CALL FUNC
1000:0009
CS:IP …….
FUNC PROC FAR 17
CS:IP 2000:010E B2 02 MOV DL, 02 SS:SP 32
09
CS:IP 2000:0110 Update IP RET 45
00
Update CS SS:SP 00
19
10
21
SS:SP 83
83
 CKV

Procedures
CALL
Far CALL (Intersegment) Indirect Call

CALL [reg16] e.g CALL DWORD PTR[BX]

 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 19: 8086 Instructions and Assembly Programming

 CKV

Procedures
CALL Near CALL (intrasegment)
Direct Call
CALL Label

Indirect Call

CALL reg16 e.g CALL BX

CALL [reg16] e.g CALL WORD PTR[BX]

 CKV

Procedures
CALL and RET
Stack Segment
Near CALL (intrasegment) Direct Call Lower Address

Addr.
CS:IP 1000:0000 BEGIN: MOV CL, 03
CS:IP 1000:0002 MOV DL, CL Higher Address
CS:IP 1000:0004 E8 07 01 CALL FUNC
CS:IP 1000:0007 MOV AL, 12 17
+107 How far?
……. SS:SP 07
32
FUNC PROC NEAR 00
45
CS:IP 1000:010E MOV DL, 02 19
SS:SP
CS:IP 1000:0110 MOV CH, 02 21
Update IP 83
CS:IP 1000:0112 RET
CS:IP ENDP 83
 CKV

Procedures
CALL and RET
Stack Segment
FAR CALL (intersegment) Direct Call
Addr. Inst Code
1000:0000
CS:IP B1 03 BEGIN: MOV CL, 03
CS:IP
1000:0002 8A D1 MOV DL, CL
CS:IP
1000:0004 9A 0E 01 00 20 CALL FUNC
1000:0009
CS:IP …….
FUNC PROC FAR 17
CS:IP 2000:010E B2 02 MOV DL, 02 SS:SP 32
09
CS:IP 2000:0110 Update IP RET 45
00
Update CS SS:SP 00
19
10
21
SS:SP 83
83
 CKV

Procedures
CALL
Far CALL (Intersegment) Indirect Call

CALL [reg16] e.g CALL DWORD PTR[BX]

BX 3000h
DS:3000h 00
DS:3001h 11
Procedure address: DS:3002h 80
7080h:1100h 70
DS:3003h
 CKV

Procedures
RET n
This adds the number ‘n’ to the stack pointer after the
return address is popped off the stack

For example

RET 4 ; adds 4 to the stack pointer after the return

address is popped
 CKV

ALP Example
Can I access data on Stack without changing SP?
.model small
Stack Segment
.stack 100h
.data COMPUTE PROC NEAR
A DW 0987H MOV BP,SP Passing Parameters
MOV AX, [BP + 4] through Stack
B DW 678H
Result DW ? MOV BX, [BP + 2] SS:BP SS:SP 0710:00FA 10
62
.code ADD AX, BX +2 0710:00FB 17
00
RET SS:SP 0710:00FC 78
32
.startup +4 0710:00FD
PUSH A COMPUTE ENDP 06
45
END SS:SP 0710:00FE 87
19
PUSH B 0710:00FF 21
09
CALL COMPUTE SS:SP 0710:0100 83
MOV RESULT, AX ;Assume address next instruction 83
.EXIT is 0721:0010
(Note: In this example DS=0720h, CS=0721h and SS =0710h)
 CKV

ALP Example
What will happen if you keep
.model small pushing variables on to stack?? Stack Segment
.stack 100h
.data COMPUTE PROC NEAR
A DW 0987H MOV BP,SP
B DW 678H MOV AX, [BP + 4]
Result DW ? MOV BX, [BP + 2] SS:BP 0710:00FA 10
.code ADD AX, BX 0710:00FB 00
.startup RET 4 SS:SP 0710:00FC 78
COMPUTE ENDP 0710:00FD 06
PUSH A 0710:00FE 87
PUSH B END
0710:00FF 09
CALL COMPUTE SS:SP 0710:0100 83
MOV RESULT, AX ;Assume address next instruction 83
.EXIT is 0721:0010 (Note: In this example DS=0720h, CS=0721h and SS =0710h)
 CKV

Passing Parameters
.model small Passing parameters through Registers
.stack 100h
.data COMPUTE PROC NEAR
A DW 0987H MUL AX
B DW 678H ADD AX, BX
Result DW ? ADC DX, 0
.code RET
.startup COMPUTE ENDP
MOV AX, A END
MOV BX, B
CALL COMPUTE
MOV RESULT, AX
.EXIT
 CKV

Passing Parameters
.model small Passing parameters through Memory or memory pointers
.stack 100h
.data ArrayADD PROC NEAR
N DW 05H ADD [BX], 5
Arr Db 67H, 23H, 45h, 89h, INC BX
78h RET
.code ArrayADD ENDP
.startup END
LEA BX, Arr
MOV CX, N
L1: CALL ArrayADD
LOOP L1
.EXIT
 CKV

ALP Example
Write factorial of a number using recursion of procedure calls. Assume
that the input is available in the memory location and the factorial nees to
be stored in the next location.
The recursion formula for factorial is:
fact(n) = 1, if n = 0,
= n * fact(n-1), if n > 0.
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 20: Macros, Assembler Directives and Programming

Models
 CKV

Procedures

Passing Parameters through Stack

Passing parameters through Registers

Passing parameters through Memory or memory pointers

 CKV
Assembler Directives
Directive: Instructions to the Assembler
Helps the assembler to convert the ALP to machine language
program

Indicates how an operand or section of a program is to be

processed by the assembler

Some generate and store information in the memory, others do

not
 CKV
Assembler Directives
Data Declaration Directives
DB (define byte) directive indicates that the data stored is in
bytes

DW (define word) directive indicates that the data stored is in

words

DD (define double word) directive indicates that the data stored

is in double word
 CKV
Assembler Directives
Example:
Data Segment
.model small
0710:0000 45h
.data ; assume DS register is initialized with 0710 0710:0001 35h
0710:0002 74h
0710:0003 00h
DATA1 DB 45H, 35H, 74H 0710:0004 20h
DATA2 DW 2000H, 37H, 2222H 0710:0005 37h
0710:0006 00h
0710:0007 22h
0710:0008 22h
 CKV
Assembler Directives
Directives for reserving memory locations
-These directives reserve memory for future use
-Memory may or may not be initialized

Example:
.model small
.data
DATA1 DW 10 DUP (5) Reserve 10 words in memory with name
DATA1 and initialize all 10 words with 0005
DATA2 DW 10 DUP (?) Reserve 10 words in memory with name
DATA2. Leave the words uninitialized
(default value is 0)
 CKV
Assembler Directives
Directives for Equating
Equate (EQU) directive equates a symbolic name to a value

Example:
COUNT EQU 10
CONST EQU 20H
MOV AH, 10
MOV AH, COUNT
MOV AL, CONST
MOV AL, 20H
 CKV
Assembler Directives
Directives for changing memory offset
ORG (originate) statement changes the starting offset address of the data
in the data segment to a desired location
Data Segment
DATA1 DB 25 ; assume DS = 0100
DATA1 0100:0000 19h
DATA2 DB 10001011b
DATA2 0100:0001 8Bh
DATA3 DB 12h DATA3 0100:0002 12h
ORG 0010h DATA4 0100:0010 32h
COUNT EQU 32h Not stored in Memory 0100:0011 61h
ASCII Values 0100:0012 39h
DATA4 DB ‘2a91’
0100:0013 31h
ORG 0018h
DATA5 DB ? DATA5 0100:0018 00h
 CKV
MACROS
A Macro is a group of instructions that perform task

All the instructions defined in the macro are inserted in the program at the
point of usage

Example:
MyMacro MACRO p1, p2, p3 ORG 100h MOV AX, 0004h
MOV AX, p1 MyMacro 4, DX, [BX] MOV BX, DX
MOV BX, p2 RET MOV CX, [BX]
MOV CX, p3
ENDM
 CKV
MACROS
In-built Macros that you have been using already in the lab sessions

.EXIT MOV AX, 4C00h

INT 21h
 CKV
X86 Programming Model
The assemblers support models which specify the number of segments
available for the user program

In EMU 8086

Tiny All the data and code fit in one segment

Small Contains two segments DS and CS of 64K bytes each

 CKV
X86 Programming Model
.MODEL SMALL ;Model definition

.STACK ;Use default 1K byte Stack

.DATA ;Begin Data Segment
;Data declarations
.CODE ;Begin code segment
.STARTUP ;Generate start-up code
…. ;user program here

.EXIT ;Generate exit code

END
 CKV
Models
The assemblers support models which specify the number of segments
available for the user program

Other models

Medium

Compact

Large

Huge
 CKV
Concept of Pseudo-instructions
Pseudo instructions are those which are not part of processor ISA but used
in Assemblers to simplify programming and debugging
Pseudo instructions get converted to actual instructions when you assemble
the code
.model small
.data ; assume Data segment starts at 0710:0000
VAR1 DB 45H, 35H, 74H
NUM DB 56h
.code
MOV BX, 0000
.startup
LEA BX, VAR1 MOV SI, 0003
LEA SI, NUM
 CKV
Concept of Pseudo-instructions
Pseudo instructions are those which are not part of processor ISA but used
in Assemblers to simplify programming and debugging
Pseudo instructions get converted to actual instructions when you assemble
the code

Example:
SHR AX, 4 If v=0 then count is 1,
if v=1 then count in CL

SHR AX, 1
SHR AX, 1
SHR AX, 1
SHR AX, 1
 CKV

Thank You
 CKV

Microprocessors and Interfacing

EEE F241/ECE F241/INSTR F241/CS F241

Lecture 21: ALP Examples

 CKV

ALP Example
Write factorial of a number using recursion of procedure calls. Assume
that the input is available in the memory location and the factorial nees to
be stored in the next location.
The recursion formula for factorial is:
fact(n) = 1, if n = 0,
= n * fact(n-1), if n > 0.
 CKV
ALP Example : Factorial using Recursion

.MODEL SMALL
.STACK
.DATA
N DW 4
RES DW 1
.CODE
.STARTUP

MOV AX, N
CALL FACT
.EXIT SP
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1
.CODE
.STARTUP

MOV AX, N
SP 0B
CALL FACT
00
0720:000B: .EXIT SP
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX ;AX=3
.STARTUP
SP 04
MOV AX, N 00
SP 0B
CALL FACT
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX ;AX=3
SP 21
.STARTUP CALL FACT 00
0721:0021:
SP 04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 SP 03
L1: PUSH AX
00
.CODE DEC AX ;AX=2
SP 21
.STARTUP CALL FACT 00
0721:0021 :
04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01 21
SP
N DW 4 RET 00
RES DW 1 SP 03
L1: PUSH AX
00
.CODE DEC AX ;AX=2
21
.STARTUP CALL FACT 00
0721:0021 :
04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
SP 02
.STACK JNZ L1
00
.DATA MOV RES, 01 21
SP
N DW 4 RET 00
RES DW 1 03
L1: PUSH AX
00
.CODE DEC AX ;AX=1
21
.STARTUP CALL FACT 00
0721:0021 :
04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
SP 21
FACT PROC NEAR 00
.MODEL SMALL CMP AX, 01
SP 02
.STACK JNZ L1
00
.DATA MOV RES, 01 21
N DW 4 RET 00
RES DW 1 03
L1: PUSH AX
00
.CODE DEC AX ;AX=1
21
.STARTUP CALL FACT 00
0721:0021 :
04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
SP 21
FACT PROC NEAR 00
.MODEL SMALL CMP AX, 01
SP 02
.STACK JNZ L1
00
.DATA MOV RES, 01 21
N DW 4 RET 00
RES DW 1 03
L1: PUSH AX
00
.CODE DEC AX ;AX=1
21
.STARTUP CALL FACT 00
0721:0021 :
04
MOV AX, N 00
CALL FACT 0B
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
SP 02
.STACK JNZ L1
00
.DATA MOV RES, 01 21
SP
N DW 4 RET 00
RES DW 1 03
L1: PUSH AX
00
.CODE DEC AX
21
.STARTUP CALL FACT 00
0721:0021 : POP AX ;AX=2
04
MUL RES ;AX = RES * 2
MOV AX, N 00
MOV RES,AX ;RES = 2
CALL FACT 0B
RET
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01 21
SP
N DW 4 RET 00
RES DW 1 SP 03
L1: PUSH AX
00
.CODE DEC AX
21
.STARTUP CALL FACT 00
0721:0021 : POP AX
04
MUL RES
MOV AX, N 00
MOV RES,AX
CALL FACT 0B
RET
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 SP 03
L1: PUSH AX
00
.CODE DEC AX
SP 21
.STARTUP CALL FACT 00
0721:0021 : POP AX ;AX=3
04
MUL RES ;AX = RES * 3
MOV AX, N 00
MOV RES,AX ;RES = 6
CALL FACT 0B
RET
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX
SP 21
.STARTUP CALL FACT 00
0721:0021 : POP AX
SP 04
MUL RES
MOV AX, N 00
MOV RES,AX
CALL FACT 0B
RET
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX
.STARTUP CALL FACT
0721:0021 : POP AX ;AX=4 SP 04
MUL RES ;AX = RES * 4
MOV AX, N 00
MOV RES,AX ;RES = 24 SP
CALL FACT 0B
RET
00
0721:000B: .EXIT
 CKV
ALP Example : Factorial using Recursion
FACT PROC NEAR
.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX
.STARTUP CALL FACT
0721:0021 : POP AX
MUL RES
MOV AX, N MOV RES,AX SP 0B
CALL FACT RET
00
0721:000B: .EXIT SP
 CKV

FACT PROC NEAR

.MODEL SMALL CMP AX, 01
.STACK JNZ L1
.DATA MOV RES, 01
N DW 4 RET
RES DW 1 L1: PUSH AX
.CODE DEC AX
.STARTUP CALL FACT
0721:0021 : POP AX
MUL RES
MOV AX, N MOV RES,AX
CALL FACT RET
0721:000B: .EXIT SP
 CKV

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