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Review of Network on Chip Routing Algorithms

Article in EAI Endorsed Transactions on Context-aware Systems and Applications · December 2020
DOI: 10.4108/eai.23-12-2020.167793

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EAI Endorsed Transactions
on Context-aware Systems and Applications Research Article

Review of Network on Chip Routing Algorithms

Khurshid Ahmad*, Muhammad Athar Javed Sethi

Department of Computer Systems Engineering, University of Engineering and Technology, Peshawar, Pakistan
[email protected], [email protected]

Abstract

System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection
system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC). In NoC
architecture node/ component of MPSOC are communicating through a network. The performance of NoC architecture
depends on topology, routing algorithm and switching technique. In this paper, different NoC routing algorithms are
review using basic parameters of NoC architecture and also provide some information about these parameters. It is
concluded that most of the researchers are interested in design of the NoC routing algorithm, which efficiently transmits
data from source to destination. When the routing algorithm is congestion aware, fault-tolerant, deadlock-free and live-
lock free, then the latency of algorithm decreases and throughput increases.

Keywords: System on Chip, Network on Chip, Routing Algorithm.

Received on 07 November 2020, accepted on 11 December 2020, published on 23 December 2020

Copyright © 2020 Khurshid Ahmad et al., licensed to EAI. This is an open access article distributed under the terms of the
Creative Commons Attribution license, which permits unlimited use, distribution and reproduction in any medium so long as the
original work is properly cited.

doi: 10.4108/eai.23-12-2020.167793

1. Introduction
The System on Chip (SoC) has a prominent role in the
computing world. It is used in mobile computing, embedded
system and now also implied to a personal computer such as
laptop and tablet PC etc. SoC is a design methodology used
by very-large-scale integration (VLSI) designers. The Fig (1). Interconnection System of SoC
interconnection system of SoC based on share bus or
dedicated bus. The basic problem in the bus system as that it NoC is a communication network between multiple
allows one communication at the time [1]. Advancement in devices. Devices are connected in regular or irregular
technology, SoC in an embedded system is increasingly topology [7-9]. The devices are processor, memory, DSP
large and complex [2]. Fig (1) shows the interconnection core etc are called processing element (PE). The PE has two
system of SoC in which different devices are connected types, homogeneous and heterogeneous. Fig (2) shows 4*4
through a shared bus system. The problem of mesh topology of NoC. In which PEs are connected to local
communication arises because bus architecture cannot meet routers through a network interface (NI) and routers are
the requirement like area utilisation, single clock connected to each other with a point to point connection.
synchronisation, propagation delay, latency, throughput and The NI transforms the message to packet and packet
power consumption [3]. Network on chip (NoC) appear as a received by router send it to neighbour router. The packet
better solution for the implementation of SoC [1]. NoC can move to the destination is travelling through routers [10,
be defined as “A communication network targeted for on- 11].
chip communication”. NoC is efficient for on-chip
communication for SoC [4-6].

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Khurshid Ahmad, Muhammad Athar Javed Sethi

simulator on which the review routing algorithms are

implemented.

2. Contemplation on the routing algorithm

Every routing algorithm has a different impact on different
NoC architecture. It affects different properties of NoC
architecture such as latency, throughput and power
consumption.
The routing algorithm is similar to routing in any
network. Routing algorithm decides path followed by a
packet in communication from source to destination [1, 12,
13]. They prevent deadlock, live-lock and starvation
situation. Deadlock is cyclic dependency among node
making access to resources where no progress can be made.
Live-lock as refers to a situation where packet circulates in
the network but not reaching to the destination. In starvation
Fig (2). 4*4 NoC packet in buffer request for output channel but output
channel also allocated to another packet [1].
The overall performance of NoC depends on topology,
routing algorithm, flow control and switching technique [4]. 3. Routing type
Topology means how nodes are connected in a network.
There are different types of topology such as mesh, torus, Different types of routing algorithms are developed for the
tree, ring, star, spidergon and also some irregular topology designing of NOC. Routing algorithms are classified on
[10]. Routing algorithm defines the path taken by a packet three key characteristics. Which are routing decision,
from source to destination. XY, IX/Y, XYX etc. are some defining path and path length [1, 12]. On the base of the
example of routing algorithm [4]. There are two major types routing decision, there are two types of source and
of switching, circuit switching and packet switching. In distributed routing. In source, routing path defines by source
circuit switching a physical or virtual link are establishing router and in distributed routing, each router decides the
between source and destination. In packet switching next direction for packet [1]. According to path defining or
message is divide into packets at source and routed to the adaptively, the routing algorithm has two type deterministic
destination. The routing algorithm determines a route for and adaptive algorithms. The path is completely determined
packet [3]. The understanding of routing algorithm is very from source to destination in advance in the deterministic
critical in designing of NoC architecture. algorithm. There also as another type partially adaptive
Routing algorithms is a key factor affecting NoC network which restrict some direction [13]. On the base of path
communication. In this review, we compare different length, there are two types minimal and non-minimal.
routing algorithm on the bases of a basic parameter of NoC Shortest path selection algorithm is minimal and the longest
architecture. The parameter for the comparison of routing path selection algorithm is non-minimal [1, 13].
algorithm are topology, routing type, switching technique, The routing algorithms GOAL, GAL, DyXY, BARP,
packet and flit size, power dissipation, latency, throughput ADBR, MaS, Fault-tolerant, FAFT, FT-DyXY, Free-rider,
and simulator on which routing algorithm are implemented. Novel Adaptive, Traffic allocator, MCAR, Efficient
The comparison of routing algorithms is shown in Table 1. deadlock-free, ESPDA and Adaptive multipath are adaptive
We believe that this review paper is helpful for the routing algorithm [9, 14-28]. OE and 3DEP are partial
researcher community to resolve routing issue of NoC adaptive routing algorithm [29, 30]. DyAD and FA-DyAD
architecture in future. are adaptive and deterministic [31, 32]. The deterministic
The remainder of the paper is organised in such a way routing algorithms are FTXY and ZigZig [33, 34]. Some
that in section 2, we define deadlock, live-lock and more classification is possible like congestion aware
starvation situation of routing algorithms. In section 3, algorithm, and Fault-Tolerance-routing algorithm will
different types of routing algorithm are discus. In section 4, discuss in section 6 and 7.
we discussed topology and its type. In section 5, we
discussed switching technique and also which switching
technique is used in the implementation of which routing 4. Topology
algorithm. In section 6 and 7, we discussed which one
algorithm is congestion aware and which one is fault- Topology in NoC is an organisation of router and channel.
tolerant. In section 8, the power dissipation of review Topology is the roadmap for communication of PE in NoC
routing algorithms is the discus. In section 9, latency and [35]. It’s divide into two types [10]. In regular topology,
through are discus. In section 10, we discussed different nodes are connected in a specific pattern. Mesh, torus, star,

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 Review of Network on Chip Routing Algorithms

ring and tree are popular regular topology [10, 35-38]. The
mash topology has M rows and N columns. The intersection
of row and column consists of routers and the router are
connected to its neighbours. Tours topology are similar to
mesh but end routers are connected together with the same
row and column routers. In star topology, all routers are
connected to a central router. The router is connected to its
two neighbours circle shape are ring topology. In tree
topology, a child router is connected to its parent router. Fig
(3-6) shows the structure of torus, star, ring and tree
topology. In irregular, topology nodes are not connected in
fix pattern. Fig (7) shows irregular topology.

Fig (6). Tree topology

Fig (3). Torus topology

Fig (7). irregular topology

To design the routing algorithm for the network, the

choosing of topology is the principle step. The performance
of the routing algorithm depends on the topology on which
it’s implemented and also on the number of routers in the
topology. When the same algorithm is implemented on mesh
4×4, and mesh 8×8 have different performance [28].
O1TURN [39], DyXY [16], BARP [18] and FT-XY [33] are
implemented on mesh topology having a different number
Fig (4). Star topology of the router. In this review, Table 1 shows that most of the
routing algorithm is implemented on a mesh topology.

Fig (5). Ring topology

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Table 1. NoC Routing algorithm

Compression Parameters
Year Routing Routing Switching Packet Power Latency Throug Simulato
Algorithm

Topology

Type characteristic technique and flit dissipation hput r

S.NO

Size

1 OE 2000 15×1 Partial Deadlock Event-

[29] 5 2D adaptive free - - - - - driven
mesh simulator
2 GOAL 2003 Torus Adaptive Cycle
[14] - - - - - - accurate
network
simulator
3 GAL 2004 8×8 Adaptive Congestion Wormhole Cycle
[15] Torus aware - - - - accurate
network
simulator
4 DyAD 2004 6×6 Deterministi Congestion Wormhole At Worm_si
[31] 2D c and aware and injecti m
mesh Adaptive Deadlock on rate simulator
free - - - 0.0167
are
0.027
packet/
cycle
5 O1TU 2005 4×4, Deadlock 5 Flit PoPnet
RN 8×8 - free - - - - simulator
[39] 2D
mesh
6 DyXY 2006 3×3, Adaptive Congestion At Event-
[16] 9×9 aware, Average driven
2D deadlock- injection simulator
mesh free and live- rate of using
lock free - - - 0.3 are - C++
14
Approx.

7 Fault 2008 4×4 Fault-tolerant Cut 4 flit When 2 MATLA

aware 2D through fault, B
dynam mesh injection Simulink
ic - - rate 20 -
routing flit/node
[40] /cycle
then 78
cycle
8 BARP 2008 8×8, Adaptive Deadlock Wormhole Flit is Injectio Develope
[18] 14×1 and live-lock 16 bit n rate d on flit
4 2D free .25 level
mesh - message - NoC
/cycle simulator
then 400 using
cycle C++
9 IX/Y 2008 2D Adaptive Deadlock - - - At - Noxim
[41] mesh free injection

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 Review of Network on Chip Routing Algorithms

rate .05
then
below
30cycle
10 ADBR 2008 8×8 Fully Deadlock 0.00035 J at 0.175 Noxim
[17] 2D adaptive free and flow injection flit/cyc
mesh control - - rate 0.03 le
are 250
cycle
11 XYX 2009 2D Deterministi Fault tolerant 32 flit VHDL
[42] c - - - - based
NoC
simulator
12 FT-XY 2009 5×5, Deterministi Deadlock For 6×6 For the Noxim
[33] 6×6 c free Injection 6×6
2D rate 0.005- Injectio
mesh - - 0.009 n rate, -
packet/cycl 0.03 are
e/node are 85 cycle
0.02-0.09 J Approx.
13 DBFA 2009 4×4× Live-lock OPNET
LCI 4 3D - free, - - - - -
[43] Torus Asynchronou
s.
14 EDXY 2010 7×7, Congestion For 15×15 For 7×7 VHDL
[44] 15×1 aware injection In
5 2D rate 9% uniform
mesh then traffic
- - - 26.1197 injection -
rate
28%
then 100
cycle
15 FA- 2010 6×6 Deterministi Fault and Fault gpNocsi
DyAD 2D c and congestion 10%, m
[32] mesh adaptive aware injection
- - - rate .08 -
packet/c
ycle
then 630
approx.
16 Low 2011 3D Xilinx
latency consi 10.1
routing st of version
algorit 4×4 - - - - - - - is used
hm 2D for
[45] mesh simulatio
layer n of
results
17 MaS 2012 10×1 Adaptive, Live-lock Wormhole 8 flit At Average On-chip
routing 0 buffer less free and 128 injection latency network
[19] mesh bit rate of 0.21 of 53 simulator
Flit/cycle/n cycle
ode are
6.5w
18 Fault- 2012 8×8 Adaptive 16 flit XMulato
toleran 2D - - and 128 - - - r
t mesh bit

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routing
[9]
19 CATR 2012 8×8, Congestion 1-5 flit 2.51w At Impleme
A [46] 14×1 aware distribut injection nted
4 2D - - ed rate 0.35 - through
mesh uniform f/n/c are VHDL
ly 200
cycle
20 Precon 2012 Based on the wormhole NIRGA
certed virtual circuit M
wormh - - - - - -
ole
routing
[47]
21 FAFT 2013 4×4× Fully Fault-tolerant Noxim
routing 3 3D adoptive - - - - -
[20] mesh
22 FT- 2014 3D Adaptive Fault-tolerant 5 flit Booksim
DyXY mesh - - - -
Z [21]
23 Free- 2014 16×1 Adaptive Congestion 5 flit Booksim
Rider 6 2D aware and 128
[22] mesh bit
24 Novel 2015 8×8× Adaptive Congestion At At At Noxim
adaptiv 4, aware injection injection injecti
e 16×1 - - rate 0.5 are rate 0.5 on rate
routing 6×1 1 are 1 0.5 are
[23] 3D 1
mesh
25 Distan 2015 2D 2-10 flit System C
ce mesh platform
predict - - - - - -
ion
XY
[48]
26 DRTL 2016 4×4× Deadlock Wormhole 5 flit Alpha
[49] 4 3D free and 64 EV6 core
mesh bit model is
- - - - used
result
simulatio
n
27 Traffic 2016 6×6 Adaptive A When load When NIRGA
allocati 2D packet 50% then load M
on mesh is 20 61.973 mw 50%
routing - - bytes then -
[24] 45.9084
cycle/fli
t
28 MCAR 2017 8×8, Adaptive Congestion 7.85% on 5.84% Booksim
[27] 16×1 aware - - average - on 2.0
6 2D averag
mesh e
29 Efficie 2017 4×4× Adaptive Dead lock- A Noxim
nt 4, free packet
deadlo 8×8× - is 8 bit - - -
ck-free 4 3D
adaptiv mesh

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 Review of Network on Chip Routing Algorithms

e [26]
30 ESPA 2017 8×8 Fully Dead lock- 5 flit GPU
DA 2D adaptive free and 64 based on
[25] mesh based on - bit - - - cyclic
virtual accurate
channel NoC
31 ZigZig 2017 2D deterministi Packet The load is Average NIRGA
[34] mesh c is 50% then latency M
- - 20bytes 62.698 mw is -
46.2517
cycle/fli
t
32 Adapti 2018 4×4, Adaptive Congestion 8 flit For 4×4 HNOC
ve 8×8 aware and 32 Load based on
multip 2D - bit - 0/9 - OMNET
ath mesh GB/sec ++
[28] 330 Ns
33 Link- 2018 8×8 Congestion Wormhole Flit is 2.86 mw RTL
Sharin 2D - aware 32 bit - - level by
g [50] mesh using
VHDL
34 UMF 2019 Mesh - Dead lock - 5 flit - - - PopNet
[51] free
35 TBTF 2019 8×8 Congestion Offer OPNET
TA 2D aware, load
[52] mesh - thermal-fault - - - - increas
tolerant es high
throug
hput
36 3DEP 2019 3D Partially Dead lock - - - - - Noxim
[30] mesh adaptive free
37 CFPA 2019 Mesh Congestion HNOC
[53] and aware, fault- for
torus tolerant algorithm
- - - - - - and MC
used for
circuit-
level
delay

5. Switching Technique
Switching technique refers to the flow control mechanism of the packet is forwarded to the next router if it ensures that
messages between routers. The basic switching techniques the whole packet is store in it [10, 54].
that are used in NoC is circuit switching and packet Due to pipeline nature and low latency wormhole
switching. Packet switching is further divided into three switching technique are preferring in designing of routing
broad categories wormhole, store and forward and virtual algorithm. The GAL, DyAD, BARP, MaS, Preconcerted
cut through [10, 54]. In the wormhole, the packet is divided wormhole routing, DTRL and Link sharing are implemented
into flit (head flit, body flit and tail flit). Head flit contains using wormhole switching technique [15, 18, 19, 31, 47, 49,
source and destination information, body flit contains data 50].
which is transmitted to destination and tail flit contain
ending information of flit. Due to the pipelined nature of
wormhole, it redacts message latency [31, 54, 55]. In store 6. Congestion Awareness
and forward technique, the whole packet is store in the
router then routed to the next router. In virtual cut through, It’s characteristic of routing algorithm which improves the
performance of NoC by distributing the load over network

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and send the traffic over the less congested area. On 9. Latency and Throughput
congestion awareness basis routing algorithm are divided
into two types. Congestion oblivious algorithm and The performance of the routing algorithm depends on
congestion aware algorithm [46, 56]. Congestion oblivious latency and throughput. The performance of routing is batter
algorithm is unable to balance the load over the network and when its latency is low, and throughput is high. Most of the
can’t consider the congestion status of the network. Without researchers compare their own proposed routing algorithm
congestion awareness interconnection system of the network latency and throughput with other routing algorithms for
is unbalanced and burst. On the other hand, the congestion performance evaluation. Throughput of CFPA is compared
aware algorithm routes the traffic through the largest with XY and DyAD and shown that its throughput is better
available virtual channel. than XY and DyAD [53].
Table 1 show that GAL, DyAD, DyXY, BARP, EDXY, The latency and throughput of routing algorithm depend
FA-DyAD, CATRA, Free-Rider, Novel adaptive routing, on the number of tiles in NoC, e.g. for same algorithm
DTRL, MCAR, Adaptive multipath, Link sharing and CFPA latency and throughput for 4×4 and 8×8 are different. When
are congestion aware algorithms [15, 16, 20, 22, 27, 28, 31, the number of tiles in NoC increases the latency of routing
32, 44, 46, 50, 52, 53]. Congestion awareness decrees algorithm increase and throughput is decrees [23, 28, 34,
latency and increases throughput. Congestion aware 44]. Latency and throughput of routing algorithm also
algorithms are further divided on the base of sharing of depend on the injection rate [16, 18, 32, 40]. Latency and
congestion information are local and non-local [22]. throughput of the review routing algorithms are shown in
Table 1.

7. Fault tolerance
10. Simulator
Fault tolerance is network property to examine the
functioning of the network component and remains its There are three approaches for the to evaluate the
functioning when some components are inactive/faulty. performance of the system
Fault can occur as a result of a defect in the system, • Actual system monitoring
improper environment and improper design of a system. • Mathematical modelling
Fault in NoC is categories in two groups on the base of time • Simulation modelling
and occurrence. Hardware fault occurs due to hardware fault The simulation environment provides an extensible
of the system and for its removing extra hardware or framework for NoC evaluation and provides more feature,
resources are required [57-59]. The soft fault is denoted by a different topology, swathing technique, routing algorithm,
bug in the software and it can be addressed by routing flow control polices and high accuracy [67-69].
algorithm. In this review, Table 1 shows most of the routing
Scientists and researchers propose different fault-tolerant algorithm performance is evaluated on Noxim, Booksim and
routing to overcome fault in NoC [10, 60]. A routing NIGRAM simulator. Noxim simulator is used for the
algorithm for fault tolerance is Fault aware dynamic routing, performance evaluation of ADBR, FT-XY, FAFT routing
FA-DyAD, FAFT routing, FT-DyXY, TBTFTA and CFPA algorithm, Novel adaptive routing, Efficient deadlock-free
[20, 21, 32, 40, 52, 53]. The compression of these adaptive routing and 3DEP. Booksim simulator is used for
algorithms is shown in table 1. FT-DyXY, free-rider and MCAR. Precocerted wormhole
routing, traffic allocation routing and ZigZig routing
algorithm performance are evaluated through NIGRAM
8. Power Dissipation simulator. Some other simulator Event-driven, XMultar,
PopNET, gpNoCsim, OpNET, Matlab simulator and event-
In the designing of the routing algorithm, the power
driven are used for performance evaluation of routing
dissipation is under consideration of scientists and
algorithms.
researchers. Power dissipation is divide into two parts; static
and dynamic. Static power relates to manufacturing
technology and dynamic power depends on the router 11. Conclusion
activity [61]. In [62-66] are the technique are proposed to
reduce power consumption. This paper review different routing algorithm of NoC on the
The power consumption of FT-XY under uniform traffic base of different parameter. In our view, it’s helpful for the
of 4×4 NoC is .01 to .09 J and for 6×6 NoC its .02 to .09 J researcher community to find and resolve the unanswered
for injection rate of .005 to .019 packet/cycle/node [33]. The issue of this area. Based on Table 1, it is concluded that
power consumption for ADBR is .00035J, for MaS most of the researchers are interested in to design the
algorithm it’s a 6.5w at injection rate of 0.21 routing algorithm, which has low latency, high throughput,
packet/cycle/node, for Traffic allocation routing algorithm low power consumption, congestion aware and fault-
it’s 61.973mw when load is 50%, for ZigZig algorithm it’s tolerant. From this review it is concluded that, in the
62.698mw when load is 50% and for Link sharing algorithm designing of routing algorithm the designers/researchers
it’s 2.86mw [17, 19, 24, 34, 50]. should compromise on some parameters. When the

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 Review of Network on Chip Routing Algorithms

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and live-lock free than power consumption, area utilisation the latency is decrease and throughput is increase.
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