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Developing Embedded

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Applications Using

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CompactRIO and

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LabVIEW FPGA TM

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Participant Guide

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Course Software Version 2023 Q3

November 2023 Edition
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Part Number 328491C-01

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Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

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Copyright
© 2023 National Instruments Corporation. All rights reserved.
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Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or
mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole
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or in part, without the prior written consent of National Instruments Corporation.

NI respects the intellectual property of others, and we ask our users to do the same. NI software is protected by
copyright and other intellectual property laws. Where NI software may be used to reproduce software or other
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materials belonging to others, you may use NI software only to reproduce materials that you may reproduce in
accordance with the terms of any applicable license or other legal restriction.
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End-User License Agreements and Third-Party Legal Notices

You can find end-user license agreements (EULAs) and third-party legal notices in the following locations:
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• Notices are located in the <National Instruments>\_Legal Information and <National

Instruments> directories.
• EULAs are located in the <National Instruments>\Shared\MDF\Legal\License directory.
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• Review <National Instruments>\_Legal Information.txt for more information on including legal

information in installers built with NI products.
 Trademarks
Refer to the NI Trademarks and Logo Guidelines at ni.com/trademarks for more information on NI trademarks.
ARM, Keil, and µVision are trademarks or registered of ARM Ltd or its subsidiaries.
LEGO, the LEGO logo, WEDO, and MINDSTORMS are trademarks of the LEGO Group.
TETRIX by Pitsco is a trademark of Pitsco, Inc.

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FIELDBUS FOUNDATION™ and FOUNDATION™ are trademarks of the Fieldbus Foundation.
EtherCAT® is a registered trademark of and licensed by Beckhoff Automation GmbH.

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CANopen® is a registered Community Trademark of CAN in Automation e.V.
DeviceNet™ and EtherNet/IP™ are trademarks of ODVA.
Go!, SensorDAQ, and Vernier are registered trademarks of Vernier Software & Technology. Vernier Software &

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Technology and vernier.com are trademarks or trade dress.
Xilinx is the registered trademark of Xilinx, Inc.

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Taptite and Trilobular are registered trademarks of Research Engineering & Manufacturing Inc.
FireWire® is the registered trademark of Apple Inc.
Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries.

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Handle Graphics®, MATLAB®, Real-Time Workshop®, Simulink®, Stateflow®, and xPC TargetBox® are registered
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Tektronix®, Tek, and Tektronix, Enabling Technology are registered trademarks of Tektronix, Inc.

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The Bluetooth® word mark is a registered trademark owned by the Bluetooth SIG, Inc.

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The ExpressCard™ word mark and logos are owned by PCMCIA and any use of such marks by NI is under license.
The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of
Microsoft Corporation in the United States and other countries.
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Other product and company names mentioned herein are trademarks or trade names of their respective
companies.
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Members of the NI Partner Program are business entities independent from NI and have no agency, partnership,
or joint-venture relationship with NI.
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Patents
For patents covering NI products/technology, refer to the appropriate location: Help»Patents in your software,
the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents.
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Support
Worldwide Technical Support and Product Information
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ni.com
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NI Corporate Headquarters
11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100

For further support information, refer to the Additional Information and Resources appendix. To comment on NI
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documentation, refer to the NI website at ni.com/info and enter the Info Code feedback.
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Table of Contents

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Student Guide
A. Course Description ....................................................................................... vii

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B. What You Need to Get Started....................................................................... vii
C. Installing Course Files ................................................................................... viii
D. Course Goals ............................................................................................... viii

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Lesson 1
Programming Using LabVIEW FPGA
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A. Introduction to FPGA ....................................................................................
B. Developing an FPGA VI .................................................................................
1-3
1-8
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C. Interactive Front Panel Communication ........................................................... 1-13
D. Selecting an Execution Mode ......................................................................... 1-14
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Exercise 1-1: Explore Simulation Execution Mode ................................................ 1-17

E. Compiling an FPGA VI................................................................................... 1-22
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Exercise 1-2: Compile and Execute a VI ............................................................. 1-29

F. Compilation Considerations ........................................................................... 1-33
G. Basic Optimizations ...................................................................................... 1-37
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Lesson 2
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Using FPGA I/O and Timing

A. Configuring FPGA I/O ................................................................................... 2-3
B. Exploring I/O Types ...................................................................................... 2-7
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C. Exploring Analog CompactRIO I/O .................................................................. 2-11

D. Handling FPGA I/O Errors .............................................................................. 2-13
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E. Setting Loop Execution Rates ........................................................................ 2-15

Exercise 2-1: Acquire Tachometer and Acceleration Signals.................................. 2-21
F. Synchronizing C Series Modules..................................................................... 2-29
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G. Creating Delays between Events .................................................................... 2-32

H. Measuring Time between Events .................................................................... 2-33
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I. Benchmarking Loop Periods ........................................................................... 2-35

Exercise 2-2: Benchmark the Actual Loop Period ................................................. 2-36
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 Table of Contents

Lesson 3
Signal Processing in LabVIEW FPGA
A. Using Fixed-Point Data Type .......................................................................... 3-3
Exercise 3-1: Explore Fixed-Point Configurations ................................................. 3-12
B. Using Single-Precision Floating-Point............................................................... 3-17
Exercise 3-2: Process the Tachometer and Accelerometer Signals ......................... 3-20

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C. Performing FPGA Math & Analysis ................................................................. 3-26
D. Integrating Third-Party Intellectual Property (IP) ................................................ 3-30

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Lesson 4
Inter-Process Communication in LabVIEW FPGA

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A. Exploring Parallel Loops on FPGA ................................................................... 4-3
B. Transferring Latest Data (Tag) ....................................................................... 4-6

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Exercise 4-1: Transfer Latest Values to PID Loop ................................................ 4-15
C. Transferring Buffered Data (Stream, Message) ................................................. 4-28

Lesson 5

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Communicating between the FPGA and Real-Time VIs
A. Programmatically Communicating with the FPGA VI from the Real-Time VI.......... 5-3

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B. Deploying an FPGA VI................................................................................... 5-5
C. Transferring Latest Data (Tag) ....................................................................... 5-10
Exercise 5-1: Transfer Tag Data between FPGA and RT ....................................... 5-13

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D. Transferring Buffered Data (Stream, Message) .................................................
Exercise 5-2: Transfer Stream Data from FPGA to RT Target ................................
Exercise 5-3: Explore DMA FIFO Interleaving ......................................................
5-20
5-30
5-42
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E. Synchronizing the RT VI and FPGA VI ............................................................. 5-46
F. Implementing an FPGA Watchdog .................................................................. 5-49
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Exercise 5-4: Explore FPGA Watchdog ............................................................... 5-50

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Lesson 6
Exploring Common FPGA Optimizations
A. Optimization Use Cases ................................................................................ 6-3
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B. Optimization Techniques for FPGA Size........................................................... 6-4

C. Optimization Techniques for Speed/Throughput................................................ 6-7
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D. Executing Code in Single-Cycle Timed Loops ................................................... 6-8

Exercise 6-1: Observe Loop Speed: While Loop versus Single-Cycle Timed Loop ..... 6-11
Exercise 6-2: Fix SCTL Errors............................................................................ 6-21
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E. Implementing Pipelining................................................................................. 6-29

Exercise 6-3: Use Pipelining .............................................................................. 6-35
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F. Exploring Four-Wire Handshaking ................................................................... 6-39

Lesson 7
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Debugging and Testing in FPGA

A. Debugging and Testing FPGA Code ................................................................ 7-3
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B. Investigating Additional Resources ................................................................. 7-7

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Appendix A
Additional Information and Resources
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Student Guide

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In this student guide, you will learn about the course

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description and the items you need to get started in this
course.

Topics
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A. Course Description
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B. What You Need to Get Started
C. Installing Course Files
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D. Course Goals
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Course Description
The Developing Embedded Applications Using CompactRIO and LabVIEW FPGA course is part of a
series of courses designed to build your proficiency with LabVIEW, LabVIEW Real-Time and LabVIEW
FPGA and help you prepare for exams to become an NI Certified LabVIEW Embedded Developer and
NI Certified LabVIEW Architect.

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The participant guide is divided into lessons. Each lesson contains the following:

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• An introduction with the lesson objective and a list of topics and exercises.
• Slide images with additional descriptions of topics, activities, demonstrations, and multimedia
segments.

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• A set of exercises to reinforce topics. Some lessons include optional and challenge
• exercises.

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• A lesson review that tests and reinforces important concepts and skills taught in the lesson.

B. What You Need to Get Started

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Before you use this exercise manual, make sure you have the following items listed below:

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Note Not all exercises require all the hardware and software listed below.

Software
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LabVIEW 2023 Q3 (32-bit)
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LabVIEW Real-Time Module 2023 Q1 (32-bit)
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• LabVIEW FPGA Module 2023 Q1 (32-bit)
NI-DAQmx 2023 Q3 (32-bit)
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• NI CompactRIO 2023 Q3 (32-bit)

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Hardware
• An NI CompactRIO from either the 904x or 905x product lines
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• USB Type C or RJ45 Ethernet connection

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• NI-9211 Thermocouple Input C Series Module

• NI-9474 Digital I/O C Series Module
• Windows 10 PC
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Developing Embedded Applications Using CompactRIO and LabVIEW FPGA course USB, containing
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the following folders:

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Directory Description

C:\Exercises\FPGA Folder containing files used in the course.

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C:\Solutions\FPGA Folder containing completed course exercises.

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© National Instruments Corporation | vii

 Student Guide

C. Installing Course Files

Complete the following steps to set up the course files.
1. Insert the course USB in your computer.
2. The USB flash drive includes two partitions: a read-only partition identified as a CD drive and a
read/write USB drive.

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3. Browse the CD drive and follow the readme file instructions to complete the setup.

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4. Use the USB drive partition to save your files.

File Locations

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• Exercise files are in the C:\Exercises\FPGA folder assuming that you copied the files on your root
directory.

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• Solution files are in the C:\Solutions\FPGA folder assuming that you copied the files on your root
directory.

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D. Course Goals
This course will strengthen your knowledge on the following:

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• Design, prototype, and deploy an embedded application.
• Implement functionality on FPGA using the LabVIEW FPGA module.
•

•
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Communicate data between the FPGA, RT, and PC.
Debug, benchmark, and test your application.
Deploy your application to multiple systems.
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1

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Programming

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Using LabVIEW

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FPGA

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Learn about FPGA common usages, how to work with
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them in LabVIEW, its user interfaces, compilation details

and basic optimizations.
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Topics
A. Introduction to FPGA
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B. Developing an FPGA VI
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C. Interactive Front Panel Communication

D. Selecting an Execution Mode
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E. Compiling an FPGA VI
F. Compilation Considerations
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G. Basic Optimizations

Exercises
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Exercise 1-1 Explore Simulation Execution Mode

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Exercise 1-2 Compile and Execute a VI

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Introduction to FPGA
Objective: Explore the composition and common uses of FPGAs.

FPGA Layout and Components

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Field-Programmable FPGAs are reprogrammable integrated circuits that contain an array of

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Gate Array (FPGA) programmable logic blocks. FPGA chip adoption is driven by their flexibility,
hardware-timed speed and reliability, and parallelism.

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Unlike processors, FPGAs are truly parallel in nature, so different processing operations do not have
to compete for the same resources. Each independent processing task is assigned to a dedicated
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section of the chip and can function autonomously without any influence from other logic blocks. As
a result, the performance of one part of the application is not affected when you add more processing.
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Every FPGA chip is made up of a finite number of predefined resources with programmable
interconnects to implement a reconfigurable digital circuit and I/O blocks to allow the circuit to access
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the outside world.

FPGA resource specifications often include the number of configurable logic blocks, the number of
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fixed function logic blocks such as multipliers, and the size of memory resources like embedded block
RAM. Of the many FPGA specifications, these are typically the most important when selecting and
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comparing FPGAs for a particular application. The configurable logic blocks (CLBs) are the basic logic
unit of an FPGA. Sometimes referred to as slices or logic cells, CLBs are made up of two basic
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components: flip-flops and look-up tables (LUTs). Various FPGA families differ in the way flip-flops
and LUTs are packaged together, so it is important to understand flip-flops and LUTs.
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© National Instruments Corporation | 1-3

 Lesson 1 Programming Using LabVIEW FPGA

How an FPGA Works

FPGA resource specifications often include the number of configurable logic blocks, the number of
fixed function logic blocks such as multipliers, and the size of memory resources like embedded block
RAM. Of the many FPGA specifications, these are typically the most important when selecting and
comparing FPGAs for an application.

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The configurable logic blocks (CLBs) are the basic logic unit of an FPGA. Sometimes referred to as
slices or logic cells, CLBs are made up of two basic components: flip-flops and look-up tables (LUTs).

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Various FPGA families differ in the way flip-flops and LUTs are packaged together, so it is important
to understand flip-flops and LUTs.

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Flip-flops are binary shift registers used to synchronize logic and save logical states between clock
cycles within an FPGA circuit. On every clock edge, a flip-flop latches the 1 or 0 (TRUE or FALSE)

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value on its input and holds that value constant until the next clock edge.

Much of the logic in a CLB is implemented using very small amounts of RAM in the form of LUTs. It
is easy to assume that the number of system gates in an FPGA refers to the number of NAND gates

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and NOR gates in a chip. But all combinatorial logic (ANDs, ORs, NANDs, XORs, and so on) is
implemented as truth tables within LUT memory. A truth table is a predefined list of outputs for every
combination of inputs.

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An FPGA is analogous to a printed circuit board that has many unconnected components.
Traditionally, the devices are connected with physical wires soldered to the pins with a wire wrapping
tool or embedded in the printed circuit board. The physical wires are difficult to modify. However, the
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connections in an FPGA circuit are dynamically defined in software when the LabVIEW code compiles
and the bitstream is downloaded. The bitstream causes semiconductor switches to turn on or off,
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thereby defining the connections between gates.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

NI Products with FPGA Targets

NI has implemented this powerful microprocessor and FPGA architecture in its FPGA-enabled devices.
These devices span many different form factors, from rugged to high-performance systems, all based
on the same architecture.

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sbRIO CompactRIO EtherCAT 9145

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FlexRIO Multifunction RIO Modular Instruments

Programming with LabVIEW FPGA na

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• The LabVIEW FPGA module turns LabVIEW into a high-level synthesis (HLS) design tool.
Clearly visualize and implement true parallelism.
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• No need for hardware description languages (HDLs) such as VHDL and Verilog.
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The emergence of graphical HLS design tools, such as LabVIEW, has removed some of the major
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obstacles to the traditional HDL (hardware description language) design process. The LabVIEW
programming environment is distinctly suited for FPGA programming because it clearly represents
parallelism and data flow, so users who are both experienced and inexperienced in traditional FPGA
design processes can leverage FPGA technology.

© National Instruments Corporation | 1-5

 Lesson 1 Programming Using LabVIEW FPGA

Embedded System Communication

• Each fixed I/O uses a portion of the FPGA hardware resources.
• The bus interface to the host computer (in this case, the RT processor) also uses a portion of the
FPGA hardware resources.
The real-time component is optional in many common system configurations.

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The icons on the FPGA graphic represent that some FPGA hardware resources are used for bus

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communication from FPGA to RT and for I/O communication.

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FPGA Common Use Cases

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These are some of the most common use cases for FPGA. With FPGA, you can describe any task that
you want to execute directly on your target at specific rates (usually high rates, MHz). When you
program an FPGA, you are describing the logic that the desired process will have to complete to
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function, so it is like defining a different custom chip every time you build the FPGA code.
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FPGAs are reconfigurable, which means that once you build an application describing the functionality
for your FPGA, you can then make updates or even redesign your FPGA if needed, which is excellent
to ensure continuous improvements and sustainability for the applications.
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Performance
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• Multi-loop analog PID loop rates exceed 100 kHz on embedded RIO FPGA hardware, whereas they
run at 30 kHz in real-time without FPGA hardware.
02

• Digital control loop rates can execute up to 1 MS/s or more, depending on the target.
• Single-cycle timed loops execute up to 200 MHz or more, depending on the target and clock
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configuration.
• Due to its parallel processing ability, adding additional computation does not necessarily reduce
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the speed of the FPGA application.

Note Maximum rates vary depending on application size, requirements, and HW resources
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available.
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Reliability
• Once the FPGA is programmed, it becomes a hardware chip with all the associated reliability.
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• Furthermore, it is highly deterministic. With an FPGA, you can implement code that synthesizes
deterministic hardware down to tens of nanoseconds.
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Reconfigurability
• Reconfigurable through software. Create a chip that is reconfigurable with changes in software,
creating new hardware at any time.

1-6 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

FPGA Common Use Cases

Using LabVIEW FPGA, you can describe the logic that you need for your application in less time than
you would normally spend developing FPGA code using descriptive languages such as VHDL. The
FPGA code is still directly downloaded to the FPGA on your target. Combining LabVIEW FPGA with
LabVIEW Real-Time, you can configure applications that are highly customizable and that excel in

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performance and determinism. You can get the most out of the resources available with readable code
and graphic design.

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The emergence of graphical HLS design tools, such as LabVIEW, has removed some of the major
obstacles to the traditional HDL design process. The LabVIEW programming environment is distinctly
suited for FPGA programming because it clearly represents parallelism and data flow, so users who

m
are both experienced and inexperienced in traditional FPGA design processes can leverage FPGA
technology. In addition, so that previous intellectual property (IP) is not lost, you can use LabVIEW to

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integrate existing VHDL into your LabVIEW FPGA designs.

Note Because LabVIEW FPGA is highly integrated with hardware, there is no need to

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rewrite code in VHDL to meet timing or resource constraints, as may be the case in many
HLS code generators.

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Then, to simulate and verify the behavior of your FPGA logic, LabVIEW offers features directly in the
development environment. Without knowledge of the low-level HDL language, you can create test
benches to exercise the logic of your design. In addition, the flexibility of the LabVIEW environment

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helps more advanced users model the timing and logic of their designs by exporting to cycle-accurate
simulators such as Xilinx ISim. LabVIEW FPGA compilation tools automate the compilation process,
so you can start the process with a click of a button and receive reports and errors, if any, as
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compilation stages are completed. If timing errors do occur because of your FPGA design, LabVIEW
highlights these critical paths graphically to expedite the debugging process.
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© National Instruments Corporation | 1-7

 Lesson 1 Programming Using LabVIEW FPGA

B. Developing an FPGA VI
Objective: Learn how to add a VI to the FPGA target in your LabVIEW project and explore some
commonly used FPGA palettes.

Adding VIs to the FPGA

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To create a new FPGA VI:

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a. Right-click FPGA Target in the Project Explorer window, then select New»VI.
b. Save the VI in the appropriate folder and save the project.

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Note In this example, the FPGA target lives under the compactRIO-9056 real-time target.
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In some applications, there will not be a real-time component of the LabVIEW project.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

FPGA Palettes Overview

• VIs under the FPGA target inherit the FPGA Function Palette.
• Some palettes have similar functionality as their LabVIEW for Windows counterparts do.
• FPGA-specific palettes include:

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• FPGA I/O
• Data Storage & Transfer

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• Synchronization
• FPGA Math & Analysis
• IP Integration

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FPGA I/O Palette

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I/O Node—Performs specific FPGA I/O operations on FPGA targets. You can configure the FPGA I/O
Node with one or more FPGA I/O items.
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I/O Constant—Use the FPGA I/O constant to specify an FPGA I/O item on the block diagram.

© National Instruments Corporation | 1-9

 Lesson 1 Programming Using LabVIEW FPGA

Communication Protocols—Use the Communication Protocols functions to access communication

protocols IP, available on the LabVIEW Tools Network page on ni.com. Each Communication Protocols
function corresponds to IP. Use the IP to establish communication between primary and subordinate
through different communication protocols, such as Inter-Integrated Circuit (I2C) and Serial Peripheral
Interface (SPI).

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I/O Methods—Invokes a method on an I/O item or hardware under an FPGA target in the Project
Explorer window, such as a C Series module. In some cases, you can also invoke methods on the

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FPGA target itself. The methods available depend on the FPGA target and the FPGA I/O item or
C Series module you select.

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I/O Property—Gets or sets one or more properties on an I/O item or hardware under an FPGA target
in the Project Explorer window, such as a C Series module. In some cases, you can also set and
retrieve properties on the FPGA target itself. The properties available vary by the FPGA target, the

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C Series module, and the I/O resource.

User-Controlled I/O Sampling—Use the User-Controlled I/O Sampling functions to perform I/O with

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more specific control over the I/O hardware than you have with the FPGA I/O functions.

cRIO I/O Device—Use the cRIO I/O Device to specify a cRIO I/O item on the block diagram.

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Resources For more information, refer to LabVIEW Help.

FPGA Math & Analysis Palette

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• Keep calculations as simple as possible to preserve FPGA resources.
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• Functions perform point-by-point calculations.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

• Analog Period Measurement—Calculates the period of an evenly sampled periodic signal using
threshold crossing detection. This Express VI accepts frames of data, performs measurement on
the input data, and returns a valid single result for each frame.
• Butterworth Filter—Filters one or more input signals using a lowpass or highpass IIR Butterworth
filter.

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• DC and RMS Measurements—Calculates the DC (mean) and/or RMS values of an input signal. You
can also use this Express VI to calculate the intermediate sum, mean square, or square sum values

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in order to save FPGA resources. This Express VI accepts frames of data, performs measurement
on the input data, and returns a valid single result for each frame.
• FFT—Computes the Fast Fourier Transform (FFT). The Single Channel, Single Sample input format

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computes the FFT point by point. The Single Channel, Multiple Samples input format allows you
to perform FFT analysis on a data stream with multiple samples/cycle.

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• Mean, Variance, and Standard Deviation—Calculates the mean, variance, and/or standard
deviation of an input signal. This Express VI analyzes discrete frames of data rather than analyzing
data continuously. This Express VI waits for N cycles to collect a frame of data before returning
one valid output, where N is the number of samples in each frame. It then waits for another N

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cycles to return another valid output.
• Notch Filter—Attenuates a specific frequency band in one or more input signals using a second
order IIR notch filter.

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• Rational Resampler—Provides a rational resampling filter that updates the input sample rate by an

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L/M factor, where L is an interpolation factor and M is a decimation factor.
• Scaled Window—Minimizes spectral leakage associated with truncated waveforms. This Express
VI scales the windowed time-domain signal so that when a LabVIEW object computes the power
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or amplitude spectrum of the windowed waveform, all windows provide the same level within the
accuracy constraints of the output wavelength.
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• Z-Transform Delay Node—Stores data from one VI execution or loop iteration to the next. This
node is the Feedback Node in z-transform view.
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• Control VIs—Use the Control VIs in FPGA VIs to create control applications for FPGA targets.
• Generation VIs—Use the Generation VIs in FPGA VIs to generate signals.
High Throughput Math Functions—Use the High Throughput Math functions to achieve high
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•
throughput rates when performing fixed-point math and analysis on FPGA targets.
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• Linear Algebra Functions—Use the Linear Algebra functions to perform vector and matrix
calculations in high-speed and high-throughput FPGA applications, such as RF applications.
• NI Floating-Point Library—Redirects to the LabVIEW Tools Network page on ni.com, where you
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can download a library of floating-point math operation functions. You can use these functions in
your FPGA application to minimize resource usage outside single-cycle Timed Loops or to optimize
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timing performance inside 40 MHz single-cycle Timed Loops.

• Utilities VIs—Use the Utilities VIs in FPGA VIs to perform various tasks such as detecting state
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changes of Boolean inputs, detecting zero crossings, delaying the input value, limiting the valid
range of a signal, and performing linear interpolation.
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© National Instruments Corporation | 1-11

 Lesson 1 Programming Using LabVIEW FPGA

Front Panel Considerations

• Hardware resources inside an FPGA are limited.
• Use the minimum necessary controls and indicators for programmatic front panel communication
between FPGA and RT.
Add temporary controls and indicators for debugging if necessary but remove them afterwards.

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•

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If you only need to transfer the latest values of data to or from a host VI, you can store the data in

the host VI.

Demonstration: Creating an FPGA VI

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controls or indicators on the FPGA VI and access this data using the Read/Write Control function in
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

C. Interactive Front Panel Communication

Objective: Explore the communication method between the FPGA and the host when running from
the front panel.

FPGA VI Overview: Front Panel and Block Diagram

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To communicate between the development PC and the VI running on the FPGA, use Interactive Front
Panel Communication.

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The FPGA has no true user interface; therefore:
Must communicate data from the FPGA to the host PC or rely exclusively on I/O.

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• Front Panel displayed on the host PC.

The block diagram executes on the FPGA as compiled.

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• The communication layer shares all control and indicator values.

• Cannot use debugging tools when running FPGA VI.

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• Test with the development computer first or add indicators as probes.

To programmatically control and communicate with FPGA VIs from RT (host) VIs, use Programmatic

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FPGA Interface Communication. The front panel data you receive during Interactive Front Panel
Communication is not deterministic.

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Top-Level FPGA VI Execution

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• Front panel displayed on PC.

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• Block diagram executes on the FPGA as compiled.

• The communication layer shares all control and indicator values through interactive front panel
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communication.
• Cannot use debugging tools when running an FPGA VI on the FPGA target.
Test with simulation on the development computer first or add indicators as probes.
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Note Avoid using large front panel arrays as a data storage mechanism – use VI-scoped
memory instead.

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 Lesson 1 Programming Using LabVIEW FPGA

D. Selecting an Execution Mode

Objective: Explore the different execution modes available in LabVIEW FPGA.

Execution Mode Overview

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To select an Execution Mode:
a. In the Project Explorer window, right-click FPGA Target»Select Execution Mode and select

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Simulation (Simulated I/O).
b. In the Project Explorer window, right-click FPGA Target and select Properties.
From the Execution Mode category, select Simulation and click OK.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

The Execution Mode category includes the following components:

• FPGA Target—Executes the FPGA VI on the FPGA target.
• Simulation—Specifies whether to Use Simulated I/O or Use Custom VI for FPGA I/O when
executing the FPGA VI on a development computer.
• Simulation with Real I/O—Executes the FPGA VI on the development computer using I/O from the

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FPGA target. Some FPGA targets do not support this option. Some FPGA targets that support this
option do not support all I/O resources.

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• Third-Party Simulation—Executes the FPGA VI in an installed third-party simulator. Select this
execution mode to enable cycle-accurate simulation.

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Testing with Simulation Execution Mode
You can run the FPGA VI in Windows to check the logic of the application before compiling. The

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development computer simulates the I/O operations but does not duplicate the hardware timing. The
development computer can use either simulated I/O or real I/O from the FPGA target. Simulated I/O
can be generated using random data or a custom VI.

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Troubleshoot using traditional debugging tools:
• Execution highlighting—Execution highlighting shows the movement of data on the block diagram

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from one node to another using bubbles that move along the wires.
• Single-stepping—Single-step through a VI to view each action taken by each VI on the block

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diagram as the VI runs.

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Probe tools—Use the Probe tool to check intermediate values on a wire as the VI runs.
Breakpoints—Use the Breakpoint Tool to place a breakpoint on a VI, node, or wire and pause
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execution at that location.
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When testing is complete, set the execution mode to the FPGA target so that the VI can be compiled
and tested on the FPGA target.
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 Lesson 1 Programming Using LabVIEW FPGA

Selecting an Execution Mode: Options

FPGA Target—The FPGA VI will execute on the FPGA target. Before running on the FPGA, the code
must be compiled.

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Simulation (Simulated I/O)—The FPGA VI will execute on the development computer using simulated
data for any I/O. You can either use random data for I/O reads or you can create and use a custom VI
to generate your simulated I/O.

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Note You can also simulate your FPGA VI with real I/O data using the Desktop Execution
Node. This is covered later in this course.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 1-1: Explore Simulation Execution Mode

Goal
Create an FPGA VI and verify the functionality of the VI using the development computer.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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• Windows 10 PC na
NI-9474 Digital I/O C Series Module
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Scenario
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The hardware is already configured in NI MAX. Before you begin development, you should create a
LabVIEW project that contains the proper configuration for an FPGA target. In this case, the FPGA
target is on the cRIO-9056.
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Create an FPGA VI that performs three parallel mathematical operations on two numbers. Compiling
an application can be very time-consuming, so you should make sure the code functions properly
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before compiling. In a simple application, such as this exercise, errors are unlikely. However, as you
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create more complex applications, it is important that you test the code on the development computer
before compiling. Testing on the development computer ensures that you detect and correct errors
before you begin a lengthy compilation.
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 Lesson 1 Programming Using LabVIEW FPGA

Implementation
1. Create a project:
a. Launch NI LabVIEW.
b. Select File»Create Project»Blank Project.

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• In the C:\Exercises\FPGA directory, create a new Executing a VI folder to save the
project in it.

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c. Select File»Save Project to save the project as Basic cRIO FPGA.lvproj in the
C:\Exercises\FPGA\Executing a VI directory.
d. Notice that the project contains the root and the My Computer target.

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2. Create the CompactRIO target:
a. In Project Explorer, right-click Project: Basic cRIO FPGA.lvproj and select

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New»Targets and Devices to display the Add Targets and Devices dialog box.

Note Be sure to right-click the Basic cRIO FPGA item and not the My Computer item.

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Right-click My Computer to add new targets. However, targets under My Computer must
be internal targets on the computer, such as PCI, PCIe, PXI, and PXIe devices.

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b. Select Existing target or device.
c. Expand Real-Time CompactRIO.
d. Select the cRIO-9056 Target.
e. Click OK.
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3. Verify the proper configuration of the project:
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a. In Project Explorer, expand cRIO-9056.
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b. Expand the Chassis.
c. Verify that a node exists for each corresponding module in your CompactRIO chassis.
For example, Mod1 (Slot 1, NI 9234).
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4. Save the project.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Create an FPGA VI and Execute the VI in Simulation Mode

Note The FPGA Target should be automatically added into the project. If not, right-click
the Chassis, then select New»FPGA Target.

1. Create a VI on the FPGA Target:

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a. Right-click FPGA Target and select New»VI.

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b. Save the VI as Simple Math in the C:\Exercises\FPGA\Executing a VI\Basic cRIO FPGA
directory.
2. Set the project to execute the VI in simulation mode:

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a. Right-click FPGA Target and select Select Execution Mode»Simulation (Simulated I/O).
b. The project should now resemble Figure 1-1.

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Figure 1-1. Basic cRIO FPGA.lvproj with VI in Simulation Execution Mode

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 Lesson 1 Programming Using LabVIEW FPGA

3. Build the Simple Math VI front panel shown in Figure 1-2.

Figure 1-2. Simple Math VI Front Panel

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1 2

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1 Numeric Controls—Search for Numeric Control in the Controls Palette.
2 Numeric Indicators—Search for Numeric Indicator in the Controls Palette.

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4. Complete the block diagram as shown in Figure 1-3.

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Figure 1-3. Simple Math VI Block Diagram
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1 Numeric Controls 3 Subtract Function 5 Numeric Indicators

2 Add Function 4 Multiply Function
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Test
1. Test the VI to verify functionality in simulation execution mode:
a. Open the front panel of the Simple Math VI and run the VI.
b. Test the functionality of the VI by using several different values for X and Y and verifying that
X+Y=, X-Y=, and X*Y= each return expected values.

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2. Use the debugging tools on the Simple Math VI.

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Another advantage of testing your VI in the simulation execution mode is that you can use the
standard LabVIEW debugging tools. The debugging tools help you quickly diagnose any errors that
may occur. After you download the application to the FPGA, you can no longer access these tools in

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the compiled application. It is good practice to debug the FPGA VI as much as possible before you
compile the VI for FPGA.

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a. Open the block diagram of Simple Math VI.
b. Click Highlight Execution on the toolbar to turn on execution highlighting.

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c. Update the values on the front panel.

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d. Run the VI and observe how the values update on the block diagram.

3. Turn off execution highlighting.

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e. Insert breakpoints and probes, and run the VI (optional).

4. Leave the VI and project open for use in the next exercise.
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End of Exercise 1-1
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 Lesson 1 Programming Using LabVIEW FPGA

E. Compiling an FPGA VI
Objective: Investigate the compilation process and details of the FPGA VI.

FPGA VI Compilation Overview

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Once you have finished the verification of the logic with all the tools available, like I/O Simulation and
the different debugging tools, you can continue with the compilation now that you are more certain
that it should work correctly in the FPGA.

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How the Compilation Process Works

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The following steps outline the process of compiling FPGA VIs:

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1. Start Compile—Start the compilation process via one of four previously mentioned methods.
2. Generation of Intermediate Files—LabVIEW converts the FPGA VI into intermediate files
(HDL [hardware description language] code) to send to the compile server.
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3. HDL compilation, analysis, and synthesis—The compile worker transforms intermediate files (HDL
code) into digital logic elements.
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a. Mapping—The compile worker divides the application logic between the physical building
block on the FPGA.
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b. Placing and Routing—The compile worker assigns the logic to physical building blocks on the
FPGA and routes the connections between the logic blocks to meet the space or timing
constraints of the compilation.
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4. Bitfile creation—LabVIEW saves the bitfile in a subdirectory of the project directory and may
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download and/or run the application on the FPGA VI.

Working with Build Specifications

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The Build Specification should be created before you can compile the FPGA VI into an FPGA
application. If you click the Run button without first making a build specification, LabVIEW
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automatically creates and specifies a default build specification for the corresponding VI. LabVIEW
uses the build options you set to generate the HDL and bitfile from the block diagram. If you create
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multiple build specifications, you can specify which is the default build specification. Right-click a build
specification under an FPGA target in the Project Explorer window and select from the following
options. The options can vary depending on the hardware target.
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To add a new compilation:

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a. In the Project Explorer window, under FPGA Target, right-click Build Specifications and select
New»Compilation.
b. From the My Compilation Properties dialog box, select Source Files category. Move the
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

You can compile an FPGA VI in LabVIEW using the following methods:

1. To check if there is a valid bitfile already created for the VI, click the Run button in the FPGA VI.
If so, LabVIEW immediately runs the FPGA VI in interactive mode using the existing bitfile. If the
FPGA VI has never been compiled or has changed since the last compile, the run arrow begins the
compile process and runs in interactive mode after finishing the compile.

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2. Press <Ctrl> and click Run to force a compile, compiling the VI regardless of the current state of
the bitfile. LabVIEW does not run the VI after finishing the compile.

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3. To check if there is a valid bitfile already created for the VI, right-click the Build Specification of
the VI in the project and select Build.
4. Right-click the Build Specification of the VI in the project and select Rebuild to force a compile,

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compiling a VI no matter which state the current bitfile is in. LabVIEW does not run the VI after
finishing the compile.

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Stages of the Compilation Process
Each step of the compilation process includes some subtleties and information you can use. NI

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exposes this information in a timely manner. You can use LabVIEW FPGA software to automatically
or manually stop the compilation at any time due to an error, an estimate out of bounds, or a
user-directed cancel.

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 Lesson 1 Programming Using LabVIEW FPGA

Generating Intermediate Files (HDL Code)

1. Start compilation.
2. Generating Intermediate Files window launches.
• Generates intermediate files.

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3. Once compilation starts, do not edit the VI.
4. Create a compilation queue by starting another compilation while the first is still running.

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Do not edit VI while compiling. Either abort the compilation or save the modified VI under a different
filename and perform your edits there. You can create a queue of compilations by opening another

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FPGA VI and starting a compilation for that VI while the first compilation is still running. Once the first
compilation finishes, the next will start.
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Compilation Status Window—Configuration Report
This type of report displays project information and the Xilinx compiler configuration you specified in
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the Xilinx Options page of the build specification.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Compilation Status Window—Device Utilization Report

This report is available after the compile server completes the synthesizing step of the compilation
process. This report contains a summary of the FPGA utilization as estimated during the synthesis of
the FPGA VI. This report includes the following information:
• Device Utilization—Indicates the FPGA element, such as slices, flip-flops, LUTs, and blocks of

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RAM.
• Used—Indicates how many of the FPGA elements the compiled FPGA VI uses.

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• Total—Indicates the total number of FPGA elements in the FPGA.
• Percent—Indicates the percentage of the FPGA elements that the FPGA application uses. If the
Percent is greater than 100, a warning message alerts you that the estimated device utilization

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exceeds 100 percent. Depending on the FPGA VI and hardware, Xilinx may still be able to fit
everything on the FPGA. However, you may want to stop the compilation and optimize the

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FPGA VI.

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 Lesson 1 Programming Using LabVIEW FPGA

Compilation Status Window—Timing Report

This report is available after the compile server completes the routing step of the compilation process.
The timing report contains a summary of the FPGA clocks, including the following information:
• Clocks—Indicates the FPGA clocks.
• Requested (MHz)—Indicates the clock rate, in megahertz, at which the FPGA VI or FPGA VI

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component must be able to run. Some FPGA VI components, such as Timed Loops, are visible on
the block diagram, while others, such as CLIP, are not. If Requested (MHz) is greater than

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Maximum (MHz), the compilation fails. Click Investigate Timing Violation to analyze the timing
violations.
• Maximum (MHz)—Indicates the theoretical maximum compilation rate, in megahertz, for the FPGA

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VI or FPGA VI component. For specific FPGA targets, the Xilinx compiler does not attempt to
optimize if a design meets the timing requirements.

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Compilation Status Window—Xilinx Log Report

This log file is available only after the compilation is complete. If you are familiar with Xilinx tools, you
might be able to use this file to troubleshoot compilation failures. Click the Save button to save this
information to a file.

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 Lesson 1 Programming Using LabVIEW FPGA

Compile Worker Window

This log file is available only after the compilation is complete. If you are familiar with Xilinx tools, you
might be able to use this file to troubleshoot compilation failures. Click the Save button to save this
information to a file.

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Use the FPGA Compile Worker window to view information about a compilation. This window contains
the following components:

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• Status—Displays status information for the current compilation job.
• Jobs—Displays information about the current compilation jobs.
• Configure—Displays the Configure Compile Worker dialog box.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 1-2: Compile and Execute a VI

Goal
Compile and execute a VI on an FPGA target.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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• Windows 10 PC na
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Scenario
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Compile Simple Math VI from Exercise 1-1 to run on the cRIO-9056 FPGA. The compile server
converts Simple Math VI to a bitstream file, which can be loaded and executed on the FPGA.
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Implementation
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Part A
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Modify Basic cRIO FPGA.lvproj to execute Simple Math VI on the FPGA target and start the
compilation process:
1. From the C:\Exercises\FPGA\Executing a VI directory, open Basic cRIO FPGA.lvproj.
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2. From Project Explorer, right-click cRIO-9056»Chassis and select Deploy to deploy the chassis
settings.
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3. Set the project to execute the VI on the FPGA target:

a. Right-click FPGA Target (RIO0, cRIO0-9056) and select Select Execution Mode»FPGA Target.
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 Lesson 1 Programming Using LabVIEW FPGA

b. The project should now resemble Figure 1-4.

Figure 1-4. Basic cRIO FPGA.lvpoj with VI in FPGA Target Execution Mode

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4. Compile the Simple Math VI:

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a. Open and run Simple Math VI. When executing on the FPGA target, click Run in LabVIEW to
start the compilation. Use the local compile server to specify that LabVIEW use the compilation
tools installed on the local computer, called localhost.
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When compilation begins, LabVIEW launches the Compilation Status window.

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Note You may see a Windows Security Alert dialog box if a Windows firewall is blocking
the compile server. Click Unblock when prompted to continue compilation.
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b. Notice that LabVIEW automatically created a Build Specification for the Simple Math VI in
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Project Explorer under FPGA Target»Build Specifications.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Part B
When the compilation is complete, examine the generated reports and test the VI on the FPGA. The
Compilation Status window indicates when the compile has finished, as shown in Figure 1-5.

Figure 1-5. Compilation Status Window—Compilation Completed

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5. Examine the reports generated during compilation. Depending on your specific FPGA target, you
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can select the following reports from the Reports pull-down menu:
a. In the Compilation Status window, Summary is selected by default and is available only when
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the compilation is complete. This report contains a summary of the generated bitfile.
b. Configuration—This report displays project information and the Xilinx compiler configuration
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for the FPGA VI.

c. Estimated device utilization (pre-synthesis)—This report contains a summary of the FPGA
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utilization as estimated before the synthesis of the FPGA VI. Take particular note of the
Percent field, which indicates the percentage of the FPGA elements that the VI uses. If any
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Percent value exceeds 100 percent, then the compilation may fail.

Note The Compilation Status window for the cRIO-9056 does not have this item.
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 Lesson 1 Programming Using LabVIEW FPGA

d. Estimated device utilization (synthesis)/Estimated device utilization (placement)—This report

contains a summary of the FPGA utilization as estimated during the synthesis of the FPGA VI.
Take particular note of the Percent field, which indicates the percentage of the FPGA elements
that the VI uses. If any Percent value exceeds 100 percent, then the compilation may fail.
e. Final device utilization (map)/Final device utilization (placement)—This report contains a
summary of FPGA utilization as estimated during the mapping step of compilation.

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f. Estimated timing (map)—This report contains a summary of the FPGA clocks, as estimated

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during the mapping of the FPGA VI.
g. Final timing (place and route)—This report contains a summary of the FPGA clocks after the
routing step of compilation.

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6. Close the Compilation Status window.

Test

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1. Run the VI:
a. Change the X and Y values and click Run.

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2. Save and close Simple Math VI.
3. Save and close Basic cRIO FPGA.lvproj.

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End of Exercise 1-2

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

F. Compilation Considerations
Objective: Explore other compilation methods and error.

What Causes a Recompile?

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Moving wires on the block diagram is considered a cosmetic change. If the FPGA VI has any
non-cosmetic changes, then LabVIEW will recompile your VI on the next run. Here are some examples:

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• Change the algorithm on the block diagram.
• Add or delete functions on the block diagram.
• Rename control or indicator.

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• Add control or indicator.

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Compiling an FPGA VI Remotely: Select a Compile Server
At the start of each compilation, LabVIEW will ask you to select a compile server unless configured
otherwise.

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Use the Select Compile Server dialog box to specify a compile server for the current build specification.
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To access this dialog box, select Build from the Build Specification shortcut menu. LabVIEW displays
this dialog box by default.
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To disable the Select Compile Server prompt, select Tools»Options to display the Options dialog box
and select FPGA Module from the Category list, then remove the checkmark from the Prompt to select
a compile server for each compilation checkbox.
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• Use the local compile server—Specifies that LabVIEW uses the compilation tools installed on the
local computer, called localhost.
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• Connect to a network compile server—Specifies that LabVIEW uses the compilation tools installed
on another computer or that LabVIEW uses localhost when authentication is required.
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• Compile server name—Displays the name or IP address of the computer running the compile
server.
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• User name—Displays the name of the account that you use to log into the compile server.
• Configure—Displays the Configure Remote Compile Server dialog box.
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 Lesson 1 Programming Using LabVIEW FPGA

• Connect to LabVIEW FPGA Compile Cloud Service—Specifies that LabVIEW uses the compilation
tools available through the LabVIEW FPGA Compile Cloud Service.
• User name—Displays the name of the account that you use to log into the LabVIEW FPGA
Compile Cloud Service.
• Configure—Displays the Configure Cloud Service dialog box.

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• Prompt to select a compile server for each compilation—Specifies whether LabVIEW prompts you
to select a compile server for each compilation.

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Compiling an FPGA VI Remotely: LabVIEW FPGA Compile Cloud Service
This LabVIEW FPGA Compile Cloud Service is included in Standard Service Program (SSP) contracts

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for no additional fee. If you have an active SSP, NI recommends that you use this service. It allows
you to offload your FPGA compilations to high-performance servers and workers in the cloud for faster

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compilation times. You can also execute multiple parallel compilations using this service.

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Compiling an FPGA VI Remotely: Offload to Your Own Remote Computer

You can compile an FPGA VI on a computer other than the development computer. You might want
to do this if the development computer is slow or does not have enough memory to compile the VI for
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the FPGA device. Also, the compilation tools require several GB of hard drive space, so you can save
hard drive space. By default, LabVIEW assumes the LabVIEW FPGA Compile Server is installed on the
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Compiling an FPGA VI Remotely: Offload to Your Own Compile Farm

A compile farm consists of an on-site compile server and one or more on-site compile workers that
multiple developers can target.

Process Overview:

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1. You can create an FPGA VI on a development computer and click the Run button in LabVIEW.
2. LabVIEW submits the compile job to the compile server.

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3. The compile server sends the compile job to an available compile worker, which compiles the
FPGA VI.
4. The compile worker submits the compiled VI back to the compile server.

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5. The compile server submits the compiled VI back to the development computer. The FPGA VI is
ready to deploy to the FPGA target.

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Compiling an FPGA VI Remotely: Causes of Compilation Failure

Timing—Delays in the designed circuit exceed the period of the specified clock.
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Resource utilization—The design requires more FPGA resources than are available on the FPGA.
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FPGA VIs are limited primarily in two areas:

Speed—Relates to the actual execution speed of the FPGA gates. If the code does not execute at
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•
the loop rate you want, you must modify the application to increase the loop rate. These
modifications can change the way you create and design the FPGA VI.
Size—Relates to the actual amount of space the application uses on the FPGA. If the application
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requires more hardware components than are physically available on the FPGA, the compile fails,
and the application cannot run on the FPGA.
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 Lesson 1 Programming Using LabVIEW FPGA

Compiling an FPGA VI Remotely: Xilinx Compiler Options

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Use the Xilinx Options page to define the Xilinx options to use when you compile an FPGA VI. The
options you can specify vary depending on the target. In general, you do not need to adjust the options
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on this page unless the FPGA VI fails to compile. Use the information from the Compilation Status
window to determine which options on this page might help the FPGA VI compile successfully.
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refer to the Xilinx Documentation.
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The Xilinx Options page contains the following components:

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• Use recommended settings—Specifies that the Xilinx compiler uses the options that the target
provides. By default, this checkbox contains a checkmark. Remove the checkmark to customize
Xilinx options on this page.
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• Design Strategy—Specifies a set of Xilinx options for the application. You can select from preset
configurations to minimize the compilation time, maximize timing performance, or optimize the
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design area. You can override any of the options of a design strategy to create a custom
configuration.
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• Balanced—Selects options that balance the compilation time with the amount of effort the
Xilinx compiler uses to meet the timing and design objectives of the FPGA application.
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• Minimum Compilation Time—Selects options that minimize the compilation time by reducing
the mapping effort of the Xilinx compiler.
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• Timing Performance—Selects options that maximize the timing performance of the FPGA
application.
• Area—Selects options that optimize the area usage on the FPGA.
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• Custom—Indicates that options might not match any of the preset configurations.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

G. Basic Optimizations
Objective: Learn common techniques to optimize FPGA performance and the compilation time.

Basic Optimization Overview

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These types of optimizations are relatively easy to implement:
• Require no major changes in code architecture.

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• Should be basic programming practice for all FPGA VIs.

Limit Front Panel Objects on Top-Level VI

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When data is transferred across the bus between the FPGA and RT, it must be broken down into 32-bit
packets. This limitation is due to the number of data transfer lines on the bus. Therefore, if you have

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a front panel element that uses more than 32 bits, then that front panel element must be broken down
into several 32-bit chunks and passed along the bus piecewise. This breaking down of the data
reduces overall transfer speeds, and as such, having larger front panel objects should be avoided.

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Limit Front Panel Arrays
• Avoid using arrays on the front panel.

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• All arrays must be of fixed size.
Compile fails if the array size is larger than available FPGA resources.

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• Can quickly use large amounts of FPGA resources.

• Each bit in the array uses its own flip-flop on the FPGA.
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You can use a DMA FIFO to transfer the array between the FPGA and RT. Arrays consume significant
space on the FPGA because each bit in the array uses a flip-flop on the FPGA. Consider replacing
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arrays with FIFOs or memory items to transfer data.

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When you wire an array as an input to an FPGA VI or function, the FPGA compiler creates the
equivalent of a For Loop to process each element of the array in sequence. If you wire a cluster as an
input to an FPGA VI or function, the FPGA compiler creates parallel logic for each element of the
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cluster. The relationship between arrays and clusters is recursive, such that if you wire a cluster of
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arrays as an input, the arrays are processed in parallel, and the array elements are processed
sequentially.

Note Performing operations on arrays can limit the maximum top-level or derived clock
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rate. To maximize the FPGA clock rate, process single data points instead of arrays.
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© National Instruments Corporation | 1-37

 Lesson 1 Programming Using LabVIEW FPGA

Bitpack Boolean Logic

Each control has enabled chain overhead in addition to the size of the data type. This additional
overhead requires the use of additional logic on the FPGA. By bitpacking Boolean logic, you remove
this overhead.

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Bitpacked logic maintains the same information using fewer controls:
• Display binary data as an integer.

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• The U8 numeric control can replace eight Boolean controls.
• Use a Boolean array or cluster.
• Due to the small size of Boolean controls/indicators, this is an acceptable exception to the rule of

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avoiding arrays/clusters on the front panel.

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You can use functions to manipulate data in the same manner as you would otherwise.

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Using Small Data Types

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Choose the smallest feasible data type for a given control or indicator.
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In this example, the case selector can be reduced in size from an I32 (32-bit signed integer) to an U8
(8-bit unsigned integer) while maintaining the desired case selector values.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Eliminate Coercion Dots

Whenever a coercion dot is used, it means that the complier must determine the proper data type,
which can lead to inefficient conversion of data. Instead of leaving the coercion to chance, it is better
to directly specify the desired data type and insert the appropriate coercion function any time that you
see a coercion dot on your block diagram.

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Avoid Large Functions: Quotient & Remainder
• Consumes significant space on the FPGA:

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• Quotient & Remainder often used to increment based on iteration number.
Consider replacing with actual Increment function and Shift Register.

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 Lesson 1 Programming Using LabVIEW FPGA

Avoid Large Functions: Scale by Power of 2

If you need to divide by a power of two, use the Scale By Power of 2 function with a negative constant
wired to the n input.

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Additional Resources

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Topic Website

Execute Verilog or VHDL Code on NI LabVIEW FPGA KnowledgeBase

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FPGA Fundamentals: Basic of Field-Programmable Gate Arrays

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LabVIEW FPGA Compilation Process: From Run Button to Bitfile

Installing and Activating LabVIEW FPGA Compile Server on a Remote

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Computer KnowledgeBase

Interpreting Common Xilinx Compilation Errors in the LabVIEW FPGA

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Module
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Storing Data on an FPGA Target

LabVIEW Help
Compiling an FPGA VI Remotely (FPGA Module)
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. Which Execution Mode should you use to first test the functionality of FPGA VI?
a. FPGA Target
b. Simulation

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2. Is the statement true or false?
A bitfile (.lvbitx) is generated when an FPGA VI compiles successfully.
a. True

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b. False

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3. Which of the following practices are the best ones when developing FPGA VIs?
Select all that apply.

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a. Avoid large functions such as Quotient & Remainder, if possible.
b. Choose the smallest data types required for your application.

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c. Use as many front panel objects and array indicators as possible on top-level FPGA VIs.

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 Lesson 1 Programming Using LabVIEW FPGA

Activity: Lesson Review—Answers

1. Which Execution Mode should you use to first test the functionality of FPGA VI?
a. FPGA Target
b. Simulation

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2. Is the statement true or false?
A bitfile (.lvbitx) is generated when an FPGA VI compiles successfully.
a. True

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b. False

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3. Which of the following practices are the best ones when developing FPGA VIs?
Select all that apply.

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a. Avoid large functions such as Quotient & Remainder, if possible.
b. Choose the smallest data types required for your application.

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c. Use as many front panel objects and array indicators as possible on top-level FPGA VIs.

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 ts
2

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Using FPGA I/O

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and Timing

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Explore techniques for accessing and controlling I/O as well
as the timing of the FPGA VI.
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Topics
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A. Configuring FPGA I/O
B. Exploring I/O Types
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C. Exploring Analog CompactRIO I/O

D. Handling FPGA I/O Errors
E. Setting Loop Execution Rates
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F. Synchronizing C Series Modules

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G. Creating Delays between Events

H. Measuring Time between Events
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I. Benchmarking Loop Periods

Exercises
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Exercise 2-1 Acquire Tachometer and Acceleration Signals

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Exercise 2-2 Benchmark the Actual Loop Period

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Configuring FPGA I/O

Objective: Learn how to add the FPGA I/O to your project and access it from your VI.

Accessing FPGA I/O

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• Use FPGA I/O items to access I/O in the FPGA VI.
• In the NI Example Finder, navigate to

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Toolkits and Modules»FPGA»CompactRIO»Module Specific IO.

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Inputs and outputs (I/O) on FPGA targets allow you to connect the FPGA target to other devices. FPGA
I/O resources are fixed elements of the FPGA targets that you use to transfer data among the different
parts of the system. On some FPGA targets, FPGA I/O resources correspond to lines on front panel

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connectors, PXI backplanes, or RTSI connectors. On other FPGA targets, FPGA I/O resources are
nodes inside FPGAs that connect the part of the FPGA designed by NI with the part of the FPGA you
design through FPGA VIs. For component-level IP (CLIP), I/O resources are nodes inside FPGAs that

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connect CLIP with the FPGA VI. Each FPGA I/O resource has a specific type, such as digital or analog.
An FPGA target might have multiple I/O resources of the same or different types. You can create FPGA

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I/O items, determine the I/O resources on the FPGA target that you want to use, and then assign
unique names to the I/O resources you use.
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Note Refer to the specific FPGA target hardware documentation for information about
supported features and I/O functionality on the FPGA target you use. Refer to Managing
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Shared Resources for information about arbitrating I/O resources.

Resources For more information, refer to the Using FPGA I/O (FPGA Module) section from
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LabVIEW FPGA Module Help on ni.com.

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 Lesson 2 Using FPGA I/O and Timing

Adding FPGA I/O to a CompactRIO Project

• If using CompactRIO, detect modules when you add your chassis.
• All FPGA I/O added automatically.
• If using R Series modules, manually add FPGA I/O.

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• Select which FPGA I/O channels you want to add.

Some developers find it simpler to see all available channels at all times, whereas others prefer to only

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have the project contain the channels necessary for their application. Neither method creates more
efficient code than the other, so using all FPGA I/O channels is a matter of preference. You can also
use the FPGA Project Wizard to create your project. In this case, all FPGA I/O is added automatically.

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After select to add an Existing Target for a CompactRIO target from the Add Targets and Devices

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dialog box, you will be prompted with the Discover C Series Modules? dialog box. Selecting Discover
will halt any current FPGA execution and then add all the channels in all the modules. If you do not
want to halt your current execution or you do not want to add all the channels in all the modules,
select Do Not Discover. You can manually add each module and channel to your Real-Time project,

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as shown in the following images.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

To manually add FPGA I/O to your project:

1. Right-click the FPGA Target from Project Explorer and select New»FPGA I/O to launch the
New FPGA I/O dialog box.
2. Select I/O in the left pane of the New FPGA I/O dialog box.
3. Click the right arrow button to add the I/O to the project.

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4. To name your I/O, click the default name and enter a meaningful name for your application.
5. Click OK to add the I/O to the project.

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 Lesson 2 Using FPGA I/O and Timing

FPGA I/O Palettes

The FPGA I/O palette includes the following functions for configuring the I/O hardware:
• FPGA I/O Node—Reads or writes data from or to the FPGA I/O.
• FPGA I/O Constant—Specifies an FPGA I/O item on the block diagram.
FPGA I/O Method Node—Invokes an I/O method for a specific channel or C Series module.

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• FPGA I/O Property Node—Reads or sets property attributes of a specific channel or C Series

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module.

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Demonstration: Placing I/O Nodes
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

B. Exploring I/O Types

Objective: Explore the available FPGA I/O types, how to select and configure them.

I/O Types Overview

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The I/O types you can access and use with your FPGA are the following:
• Digital Line—Writes and/or reads Boolean value to/from digital line.

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• Digital Port—Writes and/or reads unsigned integer value to/from digital port (grouping of digital
lines).

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R Series—Integer values
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Analog I/O—Writes or reads data to/from an analog channel.

CompactRIO—Fixed-point values (can revert to integer)

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• Other
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• Motion
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• CAN
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© National Instruments Corporation | 2-7

 Lesson 2 Using FPGA I/O and Timing

Exploring Digital I/O

The data type of the digital port will depend on the number of lines in the port. Some CompactRIO
modules are unidirectional, and others are bidirectional. Refer to the hardware manual for the
capabilities of specific modules.

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If the digital I/O line or port is bidirectional and you want to change the direction of the line or port
from the FPGA VI, use the I/O Method Node and select Set Output Enable method.

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Creating Counters from Digital I/O
Counters can range from simple event counters to complex signal measurements with multiple inputs
and outputs. You can build a simple event counter with the FPGA I/O Method Node function in a While

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Loop. For example, you can use the Wait on Rising Edge method to wait for a rising edge to occur on
a digital input terminal.

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When the FPGA I/O Method Node detects an edge, the block diagram increments the counter value
and stores the counter value in a shift register on the While Loop. You can use a front panel indicator
or local variable to view the counter value.
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Note The I/O resources available and the associated methods vary by target and
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configuration. Refer to the specific FPGA target hardware documentation for information
about available methods and I/O resources.
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You can also build more advanced counters from the FPGA I/O functions. For example, an application
might require a counter with independent count up, count down, and gate inputs and an output.
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Resources For related examples, refer to Toolkits and Modules»FPGA»

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CompactRIO/R Series»FPGA Fundamentals»Counters in the NI Example Finder.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exploring Analog I/O

• Different devices have different default data types for analog I/O.
• PCI/PXI R Series devices return data as an unscaled 16-bit or 32-bit signed integer
(e.g., -32768 to 32767).
CompactRIO modules and USB R Series return fixed-point data in engineering units

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•
(voltage, ohms, etc.).

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If the FPGA target you use includes analog input resources, you can configure an FPGA I/O Node to
read an analog input value. If you configure the FPGA I/O Node to read an analog input, the FPGA I/O
Node might initiate a conversion, wait for the result, and then return the binary representation of the

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voltage as a signed integer or fixed-point number. The analog input process and the resulting data type
vary by FPGA target. For many FPGA targets, you create the FPGA VI to use the data returned by the
analog input FPGA I/O Node for operations within the FPGA VI. You can also pass the data back to

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the host VI and, if applicable, convert the data to a voltage or other physical quantity if you have a
transducer attached to the FPGA target analog input.

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The equation you use to convert the binary representation to a physical quantity depends on the FPGA
target and transducer. For example, with an NI PXI-7831R device, use the following equation to
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convert the binary representation to voltage: Input Voltage = (Binary Code / 32768) x 10.0 V.

Resources For more information, refer to the specific FPGA target hardware
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documentation.
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 Lesson 2 Using FPGA I/O and Timing

Exploring R Series Analog I/O

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All R Series multifunction devices have dedicated ADCs and digital-to-analog converters (DACs) on
every analog input/output channel, making it possible to sample/update all channels simultaneously or
at different rates. With independent ADCs, you can sample every channel on the device at the

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maximum rate (up to 1 MS/s). You can program the independent DACs to update analog output
channels at rates up to 1 MS/s.

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By using a LabVIEW FPGA Analog Input I/O Node that is reading from all eight channels of the R Series
device in the same While Loop, the program samples from all eight channels simultaneously. The lower
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loop running in parallel uses the LabVIEW FPGA Analog Output I/O Node and updates all eight analog
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

C. Exploring Analog CompactRIO I/O

Objective: Learn how to access I/O and explore the available data types and configurations the
C Series modules provide.

Using CompactRIO I/O

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• Analog Input and Analog Output modules use fixed-point data type.

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• Fixed-point data type:
• Provides some of the flexibility of floating-point data type.
• Maintains the size and speed advantages of integer arithmetic.

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Using CompactRIO I/O
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Different modules can have:
Fixed-point configurations
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• FPGA I/O Methods

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• FPGA I/O Properties

Module Data Types

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The fixed-point data type is a more efficient (for FPGA size and speed) implementation of floating-point
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data than the DBL/SGL data type. Different modules have different fixed-point configurations because
each module data has different ranges and resolutions. Some I/O nodes return scaled and calibrated
fixed-point values. The presented example shows that the data type of each of these three different
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modules has a different fixed-point configuration.

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© National Instruments Corporation | 2-11

 Lesson 2 Using FPGA I/O and Timing

Module Properties and Methods

Different modules have different properties and methods.
• The NI 9263 is an Analog Output module.
• The NI 9233 is an Analog Input module.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

D. Handling FPGA I/O Errors

Objective: Explore techniques to manage errors on the FPGA.

Access Error Wires from I/O Nodes

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You can right-click the FPGA I/O Node on the block diagram and select Show Error Terminals from the
shortcut menu to add standard LabVIEW error in and error out parameters to the function. If an error
occurs, you might receive incorrect data. Add error terminals to make sure the data you receive is

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valid. FPGA targets might report errors differently.

Resources For more information, refer to the specific FPGA target hardware

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documentation.

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Note Adding error in and error out parameters increases the amount of space the function
uses on the FPGA target. The error in and error out parameters can also cause slower
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execution on the FPGA target.

Error Clusters for Optimization

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Showing error terminals and processing errors uses FPGA resources. When resources are tight:
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• Use sequence structures for data flow. This has minimal cost on the FPGA.
• Show error terminals only for modules whose functions are critical to system operation.
• Show terminals only once per module if multiple calls are made to the module. The exception to
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this rule is for modules that have specific errors. Checking once allows you to check for general
errors.
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• Do not pass error clusters through the program or display the error cluster on the front panel.
• Unbundle the source and/or code items and handle the errors immediately.
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 Lesson 2 Using FPGA I/O and Timing

Error Clusters for Reliability

Examples of FPGA I/O errors that need to be handled:
• Any safety-critical operations
• Module-specific error codes for different CompactRIO modules
File not found (NI-9802)

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• Timeout (CAN modules)

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• CompactRIO modules and USB R Series
• Return fixed-point data in engineering units (voltage, ohms, etc.)

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Resources For more information regarding module-specific errors, refer to the
CompactRIO Error Codes (FPGA Interface) topic in LabVIEW Help. Checking for errors

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

E. Setting Loop Execution Rates

Objective: Explore functions and configurations to control the loop timing of the FPGA VI.

Timing Express VIs

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The Timing palette contains most of the FPGA timing Express VIs, except those related to the Timed
Loop. Timing control is critical to your FPGA application. The timing Express VIs include the Loop
Timer, Wait, and Tick Count Express VIs.
3
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Loop Timer Express VI—Use the Loop Timer Express VI to control a For Loop or While Loop and set
the iteration rate of the loop. A common use of the Loop Timer Express VI is to control the acquisition
or update rate of an analog or digital I/O function.
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Wait Express VI—Adds an explicit delay between two operations on the FPGA. Use the Wait Express
VI to control the pulse length of a digital output or add a trigger delay between the trigger signal and
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the resulting operation.

Tick Count Express VI—Returns the current value of the FPGA clock. Use the Tick Count Express VI
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to benchmark loop rates or create your own custom timers.

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 Lesson 2 Using FPGA I/O and Timing

Timing Express VIs Counter Considerations

Rollover Size of Internal Counter determines the maximum time the timer can track.

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Consider the possibility for the counter to rollover, meaning that it will go back to 0 after it reaches
its maximum count.

Each timing Express VI has a configuration dialog box that appears when you first add the VI to the

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block diagram or when you right-click the VI and select Properties. The dialog box allows you to
configure the timing units and the size of the internal counter. The available Counter Units include

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ticks, a single clock cycle, the length of which is determined by the clock rate for which the VI is
compiled, microseconds (µs), and milliseconds (ms). The Size of Internal Counter value determines the
maximum time the timer can track. The free running counter rolls over when it reaches the maximum
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of Size of Internal Counter specified in the configuration dialog box. To save space on the FPGA, you
should use the smallest Size of Internal Counter possible for the FPGA VI.
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Tick Period:
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• Based on the frequency of the FPGA clock.

• Uses a 40 MHz FPGA clock, the tick period is 25 ns.
Must use ticks for nanosecond timing.
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•
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Timing Express VIs

Waits the value you specify in Count between loop iterations. You can call this function in a loop to
control the loop execution rate. If an execution instance is missed, such as when the logic in the loop
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takes longer to execute than the specified interval, the Loop Timer Express VI returns immediately and
establishes a new reference time stamp for subsequent calls. To manage execution rates with the
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Loop Timer Express VI, place the Loop Timer Express VI in the first frame of a Flat Sequence structure
or a Stacked Sequence structure and put the rest of the code in subsequent frames.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Configuring Loop Timer Express VI

Counter Units:
• Ticks—clock cycles
• µSec—microseconds

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• mSec—milliseconds

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Size of Internal Counter:
• 32 Bit
• 16 Bit

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• 8 Bit

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Size of Internal Counter determines the maximum time a timer can track. To save space on the FPGA,
use the smallest Size of Internal Counter possible.

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Timing Express VIs Execution

First iteration:
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• Records current time as initial time.

• Immediately executes the code in the next frame without any delay.
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Second iteration:
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• Adds Count to initial time and waits until Count has elapsed from the initial recorded time.
• Executes the code in the next frame after Count has elapsed.
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Subsequent iterations:
• Loop Timer continues to increment the time record it initiated upon the first call.
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© National Instruments Corporation | 2-17

 Lesson 2 Using FPGA I/O and Timing

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The Loop Timer Express VI functionality here is like the Wait Until Next ms Multiple function that you

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may be familiar with already in regular LabVIEW on Windows.

The second execution adds timer count to the initial time and waits until count has elapsed.

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If Loop Timer is parallel to code in the loop (meaning no sequence structure):

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• The first iteration is not guaranteed to be synchronized with the desired timing.
• Code in a loop can execute twice within the first desired loop time.
• Subsequent iterations match the desired timing synchronization.

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If an execution instance is missed, such as when the logic in the loop takes longer to execute than the
specified Count:

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• Loop Timer returns immediately and establishes a new reference time stamp for subsequent calls.
• No delay.

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In the presented example, the Loop Express VI behavior is not the same as the Wait Until Next ms
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Multiple function.
1. Count = 100
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2. For the first three iterations, the code execution time is less than 100.
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3. On the fourth iteration, the code execution time is longer than Count (100). Therefore, on the next
iteration, the Loop Timer Express VI detects that an execution instance was missed, returns
immediately, and establishes a new reference time stamp for subsequent calls.
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If the time specified by the Count is less than the time it takes the FPGA target to execute the code
in the While Loop, the Loop Timer VI does not affect the timing of the While Loop.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

C Series Module Specific Rates

• Some cRIO modules have configurable timing.
• Do not need to use Loop Timer Express VI to time loop rate.
• Example: NI-9234

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• You can configure the data rate at which the NI-9234 module acquires and returns data.
• Static/Programmatic Configuration

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• Module Properties dialog box
• FPGA I/O Property Node

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Programmatic Configuration of NI-9234 Data Rate

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C Series Module Specific Rates Summary

• Using module specific rates, loop timing is not needed.
• Loop execution would be driven by the module specific rate.
• Additional processes in your code may slow down the overall execution.

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Loop Condition Terminals

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When programming the FPGA you can connect a False constant to the Loop Condition Terminal to
have that code execute indefinitely on the FPGA or until it is powered off. You need to take into
account that there will not be a way to stop that code from executing if you do so, other than removing
power from your device.

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While Loop Iteration Terminal Maximum na
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• The iteration terminal count will keep outputting 2,147,483,647 once it reaches this value.
• If you need a counter to rollover when it reaches its maximum value, you should implement your
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own counter.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 2-1: Acquire Tachometer and Acceleration Signals

Goal
Acquire and time FPGA I/O in a While Loop.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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• Windows 10 PC na
NI-9474 Digital I/O C Series Module
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Scenario
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You are presented with a LabVIEW project that has been started for you which you will complete
throughout various exercises in this course. Review the design requirements for our fan control and
monitoring project and then proceed to the implementation section.
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The application requirements state that this application must acquire the fan acceleration data at a
rate of 10.240 kHz. In this exercise, you will implement a process to acquire the tachometer and
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acceleration signal from the NI 9234 on the FPGA at a loop rate of 10.240 kHz. This module uses the
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Data Rate FPGA I/O property to implement its timing.

Functional Requirements for Fan Embedded Control and Monitoring Application Using LabVIEW
Real-Time and LabVIEW FPGA:
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• Control the fan speed using a PID control loop—This application must read the user-specified
fan speed setpoint, acquire the tachometer signal, calculate the actual fan speed, and use a
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PID algorithm to calculate the analog voltage level to output to set the fan speed to the
user-specified setpoint. This entire control algorithm must execute at a rate of 5 kHz. The PID
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loop period must be 200 microseconds with a maximum jitter of 10 microseconds. The fan
speed control is critical because you must protect the fan, so the fan speed control algorithm
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will be implemented in hardware for maximum reliability and safety.

• Acquire fan acceleration data—This application must acquire the fan acceleration data at a rate
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of 10.240 kHz.
• Analyze fan acceleration data—This application must convert the acceleration data to units of
g and determine if the acceleration has exceeded the maximum threshold.
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• If a failure condition occurs, the application must implement safe state logic within 200 microseconds reliably—Safe state logic must
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Lesson 2
set all outputs to a safe level to turn off the fan. The safe state logic is critical because you must protect the fan, so the safe state
logic should be implemented in hardware circuitry for maximum reliability and safety. Failure conditions have the following reasons:
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• Acceleration exceeds the maximum acceleration threshold.

Using FPGA I/O and Timing

• Fan speed exceeds the maximum fan speed threshold.

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• NI 9234 analog input module or NI 9263 analog output module outputs an error.
• If the fan acceleration exceeds the maximum threshold, then implement safe state logic, log the acceleration waveform to file, and
display the latest over-limit acceleration waveform to the user interface on the Windows PC—Each acceleration waveform must

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contain 2 seconds of data acquired at 10.24 kHz. The application must create a separate log file each time the fan acceleration
exceeds the maximum threshold.

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You will create the VI and logic to process the signals specified in the communication diagram.
Figure 2-1. Fan Control—Communication Diagram

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• The user interface on the Windows PC must allow the user to set the following,
as shown in Figure 2-2:
• Setpoint for the speed (RPM) of the fan
• PID control configuration for the control algorithm controlling the fan speed
• Maximum acceleration threshold (g)

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• Maximum fan speed threshold (RPM)
Run/stop the fan control process

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Figure 2-2. User Interface – Control Settings

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 Lesson 2 Using FPGA I/O and Timing

• The user interface on the Windows PC must also display the following,
as shown in Figures 2-3 and 2-4:
• Current FPGA PID Loop state
• Actual fan speed (RPM)
• Current acceleration (grms)

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• Latest fan acceleration waveform (g) that exceeded the maximum acceleration threshold
Actual FPGA PID control loop period (ticks)

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• CPU usage (%) of the CompactRIO RT target

• Amount of available memory (bytes) on the CompactRIO RT target

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Figure 2-3. User Interface – Data Monitoring

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Figure 2-4. User Interface – System Monitoring

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Note The first few exercises for the fan control and monitoring project will use the FPGA
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VI front panel for control of the application. Later exercises will either use the UI shown
above for control or a modified RT VI front panel.
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 Lesson 2 Using FPGA I/O and Timing

Implementation
1. From the C:\Exercises\FPGA\Acquire Tachometer and Acceleration Signals directory,
open [FPGA] Fan Control (prototype) [cRIO-9056].lvproj.
2. Configure the CompactRIO target:
a. In Project Explorer, right-click the cRIO RT target and select Properties.

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b. In the General category, set the IP Address to the IP address of your cRIO.

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c. Click OK.
3. Rename Mod1/AI0 to Tach.
a. Expand cRIO-9056»Chassis»FPGA Target»Mod1. Right-click Mod1/AI0 and select Rename.

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This FPGA I/O channel acquires the tachometer signal.
4. In Project Explorer, right-click cRIO-9056»Chassis and select Deploy to deploy the chassis

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settings.
5. Save the project.

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Create the FPGA VI
1. In Project Explorer, right-click the FPGA target and select Add»File.
2. Navigate to C:\Exercises\FPGA\Acquire Tachometer and Acceleration Signals\FPGA Main.vi

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directory.

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3. Click Add File.
4. In Project Explorer, double-click FPGA Main.vi to open it.
5. Notice that the front panel of the VI contains some decorations that will help you organize the
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controls and indicators of the FPGA VI as you develop it.
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6. Create the block diagram, as shown in Figure 2-5, to acquire and time signals from channels on the NI 9234 module.

Figure 2-5. FPGA Main VI Block Diagram

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1 Sequence structure—Right-click the Sequence structure and select Add Frame After to add additional frames.
2 Data Rate—Configure the acquisition data rate of the NI 9234 module. Place down an FPGA I/O Property Node. Right-click it and select
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Select Item»FPGA Target»Mod1. Click Property and select Data Rate. Right-click the input and select Create»Control.
3 Input Configuration—Configure the input configuration of the Tach and Mod1/AI1 channels of the NI 9234 module. Right-click the
corresponding FPGA I/O Property Node and Select Item»FPGA Target»Mod»Tach or select Item»FPGA Target»Mod1»Mod1/AI1.
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Right-click the input and select Create»Constant.

4 FPGA I/O Nodes—You can create the FPGA I/O Nodes by dragging the corresponding items from Project Explorer to the block diagram.
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Resize the FPGA I/O Node to show multiple items, if necessary.

5 Label the While Loop—Right-click the While Loop, select Visible Items»Subdiagram Label, and enter Acquisition Loop.
6 Tach and Mod1/AI1 indicators—Right-click the output terminals of the FPGA I/O Node and select Create»Indicator.
7 Input Error indicator—Right-click the FPGA I/O Node and select Show Error Terminals. Wire the error terminal as shown.
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 Lesson 2 Using FPGA I/O and Timing

7. Rearrange the front panel, as shown in Figure 2-6, to organize the controls and indicators.

Figure 2-6. FPGA Main VI Front Panel Diagram

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8. Set the Data Rate control to 10.240 kS/s (NI 9234), then right-click it and select
Data Operations»Make Current Value Default to set the default value of this control when you
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open the FPGA VI.

9. Save the VI.
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End of Exercise 2-1

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

F. Synchronizing C Series Modules

Objective: Explore the synchronization methods for C Series Modules.

Synchronization Considerations

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• Some applications using C Series I/O modules require a high level (<100 ns) of synchronization
between channels.

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• Vibration or sound measurement
• Multiple types of measurement

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Synchronizing On-Demand C Series Modules

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On-Demand Modules Use the Loop Timer VI to time their loop rate.

Examples:

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• Digital modules (NI-9474, 9401)
• Analog modules with a SAR ADC (NI-9215, 9263)

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• Multiplexed modules (NI-9211, 9207)

SAQ ADC
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Successive approximation register (SAR) analog-to-digital (ADC).
The type of ADC that an analog C Series module uses can be found in its
specifications.
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• Place all channel reads or updates in the same I/O node.
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• Can mix AI, AO, DIO channels with minimal skew.

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 Lesson 2 Using FPGA I/O and Timing

• The maximum loop rate possible is limited by the slowest channel in the FPGA I/O node.
• Digital channels can execute in one click tick.
• Analog channels require multiple clock ticks.
• Each additional channel in multiplexed modules requires additional clock ticks.

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Synchronizing Delta-Sigma C Series Modules

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Delta-Sigma Modules Many modules designed for high-speed dynamic acquisition use
delta-sigma ADCs. Internally timed and use data rate property to set their
loop rates.
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Examples:
• NI 923x
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• NI 9225, 9227, 9229

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• You can synchronize multiple delta-sigma modules and different delta-sigma models.
• Modules must use the same primary timebase source.
Modules must start acquisition at the same time.
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Resources For more information on synchronizing delta-sigma modules, refer to

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CompactRIO Developer’s Guide.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Configure modules in Project Explorer:

1. Select one of the modules, the primary to export its clock.
2. Set the rest of the modules to import this clock.

Synchronize modules on the block diagram:

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1. Set Data Rate property node for each module to same value.
2. Use the same I/O node to start all modules.

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3. Place all channels in the same I/O node.

Examples of synchronization of Delta-Sigma C Series Modules on the block diagram.

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 Lesson 2 Using FPGA I/O and Timing

G. Creating Delays between Events

Objective: Explore other timing control techniques.

When to Add Delays between Events?

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Use the Wait Express VI to create a delay between events in an FPGA VI. For example, you might
want to create a delay between a trigger and a subsequent output. You can place the LabVIEW code
for the trigger in the first frame of a sequence structure. Then place the Wait Express VI in the

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following frame. Finally, place the LabVIEW code for the output in the last frame of the sequence
structure. You can also create a series of delays using multiple Wait VIs in a sequence structure, as
shown in the following block diagram.

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Wait Express VI Configuration
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The Express VI will provide a delay for a certain time interval before the output data dependence
becomes valid.
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• Counter Units
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• Size of Internal Counter

• Determines maximum possible wait time.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

H. Measuring Time between Events

Objective: Explore functions used to measure timing.

Tick Count Express VI

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• Returns the value of a free-running FPGA counter in the units specified.
• Use Tick Count Express VI to measure time between events.

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Examples:
• Measure the time between edges on a digital signal.

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• Determine the execution time of a section of code.

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Use Cases to Measure Time between Events

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Use the Tick Count Express VI to measure the time between events, such as edges on a digital signal.
You can use the Tick Count Express VI when you need to determine the period, pulse width, or
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frequency of an input signal or if you want to determine the execution time of a section of LabVIEW
code.
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For example, to determine the amount of time it takes a function or a section of LabVIEW code to
execute, use a sequence structure with two Tick Count Express VIs, as shown in the following block
diagram. Place one Tick Count Express VI in the first frame of the sequence structure. Then place the
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LabVIEW code you want to measure in the second frame of the sequence structure. Finally, place the
other Tick Count Express VI in the last frame of the sequence structure. You can then calculate the
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difference between the results of the two Tick Count Express VIs to determine the execution time.
Subtract one from the result of the calculation to compensate for the execution time of the Tick Count
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Express VI.
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 Lesson 2 Using FPGA I/O and Timing

The Tick Count Express VI has an internal counter to track time. The internal counter for each Tick
Count Express VI you place on the same block diagram shares the same start time. Therefore, every
Tick Count Express VI that uses the same values for the Counter Units and Size of Internal Counter
options tracks the same time. For example, if you call two Tick Count Express VIs that use the same
Configure Tick Count options at the same time, they return the same Tick Count value.

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The Tick Count Express VI returns an integer value in Counter Units. The Tick Count value cannot
represent any fractional time periods that might occur when Counter Units is configured for uSec or

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mSec. Configuring Counter Units for uSec or mSec can result in timing measurements that have an
accuracy of ±1 Counter Unit value. For example, you can configure the Tick Count Express VIs in the
block diagram above to measure time in milliseconds. If the first Tick Count Express VI executes at

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47.9 milliseconds, Tick Count returns a value of 47. If the second Tick Count Express VI executes at
53.2 milliseconds, Tick Count returns a value of 53. Although this example has a 5.3-millisecond
delay, the difference between the returned values is 6 milliseconds.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

I. Benchmarking Loop Periods

Objective: Use the timing functions to benchmark the FPGA VI loop period.

Measuring Loop Periods

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Timestamp measurements are done in parallel because of the way the FPGA code is implemented. If
any new code is not made within the same combinatorial path as another set of code, the code
execution times are independent from one another. Because of this behavior, whenever you add code

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to an FPGA VI for benchmarking, it has no effect on the loop execution time, provided that the code
you are benchmarking takes longer to execute than the three ticks required to obtain and observe the
loop rate.

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By placing a Feedback Node inside a subVI, you can now easily place that subVI in any loop. The
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Feedback Node inside the subVI allows the subVI to access a value from the previous iteration of the
loop.
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You cannot do this with a shift register. To copy the shift register code to a different loop, you must
manually create another shift register in the other loop and copy the rest of the code. In contrast, by
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using a feedback node inside a subVI, you only have to place the subVI inside the other loop.
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 Lesson 2 Using FPGA I/O and Timing

Exercise 2-2: Benchmark the Actual Loop Period

Goal
Add benchmarking code to calculate the actual loop period.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
• LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)
• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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NI-9474 Digital I/O C Series Module
Windows 10 PC na
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Scenario
Add benchmarking code to calculate the actual loop period of different sorting algorithms. The
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exercise aims to compare the effectiveness of various sorting algorithms and identify the fastest one
for sorting a large dataset. You will create the VI and logic to process the signals specified in the
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communication diagram.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA
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Benchmarking

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Figure 2-7. Fan Control—Communication Diagram

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 Lesson 2 Using FPGA I/O and Timing

Implementation
1. From the C:\Exercises\FPGA\Benchmark the Loop Period directory, open
[FPGA] Fan Control (prototype) [cRIO-9056].lvproj.
2. Configure the CompactRIO target:
a. In Project Explorer, right-click the cRIO RT target and select Properties.

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b. In the General category, set the IP Address to the IP address of your cRIO.
c. Click OK.

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3. Add the Get Loop Period (tick) subVI to the project:
a. Right-click the cRIO-9056»Chassis»FPGA Target»Support VIs virtual folder and select

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Add»File.
b. Navigate to C:\Exercises\FPGA\Benchmark the Loop Period\Support VIs\

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Get Loop Period (tick).vi.
c. Click Add File.
4. Explore the Get Loop Period (tick) subVI:

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a. Double-click Get Loop Period (tick).vi in Project Explorer to open the subVI. Go to the block
diagram.
b. Explore the Tick Count function. Double-click the Tick Count function. Notice that the counter

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units are set to Ticks. Based on the Size of the Internal Counter, what is the maximum number
of ticks that this function can internally count before it rolls over back to 0?

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If the code you are benchmarking takes longer than the maximum value the Tick Count
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function can handle, the elapsed time will be much lower than expected due to rollover. Based
on the maximum number of ticks, what is the maximum amount of time that can elapse
between calls to the Tick Count function before rollover occurs?
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________ seconds
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c. Notice the Feedback Node. Like a shift register, you can use a Feedback Node to store data
from previous block diagram executions or loop iterations. When this subVI is placed inside a
loop, it will use the Feedback Node to calculate the difference between the tick counts of the
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current loop iteration and the previous loop iteration.

d. Notice that this subVI is a reentrant subVI. Select File»VI Properties. Set Category to
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Execution. Notice that Reentrancy is set to Preallocated clone reentrant execution. This means
that multiple instances of this subVI (e.g., in two different loops) execute simultaneously and
maintain their own state. FPGA subVIs are reentrant by default.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

5. Modify the block diagram, as shown in Figure 2-8, to add benchmarking code to the acquisition
loop.

Figure 2-8. FPGA Main VI Block Diagram

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1 Get Loop Period (tick) VI—From Project Explorer, drag the FPGA Target»Support VIs»Get Loop
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Period (tick).vi to the block diagram. Right-click the output and select Create»Indicator.
Rename the indicator to Acquisition Loop Period (tick).
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6. On the front panel, move the new Acquisition Loop Period (tick) indicator to the Monitoring
Values»General section.
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7. Save the VI and project.

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 Lesson 2 Using FPGA I/O and Timing

Test
1. Execute the FPGA Main VI in simulation mode:
a. Right-click the FPGA Target and select Select Execution Mode»Simulation (Simulated I/O).
b. Run the VI. Verify that the VI executes as expected.
2. Compile the FPGA Main VI:

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a. Right-click the FPGA Target and select Select Execution Mode»FPGA Target.

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b. Click the Run button to start the compilation.
c. While the FPGA Main VI is compiling, calculate and write down your prediction of what the
loop period should be below.

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Loop Period = ___________________ ticks

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Note The Loop Period of this loop is determined by the acquisition rate (kilosamples per
second) set by the Data Rate property. By default, the FPGA uses a 40 MHz clock, which
has means there are 40,000,000 ticks per second.

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d. When FPGA Main finishes compiling, run the VI. Compare your predicted loop period to the
actual result.

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Quiz
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1. Will you need to benchmark any loops in an FPGA VI in your own application back at your job?
2. If so, what unit of time is most appropriate for the loop period?
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Circle all that apply.
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• Milliseconds
• Microseconds
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• Nanoseconds
Your answer determines whether the Counter units of the Tick Count function should be mSec,
uSec, or Ticks.
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3. What is the maximum expected period of your loop?________________

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Your answer determines whether the Size of internal counter of the Tick Count function should be
8 Bit, 16 Bit, or 32 Bit.
4. If you need to benchmark the period of a loop in your own application back at your job, you can
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reuse the Get Loop Period (ticks) subVI. and modify the configuration of the Tick Count function
if necessary.
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Quiz—Answers
1. Based on the Size of the Internal Counter, what is the maximum number of ticks that this function
can internally count before it rolls over back to 0?
The Size of the Internal Counter is 32-bit.
Therefore, the maximum number of ticks before rollover is:

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2^Size of Internal Counter = 2^32 = 4,294,967,296 ticks.
2. If the code you are benchmarking takes longer than the maximum value Tick Count can handle,

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the elapsed time will be much lower than expected due to the rollover. Based on the maximum
number of ticks, what is the maximum amount of time that can elapse between calls to the Tick
Count function before rollover occurs?

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By default, the FPGA uses a 40 MHz clock, which has 40,000,000 ticks per second. Therefore,
each tick lasts 25 nanoseconds. Therefore, the maximum amount of time that can elapse between

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calls to the Tick Count function before the rollover occurs is:
(Maximum number of ticks before rollover - 1) * Time per tick =
(4,294,967,296 ticks - 1) * 25 nanoseconds = 107 seconds.

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3. While the FPGA Main VI is compiling, calculate and write down your prediction of what the loop
period should be below.

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This loop is timed by the Data Rate property node, which is set to 10.240 kS/s.
Loop Period = 1 / 10,2000 = 0.00009765625 seconds = 97.65625 μs Loop Period (ticks) =
Loop Period (seconds)/number of seconds per tick =

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0.00009765625 seconds/0.000000025 seconds = 3,906 to 3,907 ticks.

End of Exercise 2-2

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. Match each Timing VI option with its purpose.

1. Loop Timer Express VI a. Use to create delays between events.

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2. Wait Express VI b. Use to benchmark execution speeds.

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3. Tick Count Express VI c. Use to control loop execution rate.

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2. What is a potential drawback of using an 8-bit counter instead of a 32-bit counter?
e. Less FPGA resources used.

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f. 32-bit clocks are slower.
g. Maximum time the timer can track is not large enough for the application.

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3. Is the statement true or false?

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If you place a Loop Timer Express VI inside a While Loop, the Loop Timer Express VI will wait
during every iteration of the While Loop.
a. True
b. False na
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4. Is the statement true or false?

Adding benchmarking code to a While Loop will not affect the execution speed of the loop.
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a. True
a. False
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5. Which of the following do you need to synchronize an acquisition of analog input channels from
multiple delta-sigma C Series modules?
Select all that apply.
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a. Time the acquisition using a Loop Timer Express VI.

b. Configure modules to use the same primary timebase source.
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c. Start acquisition at the same time.

d. Acquire from all channels in the same FPGA I/O node.
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© National Instruments Corporation | 2-43

 Lesson 2 Using FPGA I/O and Timing

Activity: Lesson Review—Answers

1. Match each Timing VI option with its purpose.

1. Loop Timer Express VI c. Use to control loop execution rate.

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2. Wait Express VI a. Use to create delays between events.

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3. Tick Count Express VI b. Use to benchmark execution speeds.

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2. What is a potential drawback of using an 8-bit counter instead of a 32-bit counter?
a. Less FPGA resources used.

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b. 32-bit clocks are slower.
c. Maximum time the timer can track is not large enough for the application.

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3. Is the statement true or false?

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If you place a Loop Timer Express VI inside a While Loop, the Loop Timer Express VI will wait
during every iteration of the While Loop.
a. True
b. False na
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4. Is the statement true or false?

Adding benchmarking code to a While Loop will not affect the execution speed of the loop.
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a. True
b. False
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5. Which of the following do you need to synchronize an acquisition of analog input channels from
multiple delta-sigma C Series modules?
Select all that apply.
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a. Time the acquisition using a Loop Timer Express VI.

b. Configure modules to use the same primary timebase source.
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c. Start acquisition at the same time.

d. Acquire from all channels in the same FPGA I/O node.
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3

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Signal

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Processing in

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LabVIEW FPGA

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Explore data types, methods and built-in or external
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functions to process signals with the FPGA.

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Topics
A. Using Fixed-Point Data Type
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B. Using Single-Precision Floating-Point

C. Performing FPGA Math & Analysis
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D. Integrating Third-Party Intellectual Property (IP)

Exercises
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Exercise 3-1 Explore Fixed-Point Configurations

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Exercise 3-2 Process the Tachometer and Accelerometer Signals

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Using Fixed-Point Data Type

Objective: Learn about the Fixed-Point Data Type and its usage in LabVIEW FPGA.

Fixed-Point Data Type Overview

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• Represent rational numbers within specified range.
• Sizes between 1-64 bits.

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• Can be configured as signed or unsigned.

The fixed-point data type provides some of the flexibility of the floating-point data type but also

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maintains the size and speed advantages of integer arithmetic. By default, each operation on the
fixed-point data type generates a fixed-point result that is large enough to hold all possible output
values specified by the input types.

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Note FPGA Signal Generation VIs and some functions do not support the fixed-point data
type.

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Caution If you wire a fixed-point number to an integer, you might lose fractional bits.

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Using Fixed-Point Data Types
The range of values and resolution depends on three factors:
•

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Sign Encoding
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• Integer Word Length
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Fixed-point is a collection of data types with different ranges of values. The range is defined by the
minimum value, maximum value, and delta.
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Range—Defined by maximum and minimum values that can be represented.

Delta—Smallest change in value that can be represented with the given fixed-point configuration.
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Fixed-Point Terminology
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Sign Encoding The option that determines whether the fixed-point data is signed (±) or
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unsigned (+).
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Word Length The total number of bits used for the fixed-point data.
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Integer Word Length The number of bits used in the integer portion of the fixed-point data.
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Demonstration: Fixed-Point Data Type

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© National Instruments Corporation | 3-3

 Lesson 3 Signal Processing in LabVIEW FPGA

1 7

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5 6

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1 Overflow Status—Shown when the Include Overflow Status checkbox is enabled in the Numeric
Properties dialog box. To determine whether overflow occurs, you can configure a fixed-point
number to include an overflow status. When you include an overflow status in a fixed-point

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number, LabVIEW allocates additional storage space to track whether the overflow occurred with
that fixed-point number. After you configure a fixed-point number to include an overflow status,
you can display an overflow status LED on fixed-point controls, constants, and indicators. This

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LED lights up when the overflow status of the fixed-point number is TRUE. You can also use the
Fixed-Point Overflow? function to determine the overflow status of a fixed-point number. Use the
Fixed-Point functions to manipulate the overflow status of a fixed-point number.
2

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Sign Encoding—The setting that specifies whether the fixed-point value is signed or unsigned.
If you select signed, the sign bit is always the first bit in the bit string that represents the data.
Word Length—The total number of bits in the bit string that LabVIEW uses to represent all
possible values of the fixed-point data. LabVIEW accepts a maximum word length of 64 bits.
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Certain targets might limit data to smaller word lengths. If you open a VI on a target and the VI
contains fixed-point data with larger word lengths than the target can accept, the VI contains
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broken wires. Refer to the documentation for a target to determine the maximum word length the
target accepts.
4 Integer Word Length—The number of integer bits in the bit string that LabVIEW uses to represent
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all possible values of the fixed-point data, or, given an initial position to the left or right of the
most significant bit, the number of bits to shift the binary point to reach the most significant bit.
The integer word length can be larger than the word length and can be positive or negative.
5 Minimum—Minimum value that can be represented.
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6 Maximum—Maximum value that can be represented.

7 Delta—Smallest change in value that can be represented.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Numeric Representation Examples

The integer word length can be negative as well as positive. Any integer word length less than 1 will
result in a decimal maximum value. This amounts to the entire word occurring to the right of the
decimal point. As the integer word length becomes more negative, zeros are used to pad the increasing
distance between the fixed-point data and the decimal point. For example, <±,6,-2> would result in

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0.00XXXXXX, where the X’s represent data stored in the 6-bit word.

If the integer word length is greater than the word length, then the fixed-point data will move to the

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left of the decimal point, with zeros padding the distance between the integer word and the decimal
point. For example, <±, 6, 8> would result in XXXXXX00.0, where the X’s represent the data
stored in the 6-bit word.

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© National Instruments Corporation | 3-5

 Lesson 3 Signal Processing in LabVIEW FPGA

Fixed-Point Configuration

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Use the Fixed-Point Configuration options on the Properties dialog box to increase or decrease the
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resources a function uses. Right-click a Numeric constant, control, indicator, or function that accepts
fixed-point data and select Properties from the shortcut menu to display the Properties dialog box.
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When you set the range on inputs, the FPGA Module propagates the range throughout the block
diagram. The propagation reduces resources when possible. The FPGA Module does not propagate
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through subVIs, so coercion dots appear on the inputs of subVIs if the range is different than the range
being propagated.
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The Data Type page of the Numeric Properties dialog box will be slightly different for indicators.
Specifically, it includes an Adapt to Source checkbox. This will modify the data type of the indicator
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to match the data type of the value wired to it.

Interpreting Fixed-Point Configuration

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When performing fixed-point arithmetic, the output fixed-point configuration must adapt to the input
fixed-point configuration to avoid data loss.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Fixed-Point Arithmetic
Fixed-point data is limited to 64 bits, so if the resulting output requires more than 64 bits, precision
may be lost.

LabVIEW type propagation strictly deals with the ranges of the wires and not so much the fixed-point

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representation necessary to hold those ranges. In other words, LabVIEW calculates and propagates
the ranges of values each wire will have to pass along. LabVIEW then calculates the representation
that is as small as possible but will hold that value without losing any data.

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Arithmetic Operations

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• Addition
• Subtraction

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• Multiplication
• Division

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Addition—The integer word length of the output will be one bit longer, resulting in the word length
increasing by one as well. The decimal length does not change.

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• <±, A, B> + <±, A, B> = <±, A+1, B+1>

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In the presented example, the integer word length increases by one to accommodate the maximum
value. Since the integer word length increases, the word length must increase as well so that no
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accuracy is lost.

<±,10,7> + <±,10,6> = ?
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To accommodate both configurations without losing any accuracy, there must be 7 integer bits and 4
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decimal bits, resulting in an input configuration of <±,11,7,>.

<±,11,7> + <±,11,7> = <±,12,8>

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If one input is signed and the other is unsigned, then the word length and integer word length will
increase by one more bit.
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© National Instruments Corporation | 3-7

 Lesson 3 Signal Processing in LabVIEW FPGA

Subtraction—The output representation follows the same guidelines as in the case of addition. The
output will be signed, regardless of whether the inputs were signed or unsigned.
• <+, A, B> - <+, A, B> = <±, A+1, B+1>

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Multiplication—For the integer value of the output to accommodate the largest possible value of each

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operand, the integer word length must increase to match the sum of the integer word lengths of the
inputs. For the resolution of the output to accommodate the highest resolution of both inputs, the

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decimal word length must also increase. Thus, the word length of the output must increase to match
the sum of the word lengths of the inputs.
• <+, A, B> * <+, C, D> = <+, A+C, B+D>

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Division—Inputs can have different ranges of values. Signed and unsigned division result in different
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ranges of values for the out.
• Signed: <±, A, B> / <±, C, D> = <±, A+C+1, B+C-D+1>
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• Unsigned: <+, A, B> / <+, C, D> = <+, A+C, B+C-D>

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Configuring Fixed-Point Functions

Functions that support the fixed-point data type include modes to handle rounding and overflow. Use
the Properties dialog box for the function to select the overflow and rounding modes. Right-click a
function and select Properties from the shortcut menu to display the Object Properties dialog box.

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Adapt to Source Set whether the configuration settings for the output value adapt to the input
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values you wire to the function. For fixed-point data, LabVIEW automatically
sets the Fixed-Point Configuration settings to avoid data loss if possible.
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Rounding Mode Determines how the function handles quantization conditions.

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Overflow Mode Determines how the function handles overflow conditions.

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Adapt to Source is enabled by default to avoid data loss from the function. Typically, you can let all
functions keep Adapt to source enabled, test the code, and then compile it on the FPGA. In many
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situations, you can avoid overflow by placing a checkmark in the Adapt to source checkbox in the
configuration dialog box of the function. If you place a checkmark in this checkbox, LabVIEW attempts
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to adjust the width and range of the output data type such that neither overflow nor rounding occurs.
However, this adjustment is not possible in all situations. For example, if a function involves division,
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rounding always occurs.

If the compile fails due to a lack of FPGA resources (space), then you can try to modify your fixed-point
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code to use fewer FPGA resources. For example, if you know the expected minimum and maximum
input values for a function will be smaller than the min/max range of the input wire fixed-point
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configuration (e.g., you know that the AI0 input wire for a Multiply function for your application will
always be between -1 and +1, but the AI0 input wire has a range of -8 to 8), you could potentially
disable "Adapt to source" and decrease the word length (and integer word length) of the output data
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type to values that reflect your expected Range and Desired Delta of the function output. Then you
should set the appropriate Overflow Mode and Rounding Mode.

© National Instruments Corporation | 3-9

 Lesson 3 Signal Processing in LabVIEW FPGA

Selecting Rounding Mode

Rounding Occurs when the precision of the input value or the result of an operation is
greater than the precision of the output type.

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Rounding Mode Options
Truncate—Removes fractional bits and therefore does not require any additional hardware

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resources. However, this mode produces the largest mean error for most data streams. This mode
is the default for integer operations.
Round Half-Up—Rounds the value to the nearest value that the output type can represent. If the

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value lies directly between two such values, LabVIEW rounds to the higher of the two by adding
half the least significant bit to the value and then truncating. This method has a higher impact on

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performance than the Truncate method but produces a more accurate result.
• Round Half-Even—Rounds the value to the nearest value that the output type can represent. If the
value lies exactly between two such values, LabVIEW checks the value of the bit that becomes

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the least significant bit after rounding. If the bit is zero, then LabVIEW rounds to the lower of the
two valid values; otherwise, it rounds to the higher value. This mode has the highest impact on
performance, but it is more accurate than the Truncate method, and it eliminates the bias toward

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the higher value that can occur when you perform multiple Round Half-Up operations. This is the
default option.

Selecting Overflow Mode na

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Overflow Occurs when the result of an operation is outside the range of values that the
output type can represent.
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Overflow Mode Options

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• Wrap—Discard significant bits of the output value until it falls within the specified range.
• Saturate—Coerce the output value to the maximum or the minimum, depending on which value
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was exceeded. This option has a higher impact on performance than the Wrap method. This is the
default option.
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Configurations Considerations
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As a rule of thumb, rounding half-even and saturation overflow modes typically render the most
desirable results. Rounding usually gives an overall more accurate fixed-point representation of the
input number. Saturation prevents outputs from jumping between the top and bottom of the FXP range
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when input numbers are outside FXP bounds. The only drawback is that rounding half-even and
saturation modes requires slightly more field-programmable gate array (FPGA) logic compared to the
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truncate and wrap modes.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Fixed-Point Algorithm Development Process

Math is a common type of processing in FPGAs.
1. Typically, you start with a pencil and paper and do symbolic math.
2. Then you may create a floating-point model to avoid the complexity of a fixed point for initial
testing of the algorithm. Then you look at the bit widths necessary to capture the range and

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precision on each of the wires. Logging the min/max of each floating-point wire can help with
these decisions. Run your fixed-point code using the tests you devised for the floating-point code

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to ensure it is good enough. It will not match perfectly. You should also include tests for boundary
conditions, which can be a common source of errors. A boundary condition is a value that is above
or below a set maximum. For example, if a requirement calls for a maximum value, then you should

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test [maximum value +1], [maximum value –1], and maximum value in your fixed-point code.
3. Finally, compile and test your fixed-point algorithm on the FPGA.

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© National Instruments Corporation | 3-11

 Lesson 3 Signal Processing in LabVIEW FPGA

Exercise 3-1: Explore Fixed-Point Configurations

Goal
Use the fixed-point data type, configuring rounding and overflow modes if necessary.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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NI-9474 Digital I/O C Series Module
Windows 10 PC na
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Scenario
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You must read values from a CompactRIO analog input channel that returns fixed-point data. You must
implement fixed-point math on this data. You also know that the analog input channel is expected to
return values between -2 and 2. In this exercise, the fixed-point math algorithm scales the data by a
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constant value of 5. However, other fixed-point algorithms can involve many more operations and
grow the number of bits used by the fixed-point data type to be larger.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Implementation
Fixed-Point Configuration
1. From the C:\Exercises\FPGA\Using Fixed-Point Data Type directory, open
Fixed-Point.lvproj.

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2. Configure the CompactRIO Network Settings:
a. Right-click the CompactRIO target in Project Explorer and select Properties.

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b. In the General category, set the IP Address to the IP Address of your CompactRIO target.
3. In the Project Explorer window, cRIO-9056»Chassis»FPGA Target is set to execute FPGA VIs on

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the development computer with simulated I/O.
4. In Project Explorer, double-click cRIO-9056»Chassis»FPGA Target and open

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Fixed-Point Configuration.vi.
5. Examine the block diagram:
a. Press <Ctrl-H> to show the Context Help window. Hover your mouse pointer over the

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fixed-point wires to see their fixed-point configuration.
b. Notice the In Range and Coerce function. This function coerces the FPGA I/O Node output to
simulate an analog input channel that returns values between -2 and 2.

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6. Run the VI and notice that the Simulated AI0 indicator will always return a value between -2 and 2.

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© National Instruments Corporation | 3-13

 Lesson 3 Signal Processing in LabVIEW FPGA

7. Modify the block diagram, as shown in Figure 3-1, to scale the simulated AI0 value by 5.
Figure 3-1. Fixed-Point Configuration VI Block Diagram

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3

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1 Multiply function—Wire the x input first. Right-click the y input and select Create»Constant.
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Fixed-point constant—Configure the fixed-point constant to represent a value of 5. Right-click the
constant and select Properties. On the Data Type tab, notice that the Word Length is 24 bits.
However, you do not need 24 bits to represent a constant value of 5, so you should modify the
fixed-point configuration to use the minimum number of bits required to represent a value of 5.
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3 Fixed-Point Constant Configuration section—Set the following values.
• Encoding: Unsigned
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• Word length: 3 bits

• Integer word length: 3 bits
4 Result indicator—Create the Result indicator and observe its fixed-point configuration. Right-click
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the output of the Multiply function and select Create»Indicator. Rename the indicator to Result.
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8. Press <Ctrl-H> to show the Context Help:

a. Hover your mouse pointer over the input and output wires of the Multiply function and the
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Result indicator, and observe their fixed-point configurations in the Context Help window.
b. Notice that the Multiply function automatically increased the size of its output fixed-point
configuration based on the fixed-point configuration of its inputs. The x input has a fixed-point
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configuration of <±,24,4>, and the y input has a fixed-point configuration of 3, <+,3,3>.

The Multiply function automatically increased its fixed-point configuration to ±,27,7.
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9. Run the VI several times and verify that the Result is equal to Simulated AI0 multiplied by 5.
10. At this point, you would normally be ready to compile your fixed-point algorithm on the FPGA. In
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the previous steps, you allowed the Multiply function to automatically grow the size of the
fixed-point configuration, which helps avoid data loss. This is the safest method to use when
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creating a fixed-point algorithm. However, letting functions automatically grow the size of the
fixed-point configuration uses up more FPGA resources and might cause a compilation to fail.
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If your compilation fails due to a lack of FPGA resources, then try to modify the fixed-point
configurations in your algorithm to use less space.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Optimizing Fixed-Point Configuration

1. Identify a place where you can optimize the fixed-point configuration.
Notice the inputs of the Multiply function:
• Expected minimum of x input: -2
Expected maximum of x input: 2

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• Delta of x input: 9.536743E-7

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• Constant value of y input: 5
Because the y input is a constant of 5, we can predict the expected range of the Multiply function
output:

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• Expected minimum of output (-2 × 5): -10
• Expected minimum of output (-2 × 5): -10

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2. Configure the Multiply function to use the minimum number of bits to represent the expected
output:
a. Right-click the Multiply function and select Properties.

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b. On the Output Configuration tab, disable the Adapt to source checkbox.
c. Decrease the Integer Word Length to the smallest number of bits that can still represent the

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expected minimum and maximum output values of -10 and 10.
d. Decrease the Word Length to the smallest number of bits that can still represent the original
delta of 9.536743E-7.

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e. Verify that the configuration is set to the following values:
• Sign encoding: Signed
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• Word length: 25 bits
Integer word length: 5 bits
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• Rounding mode: Round Half-Even

Overflow mode: Saturate
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• Enable the Include overflow status checkbox.

f. Click OK.
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g. Notice that the Multiply function has a blue coercion dot on its output terminal. The blue
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coercion dot indicates that you have set the fixed-point configuration of the output differently
from the default.
3. Modify the Result indicator to update its fixed-point configuration:
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a. Right-click the Result indicator and select Properties.

a. On the Data Type tab, enable the Adapt to source checkbox. Now the Result indicator will
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adapt to the fixed-point configuration of its input wire.

b. Click OK.
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4. Run the VI several times and verify that the Result is still equal to Simulated AI0 multiplied by 5.
The result should still be accurate even though we have decreased the number of bits used by the
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fixed-point data type.

5. Save the VI.
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© National Instruments Corporation | 3-15

 Lesson 3 Signal Processing in LabVIEW FPGA

6. Observe overflow behavior:

a. On the block diagram, change the constants wired into the In Range and Coerce function from
-2 and 2 to -7 and 7.
b. The previous optimization you implemented was based on an expected Simulated AI0 value
between 2 and -2. By increasing the range of Simulated AI0, we are forcing an overflow

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condition.
c. Go to the front panel.

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d. Right-click the Result indicator and select Visible Items»Overflow Status LED. You should now
see an LED on the indicator that is lit whenever an overflow condition occurs.
e. Run the VI until you see the Overflow Status LED illuminate.

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Overflow occurs when the result of the Multiply function is outside the range of values of its
output configuration. In this case, you have configured the Multiply output to have a minimum

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and maximum of -16 and 16 and to saturate at those values if overflow occurs.
7. Save and close the VI and project when finished.

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End of Exercise 3-1

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

B. Using Single-Precision Floating-Point

Objective: Explore the characteristics and usage of the Single-Precision Floating-Point Data Type.

Single-Precision Floating-Point Overview

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LabVIEW FPGA supports the single-precision floating-point (SGL) data type in FPGA VIs.

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Benefits

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• Easier to rapidly prototype.

Caveats

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• Requires significantly higher FPGA resource usage than fixed-point data type for some operations.
• Most functions cannot perform floating-point operations inside SCTL.

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The single-precision floating-point data type is supported in LabVIEW FPGA 2012 or later.
Double-precision floating point is not supported in LabVIEW FPGA, so DBL calculations can only be
done on the host computer.

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The single-precision floating-point (SGL) data type provides more accuracy than a 24-bit fixed-point
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data type but reduces overall performance due to the increased latency of functions and the large
number of FPGA resources that it uses for some functions. There is no extra overhead (for SGL when
compared to fixed-point) in functions that just move data, such as Memory Read/Write, Index Array,
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and Feedback nodes. However, all the math functions (add, multiply, etc.) will introduce additional
overhead when using the SGL data type, some more than others.
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For example, an Add is on the order of 10x more resource usage, but a Multiple might be closer in
resource usage. Evaluate your usage of numeric data types to determine which data type is the best
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for your design.

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Most functions cannot perform single-precision floating-point operations inside a Single-Cycle Timed
Loop because they require more than one clock cycle to execute, but they do not have handshaking
signals.
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Single-Precision Floating-Point Use Cases

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• Free the RT processor to perform other operations and use single-precision floating-point
conversions with I/O.
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• Operate on data from multiple inputs or outputs that return different fixed-point data types.
You need to represent very large and very small numbers in the same data path, such as with
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accumulators.
• You need to rapidly prototype.
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The most common reason to use SGL floating-point is to rapidly prototype and implement your
algorithms and logic. If your code successfully compiles and meets requirements, then you do not need
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to use fixed-point.

© National Instruments Corporation | 3-17

 Lesson 3 Signal Processing in LabVIEW FPGA

Performing I/O conversion to the FPGA frees processing on the host computer, especially in real-time
systems. If you have FPGA resources available, perform fixed-point I/O to single-precision
floating-point data conversions on the FPGA to free the host processor to perform other operations,
such as meeting real-time requirements.

Convert heterogeneous data paths into the SGL data type in order to handle them with common code.

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This conversion is useful in situations where you want to operate on data from multiple inputs that
return different fixed-point data types.

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Use single-precision floating-point to get functional hardware designs quickly. Convert to fixed-point
as necessary to optimize FPGA performance or resource usage.

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Performing I/O conversion to the FPGA frees processing on the host computer, especially in real-time
systems. If you have FPGA resources available, perform fixed-point I/O to single-precision

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floating-point data conversions on the FPGA to free the host processor to perform other operations,
such as meeting real-time requirements.

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For example, you might receive a voltage value as a fixed-point data type, convert the voltage value
into a useful engineering unit value, convert the fixed-point data type to a single-precision data type,
and send it to the host. The host processor now does not need to use any CPU resources for this

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algorithm and conversion.

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Operate heterogeneous data paths into the SGL data type in order to handle them with common code.
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This conversion is useful in situations where you want to operate on data from multiple inputs that
return different fixed-point data types.
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The figure of the FPGA VI shows an NI cRIO-9104 as it acquires data from two modules, converts it
to the SGL data type, and writes the data to a DMA FIFO.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Represent very large and very small numbers in the same data path, such as with accumulators.

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To rapidly prototype, you need to:
• Use floating-point to get functional hardware designs quickly.

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• Convert to fixed-point later as necessary to optimize FPGA performance or resource usage.

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 Lesson 3 Signal Processing in LabVIEW FPGA

Exercise 3-2: Process the Tachometer and Accelerometer Signals

Goal
Convert the raw tachometer voltage signal into fan speed (RPM) and scale the accelerometer voltage
signal into units of acceleration (g).

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Requirements

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To complete this exercise, it is necessary to have access to the following hardware and software.

Software:

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• LabVIEW 2023 Q3 (32-bit)
• NI-DAQmx 2023 Q3 (32-bit)

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• LabVIEW Real-Time Module 2023 Q1 (32-bit)
• LabVIEW FPGA Module 2023 Q1 (32-bit)

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• NI CompactRIO 2023 Q3 (32-bit)

Hardware:

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• An NI CompactRIO from either the 904x or 905x product lines
• USB Type C or RJ45 Ethernet connection
•

• NI-9474 Digital I/O C Series Module

Windows 10 PC
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NI-9211 Thermocouple Input C Series Module
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Scenario
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This exercise aims to perform inline signal processing to your acquired signals to be able to represent
your acquisition on the screen using the engineering units expected for each type of measurement.
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You will create the VI and logic to process the signals specified in the communication diagram.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA
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Tach –> RPM
Voltage –> g
Signal Processing

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Figure 3-2. Fan Control—Communication Diagram

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 Lesson 3 Signal Processing in LabVIEW FPGA

Implementation
1. From the C:\Exercises\FPGA\Process Tachometer and Acceleration directory, open
Fan Control (prototype) [cRIO-9056].lvproj.
2. Configure the CompactRIO target:
a. In Project Explorer, right-click the cRIO RT target and select Properties.

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b. In the General category, set the IP Address to the IP address of your cRIO.
c. Click OK.

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3. Add an existing Tachometer library to the project:
a. In Project Explorer, navigate to cRIO-9056»Chassis»FPGA Target»Support VIs.

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b. Right-click Support VIs, select New»Virtual Folder, and name it Tachometer.
c. Right-click the Tachometer virtual folder and select Add»File.

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d. Navigate to
C:\Exercises\FPGA\Tachometer Library\Tachometer\Tachometer(SGL).lvlib.
e. Click Add File.

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4. Add an existing fan acceleration analysis subVI to the project:

a. In Project Explorer, right-click the FPGA Target virtual folder and select Add»File.
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b. Navigate to C:\Exercises\FPGA\Process Tachometer and Acceleration\support\

Analyze Fan Acceleration (FPGA).vi.
c. Click Add File.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

5. Modify the block diagram, as shown in Figure 3-3.

Figure 3-3. FPGA Main VI Block Diagram

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1 Convert the raw tachometer voltage signal into fan speed (RPM):
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• From Project Explorer, drag the Get Tach RPM (FPGA).vi from the FPGA Target»Support VIs»
Tachometer»Tachometer (SGL).lvlib directory to the block diagram.
2 Scale the accelerometer voltage signal into units of acceleration (g):
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• The Sound and Vibration Signal Simulator accelerometers have a sensitivity of 175 mV/g and
the FPGA I/O Node returns the signal in units of V. Use the To Single Precision Float function
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to convert the fixed-point data type to the easier-to-use single-precision floating-point data
type. Use the Divide function to scale from units of V to g.
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3 Analyze the acceleration data:

• From Project Explorer, drag the FPGA Target»Support VIs»Analyze Fan Acceleration
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(FPGA).vi item to the block diagram. Create controls and indicators.

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© National Instruments Corporation | 3-23

 Lesson 3 Signal Processing in LabVIEW FPGA

6. Set the default value of the Max Acceleration Threshold control to 0.75:
a. On the front panel, set the Max Acceleration Threshold (g) control to 0.75.
b. Right-click the control and select Data Operations»Make Current Value Default.
7. Arrange the front panel, as shown in Figure 3-4.

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Figure 3-4. FPGA Main VI Front Panel Diagram

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8. Save the VI and project.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Test in Simulation Execution Mode

1. Run the VI in simulation execution mode:
a. Right-click the FPGA target and select Select Execution Mode»Simulation (Simulated I/O).
b. Run the VI.
c. Verify that the FPGA Main VI is operating and correctly scaling the acceleration as expected

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by looking at the indicator values, execution highlighting, single-stepping, probes, and other
tools. In this mode, the FPGA I/O Nodes will output random data.

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End of Exercise 3-2

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 Lesson 3 Signal Processing in LabVIEW FPGA

C. Performing FPGA Math & Analysis

Objective: Explore the usage of built-in functions for signal processing.

FPGA Math & Analysis Common Tasks

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Configurable, prebuilt, optimized, tested, and documented functions to perform common tasks:
• Mathematics

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• Measurements
• Control, PID
• Filtering

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• Signal Processing
High Throughput Math

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•

Use the FPGA Math & Analysis VIs and Functions to perform math, analysis, and control operations
in FPGA VIs. This palette provides functions not available elsewhere on the FPGA palette. Using these

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functions instead of writing the algorithm yourself will save development and support time. This
palette is specific to FPGA targets. The configuration and behavior of these functions will differ from
their Windows counterparts.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Node Types—FPGA Math & Analysis

1. Functions
2. Non-configurable Express VIs
3. Configurable Express VIs

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A Feedback Node is analogous to a z^(-1) block in feedback control theory and digital signal
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processing.
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Feedback Nodes may be visually depicted as Z-Transform primitives on the FPGA Block Diagram.
Some LabVIEW functions (pale yellow background) offer configuration options or optional nodes.
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Context menu options for this primitive include Direction, Appearance, Show Enable Terminal, and the
ability to move the node in or out layers of loops. The Z Transform Delay primitive is the only primitive
in the FPGA analysis palette.
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The programmer should also be aware of the Discrete Delay node available in the
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FPGA Math & Analysis VIs»High Throughput»Basic Elements palette. Nodes in the high throughput
palette are covered in a later section and in more depth in a separate course.
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 Lesson 3 Signal Processing in LabVIEW FPGA

Non-Configurable Express VI
Some Analysis VIs are non-configurable Express VIs, which can be shown as Express VIs on the block
diagram. As the name implies, they do not contain configuration dialog boxes, so nothing happens if
you double-click the node. In most cases, the additional functionality provided by these nodes adapts
the output data type to facilitate the input data type(s). As with all LabVIEW Express VIs, including

ts
the fully configurable Express VIs, you can right-click the node and select Convert to subVI to view
the underlying implementation. However, after you convert the express VI to LabVIEW code, the

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output data type no longer adapts to the input data types.

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Configurable Express VI

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

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The VIs in the FPGA Math & Analysis Palette with the blue background (analysis) or purple background
(High-Throughput Math) are fully configurable Express VIs, but they are specific to FPGA targets and
not available on Windows or RT platforms. Express VIs consume input data and generate output data,
2

and they also change their run-time behavior based on parameters configured at edit time. The
parameters are configured by double-clicking the node to launch its configuration dialog box. The
configuration dialog depends on the VI selected. In general, most configurable Express VIs in the
ht

analysis palette allow the programmer to configure the node execution mode. The execution mode
determines if the generated code is optimized for use within a Single Cycle Timed Loop or not. There
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are special considerations for operating these nodes inside a Single Cycle Timed Loop.
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There are additional configuration options in most of the high throughput math nodes. For example,
you can configure the encodings, word lengths, and integer word lengths of the input and output
terminals, whether to add internal registers for function inputs and/or outputs, and the minimum
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number of cycles between two successive values of valid input data. Throughput and latency may
change with data types. You cannot generate graphical code from high throughput math nodes.
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© National Instruments Corporation | 3-29

 Lesson 3 Signal Processing in LabVIEW FPGA

D. Integrating Third-Party Intellectual Property (IP)

Objective: Explore the usage of external functions and their integration into the FPGA VI.

LabVIEW Third-Party IP Integration

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Use the Xilinx IP functions to implement different Xilinx IP in an FPGA VI. LabVIEW implements these
functions using the IP Integration Node. The names and descriptions for these functions come from

en
Xilinx IP data sheets, available on the Xilinx website at www.xilinx.com.

The Xilinx IP palette varies by target and displays only Xilinx IP functions that your FPGA device

m
supports. Not all FPGA device families support all Xilinx IP. Refer to the Xilinx IP data sheets for
information about FPGA device family support.

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Some of the Xilinx IP requires licensing from Xilinx. You can find the licensing information in the

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Context Help window for a specific Xilinx IP. To import a license, place the .lic file in one of the
following default directories, depending on your specific FPGA target:
• Xilinx ISE—C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses, where XilinxY_Z is
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the current version of the Xilinx compilation tool for ISE for your FPGA target.
• Xilinx Vivado—C:\NIFPGA\programs\VivadoA_B\data\ip\core_licenses, where VivadoA_B is
at

the current version of the Xilinx compilation tool for Vivado for your FPGA target.

To compile VIs containing licensed IP, ensure that the license exists on the computer.
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Note You should have the Xilinx compilation tools installed on the local computer to
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configure these functions. Refer to the Xilinx Compilation Tools Readme for instructions on
installing Xilinx compilation tools for LabVIEW. If you move Xilinx IP generated on a given
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FPGA target to another FPGA target, you may need to regenerate the Xilinx IP.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Integrating Xilinx CORE Generator IP into FPGA VIs

The Xilinx Coregen IP palette displays only IP that your FPGA device family supports. Not all FPGA
device families support all IP. Refer to the data sheet of an IP for information about FPGA family
support.

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Note You need a separate Xilinx license to use some of the Xilinx CORE Generator IP.
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 Lesson 3 Signal Processing in LabVIEW FPGA

Integrating Other Third-Party IP into FPGA VIs

• Use the IP Integration Node to integrate third-party IP into the block diagram of an FPGA VI.
• Import IP from IP synthesis files, such as .vhd, .xco, .ngc files.
• Must be placed inside the SCTL.

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• Must ensure that IP meets the requirements of IP Integration Node.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Using CLIP in a LabVIEW FPGA Application

1. Create or acquire the IP.
2. Declare the Component-Level IP (CLIP) and define the IP interface in the properties of an FPGA
target.
3. Add CLIP items to the project.

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4. Use the CLIP items in an FPGA VI.

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 Lesson 3 Signal Processing in LabVIEW FPGA

Additional Resources

Topic Website

Deciding Which Data Type to Use in FPGA Designs (FPGA Module)

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Using the Single-Precision Floating-Point Data Type

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LabVIEW Help
Functions that Support the Single-Precision Floating-Point Data Type in
FPGA VIs (FPGA Module)

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Using the IP Integration Node

Increase IP Reuse With the Xilinx CORE Generator IP Palette

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Importing External IP Into LabVIEW FPGA

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. If your SGL algorithm meets the application requirements and successfully compiles, do you need
to rewrite your algorithm using the fixed-point data type?
a. Yes
b. No

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2. Which of the following are parameters used to define the range of values that are represented by
a fixed-point number?

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Select all that apply.
a. Rounding Mode

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b. Sign Encoding
c. Word Length
d. Integer Word Length

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3. Which of the following third-party FPGA IPs can you reuse in your FPGA VIs?
Select all that apply.
a. Xilinx CORE Generator IP

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b. Third-Party IP synthesis files that meet the requirements of IP Integration Node
c. CLIP
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4. Which of the following corresponds to the element used to access items from a CLIP node?
a. Verilog Node
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b. IP Integration Node
c. CORE Generator
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d. CLIP IO Node
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 Lesson 3 Signal Processing in LabVIEW FPGA

Activity: Lesson Review—Answers

1. If your SGL algorithm meets the application requirements and successfully compiles, do you need
to rewrite your algorithm using the fixed-point data type?
a. Yes
b. No

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2. Which of the following are parameters used to define the range of values that are represented by
a fixed-point number?

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Select all that apply.
a. Rounding Mode

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b. Sign Encoding
c. Word Length
d. Integer Word Length

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3. Which of the following third-party FPGA IPs can you reuse in your FPGA VIs?
Select all that apply.
a. Xilinx CORE Generator IP

na
b. Third-Party IP synthesis files that meet the requirements of IP Integration Node
c. CLIP
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4. Which of the following corresponds to the element used to access items from a CLIP node?
a. Verilog Node
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b. IP Integration Node
c. CORE Generator
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d. CLIP IO Node
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4

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Inter-Process

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Communication

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in LabVIEW

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Explore the available communication mechanisms for

processes running in the FPGA.
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Topics
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A. Exploring Parallel Loops on FPGA

B. Transferring Latest Data (Tag)
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C. Transferring Buffered Data (Stream, Message)

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Exercises
Exercise 4-1 Transfer Latest Values to PID Loop
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Exploring Parallel Loops on FPGA

Objective: Explore parallel loops, performance considerations, and how to communicate between
loops running in the FPGA.

Common Architecture

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In a typical data acquisition system, you may see architectures similar to what is shown here as a
common architecture example. Essentially, the main parts of an embedded data acquisition system

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will include the acquisition loop, the data processing loop, and a communication loop to share data
with the RT and host.

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Parallel Loops with Different Sampling Rates
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The presented loops run in parallel because there are no shared resources between the two loops.
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Parallel operations are a very powerful concept in current computer architecture. In a standard
processor-based configuration, parallel operations are not truly parallel. In processor-based
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architectures, programs running on the processor are sliced into many fragments and interleaved with
code fragments from other processes. The operating system then decides which processes are most
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important and schedules the fragments of code accordingly.

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© National Instruments Corporation | 4-3

 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Loop Rate Limitation—Longest Path

• AO takes ~35 ticks; DI takes 1 tick (HW-specific).
• DI is limited by AO when in the same loop.

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Another advantage of running code in parallel is that some sections of code can run faster than others.
One set of code in a loop can severely limit the speed of another piece of code. In this application, the
analog output runs 35 times slower than the digital input. This can become particularly critical if the

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code is arranged such that the digital line corresponds to an emergency stop switch and the
recognition of the response has to happen immediately.

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38 ticks = Read Connector0/AO0 control (1 tick) + FPGA I/O node
(AO0 takes ~35 ticks) + While Loop overhead (2 ticks)
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• Separate functions to allow DI to run independently of AO.
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• This allows you to sample DI 10 times faster by using a separate loop.

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The code is divided into two parallel operations. The loop on the left-hand side runs at the same analog
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output-limited rate of about 1 MHz. However, the code of the right-hand side loop can run at a rate
of 10 MHz, or 10 times faster. Often, when code runs too slowly, you can separate the code into
parallel operations to prevent unrelated processes from interfering with each other.
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38 ticks = Read Connector0/AO0 control (1 tick) + FPGA I/O node

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(AO0 takes ~35 ticks) + While Loop overhead (2 ticks)

4 ticks = FPGA I/O node (DIO0takes 1 tick) + write to stop indicator (1 tick) +
While Loop overhead (2 ticks)
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Note On R Series Multifunction devices, the above-mentioned case can be accomplished

on the same device. Each channel can be sampled simultaneously at different rates.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Sharing Data between Parallel Loops

What if you want to pass data from one loop to another?
• Since loops are executing in parallel, you cannot use a traditional LabVIEW wire to pass data.
• Need access to a resource that can be shared by multiple processes.

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However, you can use LabVIEW channel wires to pass data between parallel processes in LabVIEW
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RT and FPGA.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

B. Transferring Latest Data (Tag)

Objective: Explore the usage of tags to transfer single points of data.

Using Tags in LabVIEW FPGA

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To store and access latest data on the FPGA, use the following items:
• Local and Global Variables

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• Memory Items
• Register Items
• Register Wires

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Exploring Global and Local Variables

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Variables
• Block diagram elements that allow you to access or store data in the flip-flops of the FPGA.

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Store only the latest data you write to it.
• Do not need every value you acquire.

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• Do not need extra code to discard unused values.

Two types of variables on FPGA:

• Local—Accessible only by a single VI na
Global—Accessible by any VI running on the FPGA target
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•

Local Variables
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• Store data in front panel controls and indicators.

Are accessible only by a single VI.
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• Use to maintain data separately for separate re-entrant subVIs.

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To create a local variable, right-click a control or indicator on the block diagram and select
Create»Local Variable.
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If you use this approach, you may find yourself creating controls and indicators only for data sharing
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within the VI they are on. Create a coding convention to help you distinguish such controls and
indicators from those that are meant for passing data in and out of VIs.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Transfer tag data between parallel loops running in the same FPGA VI.

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You can use local variables to stop multiple parallel loops with a single front panel control.

Global Variables

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• Accessible across multiple FPGA VIs.
• To create a global variable, go to the Functions palette and select Structures»Global Variable.

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• If you created a control or indicator only to use a local variable, consider replacing it with a global
variable instead to decrease FPGA resource usage.

na
io
Replacing the local variable and corresponding control or indicator with a global variable will save
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FPGA resources by eliminating the need for the FPGA resources that implement the control/indicator
on the front panel.
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Exploring Memory Items

look up table
3

Memory Items
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• Only the most recent data is stored.

• Data can be stored in FPGA LUTs, memory, or DRAM.
Allocate an address or block of addresses.
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• Can use all available memory on the FPGA.

Use of block memory consumes relatively few logic resources, unlike a front panel array.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Memory Item Usage

• Useful if you do not need every data value that you acquire.
• If you need every data value, FIFOs are a better option.
• There is no need to discard old values.

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Two options for creation:
• Target-Scoped

en
• VI-Defined

When using a memory item, data is overwritten on subsequent writes, so no additional code is needed

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to remove the value before another write can occur.

Target-Scoped Memory Items

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• Accessible by any VI running on the FPGA target.
• Use to store data that is accessed by multiple VIs.

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Creation Process
1. Right-click the FPGA Target.

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2. Select New»Memory.
The Memory Properties dialog box launches.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Memory Properties Dialog Box: General Page

Use the General page to edit properties for memory items.
• Requested Number of Elements—The number of elements the memory item can hold. The actual
memory usage, in bytes, depends on the number of elements and the data type that is selected.
• Implementation—Specifies how the FPGA stores the memory item.

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• Look-Up Table—Stores the memory item in look-up tables available on the FPGA.

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• Block Memory (default value)—Stores the memory item using embedded blocks of memory on
the FPGA.
• DRAM—Memory external to the FPGAs, available only on some targets.

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Target-Scoped Memory Item: Memory Properties Dialog Box

Use block memory when:
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• You need a larger amount of memory.

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• You do not have enough logic resources available to use look-up tables.

Use look-up tables when:

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• Accessing memory in a single-cycle timed loop and need to read data from memory in the same
cycle as the one in which you give the address.
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• The amount of memory needed is smaller than the minimum amount of embedded block memory
on the FPGA.
You do not have enough free embedded block memory on the FPGA.
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Check the hardware documentation for information regarding the amount of block memory available
on your FPGA.

© National Instruments Corporation | 4-9

 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Memory Properties Dialog Box: Initial Values Page

Use the Initial Values page to initialize the memory item that you have created.
• Initialization Method—Specifies the method you want to use to initialize the memory item.
• Mode—Specifies the contents with which LabVIEW populates the address interval you select.
Start Address—The low end of the memory item interval you want to populate.

ts
•

• End Address—The high end of the memory item interval you want to populate.

en
• Value—The constant LabVIEW enters the memory item if you select Constant from the Mode
drop-down menu.
• Slope—Slope of the line LabVIEW enters the memory item if you select Linear from the Mode

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pull-down menu.
• Apply—Displays the initial values in the Graph Preview and Data Value tabs.

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• Graph Preview—Displays the current contents of the memory item in a waveform graph.
• Data Values—Displays the current contents of the memory item.
• Reset to Default Values—Resets the contents of the memory item to the default value for the data

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type contained in the memory item.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

2 VI-Defined Memory Item

• Use it for data that you only access from a single VI.
• Use it for maintaining separate data for separate instances of a re-entrant subVI.
• Right-click the VI-Defined Memory Configuration item and select Configure to launch the
Properties dialog box.

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Memory Write and Read
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• Add the Memory Method node from the Functions palette.

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• Select the memory item to be modified.

• Right-click the node and select Select Memory.
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• Choose to read from or write to the memory item.

• Right-click the node and select Select Method.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

• Address—The location of the data in memory on the FPGA target.

• Data—The data to be written to or read from the memory on the FPGA target.
• Add error terminals to perform error handling.

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Exploring Register Items

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• Only the most recent data is stored.
• Target-scoped and VI-defined options for creation.

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Target-Scoped

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

VI-Defined

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Use register items to store data when you need to access that data from multiple clock domains or
from different parts of your design and you need to write reusable code.
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In the FPGA Register Properties dialog box, select Initial Value from the Category list to display this
page. Use this page to initialize a register item. You can enter an initial value or call an initialization VI
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that you create.

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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

This page includes the following components:

• Use Initialization VI—Specifies whether LabVIEW uses an initialization VI that you create. The
default is unchecked.

Note You should use an initialization VI if you have specified custom control as the data
type for the register item.

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VI Path—Specifies the path to the initialization VI.

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•

• New VI from Template—Creates an instance of a template VI, saves the VI to the location you
specify in the Name the New Initialization VI dialog box, and opens the VI. You must close the
FPGA Register Properties dialog box to edit the VI.

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• Open VI—Opens the VI you specify in the VI Path field. You must close the FPGA Register
Properties dialog box to edit the VI.

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• Run VI—Runs the VI you specify in the VI Path field. LabVIEW then imports the output value into
the register item and displays the corresponding value in the Initial Value field.
Initial Value—Indicates the initial value of the register item. If you do not select an initialization VI,

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use this control to specify an initial value.

Differences from Memory items

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• Only share one element (a memory item can share a block of elements)

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Register items store scalars; Memory items store arrays.
Register items access or store data in the registers of the FPGA.
Register items do not consume block memory, which is the most limited type of FPGA resource.
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Use register items to store data when you need to access that data from multiple clock domains
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(multiple SCTLs using different FPGA clocks, e.g., share data between an SCTL using a 60 MHz clock
and an SCTL using an 80 MHz clock) or from different parts of your design and you need to write
reusable code. Register items consume fewer FPGA logic resources than FIFOs, and they do not
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consume block memory, which is the most limited type of FPGA resource.

Note Register items do not support type definitions. If your application requires you to use
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a type definition, use a global variable instead of a register item.

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The LabVIEW FPGA Module has two types of register items:

• VI-defined register items: Use VI-defined register items to create reentrant subVIs and avoid
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resource conflicts. If you configure a VI-defined register item in a reentrant FPGA VI, LabVIEW
creates a separate copy of the register item for each instance of the VI.
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• Target-scoped register items: Use target-scoped register items if you want the register item to
be visible and configurable from the Project Explorer window. Target-scoped register items are
available within any FPGA VI under the same target in the Project Explorer window.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 4-1: Transfer Latest Values to PID Loop

Goal
Update the PID Control Loop with the latest sensor values to improve control accuracy and
responsiveness.

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Requirements

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To complete this exercise, it is necessary to have access to the following hardware and software.

Software:

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• LabVIEW 2023 Q3 (32-bit)
• NI-DAQmx 2023 Q3 (32-bit)

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• LabVIEW Real-Time Module 2023 Q1 (32-bit)
• LabVIEW FPGA Module 2023 Q1 (32-bit)

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• NI CompactRIO 2023 Q3 (32-bit)

Hardware:

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• An NI CompactRIO from either the 904x or 905x product lines
• USB Type C or RJ45 Ethernet connection
•

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NI-9211 Thermocouple Input C Series Module
NI-9474 Digital I/O C Series Module
Windows 10 PC
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Scenario
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This exercise aims to use the recently introduced methods to transfer data between the FPGA loops.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Implementation
1. From the C:\Exercises\FPGA\Transfer Acquired Data to PID Loop directory, open
[FPGA] Fan Control (prototype) [cRIO-9056].lvproj.
2. Configure the CompactRIO target:
a. In Project Explorer, right-click the cRIO RT target and select Properties.

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b. In the General category, set the IP Address to the IP address of your cRIO.

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c. Click OK.
3. Examine the communication diagram for the FPGA component of this project:
a. From Project Explorer, double-click

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My Computer»Documentation»Fan Control - Communication Diagram.pdf.
b. View the FPGA component in the communication diagram.

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c. What data needs to be transferred between the loops?
__________________________________________________________
d. What type of data communication and implementation should be used for each of the following

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data? Write your choices in Table 4-1.

Table 4-1. Data to Transfer between FPGA Loops

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Data to Transfer Transfer Type Implementation
(Tag/Message/Stream) (Register Memory, FIFO,

Fan Speed
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Max Acceleration
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Input Error
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4. Examine the alternative solution presented in Table 4-2.

Table 4-2. Data to Transfer between FPGA Loops—Alternative Solution

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Data to Transfer Transfer Type Implementation

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(Tag/Message/Stream) (Register Memory, FIFO,

Local Variable, Global Variable)
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Fan Speed Tag Register

Max Acceleration Tag Register

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Input Error Tag Register

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Complete the following steps to create VI-Defined Register Configuration items and edit those to have
the result shown in Figure 4-1.
5. Create a Fan Speed (RPM) Register item.
a. From Project Explorer, open FPGA Main.vi.
b. Place a VI-Defined Register Configuration on the block diagram in the first frame of the

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Sequence structure. Double-click it and select Configure.
c. In the General category, set Name to Fan Speed (RPM).

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d. In the Data Type category, set Data Type to SGL.
e. In the Initial Value category, set Initial Value to 0.

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6. Create an Input Error Register item.
Repeat the procedure of the previous step with the following edits:

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• Name: Input Error
• Data Type: Boolean
• Initial Value: 0

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7. Create a Max Acceleration Exceeded Register item.
Repeat the procedure of the previous step with the following edits:
• Name: Max Acceleration Exceeded

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• Data Type: Boolean

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• Initial Value: 0
8. Verify that the first frame of the Sequence structure should look like Figure 4-1.
Figure 4-1. FPGA Main VI—First Frame of Sequence Structure
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9. Modify the Acquisition Loop on the block diagram, as shown in Figure 4-2, to write to the registers in the Acquisition Loop.
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Lesson 4
Figure 4-2. FPGA Main VI Block Diagram—Acquisition Loop
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Inter-Process Communication in LabVIEW FPGA

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1 Write to the Input Error Register—Place a Register Method Node on the block diagram. Right-click it and select
Select Register VI::Input Error. Right-click it again and select Select Method»Write. Wire as shown in Figure 4-2.
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2 Write to the Fan Speed (RPM) Register—Place a Register Method Node on the block diagram.
Right-click it and select Select Register»VI::Fan Speed (RPM).
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3 Write to the Max Acceleration Exceeded? Register—Place a Register Method Node on the block diagram.
Right-click it and select Select Register»VI::Max Acceleration Exceeded?.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

10. Add files that you will use in a Fan Speed Control Loop to the project.
a. In Project Explorer, double-click FPGA Target»Support VIs. Right-click Support VIs and select
Add»File.
b. Navigate to the C:\Exercises\FPGA\Transfer Acquired Data to PID Loop\support
directory and hold <Ctrl> down to select PID (SGL).vi, Analyze Fan Speed (FPGA).vi,

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PID Control Loop - Partial.vi, and click Add File.
c. Right-click FPGA Target and select New»Virtual Folder. Rename it to Type Definitions.

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d. Double-click FPGA Target»Type Definitions. Right-click Type Definitions and select Add»File.
e. In Project Explorer, double-click FPGA Target»Support VIs. Right-click Support VIs and select
Add»File.

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• Navigate to the C:\Exercises\FPGA\Transfer Acquired Data to PID Loop\controls
directory and hold <Ctrl> down to select Control Configuration.ctl and FPGA state.ctl,

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then click Add File.
11. Copy a partially completed Fan Speed Control Loop into your FPGA Main VI.
a. In Project Explorer, double-click FPGA Target»Support VIs»PID Control Loop - Partial VI

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to open it.
b. Select everything on the block diagram and copy into your FPGA Main VI block diagram.

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c. Verify that your FPGA Main VI block diagram looks similar to Figure 4-3.

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12. Examine the partially completed Fan Speed PID Control While Loop.
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Lesson 4
Figure 4-3. FPGA Main VI with Partially Completed Fan Speed PID Control While Loop
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Inter-Process Communication in LabVIEW FPGA

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1 State Machine Design Pattern—Notice that this While Loop uses a state machine design pattern. The FPGA State enum contains the
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two states in this state machine: Safe State and Control (PID). If the Change State control is set to TRUE, the state machine will transition
to the state specified by New FPGA State control. However, if the output of the Compound Arithmetic function is TRUE, the state
machine will always transition to Safe State.
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2 Change State Boolean control—Change State Boolean control is set to a Latch mechanical action. Therefore, if this Boolean control is
set to TRUE, LabVIEW will read the TRUE value from the control and then reset the control back to its default value of FALSE.
3 Stacked Shift Register—The top element of the stacked shift register outputs the value sent to the shift register during the previous
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iteration of the While Loop. The bottom element of the stacked shift register outputs the value sent to the shift register during the
iteration before the previous iteration of the While Loop. Notice that the Control (PID) case of the Case structure is able to use the stacked
shift register to determine if the state machine is transitioning from the Safe State to the Control (PID) state.
4 Analyze Fan Speed (FPGA) subVI—Similar functionality to the subVI used in the Acquisition Loop.
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5 Get Loop Period (tick) subVI—This is the same subVI used in the Acquisition Loop VI. This subVI is reentrant.
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13. Modify the block diagram, as shown in Figure 4-4, to create the Fan Speed PID Control Loop.

Figure 4-4. Fan Speed PID Control Loop

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Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

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1 Read tag data from Fan Speed (RPM) Register—Place a Register Method Node on the block diagram. Right-click it and select
© National Instruments Corporation

Select Register»VI::Fan Speed (RPM)—Right-click it again and select Select Method»Read. Wire as shown in Figure 4-4.
02
2 Read tag data from Input Error Register and Max Acceleration Exceeded Register—Place a Register Method Node on the block diagram.
Right-click it and select Select Register»VI::Input Error and Select Register»VI::Max Acceleration Exceeded.
3 Loop Timer Express VI—This function sets the loop period for the Fan Speed PID Control While Loop. In the Configure Loop Timer
window of this Express VI, set Counter units to uSec and Size of internal counter to 32 Bit.
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4 PID (SGL) subVI—In Project Explorer, drag the FPGA Target»Support VIs»PID (SGL) VI to the block diagram. This subVI implements a
PID algorithm using the SGL data type.
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5 FPGA I/O Node—In Project Explorer, drag the Mod2/AO0 FPGA I/O item to the block diagram. The PID (SGL) subVI determines the
voltage value to write to this analog output channel to achieve the specified fan speed setpoint.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

14. Modify the Safe State case of the Case structure as shown in Figure 4-5.

Figure 4-5. Safe State

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15. Arrange the front panel as shown in Figure 4-6.

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Figure 4-6. Completed Front Panel

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16. Set all the front panel control values to match Figure 4-6.
Select Edit»Make Current Values Default to set the default value of all the front panel controls.
17. Save the VI and the project.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Test in Simulation Execution Mode

Note If you are taking a vILT training and using virtual machines, you will not be able to
perform the below mentioned steps.

1. Run the VI in simulation execution mode:

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a. Right-click the FPGA Target and select Select Execution Mode»Simulation (Simulated I/O).

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b. Run the VI.
c. Click the Change State control and look at the indicator values, execution highlighting,
single-stepping, probes, and other tools to verify that the FPGA Main VI correctly transitions

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into the Control (PID) and Safe State states by setting the New FPGA State control.

Compile and Test in FPGA Target Execution Mode

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1. Set the front panel controls back to the values shown in Figure 4-4.
2. Compile the FPGA VI:

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a. Right-click the FPGA Target and select Select Execution Mode»FPGA Target.
b. Run the VI.

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c. When finished compiling, run the VI on the FPGA target.
d. Verify that the PID Loop Period (tick) indicator displays 8000 ticks, which is the number of

control.
3. Test the Control (PID) State: na
ticks that corresponds to the Requested PID Loop Period (us) of 200 us on the front panel
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a. On the Sound and Vibration Signal Simulator, set the FAN SPEED CONTROL switch to BNC.
b. Set the Fan Speed Setpoint (RPM) to 0.
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c. Set the New FPGA State control to Control (PID). Click the Change State Boolean control. The
FPGA should now be running the Control (PID) state.
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d. Change the value of the Fan Speed Setpoint (RPM) control to something between 1000 and
5000, and verify that the Fan Speed (RPM) indicator.
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4. Test the Safe State and transition to Safe State:

a. Set the Fan Speed Setpoint (RPM) back to 0.
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b. Set the Maximum Fan Speed Threshold (RPM) control to 2000.

c. Now change the Fan Speed Setpoint (RPM) control to 3000. Verify that when the fan speed
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exceeds 2,000 RPM, the fan turns off and the Current FPGA State indicator changes from
Control (PID) to Safe State.
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5. Save the VI and project.

End of Exercise 4-1

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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Exploring Channel Wires

• Pass data between parallel loops without interfering with parallelism.
• Consist of a reader and writer channel endpoint connected together.
• Visibly show data flow between parallel processes.

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Channel wire endpoints are nodes where a channel wire terminates. By connecting a channel writer
endpoint to a reader endpoint using a channel wire, you build a channel. The channel wire endpoints

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operate on the channel in the following way: the writer endpoints write data to the channel, and the
reader endpoints read data from the channel. You can use the channel wire endpoints to write or read
data between parallel sections of code. LabVIEW provides several channel templates. Each template

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expresses a different communication protocol to use between the writers and readers. Choose which
channel template to use based on your communications needs.

Creating Channel Wires

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To create a channel reader or writer endpoint, right-click a node.
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• A dialog box will prompt you to select the type of endpoint and desired template.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Endpoint Description

Read Reads a value from a Tag channel.

Read With Abort Reads a value from a Tag channel or signals the channel to abort.

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This endpoint is the same as the Read endpoint except that it has
an abort input and an aborted? output. You can use the abort

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capability of the Tag channel to close a channel abruptly, ignoring
any data left in the channel buffer. You must use this endpoint
together with the Write With Abort endpoint.

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Write Writes a value to a Tag channel.

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Write With Abort Writes a value to a Tag channel or signals the channel to abort. This
endpoint is the same as the Write endpoint except that it has an
abort input and an aborted? output. You can use the abort capability

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of the Tag channel to close a channel abruptly, ignoring any data left
in the channel buffer. You must use this endpoint together with the
Read With Abort endpoint.

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Channel Wires: Tag Data Template
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The process of sharing value is similar to that of a global or local shared variable.
Tag channel is used to share a single value among multiple readers and/or writers.
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• Writer overwrites the existing value in the channel to ensure the reader always gets the latest
value.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Use the Tag channel to share a single value among multiple readers and/or writers. Sharing the value
is similar to sharing a global or network-shared variable. Each time a writer endpoint writes a value to
the channel, the value overwrites the existing value in the channel to ensure that the reader endpoints
always read the latest value.

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Endpoint Description

Read Reads a value from a Tag channel.

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Read Scheduled Reads a value from a Tag channel at a scheduled time.

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Read With Abort Reads a value from a Tag channel or signals the channel to abort.

Write Writes a value to a Tag channel.

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Write Scheduled Writes a value to a Tag channel at a scheduled time.

Write With Abort Writes a value to a Tag channel or signals the channel to abort.

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This endpoint is the same as the Write endpoint except that it has
an abort input and an aborted? output.

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The Read With Abort and Write With Abort are similar to Read and Write endpoints, respectively. The
only difference is that they have an abort input and an abort output. The abort capability of the Tag

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channel can be used to close a channel abruptly, ignoring any data left in the channel buffer. The Read
with Abort and Write with Abort endpoints must be used together.
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The following details apply when you use this object in an FPGA VI:
• Single-Cycle Timed Loop is not supported.
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• This endpoint supports only fixed-sized one-dimensional arrays of supported data types. This
endpoint does not support variable-sized arrays even if the array resolves to a single size at compile
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time.
• This endpoint does not support LabVIEW classes.
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Note The mentioned details are subject to change with each version of the LabVIEW FPGA
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Module.

Note A channel terminal of a non-reentrant subVI can be connected to only one channel.
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If a non-reentrant subVI is called from multiple locations, the channel wires connected to a
given terminal must resolve to the same channel at compile time.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Channel Wires: Accumulator Tag Data Template

• Includes an accumulation output giving the current tag count as an I32.
• Can optionally clear the count after you read it.

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Available Channel Wire Templates

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• Tag—Use the Tag channel to share a single value among multiple readers and/or writers. Sharing

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a value is like sharing a global or network shared variable. Each time a writer endpoint writes a
value to the channel, the value overwrites the existing value in the channel to ensure that the
reader endpoints always read the latest value.
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• Accumulator Tag—Same as a Tag, but each time a writer endpoint writes a value to the channel,
the channel adds the value to the existing value. Reader endpoints can optionally clear the value
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when they retrieve the current sum.
• Stream—Use the Stream channel to communicate homogeneous data from a single writer to a
single reader. The data elements are buffered and transferred with no data loss in a first-in-first-out
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(FIFO) order.
• Lossy Stream—Same a stream, but if the channel is already full when the writer attempts to write
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a new data, the writer does not wait for space to be available.
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• One Element Stream—Same as a stream but with a size equal to one. Allowing only one element
in the buffer makes One Element Stream channels more optimized.

Demonstration: Comparing Channel Wires and Streams

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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

C. Transferring Buffered Data (Stream, Message)

Objective: Explore the available mechanisms to transfer stream and message data.

Exploring FIFO

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First-in-First-Out (FIFO) buffer The first data item written to the FIFO is the first item read and

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removed from the FIFO.

Like memory and registers for tag transfer, FIFOs can either be:

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• Target-Scoped—A single FIFO transfers data between loops on multiple VIs running on the same
FPGA target.

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• VI-Defined—A single FIFO transfers data between multiple loops in the same VI.

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To transfer data between different portions of an FPGA VI, between VIs on an FPGA target, or
between devices, use a FIFO. A FIFO is a data structure that holds elements in the order they are
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received and provides access to those elements using a first-in-first-out access policy.

The presented illustration demonstrates the behavior of elements moving through a FIFO.
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Use FIFOs to transfer data in the following ways:

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• Between parallel loops within one clock domain

• Across clock domains
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• Between peer-to-peer targets

• Between the host computer and the FPGA
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Use the FIFO Properties dialog box to create and configure FIFOs. All FIFOs except VI-defined FIFOs
have a corresponding item in the project. Therefore, if you use a FIFO other than a VI-defined FIFO
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and send the FPGA VI to another user, you must send the entire project. Otherwise, you cannot run
the FPGA VI.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Target-Scoped FIFOs
• Appear under the FPGA target in the Project Explorer window.
• Use to store data that you need to access from multiple VIs.
• Create Target-Scoped FIFOs from the Project Explorer window.

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Complete the following steps to create a target-scoped FIFO from the Project Explorer window:
1. In the Project Explorer window, right-click the FPGA target.
2. Select New»FIFO to display the FIFO Properties dialog box.
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3. On the General page, expand the pull-down menu under Implementation to display the available
options.
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4. Click OK to finish creating the FIFO.

5. Drag the FIFO from the Project Explorer window to the block diagram. LabVIEW adds a FIFO
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Method node configured for the FIFO.

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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

FIFO Properties Dialog Box

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Note The Type drop-down does not appear if you have created a VI-defined FIFO. This
page includes the following components:
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• Name—Specifies the name of the FIFO that appears in the Project Explorer window or in the
VI-Defined FIFO Configuration node. The name also appears in the FIFO Method Node on the block
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diagram, and you can use it in FIFO name controls and constants to access target-scoped FIFOs.
• Type—Specifies the type of FIFO to use. This option is not available for VI-defined FIFOs.
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• Target-Scoped—FIFOs can transfer data within the FPGA VI as well as between FPGA VIs
under the same target in the Project Explorer window.
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• Host to Target - DMA or Target to Host - DMA—DMA FIFOs can transfer data between the
host VI and target.
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• Peer to Peer Writer or Peer to Peer Reader—FIFOs can transfer data using a peer-to-peer
stream.
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• Disable on Overflow—Specifies to disable the peer-to-peer stream when the writer FIFO attempts
to write to the stream and fails. This option is only available for peer-to-peer writer FIFOs.
Disable on Underflow—Specifies to disable the peer-to-peer stream when the reader FIFO does not
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receive data from the stream. This option is only available for peer-to-peer reader FIFOs.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

• Requested Number of Elements—Specifies the desired number of elements the FIFO can hold. The
maximum number of elements the FIFO can hold depends on the Implementation you select and
the amount of resources available on the FPGA for the Implementation. If the FIFO uses built-in
control logic, the maximum number of elements also depends on the data type. The width of the
built-in FIFO must be less than or equal to 1024. If the FPGA does not have enough resources for
the Requested Number of Elements you enter, the FPGA VI fails to compile. If you select Host to

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Target - DMA or Target to Host - DMA in the Type pull-down menu, Requested Number of
Elements specifies the size of the FPGA FIFO of the DMA channel. Maximum DMA FIFO size varies

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by target. Refer to the specific FPGA target hardware documentation for more information about
DMA FIFO size limitations. If you select Block Memory in the Implementation control, restrictions
apply to the number of elements the FIFO can hold. Actual Number of Elements indicates the

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Note If you experience timeout during DMA transfers from the FPGA to a host, use the
FIFO. Configure method of the Invoke Method function and increase the Depth parameter
rather than increasing the Requested Number of Elements. Increasing the Depth parameter
increases the size of the host-side buffer, which is more likely to resolve the timeout and

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does not increase FPGA device utilization.

• Implementation—Specifies the type of storage the FIFO uses on the FPGA. You can specify the

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implementation only for target-scoped and VI-defined FIFOs. Contains the following options:
Flip-Flops—Stores the data in flip-flops available on the FPGA and provides the fastest

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performance. NI recommends using this option for small FIFOs, up to 100 bytes. You cannot
use FIFOs with an Implementation of Flip-Flops or Look-Up Table across multiple clock
domains.
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• Look-Up Table—Stores the data in look-up tables available on the FPGA. Xilinx literature
describes this implementation as distributed RAM or LUT RAM. NI recommends using this
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option for FIFOs that are 100–300 bytes. You cannot use FIFOs with an Implementation of
Flip-Flops or Look-Up Table across multiple clock domains.
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• Block Memory—Stores the data using embedded blocks of memory. Xilinx literature describes
this implementation as block RAM or BRAM. NI recommends using this option for FIFOs larger
than 300 bytes.
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Note If you select the Block Memory option, you might not be able to read data in a
target-scoped FIFO or VI-defined FIFO until up to six clock cycles after you write the data
to the FIFO. If you select the timeout interface, use the Timed Out? output of the FIFO
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Method Node that invokes the Read method to determine when the upstream data is ready.
If you select the handshaking interface, use the Output Valid output of the FIFO Method
Node that invokes the Read method to determine whether the upstream data is ready.
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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

All implementation options contain the following components:

• Actual Number of Elements—Returns the configured number of elements. Sometimes the
requested number of elements is not compatible with the FIFO configuration. In this case,
LabVIEW coerces the requested number of elements to a compatible number, and Actual Number
of Elements returns this number. If you select the built-in or target-optimal control logic, Actual
Number of Elements might return multiple numbers.

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Interpret these numbers in the following ways:

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• Built-In—Actual Number of Elements returns two numbers, which LabVIEW uses when the
handshaking interface is disabled or enabled, respectively.

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Note (Xilinx Vivado) The actual number of elements in the FIFO is unknown at
configuration time. Actual Number of Elements returns only one number, which is the

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closest power of two, greater than Requested Number of Elements. This number is a
minimum guaranteed number, which might be smaller than the actual number of elements
in the FIFO.

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• Target-optimal—LabVIEW implements the FIFO using either slice fabric or built-in control logic,
depending on the clock domain and target type. Actual Number of Elements returns two or

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three numbers: the first one for the slice fabric control logic and the other(s) for the built-in
control logic.
•

•
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Control Logic—Specifies how the FPGA implements the FIFO.
Slice Fabric—Specifies that the FPGA uses flip-flops, LUTs, and block memory to implement
the control logic for the FIFO.
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• Target Optimal—Specifies that the FPGA uses built-in FIFO control logic or slice fabric control
logic, depending on the target and application.
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• Built-In—Specifies that the FPGA uses built-in FIFO control logic. Not all FPGAs support built-in
FIFO control logic, and restrictions apply.
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Note (Xilinx Vivado) If you select the built-in control logic, you cannot use this FIFO with
the Get Number of Elements to Read or Get Number of Elements to Write method because
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the actual number of elements in the FIFO is unknown at configuration time. In simulation
mode, the Timed Out? output value of the Read or Write method might not reflect the actual
02

behavior on hardware because these methods use the conservative number in Actual
Number of Elements as the FIFO depth, which might be smaller than the actual number of
elements in the FIFO.
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FIFO: Number of Elements

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Maximum depends on the Implementation that has been selected and the amount of space available
on the FPGA for the implementation.
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You request the number of elements based on the needs of the application. LabVIEW specifies the
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

If the value specified is too large, The FPGA will fail to compile. For DMA FIFOs, Requested Number
of Elements specifies the size, in elements, of the FPGA part of the FIFO.

Requested Number of Elements—Specifies the desired number of elements the FIFO can hold. The
maximum number of elements the FIFO can hold depends on the Implementation you select and the
amount of resources available on the FPGA for the Implementation. If the FIFO uses built-in control

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logic, the maximum number of elements also depends on the data type. The width of the built-in FIFO
must be less than or equal to 1024. If the FPGA does not have enough resources for the Requested

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Number of Elements you enter, the FPGA VI fails to compile. If you select Host to Target - DMA or
Target to Host - DMA in the Type pull-down menu, Requested Number of Elements specifies the size
of the FPGA FIFO of the DMA channel. Maximum DMA FIFO size varies by target. Refer to the specific

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FPGA target hardware documentation for more information about DMA FIFO size limitations. If you
select Block Memory in the Implementation control, restrictions apply to the number of elements the
FIFO can hold. Actual Number of Elements indicates the number of elements in the FIFO, which may

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not be the same as Requested Number of Elements.

Note If you experience timeout during DMA transfers from the FPGA to a host, use the

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FIFO. Configure the method of the Invoke Method function and increase the Depth
parameter rather than increasing the Requested Number of Elements. Increasing the Depth
parameter increases the size of the host-side buffer, which is more likely to resolve the

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timeout but does not increase FPGA device utilization.

FIFO: Implementation
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Implementation—Specifies the type of storage the FIFO uses on the FPGA. You can specify the
implementation only for target-scoped and VI-defined FIFOs. Contains the following options:
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• Flip-Flops—Stores the data in flip-flops available on the FPGA and provides the fastest
performance. NI recommends using this option for small FIFOs, up to 100 bytes. You cannot use
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FIFOs with an Implementation of Flip-Flops or Look-Up Table across multiple clock domains.
• Look-Up Table—Stores the data in look-up tables available on the FPGA. Xilinx literature describes
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this implementation as distributed RAM or LUT RAM. NI recommends using this option for FIFOs
that are 100–300 bytes. You cannot use FIFOs with an Implementation of Flip-Flops or Look-Up
Table across multiple clock domains.
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• Block Memory—Stores the data using embedded blocks of memory. Xilinx literature describes this
02

implementation as block RAM or BRAM. NI recommends using this option for FIFOs larger than
300 bytes.
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Note If you select the Block Memory option, you might not be able to read data in a
target-scoped FIFO or VI-defined FIFO until up to six clock cycles after you write the data
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to the FIFO. If you select the timeout interface, use the Timed Out? output of the FIFO
Method Node that invokes the Read method to determine when the upstream data is ready.
If you select the handshaking interface, use the Output Valid output of the FIFO Method
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Node that invokes the Read method to determine whether the upstream data is ready.
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© National Instruments Corporation | 4-33

 Lesson 4 Inter-Process Communication in LabVIEW FPGA

VI-Defined FIFOs
Right-click the VI-Defined FIFO Configuration item and select Configure to launch the Properties
dialog box.

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FPGA FIFO Write and Read
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• Place a FIFO Method Node from the Functions palette.
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• Right-click the object and select Select FIFO»VI::FIFO.
• This associates a node with a defined FIFO.
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• Right-click the object and select Select Method.

• Choose Write or Read.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

FPGA FIFO Write and Read

Element—The data element to write and or read.

Timeout—Sets the number of ticks that the method waits for available space or data if the FIFO is full
or empty.

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Timed Out?—True if the attempt to write or read failed. Does not overwrite or add new element.
FIFO transfer may be lossy if the write times out.

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•

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The default Timeout value is 0, resulting in no wait. If you set the Timeout value to -1, then the node
will wait indefinitely. FIFO write can fail if the FIFO was full at the time that the FIFO Write method
was called.

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FIFO Overflow and Underflow

•
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Overflow: Write loop executing faster than the read loop.
FIFO is filled, and the FIFO Write method times out.
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• Data is not written to the FIFO until space is available in the FIFO.
Space can be created by reading data or resetting the FIFO.
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•

• Data is lost until space is made available.

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Underflow: Write loop executing slower than read loop.

• FIFO is empty and the FIFO Read method times out.
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Handling FIFO Overflow and Underflow

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The method for handling overflow/underflow depends on the importance of lossless transfer.
• Latch Timed Out? output of the read/write method so that the operator can see if a timeout
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ever occurred.
• Use Timed Out? output as a condition for termination of loop execution.
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Demonstration: Writing and Reading Elements to and from FPGA FIFOs

© National Instruments Corporation | 4-35

 Lesson 4 Inter-Process Communication in LabVIEW FPGA

The following methods can be used to avoid underflow/overflow conditions by monitoring the status
of the FIFO.

Get Number of Elements to Read: Returns the number of elements remaining to be read.

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Get Number of Elements to Write: Returns the number of empty elements remaining in the FIFO.

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Clear Method

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• FIFOs retain data if the FPGA is stopped and restarted.
Use the Clear Method to empty a target-scoped or VI-defined FIFO.

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•

• Place the FIFO Method node.

• Right-click the object and choose Select Method»Control»Clear.
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Additional Resources
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Topic Website

Global Variables
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LabVIEW Help
Communicating Data between Parallel Sections of Code Using
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Channel Wires

Introduction to LabVIEW Channel Wires ni.com

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. Which of the following options can you use to transfer stream or message data between parallel
loops on an FPGA?
Select all that apply.
a. Local variable

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b. Memory item
c. Register item

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d. FIFO
e. Channel Wire

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2. Which of the following is not a supported Channel Wire template in LabVIEW FPGA?
a. Lossy Stream
b. Accumulator Tag

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c. High Speed Stream
d. One Element Stream

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3. Which of the following may result if an FPGA VI with a FIFO Read or Write does not monitor the
Timed Out? output, assuming that the Timeout is not -1 (infinite)?
Select all that apply.
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a. Attempts to write when there is no room in the FIFO may go undetected.
b. Attempts to read from an empty FIFO may be misinterpreted as having produced valid data.
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c. The FIFO may result itself automatically.

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d. LabVIEW will report a code generation error.

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4. Match each method of FIFO implementation with its recommended usage.

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1. Block Memory a. For FIFOs < 100 bytes

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2. Flip-Flops b. For FIFOs that are 100 to 300 bytes

3. Look-Up Table c. For FIFOs > 300 bytes

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 Lesson 4 Inter-Process Communication in LabVIEW FPGA

Activity: Lesson Review—Answers

1. Which of the following options can you use to transfer stream or message data between parallel
loops on an FPGA?
Select all that apply.
a. Local variable

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b. Memory item
c. Register item

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d. FIFO
e. Channel Wire

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2. Which of the following is not a supported Channel Wire template in LabVIEW FPGA?
a. Lossy Stream
b. Accumulator Tag

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c. High Speed Stream
d. One Element Stream

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3. Which of the following may result if an FPGA VI with a FIFO Read or Write does not monitor the
Timed Out? output, assuming that the Timeout is not -1 (infinite)?
Select all that apply.
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a. Attempts to write when there is no room in the FIFO may go undetected.
b. Attempts to read from an empty FIFO may be misinterpreted as having produced valid data.
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c. The FIFO may result itself automatically.

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d. LabVIEW will report a code generation error.

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4. Match each method of FIFO implementation with its recommended usage.

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1. Block Memory c. For FIFOs > 300 bytes

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2. Flip-Flops a. For FIFOs < 100 bytes

3. Look-Up Table b. For FIFOs that are 100 to 300 bytes

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 ts
5

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Communicating

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between the

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FPGA and

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Real-Time VIs
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Explore the available mechanisms to transfer data between

the FPGA and the RT VIs.
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Topics
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A. Programmatically Communicating with the FPGA VI from the

Real-Time VI
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B. Deploying an FPGA VI
C. Transferring Latest Data (Tag)
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D. Transferring Buffered Data (Stream, Message)

E. Synchronizing the RT VI and FPGA VI
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F. Implementing an FPGA Watchdog

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Exercises
Exercise 5-1 Transfer Tag Data between FPGA and RT
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Exercise 5-2 Transfer Stream Data from FPGA to RT Target

Exercise 5-3 Explore DMA FIFO Interleaving
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Exercise 5-4 Explore FPGA Watchdog

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Programmatically Communicating with the FPGA VI

from the Real-Time VI
Objective: Learn how to programmatically communicate with the FPGA VI from the RT VI.

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Developing the Real-Time VI on Real-Time Target
To add a VI under the Real-Time target, right-click cRIO Target in the Project Explorer window, then

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select New»VI.

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Exploring FPGA Interface Functions

• Establish communication with the FPGA VI from the RT VI.
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• Control the execution of the FPGA VI on the FPGA target.

• Read and write data to the FPGA VI.
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• Terminate communication with the FPGA VI.

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© National Instruments Corporation | 5-3

 Lesson 5 Communicating between the FPGA and Real-Time VIs

Opening FPGA VI Interface Function

When the Open FPGA VI Reference function first executes on the block diagram, the function checks
whether the compiled FPGA VI already exists on the FPGA target. If the compiled FPGA VI is not on
the FPGA target, the Open FPGA VI Reference function downloads the compiled FPGA VI to the FPGA
target.

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If you place a checkmark in the Run the FPGA VI checkbox in the Configure Open FPGA VI Reference
dialog box, the FPGA VI starts running if it is not already running. The Open FPGA VI Reference

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function will just open a reference to the FPGA VI if the FPGA VI is already downloaded and running.
If you want to restart the FPGA VI, you can use the Invoke Method function to abort or reset the FPGA
VI, then use the Invoke Method function to run the FPGA VI again.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

B. Deploying an FPGA VI
Objective: Explore different methods to deploy the FPGA bitfile.

FPGA Bitfile Deployment Methods

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Before using an FPGA with LabVIEW, the FPGA should have a bitfile deployed to it. This can be done
in two ways.

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• Deploy the FPGA bitfile dynamically with the Open FPGA VI Reference Function. The FPGA bitfile
will be deployed only when the FPGA reference is opened.
• Save the FPGA bitfile to the FPGA flash. The FPGA bitfile will be automatically deployed during

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power-up.

Note Download an FPGA VI to flash memory on the FPGA target from Project Explorer.

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Bitfile Deployment from RT VI Method

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RT VI can deploy the bitfile directly to the FPGA fabric, or a bitfile can be downloaded onto the
FPGA Flash. The FPGA Flash is persistent and sits alongside the FPGA fabric itself.

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The Open FPGA VI Reference function checks if the bitfile is loaded and loads the bitfile if it has not
already been loaded. The only issue with this method is that one must wait until the OS and VI/EXE
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have loaded before this function executes and starts the FPGA VI/bitfile. In many cases, it is
unacceptable to have the FPGA I/O state uncontrolled as the OS and VI/EXE load.
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© National Instruments Corporation | 5-5

 Lesson 5 Communicating between the FPGA and Real-Time VIs

If you use the Open FPGA VI Reference function, the FPGA loads only after the OS and VI/EXE have
been loaded. Between reboots or on the initial device power on, the FPGA state is uncontrolled. By
default, the FPGA pins float when the I/O state is uncontrolled. The C Series modules are set to accept
floating FPGA pin signals and have a default behavior when they detect floating FPGA pin signals.
Generally, C Series modules will be digital low or analog 0 Volts when the I/O state of the FPGA is
uncontrolled. However, between soft reboots and managing the FPGA state for fail-safe reasons, it is

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useful to have control of the FPGA I/O state independent of the OS and VI/EXE.

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Bitfile Deployment from Flash Method
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In this case, the bitfile is already downloaded onto the FPGA flash. Now, each time the system power
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up or reboots, the FPGA loads the bitfile from the FPGA flash to the FPGA fabric.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

1. The first step in the FPGA Flash Deployment Method is to configure the build specification to
generate a bitfile that is set to run automatically when loaded onto the FPGA target. To do so,
enable the Run When loaded to FPGA option in Build Specifications and then generate the bitfile
using the build specification.

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© National Instruments Corporation | 5-7

 Lesson 5 Communicating between the FPGA and Real-Time VIs

2. The second step in the FPGA Flash Deployment Method is to download the bitfile to the FPGA
flash. You can do this either manually or programmatically.
Manual Method is good for downloading to one or a few FPGA targets.
a. Right-click the FPGA Target in the Project Explorer and select RIO Device Setup to open the
configuration window. In the RIO Device Setup dialog box, use the Download Bitfile tab to
download a bitfile to flash, and use the Device Settings tab to configure when the FPGA loads

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the bitfile from Flash memory. There are three options:

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• Do not autoload—Leaves the I/O state uncontrolled.
• Autoload VI on device powerup—Starts running the FPGA on device power but will not
start running on soft reboots.

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• Autoload on device reboot—Starts running the FPGA on device power and on soft reboots.

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Note Some cRIOs (e.g., the cRIO-906x) do not have the Device Settings tab because those
cRIOs already autoload on device powerup and reboot. For example, if you have downloaded
a bitfile to the NI cRIO-906x, it will be autoloaded by default at startup. If you want to
disable bitfile autoloading, either use the Disable FPGA Startup Application setting in

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NI MAX or click the Erase Bitfile on Flash button in the RIO Device Setup Utility.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Programmatic Method is good for downloading to several FPGA targets.

To download a bitfile to several FPGA targets, use the System Configuration VIs. The subsequent
example shows how to download the bitfile to the FPGA flash of the cRIOs at the IP addresses shown
in the string array constant. This VI block diagram is typically running on a Windows PC and
downloads the bitfile from the Windows PC onto the FPGA flash of the FPGA targets.

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Note You can also use the Find Systems VI to return a string array of the addresses of all
the systems (e.g., cRIO) found on the network.
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This is what the timeline of events looks like for an application that has an FPGA bitfile downloaded
to flash and is set to start either on device power or reboot. Note that the FPGA I/O state is always
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controlled.
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© National Instruments Corporation | 5-9

 Lesson 5 Communicating between the FPGA and Real-Time VIs

C. Transferring Latest Data (Tag)

Objective: Use tags to transfer latest data points and explore the tag communication mechanisms.

Read/Write Control Function

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Read/Write Control Reads a value from or writes a value to a control or indicator in the FPGA VI

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on the FPGA target. A host VI can control, and monitor data passed through
the FPGA VI front panel.

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You cannot access values on any wires on the FPGA VI block diagram that do not have controls or
indicators unless the data is stored in a DMA FIFO.

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Programmatic Front Panel Communication

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Use the Read/Write control with the reference to the FPGA created by the Open FPGA VI Reference.vi
to programmatically communicate with the FPGA, to read values coming from it, or update
parameters.
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RT VI
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

FPGA VI

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Programmatic Front Panel Communication Use Cases
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• Sending configuration parameters or data from RT to FPGA
• Reporting status from FPGA to RT
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• Sending commands between RT and FPGA

• Transferring latest data between RT and FPGA
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• Creating a test bench for an FPGA VI

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An advantage of programmatic front panel communication relative to other methods of transferring

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data between the FPGA and the host is its low overhead. Although you cannot attain high throughput
with programmatic front panel communication, each call to the Read/Write Control function initiates
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data transfer with minimal delay. Therefore, programmatic front panel communication is ideal for
small, frequent data transfers.
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A disadvantage of programmatic front panel communication is that this method transfers only the
most current data stored on the control or indicator of the FPGA VI. For example, data could be lost
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if the FPGA VI writes data to an indicator faster than the host VI can read the data. Also, each control
or indicator on the FPGA VI uses resources on the FPGA. Best practices in FPGA programming
recommend limiting the number of front panel objects in FPGA VIs. Finally, transferring data between
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the FPGA VI and the host VI using front panel controls and indicators requires the use of the host
processor. As a result, the speed of data transfer is highly dependent on the speed and availability of
the host processor. A slower processor or lack of processor availability results in slower data transfer
from the FPGA target to the host.

© National Instruments Corporation | 5-11

 Lesson 5 Communicating between the FPGA and Real-Time VIs

FPGA Interface Functions: Invoke Method

Invoke Method Invokes an FPGA Interface method or action from a host VI on an FPGA VI.

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The following methods are supported by most targets:

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• Run

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• Abort
• Get FPGA VI Execution Mode
• Reset

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• Download

The methods you can choose from depend on the target hardware and the FPGA VI. You must wire

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the FPGA VI Reference In input to view the available methods in the shortcut menu.

Close FPGA VI
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FPGA Interface Functions: Close FPGA VI Reference

Stops and resets the FPGA VI running on the FPGA target and closes the
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Reference reference to the VI.
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Right-click the Close FPGA VI Reference function on the block diagram and select Close to close the
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reference without resetting the FPGA VI running on the FPGA target. The default is Close and Reset
if Last Reference, which closes the reference, stops the FPGA VI and resets the FPGA VI running on
the FPGA target.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 5-1: Transfer Tag Data between FPGA and RT

Goal
Transfer tag data between FPGA and RT target using the Read/Write Control function.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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• Windows 10 PC na
NI-9474 Digital I/O C Series Module
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Scenario
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You will implement the transfer of tag data between the FPGA and RT target and create an RT VI that
resembles a part of the final course project. This course communication diagram is an approximation
to the exercise communication schema. You will create the VI and logic to process the signals
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specified in the communication diagram.

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© National Instruments Corporation | 5-13

 Lesson 5 Communicating between the FPGA and Real-Time VIs
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Figure 5-1. Fan Control—Communication Diagram

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Implementation
1. Review the communication diagram of the course project.
b. From the C:\Exercises\FPGA\Transfer Tag Data from FPGA to RT\Documentation folder,
open Fan Control - Communication Diagram.pdf file.
2. List all the data that needs to be transferred between the FPGA and RT Target. For each data that

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needs to be transferred, identify the transfer type (tag, message, or stream).

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Table 5-1. Data to Transfer between FPGA and RT Target
Data to Transfer Transfer Type (Tag/Message/Stream)

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3. From the C:\Exercises\FPGA\Transfer Tag Data from FPGA to RT directory, open
[FPGA] Fan Control (prototype) [cRIO-9056].lvproj.
a. From Project Explorer, open FPGA Main.vi and run it.

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• This is done so that the bitfile gets compiled as you continue with the next part of the
exercise, which is creating the RT VI.
4. Create an RT VI.
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a. In Project Explorer, right-click the RT Target cRIO-9056 item and select New»VI.
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b. Save the VI as C:\Exercises\FPGA\Transfer Tag Data from FPGA to RT\
RT Main - RT-FPGA Transfer Tag Data.vi.
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 ts
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5. To transfer tag data between the RT VI, modify the block diagram, as shown in Figure 5-2.
5-16

Lesson 5
Figure 5-2. RT Main - RT-FPGA Transfer Tag Data Block Diagram—True Case
|

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Communicating between the FPGA and Real-Time VIs

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1 Open FPGA VI Reference function:
a. Right-click the function and select Configure Open FPGA VI Reference.

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b. Select VI and browse to FPGA Main.vi. This will deploy the bitfile associated with the FPGA VI if it is not already deployed on the
FPGA. Notice there is also a Bitfile option if you want to select a specific bitfile. This will deploy this bitfile if it is not already deployed
on the FPGA.

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c. Leave the Run the FPGA VI and Dynamic mode options enabled. With this configuration, this function will run the FPGA VI if it is
not already running. Click Help to read more information about this dialog box.
d. Click OK.
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2 Transfer tag data between the RT VI and FPGA VI using the Read/Write Control function:
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a. Wire the FPGA VI Reference wire from the Open FPGA VI Reference function to the Read/Write Control function. The Read/Write
Control function is now able to populate with the names of all the controls and indicators on the FPGA VI specified by the Open
FPGA VI Reference function.
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b. Resize this function to show enough items.

c. Select the items. Right-click each item and select Change to Read and Change to Write as necessary.
d. Create controls and indicators from the input and output terminals.
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3 Using the functions shown, change the FPGA State if the value of the New FPGA State control has changed or if this is the first iteration
of the While Loop.
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4 Time the loop to execute once every 100 milliseconds.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

6. Switch to the False case of the Case Structure and modify it, as shown in Figure 5-3.

Figure 5-3. RT Main - RT-FPGA Transfer Tag Data VI Block Diagram—False Case

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7. Rearrange the front panel and set the control values, as shown in Figure 5-4.

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Figure 5-4. RT Main - RT-FPGA Transfer Tag Data VI Front Panel

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8. Save the VI and the project.

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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Test
If you are using in-person hardware, on the Sound and Vibration Signal Simulator, set the following
switches (optional):
1. Verify that all the controls are set to the values shown in Figure 5-4.
2. On the Sound and Vibration Signal Simulator, set the Fan Speed Control switch to BNC and the

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other switch to UNBALANCED FAN.
3. Run the RT Main - RT-FPGA Transfer Tag Data VI, which runs this RT VI on the processor of the

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RT target. You have programmed the RT VI to do the following:
a. Load and run the FPGA bitfile on the FPGA.
b. Transfer tag data between the FPGA VI and RT VI.

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4. Set the Fan Speed Setpoint (RPM) control to 3000.

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5. Notice that the fan does not rotate because the FPGA VI is still in Safe State.
6. Set the New FPGA State control to Control (PID).
7. Verify that the fan starts to rotate and settles at a fan speed of 3000 RPM.

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8. Click the Stop button to stop the VI.
9. Save the VI.

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End of Exercise 5-1

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

User-Defined I/O Variables

Note This topic is only relevant to those who use CompactRIO devices in hybrid mode,
which is a fairly niche subset of LabVIEW FPGA users.

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User-defined I/O variables can be useful if your RT VI is running on an RT target already using both
the NI Scan Engine and FPGA (i.e., hybrid mode). Your RT VI can use Scan Engine I/O Variables to
access the C Series modules in Scan Interface Mode. In addition, you can create a User-Defined I/O

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Variable that you can access in both the FPGA VI and RT VI for tag (latest) data transfer.

User-Defined I/O Variables

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• Read/write in FPGA VI and for FPGA-RT tag data transfer.

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Scan Engine I/O Variables
• Read/write in RT VI.

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Use Cases
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• Similar use cases as programmatic front panel communication, but with the timing and
synchronization of the NI Scan Engine.
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• Transfer time-coherent sets of data.

Disadvantages
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• Including the NI Scan Engine uses FPGA resources.

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• Limited by the specified Scan Period of the NI Scan Engine.

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 Lesson 5 Communicating between the FPGA and Real-Time VIs

D. Transferring Buffered Data (Stream, Message)

Objective: Use streams and messages to transfer multiple data points and explore the
communication mechanisms for their implementation.

Buffer Overview

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Buffer An area of computer memory that stores multiple data items.

• To transfer larger amounts of data at high rates between the FPGA target and the host,

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you should buffer your data.
• The best way to transfer buffered data is by using Direct Memory Access (DMA) data transfer

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methods.

DMA FIFO Overview

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Direct Memory Access A FIFO-based method for transferring data between an FPGA target and host
(DMA) computer.

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Consists of two parts—FPGA and host.

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• In this class, the host is the RT target.

• Streams large amounts of data between the RT target memory and the FPGA.
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• Is unidirectional.
• Requires little CPU resources.
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• Provides better performance than using the CPU to read and write data to the indicators and
controls.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

DMA FIFO: FPGA to RT Transfer

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DMA uses FPGA memory to store data and then transfer it at high speed to host processor memory
with very little processor involvement. This uses much fewer processor cycles when sending large
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blocks of data compared to the front panel indicator with the FPGA Read/Write method.
Here are some programming tips for implementing DMA:
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• When setting the FPGA buffer size, you can use the default size (1023). Creating a larger FPGA
memory buffer typically has no benefits.
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• If you are passing an array of data, the Number of Elements input should always be an integer
multiple of the array size. For example, if you are passing an array of 8 elements, the Number of
Elements should be an integer multiple of 8 (such as 80, which would give 10 samples of 8
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elements each).
Each DMA transaction has overhead, so reading larger blocks of data is typically better. The DMA
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•
FIFO Read function automatically waits until the Number of Elements you requested becomes
available, minimizing processor usage.
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• Packing 16-bit channel data into a U32 (since DMA uses the U32 data type) typically does not
have benefits. That is because the PCI bus has a very high bandwidth for sending DMA data, so
you are most likely nowhere near using up all the bus bandwidth. Instead, it is typically the
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processor that is the bottleneck in processing the data being streamed. Packing the data in the
FPGA means it has to be unpacked on the processor, adding additional processor overhead. In
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general, you should send each channel as a U32 even if you are acquiring 16-bit data.
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The Timed Out? output on the DMA FIFO Write function is an error indicator. Under normal operation,
this should never occur, so it is recommended that you stop the application if this error occurs and
reset the FPGA before restarting.
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

DMA FIFO: Relative Transfer Rates

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Creating and Configuring DMA FIFOs

Create DMA FIFOs from the Project Explorer window. In this course, Target to Host – DMA means an
FPGA-to-RT transfer, and Host to Target – DMA means an RT-to-FPGA transfer. In the Type
pull-down control, select either Target to Host – DMA or Host to Target – DMA. Each DMA FIFO
transfers data in one direction. Either from the host VI to the target or from the target VI to the host.

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Selecting DMA FIFO Sizes by setting the FPGA buffer size:

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• In the FIFO Properties dialog box of the DMA FIFO, use Requested Number of Elements to set the
size of the buffer on the FPGA.
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• Save resources by choosing the smallest size that is reasonable for your application.
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The default FPGA buffer size of 1023 is typically enough for most applications.
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Selecting DMA FIFO Sizes by setting the RT (host) buffer size:

• The default is either 10,000 elements or twice the size of the FPGA FIFO buffer,
whichever is greater.
• Use the Configure Method in the RT VI to specify a different size.

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FIFO.Configure Method—Specifies the depth of the host memory part of the DMA FIFO. The new
depth is implemented when the next FIFO Start, FIFO Read, or FIFO Write method executes. Before
the new depth is set, LabVIEW empties all data from the host memory and FPGA FIFO. This method

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is optional.

Depth—Specifies the number of elements in the host memory part of the DMA FIFO. On certain
targets, the value wired to this parameter may not be the actual number of elements allocated for the

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host memory part of the DMA FIFO. On these targets, the number of bytes allocated in memory will
be coerced to a multiple of 4096 bytes, which may increase the actual number of elements in the host

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memory part of the DMA FIFO. If you do not wire this parameter, the Invoke Method function uses a
default of 10,000 elements or twice the size of the FPGA FIFO buffer, whichever is greater.
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Place the DMA FIFO onto the block diagram of your FPGA VI by dragging it from Project Explorer.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

On the RT VI:
• Open a reference to the FPGA.
• Add an Invoke Method function.

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Using DMA FIFOs Effectively
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Using Target to Host DMA FIFO
• RT VI
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Read Data
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• FPGA VI
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Write Data
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The presented example shows a Target to Host DMA FIFO, where the FPGA VI writes and the RT VI
reads. You can also create a Host to Target DMA FIFO, where the RT VI writes and the FPGA reads.
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Target to Host DMA FIFOs are more common.

Note Target to Host – DMA is the name specified in the FIFO Configuration dialog box of
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Using Target to Host DMA FIFO: Best Practices

FPGA VI—The FPGA VI writes data to the DMA FIFO and uses a feedback node to latch whether an
overflow has occurred.

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RT (Host) VI—The RT (Host) VI uses the first DMA FIFO Read to immediately determine how many

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elements are remaining in the DMA FIFO. Note that the first DMA FIFO Read has a timeout of 0 and
reads 0 elements. If the first DMA FIFO Read determines that at least 10 elements remain in the DMA
FIFO, the Host VI will use a second DMA FIFO Read to read 10 elements from the DMA FIFO. If not,

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the Host VI does not read any elements from the DMA FIFO and uses a Wait function in the False case
of the Case structure to specify how long to wait before polling the DMA FIFO again. The Wait
prevents the While Loop from using 100 % of the CPU.
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Note All the DMA FIFO Read methods on the Host VI have 0 wired to the timeout input.
On some RT targets, such as the cRIO, any timeout value other than 0 will cause the
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DMA FIFO Read method to use 100 % of the CPU to actively check the DMA FIFO for the
number of elements.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Using Target to Host DMA FIFO: Handling Underflow Errors

Underflow Error—If the DMA FIFO Read is configured to read n elements and times out before n or
more elements are available, the DMA FIFO Read returns Error -50400.
• You will not receive this error if you check if the number of elements you want to read is available
before reading.

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RT VIs

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Using Target to Host DMA FIFO: Handling Overflow Errors

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Overflow—FIFO is filled as a result of data being written faster than it is read, data may be lost.
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• Reduce the rate at which you write data to the FIFO.

• Increase the number of elements to read on the host.
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• Increase FPGA and host buffer sizes.

• Reduce the load on the CPU.
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• The speed of the CPU and competing tasks impact the transfer data from DMA to application
memory.
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The speed of the overall DMA transaction is limited by the processor (windows, real-time). The
processor is not used for DMA transfer, but it is used to copy the memory from DMA to application
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memory. The speed of the CPU and competing tasks limit the availability of CPU resources.
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Increasing the host buffer size is a common necessity for many applications. The default host buffer
size of 10,000 elements (or twice the FPGA buffer size) is on the small side but is adequate for some
single-point applications. Many data streaming applications (which are the most common use cases
for DMA) use a host buffer size of at least 1,000,000 elements. For example, many cRIO data
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Identifying DMA FIFO Overview

Check to determine if the Write Method has timed out.

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It is very important to latch the overflow, as overflow typically will not be persistent.

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Recovering from a DMA FIFO Overflow

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There are two primary methods for clearing the DMA FIFO when an overflow occurs, depending on
whether you want to keep the data is in the DMA FIFO.
•

•
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Reset the FPGA VI—Discards the data in the DMA FIFO.
Flushing the buffer—Reads the remaining data in the DMA FIFO.
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Either method can be performed to initialize the DMA FIFO at the beginning of execution.
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Clearing DMA FIFO: Reset FPGA VI Method

Simulation execution mode
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• FIFOs automatically reset when the VI stops and restarts.

FPGA Target execution mode

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• FIFOs do not automatically reset.

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To reset programmatically:
• Use the Invoke Method function.
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• Use the Close FPGA VI Reference function configured to Close and Reset if Last Reference.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Clearing DMA FIFO: Reset FPGA VI Method

• The Reset method will abort and reset the FPGA VI to its default state (clears the DMA FIFO).
• Use the Run method to run the FPGA VI on the FPGA target again.

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Clearing DMA FIFO: Flush DMA FIFO Buffer Method

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• Stop writing to the DMA FIFO.
• Find out how much data remains in the DMA FIFO.
•

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Read all the remaining elements to empty the DMA FIFO.

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Note If your DMA FIFO data is interleaved, it is usually impossible to use the data you
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Exercise 5-2: Transfer Stream Data from FPGA to RT Target

Goal
Transfer data between the FPGA and RT target using a DMA FIFO.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection
• NI-9211 Thermocouple Input C Series Module
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• Windows 10 PC na
NI-9474 Digital I/O C Series Module
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Scenario
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The exercise aims to optimize data exchange between the LabVIEW Real-Time application and the
FPGA. You will create the VI and logic to process the signals specified in the communication diagram.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA
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Figure 5-5. Fan Control—Communication Diagram

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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Implementation
1. Review the communication diagram of the course project.
a. From the C:\Exercises\FPGA\Transfer Stream Data from FPGA to RT\Documentation
folder, open Fan Control - Communication Diagram.pdf file.
2. List all the data that needs to be transferred between the FPGA and RT Target. For each data that

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needs to be transferred, identify the transfer type (tag, message, or stream).

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Table 5-2. Data to Transfer between FPGA and RT Target
Data to Transfer Transfer Type (Tag/Message/Stream)

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3. From the C:\Exercises\FPGA\Transfer Stream Data from FPGA to RT, open
[FPGA] Fan Control (prototype) [cRIO-9056].lvproj.
4. From Project Explorer, open RT Main - RT-FPGA Transfer Tag Data.vi.

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5. Save a copy of this VI:

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a. From this VI, select File»Save As. Then select Copy»Open additional copy. Ensure that the
Add copy to [FPGA] Fan Control (prototype) [cRIO-9056].lvproj checkbox is enabled.
b. Click Continue.
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c. Save the VI as C:\Exercises\FPGA\Transfer Stream Data from FPGA to RT\
RT Main - RT-FPGA Transfer Stream Data.vi.
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6. Close RT Main - RT-FPGA Transfer Tag Data VI.

You will modify RT Main - RT-FPGA Transfer Stream Data VI for the rest of this exercise.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

7. Create the DMA FIFO that you will use to transfer stream acceleration data from the FPGA VI
to the RT VI:
a. In Project Explorer, right-click FPGA Target»New»FIFO.
b. Configure the FPGA FIFO Properties window, as shown in Figures 5-6 and 5-7.
The Requested Number of Elements item is where you can configure the FPGA buffer size of

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the DMA FIFO. Usually, you should just leave this item at the default value.

Figure 5-6. Acceleration DMA FIFO Properties—General

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Figure 5-7. Acceleration DMA FIFO Properties—Data Type

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FPGA VI—Write Stream Data to the DMA FIFO

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Lesson 5
1. From Project Explorer, open the FPGA Main.vi.
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2. To write stream data to the Acceleration DMA FIFO, modify the block diagram, as shown in Figure 5-8.

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Communicating between the FPGA and Real-Time VIs

Figure 5-8. FPGA Main VI Block Diagram—Acquisition Loop

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1 Acceleration DMA FIFO—Write stream data to the Acceleration DMA FIFO.

From Project Explorer, drag the FPGA Target»Acceleration DMA FIFO item to the block diagram.
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2 Right-click the Timed Out? terminal from the Acceleration DMA FIFO to create the DMA FIFO Overflow? indicator.
3 DMA FIFO Overflow?—On the front panel of the FPGA VI, move the DMA FIFO Overflow? Boolean indicator to the Acceleration section.
If the Timed Out element of the DMA FIFO Write node ever outputs TRUE, an overflow has occurred. This means you have written data
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to the DMA FIFO faster than it has been read, so you have lost data. If an overflow has ever occurred, then output a TRUE value on the
DMA FIFO Overflow indicator. Use the Feedback Node and Or function to implement this.
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3. Save the VI.

4. Click the Run button to compile the FPGA VI. While the FPGA VI is compiling, continue the rest of the steps in this exercise
to develop the RT VI.
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RT VI—Read Stream Data from the DMA FIFO

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1. To reset the FPGA VI, configure the DMA FIFO host buffer size, set the starting values of the FPGA VI controls, and run the FPGA VI,
open RT Main - RT-FPGA Transfer Stream Data.vi and add code to the left of the While Loop, as shown in Figure 5-9.

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Figure 5-9. RT Main - RT-FPGA Transfer Stream Data VI Block Diagram—Initialization

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Reset Invoke Method—Reset the FPGA VI. Place an Invoke Method on the block diagram. Right-click it and select Method»Reset. This
aborts and resets the FPGA VI to the default state of the VI and clears the FIFOs.
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© National Instruments Corporation

2 Acceleration.Configure Invoke Method—Configure the number of elements on the host FIFO of the DMA channel. Place an Invoke
02
Method on the block diagram. Wire in the FPGA reference wire. Right-click it and select Method»Acceleration»Configure. Right-click the
input and select Create»Constant, and set it to 102,400. The FPGA VI will write 10,240 elements per second to the DMA FIFO. Later
in this exercise, you will add code to this RT VI to read 10,240 elements per second from the DMA FIFO. Here, we set the host FIFO to
102,400 elements, which should be large enough to prevent a DMA FIFO overflow in this application.
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3 Read/Write Control function—Set the starting values of the controls in the FPGA VI by using the Read/Write Control function. Data Rate
constant. Open the FPGA VI and copy the Data Rate control from the FPGA VI to this RT VI. On the block diagram of this RT VI, right-click
the Data Rate control and select Change to Constant.
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4 Run Invoke Method—Run the FPGA VI. Place an Invoke Method on the block diagram. Right-click it and select Method»Run.
5 Local Variable of Stop button—Initialize the Stop control on the RT VI to FALSE. Create a local variable of the Stop control by
right-clicking the Stop control and selecting Create»Local Variable. Then go to the front panel, right-click the Stop control, and select
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Mechanical Action»Switch When Released. To use a local variable on a Boolean control, you must use a switch mechanical action.
| 5-35

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2. To transfer stream data between the RT VI and FPGA VI using a DMA FIFO, modify the block diagram, as shown in Figure 5-10.
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Lesson 5
Figure 5-10. RT Main - RT-FPGA Transfer Stream Data VI Block Diagram—Initialization
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Communicating between the FPGA and Real-Time VIs

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1 2 3 4 6
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1 Acceleration. Read Invoke Method—Check if there is a specified number of samples available to read from the DMA FIFO. Place an Invoke
Method on the block diagram. Wire the FPGA Reference wire into this node. Click Method and select Acceleration»Read.
2 Number of Elements—Read a specified number of samples from the Acceleration DMA FIFO.
3 Analyze Acceleration (RT) VI—Analyze the acceleration data by performing a grms calculation. In Project Explorer, right-click the
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cRIO-9xxx»Support VIs virtual folder and select Add»File.

Select C:\Exercises\FPGA\Transfer Stream Data from FPGA to RT\support\Analyze Acceleration(RT).vi.
From Project Explorer, drag the cRIO-9056»Support VIs»Analyze Acceleration (RT) VI to the block diagram.
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4 Build Waveform—Convert the acceleration data into a waveform data type.

5 Spectral Measurements Express VI—Perform a power spectrum on the acceleration waveform. Place the Spectral Measurements Express
VI on the block diagram. In the configuration window, select Power spectrum and click OK.
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6 Local variable—Stop the bottom loop if the Stop control value is TRUE. Right-click the Stop control on the block diagram and select
Create»Local Variable. Right-click it and select Change to Read.
7 True Constant—If either loop exits, ensure that the other loop stops by setting the Stop control value to TRUE. Use a local variable.
8 DMA FIFO Monitor Overflow?—Monitor the DMA FIFO overflow status. Resize the Read/Write Control function to show another element.
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Select the DMA FIFO Overflow?.

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3. Arrange the front panel to loop like Figure 5-11.

Figure 5-11. RT Main - RT-FPGA Transfer Stream Data VI Front Panel

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1 Acceleration (grms)—Add and rename the Numeric indicator to Acceleration(grms).

2 DMA FIFO Overflow?—Add and rename the Boolean LED to DMA FIFO Overflow?.
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3 Acceleration Waveform—Add and rename the Waveform Graph (Silver) to Acceleration Waveform. Change the x-axis label from Time
to Time(s). Disable the X Autoscale from the context menu and set the X scale on the graph to start at zero and end at 0.1.
4 Power Spectrum—Add and rename the Waveform Graph (Silver) to Power Spectrum. Change the x-axis label from Time to
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 Lesson 5 Communicating between the FPGA and Real-Time VIs

4. Switch to the False case of the Case Structure in the bottom loop. Modify it, as shown in
Figure 5-12, so that the loop will check the number of elements available in the DMA FIFO every
n milliseconds when waiting for the specified number to be available.

Figure 5-12. RT Main - RT-FPGA Transfer Stream Data VI Block Diagram—False Case

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5. Save the VI and project.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Test
If you are using in-person hardware, on the Sound and Vibration Signal Simulator, set the following
switches (optional):
1. Verify that the FPGA VI is finished compiling. Close the FPGA VI.
2. On the Sound and Vibration Signal Simulator, set the Fan Speed Control switch to BNC and the

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other switch to UNBALANCED FAN.
3. Verify that all the controls on the RT VI are set to the values shown in Figure 5-8.

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4. Change the Max Acceleration Threshold (g) control value to 1, so you will be able to observe higher
acceleration signals before transitioning to Safe State for testing.
5. Run the RT Main - RT-FPGA Transfer Stream Data VI, which runs this RT VI on the processor of

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the RT target. You have programmed the RT VI to do the following actions:
a. Load and run the FPGA bitfile on the FPGA.

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b. Transfer tag data between the FPGA VI and RT VI.
c. Read stream data from FPGA VI using the Acceleration DMA FIFO.

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6. Set the New FPGA State control to Control (PID).
7. Set the Fan Speed Setpoint (RPM) control to 4500.

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Note Confirm that the Max Fan Speed Threshold (RPM) to 6000.

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8. Verify that the fan starts to rotate and settles at a fan speed of 4500 RPM.
9. Verify that the DMA FIFO Overflow indicator is not lit. If this indicator is lit, then you know a DMA
FIFO overflow has occurred.
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10. Notice that the FPGA VI can stream every point of acceleration data to the RT VI.
The Acceleration Waveform graph shows every point in the acceleration waveforms. The Power
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Spectrum graph displays the waveform in the frequency domain. This requires having every point
of data of the acceleration waveform.
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11. Set the New FPGA State control to Safe State. The fan should now stop rotating.
12. Click the Stop button to stop the VI.
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13. If you wish to take a closer look at the time domain, you can zoom in on the Acceleration
Waveform graph by looking at x-axis time from just 0 to 0.05 seconds, as shown in Figure 5-13.
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14. If you wish to take a closer look at the frequency domain, you can zoom in on the Power Spectrum
graph by looking at x-axis frequencies from just 0 to 1000 Hz, as shown in Figure 5-13. You
should see a peak at approximately 75 Hz. At 4,500 RPM, the unbalanced fan is spinning 75 times
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per second. You will also see harmonics.

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 Lesson 5 Communicating between the FPGA and Real-Time VIs

Figure 5-13. Acceleration Waveform and Power Spectrum Graphs

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15. Save the VI and the project.
16. Close the VI and the project.
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End of Exercise 5-2

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

DMA FIFO: Interleaving

• There is a limited number of DMA FIFO channels available.
• 16 channels are available for cRIO-9056.
• What if you want to acquire and transfer data from multiple channels on multiple modules?

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• You can interleave data of the same type prior to writing to the DMA FIFO.

DMA FIFO Interleaving: FPGA VI

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• Combine multiple elements of the same data type into a single array.
• Module 1 Channel 0—Index 0

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• Module 1 Channel 1—Index 1
• Iterate through that array, writing the data one element at a time to the DMA FIFO.

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FPGA VI

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DMA FIFO De-interleaving: Host VI

• Read data from the DMA FIFO.
3

• Divide the data into multiple arrays, each representing a single channel of acquisition.
Process the data for each channel.
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RT VIs
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© National Instruments Corporation | 5-41

 Lesson 5 Communicating between the FPGA and Real-Time VIs

Exercise 5-3: Explore DMA FIFO Interleaving

Goal
Explore how you can transfer multiple channels of data through a single DMA FIFO by interleaving the
DMA FIFO.

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Requirements

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To complete this exercise, it is necessary to have access to the following hardware and software.

Software:

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• LabVIEW 2023 Q3 (32-bit)
• NI-DAQmx 2023 Q3 (32-bit)

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• LabVIEW Real-Time Module 2023 Q1 (32-bit)
• LabVIEW FPGA Module 2023 Q1 (32-bit)

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• NI CompactRIO 2023 Q3 (32-bit)

Hardware:

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• An NI CompactRIO from either the 904x or 905x product lines
• USB Type C or RJ45 Ethernet connection
•

•
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NI-9211 Thermocouple Input C Series Module
NI-9474 Digital I/O C Series Module
Windows 10 PC
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•

Scenario
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The exercise aims to prepare the acquired data to be shared with the RT VI, you will use basic
LabVIEW programming functions to act upon all the channels as an array and then extract the signals
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that will be updated and shared. You will create the VI and logic to process the signals specified in
the communication diagram.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA
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Figure 5-14. Fan Control—Communication Diagram

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© National Instruments Corporation | 5-43
 ts
Implementation

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5-44

Lesson 5
1. From the C:\Exercises\FPGA\Sample Project directory, open Fan Control (deploy) [cRIO-9056].lvproj.
|

2. From Project Explorer, open FPGA Main.vi.

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ni.com

Communicating between the FPGA and Real-Time VIs

3. In the FPGA Main VI, explore the Acquisition Loop and notice how it interleaves multiple channels of data into a single DMA FIFO,
as shown in Figure 5-15.

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4. Transfer multiple channels of data through a single DMA FIFO by interleaving the DMA FIFO.

Figure 5-15. FPGA Main VI Block Diagram—Acquisition Loop—Interleave DMA FIFO

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1 Build Array—The Build Array function combines data from each channel into a 1D array.
2 For Loop—For Loop processes the data and writes the data to the Acceleration DMA FIFO for every channel, one channel at a time.
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5. From Project Explorer, open RT Main.vi.

6. From RT Main VI, open the RT Loop - Analyze Acceleration subVI.
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7. Explore the RT Loop - Analyze Acceleration subVI block diagram and notice how it de-interleaves the elements of the DMA FIFO back
into separate arrays for each channel, as shown in Figure 5-16.

Figure 5-16. FPGA Main VI Block Diagram—Acquisition Loop

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3

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Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

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1
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Read data from the DMA FIFO—The number of elements to read from the DMA FIFO should be the number of samples per channel
multiplied by the number of channels. In this example, the number of samples per channel is two seconds worth of data
3
(i.e., Data Rate (Hz) multiplied by 2), and the number of channels is 2.
© National Instruments Corporation

2 De-interleave the data—The Decimate 1D Array function de-interleaves the data into a separate array for each channel. The top output
02
wire contains the data for the Mod1/AI1 channel, and the bottom output wire contains the data for the Mod1/AI2 channel.
3 Process the data for each channel—This example uses the Build Array function and For Loop to process the data for each channel.
2

End of Exercise 5-3

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 Lesson 5 Communicating between the FPGA and Real-Time VIs

E. Synchronizing the RT VI and FPGA VI

Objective: Explore techniques to synchronize your VIs.

Techniques Overview

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Boolean Flag—Use of a Read/Write control to send a Boolean flag to the FPGA.

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Interrupts—A physical hardware line to the host that the FPGA target asserts.

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Exploring Boolean Flag
Use Cases
• RT VI notifies the FPGA Vi of an event.na
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• Easy way for RT VI to tell FPGA VI to run something.
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RT VI FPGA VI
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Use the Boolean flag method when you need the host VI to notify the FPGA VI of an event. Notice
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that the Boolean control on the FPGA VI has latching mechanical action. When the Host VI sets this
Boolean control to True with the Read/Write Control function, the Boolean control on the FPGA VI will
output a True value and then automatically latch back to a False value.
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5-46 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exploring Interrupts
Use Cases
• FPGA VI notifies the RT VI of one-time or infrequent events.
• FPGA has started or is ready.

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• Task has finished.

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• Trigger occurred.
• Error occurred.
• Generate interrupts from the FPGA VI.

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• Minimize CPU usage of host processor.

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You can generate an interrupt on the FPGA VI to notify the Host of one-time or infrequent events. One

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advantage of using interrupts instead of polling is that interrupts minimize the use of the host
processor. However, the overhead required to process the interrupt increases latency relative to
polling-based synchronization.
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Interrupts require the execution of a low-level driver on the host, so a host VI can process more polling
at

operations per second than interrupts per second. An example of a polling operation is the Host using
the Read/Write Control function to continually read the status of a Boolean control on the FPGA VI in
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a loop at a specified rate.

Interrupt VI on FPGA
3

IRQ Number—Specifies which logical interrupt (0–31) to assert. The default is 0.

02

Wait Until Cleared—Specifies if this VI waits until the host VI acknowledges the logical interrupt.
The default is FALSE.
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Interrupt VI becomes a shared resource if you use more than one and can induce jitter.
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Exploring Acknowledge IRQ Method

Acknowledges and resets any interrupts that have occurred to their default values.
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• Use this method after the Wait on IRQ method.

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© National Instruments Corporation | 5-47

 Lesson 5 Communicating between the FPGA and Real-Time VIs

Exploring Wait on IRQ Method

RT VI can wait on and acknowledge interrupts.

IRQ Number(s)—Specifies the logical interrupt or array of logical interrupts for which the function
waits.

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Timeout (ms)—Specifies the number of milliseconds the VI waits before timing out.
-1 = infinite timeout.

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Timed Out—Returns TRUE if this method has timed out.

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IRQ(s) Asserted—Returns the asserted interrupts. Empty or -1 array indicates that no interrupts were
received.

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Interrupt Example: Synchronize Start of Code in RT and FPGA
The subsequent example shows how to use an interrupt to synchronize the start of code in the host
VI and the FPGA VI.
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RT VI
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FPGA VI
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5-48 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

F. Implementing an FPGA Watchdog

Objective: Explore the usage of watchdogs in the FPGA.

What Is a Watchdog?

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• FPGA VI monitors the status of the RT VI.
• FPGA VI can act if RT VI becomes unresponsive.

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• Reboot RT target.
• Set I/O to safe states.

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Implementation Overview
This code is a simplified version of the code in the FPGA Control sample project in LabVIEW.

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RT VI

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FPGA VI
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© National Instruments Corporation | 5-49

 Lesson 5 Communicating between the FPGA and Real-Time VIs

Exercise 5-4: Explore FPGA Watchdog

Goal
Explore the inter-target tag communication between Watchdog Loop on the RT VI and FPGA
Watchdog Loop on the FPGA VI.

ts
Requirements

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To complete this exercise, it is necessary to have access to the following hardware and software.

Software:

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• LabVIEW 2023 Q3 (32-bit)
• NI-DAQmx 2023 Q3 (32-bit)

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• LabVIEW Real-Time Module 2023 Q1 (32-bit)
• LabVIEW FPGA Module 2023 Q1 (32-bit)

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• NI CompactRIO 2023 Q3 (32-bit)

Hardware:

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• An NI CompactRIO from either the 904x or 905x product lines
• USB Type C or RJ45 Ethernet connection
•

•
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NI-9211 Thermocouple Input C Series Module
NI-9474 Digital I/O C Series Module
Windows 10 PC
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•

Scenario
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The exercise aims to explore the use of the FPGA Watchdog in our Sample Project and understand the
impact of the Pet Watchdog control for this type of applications. You will create the VI and logic to
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process the signals specified in the communication diagram.

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5-50 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA
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Figure 5-17. Fan Control—Communication Diagram

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© National Instruments Corporation | 5-51
 Lesson 5 Communicating between the FPGA and Real-Time VIs

Implementation
1. Review the communication diagram of the sample project.
a. From the C:\Exercises\FPGA\Sample Project\Documentation folder, open
Sample Project Diagram.png.
b. Notice the inter-target tag communication between the Watchdog Loop on the RT VI and the

ts
FPGA Watchdog Loop on the FPGA VI.
2. From the C:\Exercises\FPGA\Sample Project directory, open

en
Fan Control (deploy) [cRIO-9056].lvproj.
3. From Project Explorer, open FPGA Main.vi.

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4. In the FPGA Main VI, explore the Watchdog Loop. If the RT VI does not continually set the
Pet Watchdog control to TRUE within the Watchdog Timeout Period, this loop will reboot the RT
application.

tru
Note It is important to notice that the Watchdog implemented here is made possible by the
specific mechanical action of the Pet Watchdog button set to “Latch”. Otherwise, if left in

ns
default “Switch”, it would never reset and would miss any RT hangs.

5. From Project Explorer, open RT Main.vi.

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6. From the RT Main VI block diagram, open the RT Loop - Watchdog subVI.
7. Explore the RT Loop - Watchdog subVI block diagram. As long as the RT VI is responsive, this loop

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continually pets the watchdog at the specified Watchdog Pet Rate (ms).
8. Close the RT Loop - Watchdog subVI without saving.
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9. Close this project without saving any VIs or the project.
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End of Exercise 5-4

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Additional Resources
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Topic Website

Downloading an FPGA VI to the Flash Memory of an FPGA Target

2

(FPGA Module)

Using I/O Variables (Real-Time, Windows) ni.com

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Determining the Number of DMA Channels for an NI FPGA Target

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5-52 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. Which of the following are necessary in an RT VI that reads and writes values of controls and
indicators on the FPGA VI?
Select all that apply.
a. Open FPGA VI Reference

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b. Read/Write Control
c. Invoke Method

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d. Close FPGA VI Reference

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2. Which of the following are considerations to FPGA buffer sizing?

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Select all that apply.
a. Depends on the number of resources available on the FPGA.
b. Refer to the specific FPGA target documentation for any potential limitation.

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c. It does not matter if you select a larger buffer than what you need.

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3. Match the communication methods to their corresponding usage.

1. Front Panel Controls/Indicators na a. Use to transfer stream or message data.

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2. DMA FIFO b. Use to transfer tag (most recent) data.

3. Interrupts c. Use to transfer information about one-time or

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infrequent events.
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4. You have developed an application that acquires data and uses a DMA FIFO to transfer data from
3

the FPGA to the RT. However, the DMA FIFO repeatedly fills, resulting in an overflow condition.
02

Which of the following techniques can be used to address this problem?

Select all that apply.
a. Reduce the speed of acquisition on the FPGA VI.
2

b. Increase the number of elements to read on the RT VI.

c. Decrease the rate at which the RT VI reads data.
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d. Increase the rate at which the RT VI reads data.

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5. Match each tool with its function.

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1. FPGA Watchdog a. RT VI notifies the FPGA VI of an event.

2. Boolean Flag b. FPGA VI notifies the RT VI of one-time or

infrequent events.
C

3. Interrupts c. Monitor the status of the RT VI and act if RT VI

becomes unresponsive.

© National Instruments Corporation | 5-53

 Lesson 5 Communicating between the FPGA and Real-Time VIs

Activity: Lesson Review—Answers

1. Which of the following are necessary in an RT VI that reads and writes values of controls and
indicators on the FPGA VI?
Select all that apply.
a. Open FPGA VI Reference

ts
b. Read/Write Control
c. Invoke Method

en
d. Close FPGA VI Reference

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2. Which of the following are considerations to FPGA buffer sizing?

tru
Select all that apply.
a. Depends on the number of resources available on the FPGA.
b. Refer to the specific FPGA target documentation for any potential limitation.

ns
c. It does not matter if you select a larger buffer than what you need.

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3. Match the communication methods to their corresponding usage.

1. Front Panel Controls/Indicators na b. Use to transfer tag (most recent) data.

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2. DMA FIFO a. Use to transfer stream or message data.

3. Interrupts c. Use to transfer information about one-time or

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infrequent events.
N

4. You have developed an application that acquires data and uses a DMA FIFO to transfer data from
3

the FPGA to the RT. However, the DMA FIFO repeatedly fills, resulting in an overflow condition.
02

Which of the following techniques can be used to address this problem?

Select all that apply.
a. Reduce the speed of acquisition on the FPGA VI.
2

b. Increase the number of elements to read on the RT VI.

c. Decrease the rate at which the RT VI reads data.
ht

d. Increase the rate at which the RT VI reads data.

ig

5. Match each tool with its function.

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1. FPGA Watchdog c. Monitor the status of the RT VI and act if RT VI

becomes unresponsive.

2. Boolean Flag a. RT VI notifies the FPGA VI of an event.

C

3. Interrupts b. FPGA VI notifies the RT VI of one-time or

infrequent events.

5-54 | ni.com
 ts
6

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Exploring

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Common FPGA

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Optimizations

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na
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Learn about optimizations for the FPGA performance and
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resource usage.
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Topics
A. Optimization Use Cases
3

B. Optimization Techniques for FPGA Size

C. Optimization Techniques for Speed/Throughput
02

D. Executing Code in Single-Cycle Timed Loops

E. Implementing Pipelining
2

F. Exploring Four-Wire Handshaking

Exercises
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Exercise 6-1 Observe Loop Speed: While Loop versus Single-Cycle

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Timed Loop
Exercise 6-2 Fix SCTL Errors
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Exercise 6-3 Use Pipelining

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Optimization Use Cases

Objective: Explore scenarios in which optimizations can be implemented.

Optimization Scenarios

ts
Optimize your FPGA code if one of the following scenarios occurs:
• Your FPGA code does not execute fast enough.

en
For example, the processing code in your acquisition loop does not execute fast enough, so the
acquisition loop runs slower than the required acquisition rate. You should optimize your code so
that the acquisition loop runs at its required faster rate. You must optimize for speed.

m
tru
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• Your FPGA code does not fit on the FPGA.
When you try to compile your FPGA VI, the compilation fails and tells you that there are not

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enough FPGA resources (flip-flops, LUTs, DSP48, block memory, etc.) to implement your FPGA
VI. You should optimize your code so that it fits on the FPGA. You should optimize for size.

na Compilation failed
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© National Instruments Corporation | 6-3

 Lesson 6 Exploring Common FPGA Optimizations

B. Optimization Techniques for FPGA Size

Objective: Explore the techniques used to optimize the size the code takes in FPGA.

Considerations for Reducing the FPGA Bitfile Size

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• Avoid using large arrays on front panel of top-level FPGA VI.
• Basic optimizations listed in Programming Using LabVIEW FPGA.

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• Replace SGL with FXP data type.
• Non-reentrant subVIs.
Multiplex a large algorithm.

m
•

Multiplex a Large Algorithm

tru
If your algorithm does not need to hold any state data or use data from a previous iteration, it is very
simple to just put the algorithm in a For Loop to multiplex your data through the algorithm.

ns
The advantage of this technique is that it uses much fewer FPGA resources. In this example, the
caveat is that it will take 8x longer to run 8 channels of data one-by-one through the algorithm in the
For Loop. However, if the above code is executing in a While Loop, then as long as the total amount

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of time to multiplex all 8 channels through the algorithm does not increase the required loop period,
then the added time from multiplexing has no detrimental effects.

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Use less FPGA

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6-4 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Multiplex a Large Algorithm

• If your algorithm needs to hold state data or value from previous iteration, then you can use a
Memory Item to store this data for each channel.
• PID—previous iteration data (previous i data)
Tachometer—time of the previous edge, previous tachometer state

ts
•

Original subVI (previous i data) Multiplexed subVI (previous i data for n channels)

en
m
tru
ns
Alternatively, you can replace Feedback Nodes with Memory Items and a Channel # control.

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Shift registers and Feedback Nodes are implemented using flip-flops unless the compiler can optimize
one or more into a Look-Up Table (LUT). If your code does not depend on the initial value of the

na
Feedback Node to function correctly, you can save additional resources by selecting the Ignore FPGA
reset method option on the FPGA Implementation page of the Feedback Node Properties dialog box.
This allows the compiler to remove the reset logic from the register and implement it using shift
io
register lookup tables (SRLs) instead of flip-flops. SRLs can combine multiple delays into a single LUT,
which can significantly reduce FPGA resources relative to flip-flops.
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Original subVI (previous i data)

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© National Instruments Corporation | 6-5

 Lesson 6 Exploring Common FPGA Optimizations

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Multiplex a Large Algorithm: Result

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na Multiplexed subVI
(previous i data for n channels)
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Demonstration: Multiplexing a Large Algorithm

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6-6 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

C. Optimization Techniques for Speed/Throughput

Objective: Explore the techniques used to optimize the throughput of the FPGA.

Throughput Overview

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Throughput The rate at which the system can process inputs.

en
• It is a number of measurements taken per time.
• It is not a measure of how recent they are, but rather of their volume.
Although throughput is generally represented in samples per second

m
•
(S/s), many computer components are rated in B/s, MB/s, GB/s,
and so on.

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Speed/Throughput Optimization Considerations

ns
• Execute code inside a Single-Cycle Timed Loop (SCTL).
• Pipeline the code.
• Use Four-Wire Handshaking Protocol.

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• Reentrant subVIs.

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© National Instruments Corporation | 6-7

 Lesson 6 Exploring Common FPGA Optimizations

D. Executing Code in Single-Cycle Timed Loops

Objective: Optimize the code with single-cycle timed loops.

Dataflow in FPGA

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The following figure shows a simple VI that has a Boolean control, a Not function, and a Digital Output
function.

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na
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N

• The Boolean control has some logic associated with the data register to retrieve data from a host
3

application. A flip-flop links the enable chain.

02

• The Not function has the logic associated with the function itself, a synchronization flip-flop, and
an enable chain flip-flop.
• The Digital Output function has a synchronization flip-flop and an enable chain flip-flop.
2

When the program runs, the enable line goes high to enable the synchronization flip-flop associated
with the Boolean control. Meanwhile, a rising edge of the clock pushes the data from the register
ht

through the flip-flop. Downstream, the previous values are held on the outputs of the flip-flops. During
the next rising edge of the clock, the synchronization flip-flop associated with the Not function passes
ig

the new value through. On the third rising edge of the clock, the enable in of the digital output is high,
and the new value is pushed through the flip-flop to the I/O pins. The data is synchronized using a
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flip-flop that pushes the data through the flip-flop on the first rising edge of the clock.
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6-8 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

LabVIEW executes code in a dataflow manner. Nodes execute when data is present on all inputs.
When the node finishes execution, the outputs of the node pass data to the next node downstream.
The previous figure shows an example of the FPGA hardware required to implement a Boolean
operation.

LabVIEW code is transformed into FPGA logic in three sections: logic, synchronization, and the enable

ts
chain. The logic, shown in the upper third of the figure, corresponds to the actual LabVIEW operation.
In this example, the LabVIEW code is a Not function corresponding to an inverter in the FPGA

en
hardware. The synchronization register shown in the middle of the figure guarantees that data is
output only on rising edges of the clock. The final portion of FPGA code that is generated from the
LabVIEW code is the enable chain. The enable chain is an additional register that only outputs on the

m
rising edge of the clock. The enable chain guarantees that the FPGA logic executes in the same order
depicted on the block diagram.

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Due to the enable chain overhead, each function or VI takes a minimum of 1-clock cycle. Some
functions, such as analog input operations, can take hundreds of clock cycles, depending on the
complexity of the operation and hardware limitations.

ns
A VI can run only as fast as the sum of the items in a combinatorial path. One advantage of using an
FPGA is that code can run in true parallel with another operation. Because you can create code in

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parallel, it is often best to design code so that as many parallel operations can take place as possible.
This uses the same amount of FPGA space and can increase the execution speed by reducing the

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combinatorial path size.

Executing Code in Single-Cycle Timed Loops

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Use a single-cycle Timed Loop to convert the 12 clock-cycle While Loop into 1 clock-cycle
Single-Cycle Timed Loop.
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© National Instruments Corporation | 6-9

 Lesson 6 Exploring Common FPGA Optimizations

Single-Cycle Timed An SCTL is a Timed Loop that has been placed onto the block diagram of an
Loop (SCTL) FPGA VI.

The structure name is the same as the Timed Loop structure as used in Real-Time and in Windows.

ts
However, the Timed Loop on the FPGA block diagram executes one iteration per clock cycle.

en
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LabVIEW automatically optimizes code inside an SCTL.
• Removed enable chain registers from code inside the SCTL.
•

•
Executes more quickly.
Consumes less space on the FPGA. na
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• All code in the SCTL finishes executing within one tick of the specified FPGA clock.
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7 Ticks 1 Tick
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Timed Loop Behavior Based on Target

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• FPGA Target
Executes as a single-cycle Timed Loop.
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• Use to optimize performance, such as resource utilization and throughput, or to simply meet
the performance requirements of your application.
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• RT Target or Windows/My Computer Target

Executes as a Timed Loop.
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• Implement multi-rate timing capabilities, precise timing, feedback on loop execution, timing
characteristics that change dynamically, or several levels of execution priority.
C

• Use to separate deterministic from non-deterministic tasks.

Resources For more information about differences in FPGA and RT Windows, refer to
Timed Loop VI Help.

6-10 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 6-1: Observe Loop Speed: While Loop versus Single-Cycle

Timed Loop
Goal
Improve loop execution speeds using a single-cycle Timed Loop. Benchmark the speed of a While Loop

ts
and single-cycle Timed Loop running the same code. Observe the difference in speed between the two.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

m
Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
• LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)
• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines
•

•
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USB Type C or RJ45 Ethernet connection
NI-9211 Thermocouple Input C Series Module
NI-9474 Digital I/O C Series Module
io
•

• Windows 10 PC
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Scenario
You are given a VI containing code to benchmark the total number of clock ticks it takes for a While
N

Loop to run 1,024 iterations and calculate the average number of clock ticks per iteration. You
complete the block diagram to simultaneously obtain the same benchmark and calculation for a
3

single-cycle Timed Loop. You then compare the results.

02

Implementation
1. From the C:\Exercises\FPGA\Comparing While Loop and SCTL directory,
2

open While Loop versus SCTL.lvproj.

2. Configure the CompactRIO target:
ht

a. From Project Explorer, right-click the CompactRIO Target and select Properties.
b. In the General category, set the IP Address to the IP address of your CompactRIO target.
ig

3. From Project Explorer, open While Loop SCTL Benchmarking.vi. You will finish building this VI
in this exercise.
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4. Examine the functionality on the block diagram:

a. Notice that there are two sequence structures. Because there is no wire or data dependency
op

connecting the two sequence structures to each other, the two sequence structures will run
in parallel.
b. Observe the top sequence structure. This sequence structure gets the value of the free-running
C

counter in units of ticks before and after the code in the second frame of the sequence
structure runs.

© National Instruments Corporation | 6-11

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c. Observe the bottom sequence structure. This sequence structure contains the same functionality as the top sequence structure,
6-12

Lesson 6
except that it does not contain a While Loop.
d. Observe the code to the right of each sequence structure. This code calculates the total number of ticks it takes to run the While
|

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Loop 1,024 times. It also calculates the average number of ticks per loop iteration.

Exploring Common FPGA Optimizations

5. Modify the block diagram to benchmark a single-cycle Timed Loop, as shown in Figure 6-1.

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Figure 6-1. While Loop SCTL Benchmarking VI Block Diagram

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1 Timed Loop—Double-click the Input node of the Timed Loop. Notice that the Timed Loop is configured to use the top-level timing source,
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which is the 40 MHz Onboard Clock on the FPGA. This means that the Timed Loop is configured to run at a rate of 40 MHz.

6. Save the VI.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Test
1. Set the front panel controls to the values that you want the VI to average.
2. Compile the VI on the FPGA.
3. Run the While Loop SCTL Benchmarking VI to start the compile process.
4. When the VI finishes running, verify that the values in the Average Value (1234) indicator and

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Average Value (ABCD) indicator are correct.
5. Compare the Ticks (While Loop) and Ticks (SCTL) indicators.

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6. The Ticks (While Loop) indicator shows the number of FPGA clock ticks required to run the While
Loop 1,024 times. The Ticks (SCTL) indicator shows the number of FPGA clock ticks required to

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run the single-cycle Timed Loop 1,024 times.
7. Compare the Avg Ticks (While Loop) and Avg Ticks (SCTL) indicators.

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8. The Avg Ticks (While Loop) indicator shows the average number of FPGA clock ticks required to
run each iteration of the While Loop. The Avg Ticks (SCTL) indicator shows the number of FPGA
clock ticks required to run each iteration of the single-cycle Timed Loop.

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9. Notice that the While Loop requires about 7 FPGA clock ticks to run each iteration. The
single-cycle Timed Loop is much faster and only requires 1 FPGA clock tick to run each iteration.

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Note All operations in a single-cycle Timed Loop must be able to be completed within one
cycle of the FPGA clock.

End of Exercise 6-1

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© National Instruments Corporation | 6-13

 Lesson 6 Exploring Common FPGA Optimizations

Using FPGA Clocks

• This FPGA code always requires 5 clock ticks.

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• Time of clock tick = 1 / clock frequency.
• The default FPGA clock frequency depends on the hardware. For example, clock frequency is
40 MHz for R Series boards and cRIO.

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• Altering clock frequencies alters the execution speed of FPGA code.

Executing Code in Single-Cycle Timed Loops

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FPGA Clocks
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diagram. na
Determine the execution time of the individual VIs and functions on the FPGA VI block
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Types of FPGA Clocks
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• Base Clock and Derived Clock

• Top-level Clock
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Using FPGA Base Clock

FPGA Base Clock
• Digital signal existing in hardware that you can use as a clock for an FPGA application.
• FPGA targets have an onboard clock.

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FPGA Derived Clock

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• Created from a base clock.

• Can derive clock frequencies other than the base clock frequency.
Can use derived clocks as a clock for an FPGA application.
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© National Instruments Corporation | 6-15

 Lesson 6 Exploring Common FPGA Optimizations

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FPGA Top-Level Clock
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• Clock that the FPGA VI uses outside of SCTLs.
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• Controls the execution rate of the code outside of SCTLs.

• Default top-level clock is the onboard FPGA clock.
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6-16 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Changing the FPGA Top-Level Clock Rate

• LabVIEW FPGA functions are designed to compile successfully at clock rates of 40 MHz.
• Not all FPGA VIs successfully compile with faster clock rates.
• The Compilation Status window will report a failure if the clock rate is too fast for the
FPGA VI.

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Using FPGA Clocks with SCTL

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• Can configure a SCTL to use a specific FPGA clock as its timing source.
• Default timing source is the top-level.

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• Can set a different base clock or derived clock as the timing source.

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• All code in the SCTL must finish executing within 1 cycle of the selected timing source for the
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FPGA VI to compile successfully.

FPGA compilation fails with a timing violation report when the code in the DCTL takes more than
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•
the specified time.
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SCTL code must finish executing within

1 cycle of the 80 MHz derived clock.
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© National Instruments Corporation | 6-17

 Lesson 6 Exploring Common FPGA Optimizations

FPGA Clock Summary

• Base Clock—Digital signal existing in hardware that you can use as a clock for an FPGA
application.
• Derived Clock—Created from a base clock that you can use as additional clocks for an FPGA
application.

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• Top-Level Clock—The clock that the FPGA VI uses outside of SCTLs.

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Troubleshooting SCTL Errors
You can use most VIs and functions available when you target an FPGA target in a single-cycle Timed
Loop. However, you cannot use the following VIs, functions, and structures in a single-cycle Timed

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Loop. LabVIEW reports a code generation or compile-time error for the single-cycle Timed Loop when
you try to compile an FPGA VI with any of the following VIs, functions, or structures in a single-cycle

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Timed Loop:
• Analog Period Measurement VI
• Butterworth Filter VI

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• Discrete Delay VI
• Divide function

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• FIFO Clear function
• FPGA I/O Method Node except with some FPGA targets
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• Interrupt VI na
FPGA I/O Property Node except with some FPGA targets
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• Look-Up Table 1D VI with the Interpolate data checkbox selected
• Loop Timer VI
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• Multiple FPGA I/O Nodes configured for the same I/O resource if at least one node is inside the
loop and at least one node is outside the loop
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• Non-reentrant subVIs if you use multiple instances

• Notch Filter VI
PID VI
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• Quotient & Remainder function

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• Reciprocal function
• Rotate 1D Array function
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• Sine Wave Generator VI

• Single-precision floating-point operations
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• Square Root function

• Timed Loop
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• Wait Express VI
• Wait on Occurrence function
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• While Loop
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Resources For more information and a detailed list of unsupported objects, refer to
LabVIEW FPGA Help.
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6-18 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

SCTL Errors—Unsupported Objects

• Code Generation Errors window shows unsupported objects.
• Appears if errors occur while generating intermediate files.
• Xilinx compilation process does not occur.

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Note You do not need to wait for the compilation to finish to find these errors.
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SCTL Errors—Combinatorial Paths

• SCTL limited by logic and routing delays in FPGA circuitry.
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• If total path propagation takes longer than 1 clock cycle, compilation fails.
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• No way to pre-determine path length.

• Try to reduce path length before using SCTL.
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A combinatorial path is the path through logic between the output of a register and the input of another
register on an FPGA. A register stores data on an FPGA and updates the data on the rising edge of a
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clock. Long combinatorial paths take more time to execute and limit the maximum clock rate of the
clock domain.
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Long combinatorial paths are typically a problem in single-cycle Timed Loops because the logic
between the input register and the output register must execute within one period of the clock rate
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you specify. In the single-cycle Timed Loop, registers within and between components are removed,
increasing the length of the combinatorial path between registers. If the code in a combinatorial path
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does not execute within a clock cycle, LabVIEW returns a timing violation in the Compilation Failure
dialog box.

Note Deeply nested Case structures can also cause LabVIEW to return a timing violation
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in the Compilation Failure dialog box.

© National Instruments Corporation | 6-19

 Lesson 6 Exploring Common FPGA Optimizations

• Investigate timing violations with the Timing Violation Analysis window:

• See the logic, routing, and total delay of each item.
• Show the path of the timing violation on the block diagram.

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SCTL Errors—Combinational Paths
• Fix the timing violations.
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Speed up the path by optimizing the code in the SCTL.
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• Select a slower clock for the SCTL timing source.
Speed up the path by moving some code out of the SCTL.
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• Speed up the path by reducing its length further using pipelining.

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To reduce the length of a combinatorial path, first, simplify the logic as much as possible. Once you
have reduced the logic to its simplest form, you can further reduce the length of a combinatorial path
by dividing the logic into discrete steps and pipelining your design.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 6-2: Fix SCTL Errors

Goal
Examine and fix errors in a single-cycle Timed Loop caused by unsupported objects and clock rates.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection

Scenario
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You inherited an FPGA VI that contains code in a single-cycle Timed Loop. When you try to compile
the VI in this exercise, you run into errors caused by unsupported objects and clock rates. You will
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use the Code Generation, Compilation Status, and Timing Violation Analysis windows to examine and
fix the errors.
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Implementation
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1. From the C:\Exercises\FPGA\Fixing SCTL Errors\Investigate Timing Errors directory,

open [cRIO-9056] Investigate SCTL Errors.lvproj.
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2. Configure the CompactRIO target:

a. Right-click the CompactRIO target in Project Explorer and select Properties.
02

b. In the General category, set the IP Address to the IP Address of your CompactRIO target.
3. From Project Explorer, open Investigate SCTL Errors.vi.
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4. Examine the block diagram:

a. Notice that the first frame of the Sequence Structure starts the analog input acquisition on the
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NI 9234.
b. Notice that the second frame of the Sequence Structure contains a single-cycle Timed Loop
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that contains code to acquire from an analog input channel on the NI 9234 and calculates the
average of the last four values.
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c. What functions do you see in the Timed Loop that are not supported in a single-cycle Timed
Loop?
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d. Notice the True constant wired to the Conditional terminal of the Timed Loop, this configures
the single-cycle Timed Loop to only run one iteration when it is called.
e. Notice that the While Loop will stop if the Stop control is TRUE.
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f. Notice that the last frame of the Sequence Structure stops the analog input acquisition on the
NI 9234.

© National Instruments Corporation | 6-21

 Lesson 6 Exploring Common FPGA Optimizations

5. Run the VI to start the compilation process. Because the single-cycle Timed Loop contains
unsupported objects, LabVIEW will pop up a Code Generation Errors window instead of compiling
the VI.
6. Examine the Code Generation Errors window:
a. Notice that the Divide function and the FPGA I/O Node: Mod2/AI0 (Read) are not supported

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inside the single-cycle Timed Loop.

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Note Some FPGA I/O Nodes are supported in the single-cycle Timed Loop.

b. Select each unsupported object and read the Details section.

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c. Select each unsupported object and click Show Error to see where the object is on the block
diagram.

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d. Close the Code Generation Errors window when finished.

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6-22 | ni.com
 ts
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7. To remove the unsupported objects from the single-cycle Timed Loop, modify the block diagram, as shown in Figure 6-2.

Figure 6-2. Investigate SCTL Errors VI Block Diagram

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Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

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© National Instruments Corporation

Divide function—Delete the unsupported Divide function.

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1 Average Acceleration indicator—Right-click the indicator and select Adapt to Source.
2 Scale By Power Of 2 function—Right-click the n input and select Create»Constant. Set the constant to -2. This accomplishes the division
by 4 functionalities using a function that is supported in the single-cycle Timed Loop.
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3 FPGA I/O Node—Move this object outside the single-cycle Timed Loop because it is not supported in the single-cycle Timed Loop.
4 Stop control—Move this object outside of the single-cycle Timed Loop.
5 Timed Loop—Right-click the loop condition terminal and select Create»Constant. Set the constant to TRUE. This technique configures
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the single-cycle Timed Loop to only run one iteration when it is called.
6 While Loop—Use the While Loop to implement the looping functionality of the code. Wire the Stop control to the loop iteration terminal
of the While Loop.
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7 Shift registers—Delete the shift register on the single-cycle Timed Loop. Create and wire the shift register on the While loop as shown
in Figure 6-2. Expand the shift register to display three elements.
| 6-23

8. Save the VI.

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 Lesson 6 Exploring Common FPGA Optimizations

9. Increase the FPGA clock rate:

a. Add a 200 MHz derived clock.
b. In Project Explorer, double-click cRIO-9056»Chassis»FPGA Target. Right-click 40 MHz
Onboard Clock and select New FPGA Derived Clock.
c. Set Desired Derived Frequency to 200 MHz.

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d. Click OK.

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Note Create derived clocks to create clocks with frequencies other than the base clock
frequency.

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10. Set the single-cycle Timed Loop to use the 200 MHz derived clock:
a. Double-click the Input Node of the single-cycle Timed Loop.

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b. Enable the Select Timing Source checkbox.
c. Select 200 MHz in the Available Timing Sources section.
d. Click OK.

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11. Save the VI.
12. Run the VI to start the compilation process.

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13. Investigate the timing violations that caused the compilation process to fail:
• When the compile fails, set Reports to Summary in the Compilation Status window. Notice

14. Click Investigate Timing Violations.

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that the compilation failed due to timing violations.

15. Examine the Timing Violation Analysis window, which displays the objects in the Timed Loop:
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a. Notice the time requirement of 5.00 ns. Because all operations in the single-cycle Timed Loop
must execute within one FPGA clock cycle, the operations must execute within less than 5 ns
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(1/200,000,000 seconds), which is the FPGA clock period of the 200 MHz derived clock.
b. You can see the total delay required for each path and item.
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c. What is the total delay of Path 1? _____________________ ns.

d. Notice that the total delay of Path 1 exceeds the time requirement of 5.00 ns.
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Note The total delay is the sum of the logic delay and the routing delay. The logic delay
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indicates the amount of time in nanoseconds that a logic function takes to execute. The
routing delay indicates the amount of time in nanoseconds that a signal takes to traverse
between FPGA logic blocks.
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e. Select the Timed Loop object and click Show Element to display the path on the block diagram.
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f. Close the Timing Violation Analysis window when finished.

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6-24 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

16. Fix the timing error by modifying the derived FPGA clock to an appropriate rate.
a. Add a 80 MHz derived clock:
i In Project Explorer, double-click cRIO-9056»Chassis»FPGA Target. Right-click 40 MHz
Onboard Clock and select New FPGA Derived Clock.
ii Set Desired Derived Frequency to 80 MHz.

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iii Click OK.
b. Double-click the Input Node of the Timed Loop.

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c. Enable the Select Timing Source checkbox.
d. Select 80 MHz in the Available Timing Sources section.

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e. Click OK.
17. Save the VI and the project.

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© National Instruments Corporation | 6-25

 Lesson 6 Exploring Common FPGA Optimizations

Test
If you are using in-person hardware, on the Sound and Vibration Signal Simulator, set the following
switches (optional):
1. Compile the VI on the FPGA:
• Run the Investigate SCTL Errors VI to start the compile process.

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2. Test the application.
At the end of compilation, the program should download, and the FPGA VI should begin to report

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an averaged acceleration signal value from the Y Acceleration output of the Sound and Vibration
Signal Simulator box:
a. Switch the Fan Speed Control switch to DIAL.

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b. Twist the Fan Speed Control dial to vary the Mod1/AI0 signal.

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c. When finished, click Stop to stop the application.
3. Close the VI and the project.

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End of Exercise 6-2

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6-26 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Optimizing Code within a While Loop

You can also include logic in a single-cycle Timed Loop to optimize code in an FPGA VI, as shown in
the following block diagram. If you use a single-cycle Timed Loop within a While Loop, as shown, wire
a True constant to the condition terminal so that the code within the Timed Loop executes only once.

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If you want to use the single-cycle Timed Loop, all operations inside the loop must fit within 1 cycle
of the FPGA clock. You can use most VIs and functions in a single-cycle Timed Loop. However,
LabVIEW reports a code generation or compile-time error for the single-cycle Timed Loop when you

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compile an FPGA VI with certain VIs, functions, or structures in a single-cycle Timed Loop. Refer to
Timed Loop for more information about objects you cannot use in a single-cycle Timed Loop.

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FPGA Inter-Process Communication between Multiple Clock Domains

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Multiple Clock Domains

Single-cycle Timed Loops can run under different clock domains. For example, one SCTL can run using
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a 40 MHz clock, and another SCTL can run using an 80 MHz clock.

Register Items and Local and Global Variables

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You can write to a register item or a local or global variable from only one clock domain. You can then
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read from the register item or local or global variable in as many clock domains as you need. LabVIEW
transfers data from the writing domain to the reading domain and uses handshaking to avoid data
corruption. You must wait several clock cycles for both the writing and reading domains to handshake
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a new value. Some values you write from one clock domain might not be read by the destination
domain because of the handshaking overhead. To avoid cases where data is written faster than it can
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be read, you should program additional logic to ensure two-way communication between the reader
and writer, thus preventing data loss.
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Note To ensure that all data written in the same iteration of the sending clock domain
arrive together in the destination clock domain, place the data in a cluster. The data for each
register item or variable handshake separately.

© National Instruments Corporation | 6-27

 Lesson 6 Exploring Common FPGA Optimizations

Memory Items Implemented Using Block Memory

You can use a target-scoped or VI-defined memory item to store data and access it from a different
clock domain only if you implement the memory item using block memory. To change the memory
implementation, choose Block Memory as the Implementation of the memory item on the General page
of the Memory Properties dialog box. In this implementation, you can use only one writer node and

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one reader node for each memory item.

Caution When you use memory items implemented using block memory in multiple clock

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domains, it is possible to read from and write to the same address simultaneously. However,
doing so can result in reading incorrect data.

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Note Memory Items are not always recommended to transfer data between multiple clock
domains.

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Block Memory FIFOs
You can use a target-scoped or VI-defined FIFO to transfer data between clock domains only if you

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implement the FIFO using block memory. To change the FIFO implementation, choose Block Memory
as the Implementation of the memory item on the General page of the FIFO Properties dialog box. You
can write data to a block memory FIFO from only one clock domain. You can then read the FIFO from

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only one other clock domain.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

E. Implementing Pipelining
Objective: Learn how to implement pipelining in your FPGA VI.

Overview and Use Cases

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Pipelining A technique you can use to increase the throughput or speed of an FPGA loop.

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• Takes advantage of the parallel processing capabilities of the FPGA.
• By using parallel processing, pipelining increases the efficiency of sequential code.

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• The code should be divided into discrete steps.
• Wire inputs and outputs of each step to Feedback Nodes or shift registers.

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Feedback Nodes are identical in functionality to a shift register and are often preferable from a user
standpoint because they maintain a more congruous appearance like that in the initial code. The
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Feedback Node uses the value wired to the initializer terminal as the initial value for the first iteration
or execution. The Feedback Node then stores the previous iteration result for each subsequent
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execution. If you do not wire a value to the initializer terminal, the Feedback Node uses the default
value for the data type and continues building on previous results in subsequent executions.
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You can use the Feedback Node to implement a pipeline and reduce long combinatorial paths. When
you use the Feedback Node inside a Case structure, the Feedback Node updates data only on clock
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cycles when the owning sub-diagram executes.

The Feedback Node is implemented as a register and requires logic resources in proportion to the width
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of the data type. Using the initialization terminal slightly increases logic resource usage.
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© National Instruments Corporation | 6-29

 Lesson 6 Exploring Common FPGA Optimizations

Basic Example of Pipelining

• Simple set of code with inputs and outputs.
• Takes 7 clock cycles to execute.
• 5 cycles for the code, 2 for the loop.

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• If Input = 1 for I = 0...3.
• Output = 1, 5, 9, 13.

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Implementation and Optimization
• Passes data to the next step of code by using shift registers.

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• Takes 5 clock cycles to execute.
• 3 cycles for the code, 2 for the loop.
• If Input = 1 for I = 0…3.
• Output = ?, ?, 1, 5. na
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Pipelining the analog input and output operations drastically reduces the loop period, increasing the
sample rate, or control loop rate. Because the analog input and analog output operations both take a
long time to run on the FPGA, it is efficient to put them in parallel on the FPGA and have them run at
the same time.

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Note There are blue coercion dots on the math functions. Any arithmetic functions
performed on fixed-point data will generate outputs with larger integer and word lengths to
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accommodate any possible outputs. To control the fixed-point word and integer lengths,
right-click the arithmetic function and select Properties. Navigate to the Output
Configuration tab and de-select Adapt to Source. In the Encoding section, you can specify
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the integer and word length of the fixed-point data that is generated.
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• What can you do if your code executes too slowly?

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12 cycles
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In the presented figure, the longest path is from the DIO to the position indicator. Because little is done
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in parallel, perform the operations in the Case structures in parallel.

© National Instruments Corporation | 6-31

 Lesson 6 Exploring Common FPGA Optimizations

a. You can shorten the longest path using basic optimizations. Reduce the Depth of the Data
Flow. Execute the increment and decrement functions in parallel to shorten the path.

9 cycles

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b. You can shorten the longest path further by implementing pipelining. Implement pipelining to
reduce the loop rate to 6 clock cycles.

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6 cycles

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Using Pipelining in SCTL

• SCTL that is limited by propagation delays through the FPGA circuitry.
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• If total combinatorial path propagation takes longer than 1 clock cycle, compilation fails.
• First, shorten the longest path using basic optimizations.
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• If necessary, reduce the length of the combinatorial path further using pipelining.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Implementation in SCTL
Within this SCTL, the combinatorial path is too long for the FPGA to successfully compile. You should
reduce the combinatorial path by pipelining the block diagram.

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© National Instruments Corporation | 6-33

 Lesson 6 Exploring Common FPGA Optimizations

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When you implement a pipeline, the output of the final step lags the input by the number of steps in
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the pipeline, and the output is invalid for each clock cycle until the pipeline fills. The number of steps
in a pipeline is called the pipeline depth, and the latency of a pipeline, measured in clock cycles,
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corresponds to its depth. For a pipeline of depth N, the result is invalid until the Nth loop iteration, and
the output of each valid loop iteration lags the input by N-1 iterations.
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The subsequent block diagram shows a pipeline with three steps. Therefore, the result of the final step
is invalid until the 3rd loop iteration (i = 2), and the output of each valid loop iteration lags its
corresponding input by two iterations.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Exercise 6-3: Use Pipelining

Goal
Speed up the path inside a single-cycle Timed Loop by reducing the path length using pipelining.

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Requirements
To complete this exercise, it is necessary to have access to the following hardware and software.

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Software:
• LabVIEW 2023 Q3 (32-bit)

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• NI-DAQmx 2023 Q3 (32-bit)
LabVIEW Real-Time Module 2023 Q1 (32-bit)

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• LabVIEW FPGA Module 2023 Q1 (32-bit)

• NI CompactRIO 2023 Q3 (32-bit)

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Hardware:
• An NI CompactRIO from either the 904x or 905x product lines

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• USB Type C or RJ45 Ethernet connection

Scenario
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You inherited an FPGA VI that contains code in a single-cycle Timed Loop that needs to execute using
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an 80 MHz derived clock. However, the code currently cannot finish executing within one FPGA clock
cycle of the 80 MHz clock. You use pipelining to speed up the code so that it can run using the 80 MHz
clock.
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Implementation
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1. From the C:\Exericses\FPGA\Implementing Pipelining\Pipelining directory,

open [cRIO-9056] Pipelining.lvproj.
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• Configure the CompactRIO target.

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a. In Project Explorer, right-click CompactRIO Target and select Properties.

a. In the General category, set the IP Address to the IP Address of your CompactRIO target.
2. From Project Explorer, open Pipelining.vi.
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© National Instruments Corporation | 6-35

 Lesson 6 Exploring Common FPGA Optimizations

3. Examine the block diagram:

• Notice that the single-cycle Timed Loop is using a 80 MHz derived clock. Because all
operations in the single-cycle Timed Loop must execute within one FPGA clock cycle, the
operations must execute within less than 12.50 ns (1/80,000,000 seconds), which is the
FPGA clock period of an 80 MHz derived clock.

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If you compile this VI, the compilation fails due to timing violations and you would investigate
the Timing Violation Analysis window, as shown in Figure 6-3.

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Figure 6-3. Timing Violation Analysis Window

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4. Examine the Timing Violation Analysis window in Figure 6-3:

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a. What is the total delay of Path 1? __________________________ ns.

b. Notice that the total delay of Path 1 exceeds the time requirement of 12.49 ns.
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c. How can you use pipelining to reduce the total delay of Path 1 to less than or equal to
12.49 ns?
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

5. Modify the block diagram, as shown in Figure 6-4, to speed up the path inside the single-cycle
Timed Loop by reducing the path length using the pipelining technique.

Figure 6-4. Pipelining VI Block Diagram

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1 Feedback Node—Delete the wires between the Process Data subVIs. Place two Feedback Nodes

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on the block diagram. Right-click each Feedback Node and select Change Direction.
2 Greater Or Equal? function—Because this pipeline has three steps, the first valid output of the

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final step does not occur until the third iteration of the single-cycle Timed Loop. Therefore, use
the Greater Or Equal? function to indicate whether the output of the final step is valid.
Case structure—Place the Result indicator in the True case. Leave the False case empty.
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Note When you implement a pipeline, the output of the final step lags behind the input by
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the number of steps in the pipeline, and the output is invalid for each clock cycle until the
pipeline fills. The number of steps in a pipeline is called the pipeline depth, and the latency
of a pipeline, measured in clock cycles, corresponds to its depth. For a pipeline of depth N,
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the result is invalid until the Nth clock cycle, and the output of each valid clock cycle lags
behind the input by N-1 clock cycles.
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6. Save the VI and the project.

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 Lesson 6 Exploring Common FPGA Optimizations

Test
1. Compile the VI on the FPGA.
• Run the Pipelining VI to start the compile process.
2. Verify that the FPGA VI now compiles successfully due to your pipelining optimization.
3. When finished, abort the execution of the FPGA VI.

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4. Close the VI and the project.

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End of Exercise 6-3

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

F. Exploring Four-Wire Handshaking

Objective: Explore the four-wire handshaking optimization to improve throughput.

Performing High Throughput FPGA Math & Analysis

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To increase the throughput of Express VIs, place them inside an SCTL and use four-wire handshaking.

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VI Execution Modes
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Outside Single-Cycle Timed Loop Inside Single-Cycle Timed Loop
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The Express VI generates different codes depending on its configuration parameters. The Execution
Mode configuration parameter determines if the Express VI may be placed inside a Single-Cycle Timed
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Loop or not. In the presented example, due to the algorithm, this node (Mean, Variance and Standard
deviation Express VI) includes a handshaking terminal even when it is configured for execution outside
a single-cycle timed loop, and there are additional terminals on the Express VI configured to operate
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inside a Single-Cycle Timed Loop. These terminals are also used for handshaking between upstream
and downstream nodes and will be covered in more detail later. Lastly, point out that when the
Execution Mode is Inside SCTL, there is a Latency specification.

© National Instruments Corporation | 6-39

 Lesson 6 Exploring Common FPGA Optimizations

FPGA Loop Throughput and Latency

Throughput The minimum number of FPGA clock cycles that must elapse before this
function can receive valid input data.

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Latency The number of iterations before generating a valid result for the
corresponding input.

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Most FPGA Math & Analysis VIs (when set to execute in a SCTL) are multi-cycle, which means these
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functions take more than 1 cycle to return a valid result. If you place a multi-cycle node inside a
single-cycle Timed Loop, it does not return a valid value during every clock cycle. The throughput rate
of the function and the values of the handshaking terminals determine the clock cycles during which
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this function produces a valid value. The throughput rate, in cycles/sample, is the minimum number
of FPGA clock cycles that must elapse before this function can receive valid input data. Latency is the
number of iterations before generating a valid result.
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Note Throughput and latency may change depending on how the node is configured. In
many functions, you can configure the throughput. Consider an SCTL iteration to be an
FPGA cycle.

6-40 | ni.com
 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

High Throughput Square Root Example

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Most multi-cycle Express VIs implement throughput and latency as shown in the presented figure.
For this example, in the configuration of the High Throughput Square Root VI, the throughput is
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2 cycles/sample, and the latency is 8 cycles.

Throughput
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Two SCTL iterations (i.e., FPGA clock cycles) must elapse before the function can accept a new input.
Notice that there are two SCTL iterations between this function accepting input A, input B, input C,
input D, and input E.

© National Instruments Corporation | 6-41

 Lesson 6 Exploring Common FPGA Optimizations

Latency
This requires 8 cycles from the time it accepts input A to when it generates a valid output A’ that
corresponds to input A. Notice that eight SCTL iterations (i.e., FPGA clock cycles) occur between
input A and output A’, input B, and output B’, input C and output C’, etc.

The example function requires 8 cycles before it outputs the first valid result. But afterwards, this

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example function will output a new valid result every two cycles. The timing above shows how most
functions with a throughput setting execute.

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FFT Express VI Example

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The FFT Express VI implements throughput and latency differently from other multi-cycle Express VIs.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

FFT Express VI
For most VIs with a throughput setting, the throughput specifies the number of iterations between
when the VI can accept a new input. However, the FFT Express VI throughput behaves slightly
differently because the FFT Express VI must process frames of n points, where n is defined by the
Length parameter in the configuration window of the Express VI. Because of this, the FFT Express VI

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accepts n new inputs in consecutive Iterations and returns the corresponding n outputs in consecutive
iterations after the number of iterations determined by latency. The throughput indicates how often
the FFT Express VI can accept a new frame of n points.

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Latency

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The example configuration of the FFT Express VI requires 228 cycles from the time it accepts the first
input of Frame A to when it generates the first valid output of Frame A’ that corresponds to Frame A.
Notice that 228 SCTL iterations (i.e., FPGA clock cycles) occur between input Frame A and output

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Frame A’, input Frame B and output Frame B’, etc.

Note Frame A consists of 64 consecutive inputs, and Frame A’ consists of 64 consecutive

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outputs. This is because the configured length of this FFT Express VI is 64.

Throughput

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The throughput of 4.07 cycles/sample is the overall throughput when using this configuration of the
FFT Express VI. In this example, Frame A consumes inputs for 64 consecutive cycles and waits

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196 cycles before consuming inputs for another 64 consecutive cycles. This gives you an overall
throughput of 4.0625 cycles/sample ((64+196) / 64). Rounding to a slower throughput, you get
~4.07 cycles/sample.
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 Lesson 6 Exploring Common FPGA Optimizations

VI Handshaking

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In a single-cycle Timed Loop, handshaking is necessary because multi-cycle nodes need more than one
cycle to compute valid data, but the single-cycle Timed Loop forces these nodes to return data every

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clock cycle. Therefore, multi-cycle nodes do not return valid data every clock cycle (due to throughput
and latency). To ensure the numerical accuracy of an algorithm, nodes that depend on this data must
know whether the data is invalid or valid.
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NI has established a handshaking protocol you can use with certain nodes inside a single-cycle Timed
Loop. This protocol involves the following terminals:
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• input valid—Specifies that the next data point has arrived for processing.
output valid—Indicates that the current data point produced by the node is valid and ready to be
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•
used by downstream nodes. This terminal also exists for many math and analysis functions that
run outside of the SCTL, simply due to the nature of the algorithm.
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• ready for output—Specifies whether the downstream node can accept a new data point.
ready for input—Indicates whether the node can accept a new data point during the next clock
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•
cycle.

Note Because this protocol involves four terminals, handshaking in FPGA VIs is sometimes
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Since ready for input indicates readiness on the next clock cycle, a feedback node is used.
Handshaking determines:
• When a function discards data from upstream nodes
• When a function accepts data from upstream nodes
• When downstream nodes discard data from an upstream function

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• When downstream nodes accept data from an upstream function

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Note These nodes may contain an initial initialization cycle. If you convert them to subVIs,
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you may notice the First Call? primitive is wired to the Reset? terminal of the internal
implementation.
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 Lesson 6 Exploring Common FPGA Optimizations

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Throughput is the rate at which a node is ready to accept new data. In a series of connected nodes

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inside a SCTL, the node with the slowest throughput will bottleneck the entire SCTL.

For a series of connected nodes inside a single-cycle Timed Loop, the fastest throughput rate refers

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to the fewest number of clock cycles, after which you can send more data to the series. The fastest
throughput rate is equal to the throughput rate of the slowest node (that is, the node with the highest
value of its Throughput control) in the series. This node is the bottleneck for all nodes in the series. If
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the system sends data to this series at a rate that is faster than this fastest rate (that is, the system
waits fewer than the fewest number of allowable clock cycles before sending data to the series),
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LabVIEW discards data points.

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To determine the fastest throughput rate for a series of nodes, first determine the throughput rate of
each node by looking at the Throughput control for that node. You can see this control by
double-clicking a node or by displaying the Context Help window of the node. The Throughput control
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with the highest value (that is, the slowest node) has the fastest rate (that is, the fewest number of
cycles) at which the system can send data to this series of functions.
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Latency for a Series of Nodes

Calculate the total latency for a series of nodes by adding the latency of every node together. For
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example, if Node A has a latency of 0 cycles, Node B has a latency of 3 cycles, and Node C has a
latency of 228 cycles, then the total latency for the series of nodes is 231 cycles.
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Caution
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Use caution when branching wires. It is important to consider node latency when branching wires. If
the latency between two parallel branched paths is different, data along the two branches may not be
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Performing High Throughput Math

• Achieve high FPGA fixed-point math and analysis rates.
• Perform operations unavailable in basic Numeric palette:
• Trigonometric,

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• Logarithmic, etc.
• All operations are supported inside the SCTL:

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• Divide inside an SCTL.
• Use SCTL to optimize the bitfile size.

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These functions are like the Numeric functions but support higher throughput rates, handshaking
terminals inside a single-cycle Timed Loop, input/output registers, and automatic pipelining. The High
Throughput Add, Subtract, and To Fixed-Point functions are single-cycle functions. These functions

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execute in a single FPGA clock cycle. All other High Throughput Math functions are multi-cycle
functions. These functions need more than one clock cycle to execute.

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 Lesson 6 Exploring Common FPGA Optimizations

Performing High Throughput Math

There are additional configuration options for most of the High Throughput Math nodes. For example,
you can configure the encodings, word lengths, and integer word lengths of the input and output
terminals, whether to add internal registers for function inputs and/or outputs, and the minimum
number of cycles between two successive values of valid input data. Throughput and latency may

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change with data types. You cannot generate graphical code from High Throughput Math nodes.

The node generates different code depending on its configuration parameters. The Execution Mode

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configuration parameter determines if the node may be placed inside a Single-Cycle Timed Loop or
not. Notice there are additional terminals on the node configured to operate inside a Single-Cycle
Timed Loop. These terminals are also used for handshaking between upstream and downstream nodes

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in the same way as shown in the previous section. You can configure the throughput of this node.
Changing the throughput adds internal pipelining to the implementation, but this is not the same kind

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of pipelining you’re used to in LabVIEW FPGA programming. This pipeline does not increase latency.

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Additional Resources
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Topic Website
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Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module) ni.com

Implementing Multiple Clock Domains (FPGA Module) LabVIEW Help

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

Activity: Lesson Review

1. Match the following FPGA clock items with their sources.

1. FPGA base clock a. Clock that an FPGA VI uses outside of SCTLs.

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2. FPGA derived clock b. Clock created from a base clock that you can
use as additional clocks for an FPGA application.

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3. FPGA top-level clock c. Digital signal existing in hardware that you can
use as a clock for an FPGA application.

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2. Which of the following objects are NOT supported in single-cycle Timed Loops?
Select all that apply.
a. Add

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b. While Loop
c. Loop Timer VI

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d. NI 9211 Analog Input FPGA I/O Node

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3. Which of the following are ways to avoid timing violations when using SCTL in FPGA?
Select all that apply.
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a. Optimize the code in the SCTL.
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b. Move some code out of the SCTL.
c. Select a faster clock for the SCTL timing source.
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d. Select a slower clock for the SCTL timing source.

e. Speed up path by reducing its length further using pipelining.
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© National Instruments Corporation | 6-49

 Lesson 6 Exploring Common FPGA Optimizations

Activity: Lesson Review—Answers

1. Match the following FPGA clock items with their sources.

1. FPGA base clock c. Digital signal existing in hardware that you can
use as a clock for an FPGA application.

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2. FPGA derived clock b. Clock created from a base clock that you can

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use as additional clocks for an FPGA application.

3. FPGA top-level clock a. Clock that an FPGA VI uses outside of SCTLs.

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2. Which of the following objects are NOT supported in single-cycle Timed Loops?
Select all that apply.
a. Add

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b. While Loop
c. Loop Timer VI

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d. NI 9211 Analog Input FPGA I/O Node

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3. Which of the following are ways to avoid timing violations when using SCTL in FPGA?
Select all that apply.
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a. Optimize the code in the SCTL.
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b. Move some code out of the SCTL.
c. Select a faster clock for the SCTL timing source.
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d. Select a slower clock for the SCTL timing source.

e. Speed up path by reducing its length further using pipelining.
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 ts
7

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Debugging and

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Testing in FPGA

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Learn techniques for debugging and testing your FPGA VI
and explore some additional resources.
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Topics
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A. Debugging and Testing FPGA Code
B. Investigating Additional Resources
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. Debugging and Testing FPGA Code

Objective: Explore setting and debugging techniques in the FPGA.

Using Simulation Mode

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To avoid unnecessary compilations, use Simulation Mode.

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Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI
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before compiling it by executing the FPGA VI in simulation mode using simulated I/O. When you use
this test method, LabVIEW generates random data for the inputs or uses a custom VI that you create
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to provide I/O. You can also use the FPGA Desktop Execution Node to communicate with FPGA
resources that you select and to debug your FPGA design. For some FPGA targets, you can also
execute the FPGA VI in simulation mode using real I/O.
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When you run the FPGA VI in simulation on the development computer, you can use all traditional
LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and
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single-stepping, as well as debugging techniques that are specific to the FPGA host VI context.

© National Instruments Corporation | 7-3

 Lesson 7 Debugging and Testing in FPGA

To debug your FPGA design in simulation mode using simulated I/O, select from the following options:
• Sampling probes—Use this option to check intermediate values on a wire as a VI runs and to view
changes in signal data over time.
• FPGA Desktop Execution Node—Use this option if you need to test individual design elements of
your FPGA VI or for system-level testing for designs that rely on supported features. Supported

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features include front panel controls and indicators, I/O resources, and resources that use
simulated time.

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• Custom VI Test Bench—Use this option if you need to create the data coming from a particular
input or monitor an output.

The Sampling Waveform Probe gives you the ability to visualize multiple signals on a waveform graph

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based on sampling events.

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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

You can use traditional debugging tools such as probes, execution highlighting, breakpoints, and
single-stepping when simulating your FPGA VIs on the development computer. However, in FPGA
designs that involve communication protocols, you need to view signals in relation to each other with
history data in order to debug the application. The LabVIEW 2013 FPGA Module introduced a new
probe based on sampling events that makes it easy to visualize signals on a waveform graph, including
relevant timing information.

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The Sampling Waveform Probe can use While Loops, For Loops, and FPGA clock domains as sampling

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event sources. Multiple wires on the block diagram can be associated with those sampling sources,
so they can be visualized together on the Sampling Probe Watch Window. This new way of
visualization makes it easier to analyze multiple signals, especially when they are generated within a

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single-cycle Timed Loop.

Demonstration: Using Sampling Probes for Debugging

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Desktop Execution Node

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• Executes FPGA VI in simulation mode.
• Passes values to FPGA I/O nodes and FPGA controls/indicators.

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 Lesson 7 Debugging and Testing in FPGA

Test FPGA VI with Real-World I/O Data

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Demonstration: Debugging with Desktop Execution Node

Unit Testing for LabVIEW FPGA
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Option 1: Run Directly on Host

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• Allows you to use graphs.

• Allows you to use Unit Test Framework.
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Option 2: Run in Simulation Execution Mode

Allows you to define I/O simulation without modifying code.
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Compiling each FPGA VI for unit testing is not feasible. One unit testing option for LabVIEW FPGA VIs
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is to run the VIs on a Windows target. This allows you to test the logic and algorithms. On a Windows
target, you can use graphs, and you can also use the NI LabVIEW Unit Test Framework toolkit.
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Another unit testing option for LabVIEW FPGA VIs is testing the VIs using the Simulation Execution
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

B. Investigating Additional Resources

Objective: Explore additional resources for FPGA programming.

NI CompactRIO Waveform Library

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CompactRIO Waveform Programming library and template for performing waveform data

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Library acquisition (stream data from FPGA to RT).
• Uses many FPGA best practices.
• Easily modify the examples to jump-start your application

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development.
• Install from VI Package Manager.

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FPGA VI Template Example:

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• Uses IRQ to synchronize FPGA VI and RT VI.

• Interleaves multiple channels through DMA FIFO.
• Pipelines code to acquire and process data simultaneously.
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• Monitors DMA FIFO overflow.

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 Lesson 7 Debugging and Testing in FPGA

Additional Resources

Topic Website

Using Sampling Probes (FPGA) LabVIEW Help

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NI CompactRIO Waveform Reference Library

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NI LabVIEW for CompactRIO Developer’s Guide ni.com

NI LabVIEW High-Performance FPGA Developer’s Guide

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A

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Additional

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Information and

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Resources

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NI provides global services and support as part of our
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commitment to your success. Take advantage of product

services in addition to training and certification programs
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that meet your needs during each phase of the application

life cycle; from planning and development through
deployment and ongoing maintenance.
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 Developing Embedded Applications Using CompactRIO and LabVIEW FPGA

A. NI Services
To get started, register your product at ni.com/myproducts.

As a registered NI product user, you are entitled to the following benefits:

• Access to applicable product services.

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• Easier product management with an online account.
• Receive critical part notifications, software updates, and service expirations.

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Log in to your NI ni.com User Profile to get personalized access to your services.

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B. Services and Resources

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• Maintenance and Hardware Services—NI helps you identify your systems’ accuracy and reliability
requirements and provides warranty, sparing, and calibration services to help you maintain
accuracy and minimize downtime over the life of your system. Visit ni.com/services for more
information.

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– Warranty and Repair—All NI hardware features a one-year standard warranty that is
extendable up to five years. NI offers repair services performed in a timely manner by highly

lI
trained factory technicians using only original parts at a NI service center.
– Calibration—Through regular calibration, you can quantify and improve the measurement

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performance of an instrument. NI provides state-of-the-art calibration services. If your product
supports calibration, you can obtain the calibration certificate for your product at
ni.com/calibration.
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• System Integration—If you have time constraints, limited in-house technical resources, or other
project challenges, NI Alliance Partner members can help. To learn more, call your local NI office
at
or visit ni.com/alliance.
• Training and Certification—The NI training and certification program is the most effective way to
increase application development proficiency and productivity. Visit ni.com/training for more
N

information.
– NI offers courses in several languages and formats including instructor-led classes at facilities
3

worldwide, courses on-site at your facility, and online courses to serve your individual needs.
02

• Technical Support—Support at ni.com/support includes the following resources:

– Self-Help Technical Resources—Visit ni.com/support for software drivers and updates, a
searchable KnowledgeBase, product manuals, step-by-step troubleshooting wizards,
2

thousands of example programs, tutorials, application notes, instrument drivers, and so on.
Registered users also receive access to the NI Discussion Forums at ni.com/forums. NI
Applications Engineers make sure every question submitted online receives an answer.
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– Software Support Service Membership—The Standard Service Program (SSP) is a renewable

one-year subscription included with almost every NI software product, including NI Developer
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Suite. This program entitles members to direct access to NI Applications Engineers through
phone and email for one-to-one technical support, as well as exclusive access to online training
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modules at ni.com/self-paced-training. NI also offers flexible extended contract options

that guarantee your SSP benefits are available without interruption for as long as you need
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them. Visit ni.com/ssp for more information.

• Declaration of Conformity (DoC)—A DoC is our claim of compliance with the Council of the
European Communities using the manufacturer’s declaration of conformity. This system affords
C

the user protection for electromagnetic compatibility (EMC) and product safety. You can obtain
the DoC for your product by visiting ni.com/certification.

For information about other technical support options in your area, visit ni.com/services, or contact
your local office at ni.com/contact.

© National Instruments Corporation | A-3

 Appendix A Additional Information and Resources

C. Other NI Training Courses

NI offers courses to expand the training you received here to other areas. Visit ni.com/training to
purchase course materials or sign up for instructor-led, hands-on courses at locations around the
world.

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D. NI Certification

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Earning an NI certification acknowledges your expertise in working with NI products and technologies.
The measurement and automation industry, your employer, clients, and peers recognize your NI
certification credential as a symbol of the skills and knowledge you have gained through experience.
Visit ni.com/training for more information about the NI certification program.

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