TPS3307-18, TPS3307-25, TPS3307-33

www.ti.com SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

TRIPLE PROCESSOR SUPERVISORS

FEATURES D OR DGN PACKAGE
• Triple Supervisory Circuits for DSP and (TOP VIEW)
Processor-Based Systems
• Power-On Reset Generator With Fixed Delay SENSE1 1 8 VDD
Time of 200ms, No External Capacitor Needed SENSE2 2 7 MR
SENSE3 3 6 RESET
• Temperature-Compensated Voltage Reference
GND 4 5 RESET
• Maximum Supply Current of 40µA
• Supply Voltage Range: 2V to 6V
• Defined RESET Output From VDD ≥ 1.1V
• MSOP-8 and SO-8 Packages
• Temperature Range : – 40°C to +85°C

TYPICAL APPLICATIONS
Figure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for a
processor-based system application. This application uses TI part numbers TPS3307-33 and MSP430C325.
2.5V 5V 3.3V

• Applications using DSPs,

Microcontrollers or Microprocessors
VDD VDD
100nF w Industrial Equipment
SENSE 1 MSP430C325
w Programmable Controls
SENSE 2 RESET RESET w Automotive Systems
470kΩ TPS3307−33 w Portable/Battery Powered Equipment
GND
SENSE 3 w Intelligent Instruments
GND
620kΩ w Wireless Communication Systems
w Notebook/Desktop Computers

Figure 1. Applications Using the TPS3307 Family

DESCRIPTION
The TPS3307 family is a series of micropower supply voltage supervisors designed for circuit initialization
primarily in DSP and processor-based systems, which require more than one supply voltage.
The product spectrum of the TPS3307-xx is designed for monitoring three independent supply voltages:
3.3V/1.8V/adj, 3.3V/2.5V/adj or 3.3V/5V/adj. The adjustable SENSE input allows the monitoring of any supply
voltage >1.25V.
The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the
following supply voltage monitoring table.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS3307-18, TPS3307-25, TPS3307-33
www.ti.com
SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain
below the threshold voltage VIT+.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system
reset. The delay time, td (typ) = 200ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+.
When the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes
active (low) again.
The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to
become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high
RESET output.
The devices are available in either 8-pin MSOP or standard 8-pin SO packages.
The TPS3307-xx devices are characterized for operation over a temperature range of –40°C to +85°C.

SUPPLY VOLTAGE MONITORING

NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP)
DEVICE
SENSE1 SENSE2 SENSE3 SENSE1 SENSE2 SENSE3
TPS3307-18 3.3V 1.8V User defined 2.93V 1.68V 1.25V (1)
TPS3307-25 3.3V 2.5V User defined 2.93V 2.25V 1.25V (1)
TPS3307-33 5V 3.3V User defined 4.55V 2.93V 1.25V (1)

(1) The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.

AVAILABLE OPTIONS (1)

PACKAGED DEVICES
PowerPAD™ MARKING CHIP FORM
TA SMALL OUTLINE
µ-SMALL OUTLINE DGN PACKAGE (Y)
(D)
(DGN)
TPS3307-18D TPS3307-18DGN TIAAP TPS3307-18Y
–40°C to +85°C TPS3307-25D TPS3307-25DGN TIAAQ TPS3307-25Y
TPS3307-33D TPS3307-33DGN TIAAR TPS3307-33Y

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Function/Truth Tables
MR SENSE1 > VIT1 SENSE2 > VIT2 SENSE3 > VIT3 RESET RESET
L X (1) X (1) X L H
H 0 0 0 L H
H 0 0 1 L H
H 0 1 0 L H
H 0 1 1 L H
H 1 0 0 L H
H 1 0 1 L H
H 1 1 0 L H
H 1 1 1 H L

(1) X = Don't care

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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

Functional Block Diagram

VDD TPS3307
14 kΩ

MR

R1
SENSE 1 +
_ RESET
R2
R3 RESET
SENSE 2 + Logic + Timer
_
R4 RESET

GND
Reference
Voltage
of 1.25V _
Oscillator
SENSE 3 +

Timing Diagram
SENSEn
V(nom)
VIT–

t
MR
1

0 t
RESET
1

0 t
td td
td
RESET Because of SENSE Below VIT
RESET Because of MR
RESET Because of SENSE Below VIT–
RESET Because of SENSE Below VIT–

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TPS3307-18, TPS3307-25, TPS3307-33
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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

TPS3307Y Chip Information

These chips, when properly assembled, display characteristics similar to those of the TPS3307. Thermal
compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.

(1) (8)

(2) (7)
TPS3307Y
(3) (6)

(4) (5)
48

CHIP THICKNESS: 10 TYPICAL

BONDING PADS: 4 × 4 MINIMUM

TJ max = 150°C
TOLERANCES ARE ±10%.

ALL DIMENSIONS ARE IN MILS

56

Table 2. Terminal Functions

TERMINAL
I/O DESCRIPTION
NAME NO.
GND 4 Ground
MR 7 I Manual reset
RESET 5 O Active-low reset output
RESET 6 O Active-high reset output
SENSE1 1 I Sense voltage input 1
SENSE2 2 I Sense voltage input 2
SENSE3 3 I Sense voltage input 3
VDD 8 Supply voltage

4 Submit Documentation Feedback

 TPS3307-18, TPS3307-25, TPS3307-33
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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006
(1)
Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
UNIT
Supply voltage, VDD (2) 7V
MR pin –0.3V to VDD +0.3V
All other pins (2) –0.3V to 7V
Maximum low output current, IOL 5mA
Maximum high output current, IOH –5mA
Input clamp current, IIK (VI < 0 or VI > VDD) ±20mA
Output clamp current, IOK (VO < 0 or VO > VDD) ±20mA
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range, TA –40°C to +85°C
Storage temperature range, Tstg –65°C to +150°C
Soldering temperature +260°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation the device must not be operated at 7V for more than t = 1000h
continuously.

Dissipation Rating Table

TA ≤ +25°C DERATING FACTOR TA = +70°C TA = +85°C
PACKAGE
POWER RATING ABOVE TA = +25°C POWER RATING POWER RATING
DGN 2.14W 17.1mW/°C 1.37W 1.11W
D 725mW 5.8mW/°C 464mW 377mW

Recommended Operating Conditions

At specified temperature range.
MIN MAX UNIT
Supply voltage, VDD 2 6 V
Input voltage at MR and SENSE3, VI 0 VDD + 0.3 V
Input voltage at SENSE1 and SENSE2, VI 0 (VDD+0.3)VIT/1.25V V
High-level input voltage at MR, VIH 0.7 x VDD V
Low-level input voltage at MR, VIL 0.3 × VDD V
Input transition rise and fall rate at MR, ∆t/∆V 50 ns/V
Operating free-air temperature range, TA –40 +85 °C

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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 2V to 6V, IOH = –20 µA VDD – 0.2V
VOH High-level output voltage VDD = 3.3V, IOH = –2mA VDD – 0.4V V
VDD = 6V, IOH = –3mA VDD – 0.4V
VDD = 2V to 6V, IOL = 20µA 0.2
VOL Low-level output voltage VDD = 3.3V, IOL = 2mA 0.4 V
VDD = 6V, IOL = 3mA 0.4
Power-up reset voltage (1) VDD ≥ 1.1V, IOL = 20µA 0.4 V
VSENSE3 VDD = 2V to 6V, TA = 0°C to +85°C 1.22 1.25 1.28
1.64 1.68 1.72
VSENSE1, 2.20 2.25 2.30 V
VSENSE2 2.86 2.93 3
4.46 4.55 4.64
Negative-going input threshold
VIT– VDD = 2V to 6V,
voltage (2) VSENSE3 1.22 1.25 1.29 V
TA = –40°C to +85°C
1.64 1.68 1.73
VSENSE1, 2.20 2.25 2.32
V
VSENSE2 2.86 2.93 3.02
4.46 4.55 4.67
VIT–= 1.25V 10
VIT–= 1.68V 15
Vhys Hysteresis at VSENSEn input VIT–= 2.25V 20 mV
VIT–= 2.93V 30
VIT–= 4.55V 40
MR MR = 0.7 × VDD, VDD = 6V –130 –180
SENSE1 VSENSE1 = VDD = 6V 5 8 µA
IH High-level input current
SENSE2 VSENSE2 = VDD = 6V 6 9
SENSE3 VSENSE3 = VDD –25 25 nA
MR MR = 0V, VDD = 6V –430 –600 µA
IL Low-level input current
SENSEn VSENSE1,2,3 = 0V –25 25 nA
IDD Supply current 40 µA
Ci Input capacitance VI = 0V to VDD 10 pF

(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15µs/V
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1µF) should be placed close to the supply terminals.

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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

Timing Requirements
At VDD = 2V to 6V, RL = 1MΩ, CL = 50pF, TA = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SENSEn VSENSEnL = VIT–– 0.2V, VSENSEnH = VIT+ +0.2V 6 µs
tw Pulse width
MR VIH = 0.7 × VDD, VIL = 0.3 × VDD 100 ns

Switching Characteristics
At VDD = 2V to 6V, RL = 1MΩ, CL = 50pF, TA = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI(SENSEn) ≥ VIT+ + 0.2V,
td Delay time 140 200 280 ms
MR ≥ 0.7 × VDD. See Timing Diagram.
Propagation (delay) time, MR to RESETMR to
tPHL
high-to-low level output RESET VI(SENSEn) ≥ VIT+ + 0.2V,
200 500 ns
Propagation (delay) time, MR to RESETMR to VIH = 0.7 × VDD, VIL = 0.3 × VDD
tPLH
low-to-high level output RESET
Propagation (delay) time, SENSEn to RESET
tPHL
high-to-low level output SENSEn to RESET VIH = VIT+ +0.2V, VIL = VIT–– 0.2V,
1 5 µs
Propagation (delay) time, SENSEn to RESET MR ≥ 0.7 × VDD
tPLH
low-to-high level output SENSEn to RESET

Submit Documentation Feedback 7

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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

Typical Characteristics

NORMALIZED SENSE THRESHOLD VOLTAGE SUPPLY CURRENT

vs vs
FREE-AIR TEMPERATURE AT VDD SUPPLY VOLTAGE
°C)

18
1.005
16
Normalized Input Threshold Voltage − VIT(TA), VIT(25

VDD = 2V
1.004 MR = Open 14
12 TPS3307−33
1.003

I DD − Supply Current − µ A
10
1.002 8

1.001 6
4
1
2
0.999 0
−2
0.998
−4
0.997 SENSEn = VDD
−6
MR = Open
0.996 −8 TA = 25°C
−10
0.995 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
−40 −15 10 35 60 85
VDD − Supply Voltage − V
TA − Free-Air Temperature − °C

Figure 2. Figure 3.

INPUT CURRENT MINIMUM PULSE DURATION AT SENSE

vs vs
INPUT VOLTAGE AT MR THRESHOLD OVERDRIVE
100 10
VDD = 6V VDD = 6V
tw − Minimum Pulse Duration at Vsense − µ s

0 TA = 25°C 9 MR = Open

−100 8
I I − Input Current − µ A

−200 7

−300 6

−400 5

−500 4

−600 3

−700 2

−800 1
−900 0
−1−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 100 200 300 400 500 600 700 800 900 1000
VI − Input Voltage at MR − V SENSE − Threshold Overdrive − mV

Figure 4. Figure 5.

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SLVS199C – DECEMBER 1998 – REVISED DECEMBER 2006

Typical Characteristics (continued)

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
2.5 6.5
VDD = 2V VDD = 6V
6
MR = Open MR = Open
5.5
VOH − High-Level Output Voltage − V

VOH − High-Level Output Voltage − V

2
5
4.5

1.5 4
−40°C
3.5
−40°C 3
1 85°C
2.5
2
85°C
1.5
0.5
1
0.5
0 0
0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 −5.5 −6 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50
IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA

Figure 6. Figure 7.

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
2.5 6.5
VDD = 2V 6 VDD = 6V
MR = Open MR = Open
5.5
VOL − Low-Level Output Voltage − V

VOL − Low-Level Output Voltage − V

2
5
4.5

1.5 4
3.5
3
1 85°C 2.5 85°C
2
1.5
0.5 −40°C −40°C
1
0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 5 10 15 20 25 30 35 40 45 50 55 60
IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA

Figure 8. Figure 9.

Submit Documentation Feedback 9

 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jan-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS3307-18D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples

TPS3307-18DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples

TPS3307-18DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAP Samples

TPS3307-18DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30718 Samples

TPS3307-25D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples

TPS3307-25DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAQ Samples

TPS3307-25DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAQ Samples

TPS3307-25DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30725 Samples

TPS3307-33D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples

TPS3307-33DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAR Samples

TPS3307-33DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AAR Samples

TPS3307-33DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 30733 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jan-2024

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3307 :

• Enhanced Product : TPS3307-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3307-18DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS3307-18DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS3307-25DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS3307-25DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS3307-33DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS3307-33DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS3307-18DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0
TPS3307-18DR SOIC D 8 2500 350.0 350.0 43.0
TPS3307-25DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0
TPS3307-25DR SOIC D 8 2500 350.0 350.0 43.0
TPS3307-33DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0
TPS3307-33DR SOIC D 8 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jan-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS3307-18D D SOIC 8 75 505.46 6.76 3810 4
TPS3307-25D D SOIC 8 75 505.46 6.76 3810 4
TPS3307-33D D SOIC 8 75 505.46 6.76 3810 4

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
TM
DGN 8 PowerPAD HVSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225482/B

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 PACKAGE OUTLINE
TM
DGN0008D SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
1.89
1.63 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.57
TYPICAL
1.28

4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.57)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(1.89)

6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225481/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

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 EXAMPLE STENCIL DESIGN
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(1.89)
SYMM BASED ON
0.125 THICK
STENCIL
6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.76 X 2.11
0.125 1.57 X 1.89 (SHOWN)
0.15 1.43 X 1.73
0.175 1.33 X 1.60

4225481/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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