National University of Sciences & Technology (NUST)

Balochistan Campus (NBC), Quetta

Department of Computer Science

Faculty Member: Engr Muhammad Abid Hussain Date: __22-02-25_______

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Semester: __2nd________________________ Section: ____BSAI ______

EE223 – Digital Logic Design

Grp No. 1
Lab No # 1 Familiarization of Basic gates and ICs
S. No. Student Name Reg. No. Total Marks
S1 Ayesha Babar 516223
S2 Uzair Kakar 513802
S3 Muhammad Zafeer 513805
S4 Yusra Khosa 528818
S5 Duaa Amna 514986

This Lab Activity has been designed to familiarize the beginning students with logic gates and IC
chips, using breadboard and testing of gates and logic circuits.

Objectives:

 Familiarize the students with ICs, their categories, and different logic families.
Identify ICs on the basis of series number as well as their functional behavior and pin
numbers.
 Search data sheets of ICs from different sources and optimally use them in the design of
digital circuits.
 Perform functional verification of basic logic gates by listing the truth tables and
establishing IN/OUT relationship.
 Carry out best wiring practices in digital design.

Lab Instructions:

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva session.
 The lab report will be uploaded on LMS three days before the scheduled lab date. The students
will get the hard copy of the lab report, complete the Pre-lab task before coming to the lab and
deposit it with the teacher/lab engineer for subsequent evaluation. Alternatively, each group is to
upload a completed lab report on LMS for grading.

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

 The students failing to complete Pre-lab will not be allowed to attend lab sessions.
 The students will start the lab tasks and demonstrate design steps separately for step-wise
evaluation (the teacher/lab engineer will sign each step after ascertaining functional verification).
Any report submitted without teacher/lab engineer signatures will not be accepted.
 Remember that a neat logic diagram with pins numbered and nicely patched circuits will simplify
the troubleshooting/fault diagnostic process.
 After completion of the lab, the students are expected to unwire the circuit and deposit back
components to lab staff.
 The students will complete lab tasks within the prescribed time and submit a complete report to
the lab engineer before leaving the lab.
 There will be a viva session after the demonstration for which students will be graded
individually.

Method: The instructor evaluates each student based on the task demo, viva, and behavioral observation during the lab
and report submitted.

Getting Started with Circuit Patching

Breadboard:
Breadboards are usually used for patching small circuits and prototypes. A typical breadboard would look like this.

The internal connections are as shown below:

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

The points in the ABCDE (and FGHIJ) grid are vertically connected as indicated by a red circle. So all 5 points are the
same point. It makes no difference whether you connect a wire on any one of these points The next vertical strip is a
different point and so on.

It should be noted that upper and lower grids are horizontally connected indicated below. Each grid consists of 4

such separate horizontal strips:

IC Placement on the Breadboard

A typical 14-pin IC placement on such a breadboard is shown below:

The upper and lower horizontal strips are normally served for power (+5V) and ground (0V) respectively. But it is not
necessary to do so.

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

Never place any IC such that its opposite pins are within (connected to) the same Node on the same grid.

Procedure:

1. Make sure the trainer board is switched off while you are patching the circuit.
2. Make a neat schematic diagram mentioning the IC numbers, PIN configurations and connections between
different ICs.
3. Place the IC(s) such that the Notch is towards the left.
4. Provide the ground connection(s) by connecting the GND pin(s) of the IC(s) to O V on your trainer board
power supply with the help of jumping wires. Make sure that all the ICs are properly grounded.
5. Provide the VDD or operating voltage to each IC by connecting its VDD (or VCC) terminal to +5V on your
trainer board power supply.
6. Patch the circuit as per the schematic.
7. Connect the inputs of your circuit to the logic switches provided on your trainer board. Typically there are 8
such switches provided. The low position of the switch indicates a 0 logic level (0V) and the high position has
a logic level of 1(+5V).
8. Connect the output of your circuit to the logic probe provided on the trainer board.

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

9. Now switch on the trainer board and give the input sequence to your circuit with the help of logic switches. It
is a good practice to give the input sequence in ascending order like this:
000, 001, 010, 011, 100, 101, 110, 111 (Here No. of inputs is 3).
This pattern can be adapted for lesser or more No. of inputs.
10. Observe the output of your circuit against different inputs and record them in the truth table.
11. Compare with theoretical values and debug the circuit if needed.
12. Show your work for each lab task to your Lab Instructor.
13. Give your observations and conclusion.

Pre-Lab Tasks: (5 marks)

1. Read the topic Integrated Circuits (2.9) from your course book and answer the following questions:

Digital ICs can be categorized according to the complexity of their circuits, usually called scale integration. The
following are the six major categories. Give their full names and the range of gates available in each of them.

SSI

Full name: Small Scale Integration

Range of gates: 1 to 10 gates per chip

MSI

Full name: Medium Scale Integration

Range of gates: 10 to 100 gates per chip

LSI

Full name: Large Scale Integration

Range of gates: 100 to 10,000 gates per chip

VLSI

Full name: Very Large Scale Integration

Range of gates: 10,000 to 1 million gates per chip

ULSI

Full name: Ultra Large Scale Integration

Range of gates: 1 million to 100 million gates per chip

GSI

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

Full name: Giga Scale Integration

Range of gates: 100 million to 1 billion gates per chip

2. Another categorization concerns the Logic Families of Digital ICs. The seven of these are listed below. Give
their full name and give their utilization in terms of speed, power, etc. (e.g. Low Power, High Speed).

RTL

 Full Name: Resistor-Transistor Logic

 Utilization Characteristics:

Speed: Low speed

Power Consumption: High power consumption

DTL

 Full Name: Diode-Transistor Logic

 Utilization Characteristics:

Speed: Moderate speed (faster than RTL)

Power Consumption: Moderate power consumption

ECL

 Full Name: Emitter-Coupled Logic

 Utilization Characteristics:

Speed: Very high speed (fastest logic family for its time)

Power Consumption: High power consumption (due to continuous current flow)

TTL

 Full Name: Transistor-Transistor Logic

 Utilization Characteristics:

Speed: Moderate speed (faster than RTL and DTL, but slower than ECL)

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

Power Consumption: Moderate power consumption (higher than CMOS but lower than ECL)

CMOS

 Full Name: Complementary Metal-Oxide-Semiconductor

 Utilization Characteristics:

Speed: Can achieve very high speeds, especially in modern processes (e.g., in microprocessors)

Power Consumption: Very low power consumption, especially when in static state (almost zero when
idle)

IC Pin Numbers:

TOP VIEW
Most of the ICs have a Notch (or sometimes a dot) to denote the start of the PIN numbering. Place the IC such that the
Notch is on the left side, then the lower left PIN is numbered 1 and the numbering continues in the anticlockwise
direction.
Datasheet:

Information about any IC (its number of pins and gates inside it) can be found by simply searching by its name on the
internet. The document containing information about the IC is called its datasheet. Different manufacturers of these
chips have this information on their sites.

3. Show the correct pin numbering and connection of gates inside these blank chips with the help of their
datasheets.

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

ANSWER:

7408

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

4. Mention the manufacturer whose datasheet you consulted.

Lab Task (5 Marks)

Verify the functioning of the following ICs:

7408

7432

7404

Procedure

1. Make a schematic layout diagram in the space provided below, showing IC’s PINs and their
connections to form the logic circuit.
2. Plug in all ICs in the breadboard and power the ICs providing ground and VCC=5V to appropriate
pins. The ground pin is to be connected first and then any other connections are made.
3. By looking at the pin configuration apply input signals from a switch on the logic lab. Connect the
output to LED for display. The operation of the circuit is verified and resource lots are to be shown to
the teacher or Lab assistant. For troubleshooting of the circuit use the logic probe provided in the
lab.
4. Make the truth tables in the space provided below:
5. Mention the full name of each IC provided to you with the help of its datasheet and explain the
naming convention (You should be able to get this information from the internet).

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 National University of Sciences & Technology (NUST)
Balochistan Campus (NBC), Quetta
Department of Computer Science

Example: Quad 2-Input AND Gates SN74 LS08P

SN Standard Prefix of TEXAS INSTRUMENT.
Quad refers to 4 AND gates.
74 refers to commercial-grade IC.
LS means Low Power Schottky.
P Plastic Dual in-Line Package.
08 refers to the AND gate.

Fill in the blanks.

1. The ICs in the 7400 series are based on __TTL (Transistor Transistor Logic)_ logic family?

2. The commercial grade IC is denoted by _CD__ prefix.

3. The military grade IC is denoted by the _MC_ prefix. (

Observations/Comments:

In Question 2 (Logic Families of digital ICs) only five are mentioned not seven and one is repeated.

Question 4 is supposed to be done in the lab.

Deliverables:

Compile a single word document by filling in the solution part and submitting this Word file to the MS Team.
This lab grading policy is as follows: The lab is graded between 0 to 10 marks. The submitted solution can get a
maximum of 5 marks. At the end of each lab or in the next lab, there will be a viva related to the tasks. The viva has a
weightage of 5 marks. Insert the solution/answer in this document. You must show the implementation of the tasks in the
designing tool, along with your complete Word document to get your work graded. You must also submit this Word
document to the MS Team. In case of any problems with submissions on the MS Team, submit your Lab Manual by
emailing them to Engr. Muhammad Abid Hussain [email protected]

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