KPR

INSTITUTE OF ENGINEERING AND TECHNOLOGY

ARASUR, COIMBATORE-641 407

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

U21ECG01 – DIGITAL ELECTRONICS

I YEAR - II SEM (REGULATION 2021)

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 KPR INSTITUTE OF ENGINEERING
AND TECHNOLOGY
ARASUR, COIMBATORE – 641407

DEPARTMENT OF ELECTRONICS AND COMMUNICATIONENGINEERING

LABORATORY RECORD

Name : ……………………………………………
Register number : ……………………………………………
Year & Class :……………………………………………
Semester :……………………………………………
Course Code : ……………………………………………

Course Title : ……………………………………………

Certified that this is a bonafide of work done by the above student during the

academic year 2022-2023

Faculty in-charge HoD-ECE

SUBMITTED FOR THE PRACTICAL EXAMINATION HELD ON ---------------------------

INTERNAL EXAMINER EXTERNAL EXAMINER

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 VISION AND MISSION OF THE INSTITUTION
Vision
To become a premier institute of academic excellence by imparting technical, intellectual and
professional skills to students for meeting the diverse need of the industry, society, the nation
and the world at large
Mission
❖ Commitment to offer value-based education and enhancement of practical skills
❖ Continuous assessment of teaching and learning process through scholarly activities
❖ Enriching research and innovation activities in collaboration with industry and institute of repute
❖ Ensuring the academic process to uphold culture, ethics and social responsibility

VISION AND MISSION OF THE DEPARTMENT

Vision
To be a department of repute for learning and research with state-of-the-art facilities to enable the students
to succeed in globally competitive environment.
Mission
The Mission of the Department is to
❖ To impart knowledge and skill-based education with competent faculty striving for
academic excellence.
❖ To instill research centres in the field, that industry needs, by collaborating with
organizations of repute.
❖ To provide ethical and value-based education by promoting activities addressing
the societal needs and facilitate lifelong learning.
Program Educational Objectives (PEOs)
PEO1: Graduates will possess an adequate knowledge and have successful technical career in
Electronics and Communication Engineering or related fields.
PEO2: Graduates will possess leadership qualities and demonstrate professional and ethical values.
PEO3: Graduates will continue their life-long professional development through higher education or
entrepreneurship.
I. Program Outcomes (POs)
Graduates of Electronics and Communication Engineering will be able to
PO1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO2 Problem analysis: Identify, formulate, review research literature, and analyze complex
electronics and communication engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.

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 PO3 Design/ development of solutions: Design solutions for complex electronics and
communication engineering problems and design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
PO4 Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex electronics and communication
engineering activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual knowledge to access
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and normsof
the engineering practice.
PO9 Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
PO11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multidisciplinary environments.
PO12 Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
II. Program Specific Outcomes (PSOs)
Graduates of Electronics and Communication Engineering will be able to
PSO 1: Design and develop intelligent systems using embedded controllers, Internet of Things and
network security protocols.
PSO 2: Apply engineering knowledge and modern tools to design and implement the projects
pertaining to VLSI design, Signal & image processing and Communication.

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 RUBRICS FOR ASSESSMENT
Excellent Good Adequate Inadequate
Criteria
(4 Marks) (3 Marks) (2 Marks) (1 Mark)
Criterion #1 Able to develop Able to develop Able to use Unable to identify
Ability to setup contingency or contingency or theoretical theoretical
and conduct alternative plans alternative framework, framework,
A. Preparation & Observation

experiments. and anticipate plans. measurement measurement

problems during techniques, techniques,
experiment. testing apparatus testing apparatus
or model. or model.
Criterion #2 Able to formulate Able to evaluate Able to apply Unable to discuss
Ability to take controls and data and relate constraint and experimental
measurements evaluate to engineering assumption into processes and
/ readings and alternatives of the phenomena for the experimental protocols
present data experiment. Able decision- design. Able to
to evaluate data making. conduct
and relate to experiment
engineering correctly and
phenomena for collect data.
decision-making.
Criterion #3 Able to combine Able to evaluate Able to select and Unable to select
Ability to /organize more or compare data use and apply and describe the
analyze the than one set of and make appropriate techniques or
data data, interpret meaningful techniques or methods of
B. Results & Interpretation

theoretically data and make conclusion methods to analyzing the

and logically to meaningful analyze the data. data.
conclude conclusion.
experimental
results
Criterion #4 Able to verify Able to verify Able to identify Unable to identify
Ability to and/or validate and/or validate and verify how how results
interpret and several sets of data and relate results relate/differ from
discuss any data and relates to engineering relate/differ from theory or previous
discrepancies to engineering phenomena for theory or previous results.
between phenomena for decision results
theoretical and decision making. making.
experimental
results
Criterion #5 Able to listen Able to listen Misunderstand Unable to listen
Demonstrate carefully and carefully and the questions and carefully to
C. Viva Voce

the ability to respond to respond to does not respond questions and

effectively questions questions appropriately to does not provide
respond to appropriately; is appropriately the teacher, or an appropriate
questions able to explain has some trouble answer, or is
and interpret in answering unable to answer
results to the questions questions
teacher

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 INSTRUCTIONS TO THE STUDENTS

SAFETY:
You are doing experiments with direct supply voltage and electronics equipment’s.
Mishandling of equipment’s sometimes may cause critical problem to your body system.
To avoid this please keep in mind the followings:

▪ In case of any wrong observations, you have to SWITCH OFF the power supply
related with it.
▪ You have to tuck in your shirts or wear an overcoat.
▪ You have to wear shoes compulsorily and stand on mats made by insulating
materials to electrically isolate your body from the earth.

ATTENDANCE:
If you are absent for a lab class then you have lost several things to learn. So don’t
fail to make your presence with your record notebook having completed experiments,
observation with completed and day’s experiment particulars with required knowledge and
stationeries.

MAKING CONNECTIONS:
▪ Get circuit diagram approval from your faculty in-charge.
▪ Start to give connection as per the circuit diagram from source side.
▪ Make series circuit connections before the parallel circuits like voltmeter
connections.
▪ Before switch ON the power, get circuit connection approval from the faculty in
charge.

DOING EXPERIMENT:
▪ Start the experiment after getting permission from faculty members and do the
same by proper procedure.

OBSERVATION:
▪ Note all the required readings in their respective tables.
▪ Note all the waveforms from the CRO.

CALCULATION:
▪ Calculate the required quantities by suitable formulae and tabulate them with units.
▪ Draw the necessary graphs and write the result with reference.
▪ Get verification of observation and calculation from your staff in-charge.

RECORD:
▪ Enter the things in the record notebook those have been written in your
observation.
▪ Draw necessary graphs and complete the record before coming to the next lab
class.
▪ Write the inference of each experiment.

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 Category: PCC
U21ECG01 DIGITAL ELECTRONICS L T P J C
2 0 2 0 3

PRE–REQUISITES:
• NIL

COURSE OBJECTIVES:
• To understand the fundamentals of digital logic circuits
• To design the combinational logic circuits.
• To design the synchronous and asynchronous sequential circuits
COURSE OUTCOMES:
Upon completion of the course, the student will be able to
CO1: Apply various reduction methods to simplify logic expressions
CO2: Implement the combinational logic circuits using gates
CO3: Examine the performances of latches and flip-flops
CO4: Construct sequential logic circuits using flipflops
CO5: Design hazard free circuit for asynchronous sequential circuit

CO-PO MAPPING:

POs
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
COs

CO1 3 2 - 2 - - - 2 2 2 - 2 - 2
CO2 3 2 - 2 - - - 2 2 2 - 2 - 2
CO3 3 3 2 2 - - - 2 2 2 - 2 - 2
CO4 3 2 - 2 - - - 2 2 2 - 2 - 2
CO5 3 3 2 2 - - - 2 2 2 - 2 - 2
CO 3 2.4 2 2 - - - 2 2 2 - 2 - 2
Correlation levels: 1: Slight (Low) 2: Moderate 3: Substantial (High)
(Medium)

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 SYLLABUS:

UNIT I BOOLEAN THEOREMS AND LOGIC REDUCTION 6

Number system – Complements - Boolean theorems – Codes - Logic gates - NAND and
NOR gates – Representation of Boolean expression- SOP, POS, canonical form-
Simplification of logic functions using K-map, Quine McCluskey method
UNIT II COMBINATIONAL LOGIC DESIGN 6
Adder-1 Bit adder/subtractor, parallel adder,2’s complement adder/subtractor –
Implementation of combinational circuits – Multiplexers, decoders, encoders,
demultiplexers – Code converters – Error detection and correction codes – Parity generator
and checker
UNIT III LATCHES AND FLIPFLOPS 6
Latches – NOR, NAND – Digital pulses – Clocked flip-flops – Master/Slave flip-flop-
Asynchronous inputs – Flip-flop timing considerations –– Conversion of flip-flop
UNIT IV SEQUENTIAL CIRCUITS 6
General model of sequential circuits – Mealy/Moore models, excitation table, state table,
state diagram – Design of synchronous sequential circuits – Synchronous up/down counters,
modulus counters-Asynchronous counter-Sequence detector
UNIT V REGISTERS AND HAZARDS 6
Shift registers – Ring counter, Johnson counter– Hazards and Essential Hazards in logic
circuits - Design of Hazard free circuits
LIST OF EXPERIMENTS (INDICATIVE)
1. Characteristics of digital IC’s
2. Implementation of combinational logic design using MUX IC’s
3. Design and implementation of various data path elements (Adder/Subtractor)
4. Characteristics of flip-flop
5. Design and implementation of synchronous sequential circuit (Counters/ Shift registers)
6. Design and implementation of asynchronous mod counters

Contact Periods:

Lecture: 30 Periods Tutorial: – Periods Practical 30 Periods Project: – Periods

: Total: – 60 Periods
TEXT BOOKS:
1. M.Morris Mano, Michael D Ciletti, “Digital Design”, 6th edition, Pearson, 2018
2. Charles H. Roth, Jr, Larry L. Kinney” Fundamentals of logic design”,7th edition,
Kluwer Academic Publishers,2014

REFERENCES:

1. A.Anand Kumar, “Fundamentals of Digital Circuits”, 2nd edition, PHI Learning, 2013
2. Ronald J Tocci, Neal S Widmer, Gregory L Moss, “Digital Systems Principles
and Applications”, 10th edition, Pearson, 2009
3. Thomas L.Floyd, “Digital Fundamentals”, 11th edition, Prentice Hall, 2015
4. D. Donald Givone, “Digital Principles and Design”, 4th edition, Tata McGraw Hill, 2008

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 INDEX

EXP. PAGE
DATE NAME OF THE EXPERIMENT MARKS SIGNATURE
No. No.

1 Characteristics of digital IC’s

Design and Implementation of various data path elements (Adder / Subtractor)

2
a) Half and Full adder

b) Half and Full subtractor

Implementation of combinational logic design using gates

3
a) 4:1 Multiplexer and 1:4
Demultiplexer

4 Characteristics of flip flop

Design and Implementation of synchronous sequential circuits

5 a) Shift register

b) Counters

Design and Implementation of

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asynchronous MOD counters

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2- INPUTS OR GATE:

Pin Diagram Symbol Truth table

Inputs Output
U2A A B Y=A+B
A
Y 0 0 0
B
74LS32D 0 1 1
1 0 1
1 1 1

2- INPUTS and 3-INPUTS NAND GATE:

Pin Diagram Symbol Truth table

Inputs Output
A B Y=A.B
U3A
A 0 0 0
Y
B
74LS08D 0 1 0
1 0 0
1 1 1

Inputs Output
Y=[A.B
A B C
.C]’
U4A 0 0 0 1
A 0 0 1 1
B Y 0 1 0 1
C
74LS10D 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

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EX.NO : 01 CHARACTERISTICS OF DIGITAL IC’S
DATE :

AIM:

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY.

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-
OR are known as universal gates because all the basic gates can be derived from these gates.

OR GATE:
The OR Gate performs logical addition, commonly Known as OR Function. The OR gate
has two or more inputs and only one output. The operation of OR gate is such that a HIGH (1) on
the output is produced when any one of the inputs is HIGH (1). The output is LOW (0) only when
all the inputs are LOW (0).

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NOT GATE:
Pin Diagram Symbol Truth table

Input Output
U5A A Y = A’
0 1
A Y
1 0
74LS04N

2- INPUTS NAND GATE:

Pin Diagram Symbol Truth table

Inputs Output
A B Y=(A.B)’
U6A 0 0 1
A
Y
B 0 1 1
74LS00N 1 0 1
1 1 0

2- INPUTS NOR GATE:

Pin Diagram Symbol Truth table

Inputs Output
A B Y=(A+B)’
U7A 0 0 0
A
Y 0 1 0
B
74LS02N 1 0 0
1 1 1

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AND GATE:
The AND Gate performs logical multiplication, commonly known as AND function. The
AND gate has two or more inputs and a single output. The output of an AND gate is HIGH only
when all the inputs are HIGH. Even if any one of the inputs is LOW, the output will be LOW.

NOT GATE:
The NOT performs the basic logical function called inversion or complementation. The
purpose of this logic gate is to convert one logic to the opposite logic level. It has one input and
one output. When HIGH input is applied to an inverter, a LOW output appears at its output and
vice versa.

NAND GATE:
NAND gate is a contraction of the NOT-AND gates. It has two or more inputs and only one
output. When all the inputs are HIGH, the output is LOW. If any one or both the inputs are LOW,
then the output is HIGH. The NAND called as Universal Gate

NOR GATE:
NOR gate is a contraction of the NOT-OR gates. It has two or more inputs and only one
output. When all the inputs are LOW, the output is HIGH. If any one or both the inputs are HIGH,
then the output is LOW. The NOR called as Universal Gate

EX-OR GATE:
An Exclusive-OR gate is a gate with two or more inputs and one output. The output of a gate
is HIGH when odd numbers of HIGH inputs are applied. If Even number of HIGH inputs or all the
inputs are LOW the output will be LOW.

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2-INPUTS XOR GATE:

Pin Diagram Symbol Truth table

Inputs Output
A B Y
U8A
A 0 0 0
Y
B 0 1 1
74LS86N
1 0 1
1 1 0

2-INPUTS XNOR GATE:

Pin Diagram Symbol Truth table

Inputs Output
A B Y
U9A
A 0 0 1
Y
B
0 1 0
74LS266N
1 0 0
1 1 1

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PROCEDURE:
1. Connect the IC according to the Pin Configuration.
2. Pin 7 is connected to the ground
3. Pin 14 is Connected to VCC
4. Output is seen through LED, If LED glows, it represents logic 1, otherwise logic 0
5. Verify the outputs through truth table

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 VIVA –VOCE QUESTIONS
1 Define Digital System and give any one example

2. What is a Logic gate? List the basic logic gates

3. Which gates are called as the universal gates? What are its advantages?

4. Name the two forms of Boolean expression

5. List out the characteristics of Digital IC.

6. What is the difference between bit, nibble, byte and word?

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7. State the difference between digital signal and binary signal.

8. Given two X-OR gates, make one as a buffer and one as an inverter.

9. How 2-input NAND gate act as a Inverter?

10. What are the insides circuits of logic gates?

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RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

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HALF ADDER:

Truth table
Graphical representation:

Inputs Outputs
A B SUM CARRY

K-map:

Logic Circuit

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 DESIGN AND IMPLEMENTATION OF VARIOUS DATA PATH
EX.NO : 2 a)
ELEMENTS :
DATE : Half and Full adder

AIM:

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

THEORY:
HALF-ADDER:
The simplest combinational circuit, which performs the arithmetic addition of two binary
digits, is called a Half- adder. The half-adder has two inputs and two outputs. The two inputs are
two 1-bit numbers A and B, and the two outputs are Sum (S) of A and B and the Carry bit
denoted by C. From the truth table we can understand that the Sum output is 1 when either of
the inputs (A or B) is 1, or the carry outputs is 1 when both the inputs (A and B) are 1.

FULL –ADDER:
A half-adder has only two inputs and there is no provision to add a carry coming from the
lower order bits when multibit addition is addition is performed. For this purpose, a full-adder is
designed. A Full-adder is a combinational circuit that performs the arithmetic sum of three inputs
bits and produces a sum output and a carry.

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FULL ADDER:

Graphical representation: Truth table

Inputs Outputs
A B Cin SUM CARRY

K-map:

Logic Circuit

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It consists of three inputs and two outputs. The two input variables denoted by X (Augend bit)
and Y (Addend bit) represent the two significant bits to be added. The third input, Z , represents
the carry from the previous lower significant position. The outputs are designated by the symbols
S (for sum) and C (for Carry).

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

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 VIVA VOCE QUESTIONS

1. List the different types of adders

2. How do you execute full adder from half adder circuit? Draw the circuit

3. State difference between ripple carry adder and carry look ahead adder

4. Compare serial adder and parallel adder

5. Why carry look ahead adder faster than the ripple adder?

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6. Write any two applications of binary adder(s).

RESULT

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

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HALF SUBTRACTOR:

Graphical representation: Truth table

Inputs Outputs
A B Difference(D) Borrow (Q)

K-map:

Logic Circuit

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 DESIGN AND IMPLEMENTATION OF VARIOUS DATA PATH
EX.NO : 2 b)
ELEMENTS :
DATE : Half and Full Subtractor

AIM:

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

THEORY:
HALF-SUBTRACTOR:
The half subtractor is a combinational circuit which is used to perform subtraction of two
bits. It has two inputs, X (Minuend) and Y (Subtrahend) and two outputs D (difference) and B
(Borrow). From the truth table, it is clear that the difference output is 0 if X=Y and 1 if the X  Y; the
borrow output B is 1 whenever X<Y. If X is less than Y, then subtraction is done by borrowing from
the next higher order bit.

FULL SUBTRACTOR:
A full subtractor is a combinational circuit that performs subtraction involving three bits,
namely minuend bit, subtrahend bit and the borrow from the previous stage. It has three inputs, X
(minuend), Y (Subtrahend) and Z (borrow from the previous stage) and two outputs D (difference)
and B (borrow).

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FULL SUBTRACTOR:
Graphical representation: Truth table

Inputs Outputs
A B Cin Difference Borrow

K-map:

Logic Circuit

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PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

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 VIVA-VOCE QUESTIONS

1. How will you execute a full subtractor from a full adder?

2. Draw Half subtractor circuit using NAND gate

3. Draw Full subtractor circuit using NOR gate.

4. Construct full subtractor circuit through half subtractor circuit.

5. Write the importance of Adder/ Subtractor circuit in Microprocessor / Digital signal processor

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RESULT

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

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4×1 MULTIPLEXER:

Graphical representation: Truth table

Selection lines Output

S1 S0 Y

k-Map:

Logic circuit:

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EX.NO : 3 a) IMPLEMENTATION OF COMBINATIONAL LOGIC DESIGN USING
GATES :
DATE :
Multiplexer and Demultiplexer

AIM:

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QUANTITY.

1.
2.
3.
4.
5.

THEORY:
4 × 1 MULTIPLEXER:
The term multiplex means many into one. Multiplexing is the process of transmitting a large
number of information over a single line. A digital Multiplexer is a combinational circuit that selects
one digital information from several sources and transmits the selected information on a single
output line. A Multiplexer is also called a data selector since it selects one of many inputs and
steers the information to the output. The 4 to 1 mux has 4 input lines (D0-D3), a single output line
(Y) and two select lines (S1 and S2) to select one of the four input lines. From the truth table, a
logical expression for the output in terms of the data input and the select inputs.
The data output Y = Data input D0, if S1=0 and S2=0
Therefore Y=D0S1’S2 ’= D0 0’0’=D01.1=D0
Similarly Y=D1S1’S2; Y= D1 when S1=0 and S2=1
Y=D2S1S2’; Y =D2 when S1=1 and S2=0
Y= D3S1S2; Y =D3 when S1=1 and S2=1
If above the terms are ORed, then the final expression for the output is given by
Y = D0S1’S2 + D1S1’S2 + D2S1S2’+ D3S1S2

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1×4 DEMULTIPLEXER:
Graphical representation: Truth table

Selection lines Output

S1 S0 Y

k-Map:

Logic circuit:

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1 × 4 DEMULTIPLEXER:
The word Demultiplexer means one into many. DE multiplexing is the process of taking
information from one input and transmitting the same over one several outputs. A Demultiplexer is
logic circuit that receives information on a single input and transmits the same information over
one of several (2n) output lines. A 1 to 4 Demux has a single input (I), four outputs (D 0-D3) and two
select inputs (A and B). From the truth table, it is clear that the data input is connected to output
D0 when A=B=0 and the data input is connected to D1 when A=0 and B=1. Similarly, the data input
is connected to D2 and D3 when A=1and B=0 and when A=B=1, respectively.
Expression is given by:
D0 =IA’B’; D1=IA’B; D2=IAB’; D3=IAB

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

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 VIVA-VOCE QUESTIONS

1. What are the other names for Multiplexer and Demultiplexer

2. List the applications of Multiplexer and Demultiplexer

3. When 2×4 decoder circuit will act as 1×4 demultiplexer circuit?

4. How many number of selection lines are needed for design of 1*2n demultiplexer?

5. Distinguish between the two basic multiplexing techniques?

6. _____________component helped to demonstrate the operation of basic multiplexer principle

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RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

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44
EX.NO : 4 CHARACTERISTICS OF FLIP FLOPS
DATE :

AIM:

APPARATUS REQUIRED:
Sl.No. Component Specification Qty
1.

2.

3.

4.

5.

THEORY:
A flip flop is an electronic circuit with two stable states that can be used to store binary
data. The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers, communications,
and many other types of systems.
1) R-S flipflop
2) D flipflop
3) J-K flipflop
4) T flipflop

SR FLIP FLOP:

An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after
the inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The
set input causes the output of 0 and 1. The reset input causes the opposite to happen. Once the
outputs are established, the wiring of the circuit is maintained until S or R go high, or power is
turned off to the circuit.

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JK FLIP FLOP

Graphical representation Truth table / Characteristics table

Clock Inputs Output

J K

Logic circuit:

46
 JK FLIP FLOP:

The J-K flip-flop is perhaps the most widely used type of flip-flop. Its function is identical to
that of the S-R flip flop in the SET, RESET and HOLD conditions of operation. The difference is
that the J-K flip-flop does not have any invalid states. The logic symbol for the J-K flip-flop is
presented in Figure and its corresponding truth table is listed in Table. Notice that for J=1 and
K=1 the output toggles, that is to say that the output at time t is complemented at time t+1.

D FLIP FLOP:

The D flip-flop is widely used. It is also known as a data or delay flip-flop. The D flip- flop
captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge
of the clock). That captured value becomes the Q output. At other times, the output Q does not
change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

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D FLIP FLOP

Graphical representation Truth table / Characteristics table

Clock Input Output
D

Logic circuit:

T FLIP FLOP

Graphical representation Truth table / Characteristics table

Clock Input Output
T

Logic circuit:

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PROCEDURE

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

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 VIVA-VOCE QUESTIONS

1. State difference between Flip flop and Latch.

2. What are the applications of flip-flops?

3. What is race around condition in flip flop? How it is eliminated?

4. What are the various methods used for triggering flip-flops?

5. Distinguish between level-triggered flip flops and edge-triggered flip flops.

6. Why the flip flop is also called as Bi – stable Multi vibrator?

7. Which is the state of flip flops?

50
8. Which flip flop is called to be Universal flip-flop?

9. What are the logic gates used to realize flip flops and latches?

RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

51
SERIAL IN SERIAL OUT SHIFT REGISTER:

Circuit diagram

Truth table

Data
CLK QA QB QC QD
Input

52
EX.No. 5 a) DESIGN AND IMPLEMENTATION OF SYNCHRONOUS
SEQUENTIAL CIRCUITS:
Date:
Shift Registers

AIM:

APPARATUS REQUIRED:

S.No COMPONENT SPECIFICATION QUANTITY

1.

2.

3.

4.

THEORY:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output
of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which
causes the shift in the output of the flip flop. The simplest possible shift register is one that uses
only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register.
Each clock pulse shifts the content of register one bit position to right. Shift register are classified
into the following four types,
Serial-in Serial-out (SISO)
Serial-in Parallel-out (SIPO)
Parallel-in Serial-out (PISO)
Parallel-in Parallel-out (PIPO)
Serial-In Serial-Out (SISO):
This type of shift register accepts data serially, i.e., one bit at a time on a single input line.
It produces the stored information on its single output also in serial output also in serial form.
Data may be shifted left (form low to high order bits) using shift-left register or shifted right (from
high to low order bits) using shift-right register.

53
SERIAL IN PARALLEL OUT SHIFT REGISTER:

Circuit diagram

Truth table
CLK Serial in Serial out

54
Serial-In Parallel-Out (SIPO):
A serial-in, parallel-out shift register is similar to the serial-in, serial-out shift register in
that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin.
It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in,
parallel-out shift register converts data from serial format to parallel format.
Parallel-In Serial-Out (PISO):
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to
parallel-out one above. The data is loaded into the register in a parallel format in which all the
data bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The
data is then read out sequentially in the normal shift-right mode from the register at Q
representing the data present at PA to PD.
Parallel-In Parallel-Out (PIPO):
The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of
shift register also acts as a temporary storage device or as a time delay device similar to the
SISO configuration above. The data is presented in a parallel format to the parallel input pins PA
to PD and then transferred together directly to their respective output pins QA to QD by the
same clock pulse.

Shift register Operation

The data is shifted serially “IN” and “OUT” of the register,
Serial-in to Serial-out (SISO) one bit at a time in either a left or right direction under
clock control.
The register is loaded with serial data, one bit at a time,
Serial-in to Parallel-out (SIPO) with the stored data being available at the output in
parallel form.
The parallel data is loaded into the register
Parallel-in to Serial-out (PISO) simultaneously and is shifted out of the register serially
one bit at a time under clock control.
The parallel data is loaded simultaneously into the
Parallel-in to Parallel-out
register, and transferred together to their respective
(PIPO)
outputs by the same clock pulse.

55
PARALLEL IN SERIAL OUT SHIFT REGISTER:

Circuit diagram

Truth table

CLK DATA Q3 Q2 Q1 Q0

56
PROCEDURE:
1. Connect the circuit as per the circuit diagram and pin configuration of the ICs.
2. Clear all the flip-flops by applying a high signal to the clear (reset) input.
3. Feed the data into the Serial mode or parallel mode depends upon the circuit operation.
4. Observe the output through LED’s and it’s verified with the help of Truth tables.

PIN DIAGRAM:

57
PARALLEL IN PARALLEL OUT SHIFT REGISTER:

Circuit diagram

Truth table

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

58
 VIVA VOCE QUESTIONS
1. Which is the basic element to construct a shift register?

2. Compare SISO and PIPO.

3. Describe the different methods of data transfer from the input to the output in the shift register.

4. Which type of flip flop is used in the shift register in order to avoid timing problems?

5. What is universal shift register?

6. What are the three different shift operation of universal shift register?

7. What are the applications of shift register / universal shift registers?

59
60
RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty signature with date

61
STATE DIAGRAM FOR SYNCHRONOUS UP/DOWN COUNTER:

TRUTH TABLE:

Input Present State Next State A B C

Up /Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

62
 EX.No. 5 b) DESIGN AND IMPLEMENTATION OF SYNCHRONOUS
SEQUENTIAL CIRCUITS:
Date:
Counter

AIM:

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QUANTITY

1.
2.
3.
4.
5.
6.
7.

THEORY:
SYNCHRONOUS COUNTER (UP/DOWN COUNTER):

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable
of progressing in increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of the counter is controlled
by up/down signal. When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.

63
K MAP:

LOGIC DIAGRAM FOR SYNCHRONOUS UP/DOWN COUNTER:

CHARACTERISTICS TABLE FOR JK FLIPFLOP:

Q Qt+1 J K

64
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

PIN DIAGRAM FOR IC 7476:

65
 VIVA-VOCE QUESTIONS

1. Compare Shift register and Counter

2. How many numbers of flip flops are required for designing of MOD-8 counter?

3. Define state , state diagram & State assignment

4. What are the applications of counters?

5. What are the advantages of synchronous counter?

6. Which type of flip flop is used for the construction of the ring counter?

7. Describe the three advantages of ring counter as compared to ripple counter.

66
RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

67
4-Bit Asynchronous up Counter
Logic Circuit:

68
EX.No. 6 DESIGN AND IMPLEMENTATION ASYNCHRONOUS
COUNTERS
Date:

AIM:

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QUANTITY

1.
2.
3.
4.
5.
6.
7.

THEORY:
Asynchronous counter
The term asynchronous refers to events that do not occur at the same time. With respect to
counter operation, asynchronous means that the flip-flops within the counter are not connected in a
way to cause all flip-flops at exactly the same time. They are wired in a way that links the clock of
the next flip-flop to the Q of the current device. This causes the output count states to the ripple
through the counter. A counter is a circuit that produces a set of unique output combinations
corresponding to the number of applied input pulses. The number of unique outputs of a counter is
known as its modulus or mod number. Each flip flop is triggered by the output from the previous flip
flop expect for the first flip flop (LSB) which receives an external clock. Asynchronous counters are
commonly referred to as ripple counters because the effect of the input clock pulse is first felt by
FF0.This effect cannot get to FF1 immediately because of the propagation delay through FF0.
4 bit asynchronous up-counter
An asynchronous 4 bit binary up counter, a circuit made up of 4 J-K flip-flop cascaded to
generate four bits counting sequence. An up counter is basically a digital counting circuit which
counts up in an incremental mode.

69
4-Bit Asynchronous down Counter
Logic Circuit:

70
4 bit asynchronous down-counter
An asynchronous 4-bit binary up counter, a circuit made up of 4 J-K flip-flop cascaded to
generate four bits counting sequence. A down counter is basically a digital counting circuit which
counts down in a detrimental mode

PROCEDURE
1. Place the IC on IC Trainer Kit.
2. Connect VCC and ground to respective pins of IC Trainer Kit.
3. Connect the inputs to the input switches provided in the IC Trainer Kit.
4. Connect the outputs to the switches of output LEDs
5. Apply various combinations of inputs according to the truth table and observe condition of LEDs

71
MOD-10 Asynchronous Counter
Logic Circuit:

An MOD-10 asynchronous counter, a circuit made up of combinational logic and 4 J-K flip-flop
cascaded to generate four bits counting sequence. An MOD-10 counter is basically a digital
counting circuit which counts 10 states from 0.

72
 VIVA VOCE QUESTIONS

1. How Synchronous counters eliminate the delay problems encountered with asynchronous
counters?

2. What are the deference between synchronous counter and asynchronous counters?

3. What changes must be made to a 3-bit counter to make it a 4-bit counter?

4. What is the major drawback of asynchronous counter?

5. What is the other name of Asynchronous counter?

6. What is the maximum counting state of asynchronous counter?

7. Why the asynchronous counter is also called as ripple counter?

8. Why the synchronous counter is faster than the asynchronous counter?

73
RESULT:

PERFORMANCE POINTS (1-4)

INDICATOR
C1. Preparation
C2. Observation
C3. Results
C4. Interpretation
C5. Viva-voce
Total Marks (20)
Faculty Signature with date

74