EE1572 Microprocessors and Microcontrollers Unit I 8085 Processor

UNIT I - 8085 PROCESSOR

Syllabus: Hardware Architecture, pinouts – Functional Building Blocks of Processor – Memory
organization – I/O ports and data transfer concepts– Interrupts.

1.1 Pin Diagram | Functional Pin Diagram of 8085 Microprocessor:

Fig. (a) and (b) shows 8085 Pin Diagram and functional pin diagram of 8085 microprocessor
respectively. The signals of 8085 Pin Diagram can be classified into seven groups according to
their functions.
1. Power supply and frequency signals.
2. Data bus and address bus
3. Control bus
4. Interrupt signals
5. Serial I/O signals
6. DMA signals
7. Reset signals

1. Power Supply and Frequency Signals:

 Vcc : It requires a single +5 V power supply.
 Vss : Ground reference.
 X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two The internal clock
generator divides oscillator frequency by 2, therefore, to operate a system at 3 MHz, the crystal
of tuned circuit must have a frequency of 6 MHz.
 CLK OUT : This signal is used as a system clock for other devices. Its frequency is half
the oscillator frequency.

2. Data Bus and Address Bus:

A) AD0 to AD7 : The 8 bit data bus (D0 – D7) is multiplexed with the lower half (A0 – A7)
of the 16 bit address bus. During first part of the machine cycle (T1), lower 8 bits of memory
address or I/O address appear on the bus. During remaining part of the machine cycle (T2 and T3)
these lines are used as a bi-directional data bus.
B) A8 to A15 : The upper half of the 16 bit address appears on the address lines A8 to A15.
These lines are exclusively used for the most significant 8 bits of the 16 bit address lines.

3. Control and Status Signals:

A) ALE (Address Latch Enable) : We, know that AD0 to AD7 lines are multiplexed and
the lower half of address (A0 – A7) is available only during T1 of the machine cycle. This lower
half of address is also necessary during T2 and T3 of machine cycle to access specific location in
memory or I/O port. This means that the lower half of an address must be latched in T 1 of the
machine cycle, so that it is available throughout the machine cycle. The latching of lower half of
an address bus is done by using external latch and ALE signal from 8085 Pin Diagram.
B) RD and WR : These signals are basically used to control the direction of the data flow
between processor and memory or I/O device/port. A low on RD indicates that the data must be
read from the selected memory location or I/O port via data bus. A low on WR indicates that the
data must be written into the selected memory location or I/O port via data bus.

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C) IO/M, S0 and S1 : IO/M indicates whether I/O operation or memory operation is being
carried out. S1 and S0 indicate the type of machine cycle in progress.
D) READY : It is used by the microprocessor to sense whether a peripheral is ready or not for data
transfer. If not, the processor waits. It is thus used to synchronize slower peripherals to the
microprocessor.

4. Interrupt Signals:
The 8085 Pin Diagram has five hardware interrupt signals: RST 5.5, RST 6.5, RST 7.5,
TRAP and INTR. The microprocessor recognises interrupt requests on these lines at the end of the
current instruction execution.
The INTA (Interrupt Acknowledge) signal is used to indicate that the processor has acknowledged
an INTR interrupt.

5. Serial I/O Signals:

A) SID (Serial I/P Data) : This input signal is used to accept serial data bit by bit from the
external device.

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B) SOD (Serial O/P Data) : This is an output signal which enables the transmission of serial data
bit by bit to the external device.

6. DMA Signal:
A) HOLD : This signal indicates that another master is requesting for the use of address
bus, data bus and control bus.
B) HLDA : This active high signal is used to acknowledge HOLD request.

7. Reset Signals:
A) RESET IN : A low on this pin
 Sets the program counter to zero (0000H).
 Resets the interrupt enable and HLDA flip-flops.
 Tri-states the data bus, address bus and control bus. (Note : Only during RESET is active).
 Affects the contents of processor’s internal registers randomly.
On reset, the PC sets to 0000H which causes the 8085 Pin Diagram to execute the first
instruction from address 0000H. For proper reset operation reset signal must be held low for at
least 3 clock cycles. The power-on reset circuit can be used to ensure execution of first instruction
from address 0000H.
B) RESET OUT : This active high signal indicates that processor is being reset. This
signal is synchronized to the processor clock and it can be used to reset other devices connected in
the system.

1.2 Hardware Architecture of 8085 Microprocessor

Control Unit:
Generates signals within Microprocessor to carry out the instruction, which has been
decoded. In reality causes certain connections between blocks of the µP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit:

The ALU performs the actual numerical and logic operation such as add, subtract, AND,
OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores
result of operation in Accumulator.

Registers:
The 8085/8080A-programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the
program counter. The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B, C, D, E, H, and L as shown in the figure. They can be combined as register pairs -
BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to
store or copy data into the registers by using data copy instructions.

Accumulator:
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The result of
an operation is stored in the accumulator. The accumulator is also identified as register A.

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Architecture of 8085
Flags:
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero (Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are
Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger than
eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When
an arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is set to one. The first
Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is
not used as a register; five bit positions out of eight are used to store the outputs of the five flip-
flops. The flags are stored in the 8-bit register so that the programmer can examine these flags
(data conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor.
The conditions (set or reset) of the flags are tested through the software instructions. For example,
the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY
flag is set.

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Program Counter (PC):

This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a16-bit register.
The microprocessor uses this register to sequence the execution of the instructions. The function
of the program counter is to point to the memory address from which the next byte is to be fetched.
When a byte (machine code) is being fetched, the program counter is incremented by one to point
to the next memory location

Stack Pointer (SP):

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading 16- bit
address in the stack pointer.

Instruction Register/Decoder:
Temporary store for the current instruction of a program. Latest instruction sent here from
memory prior to execution. Decoder then takes instruction and „decodes‟ or interprets the
instruction. Decoded instruction then passed to next stage.

Memory Address Register:

Holds address, received from PC, of next program instruction. Feeds the address bus with
addresses of location of the program under execution.

Control Generator:
Generates signals within µ P to carry out the instruction which has been decoded. In reality
causes certain connections between blocks of the µP to be opened or closed, so that data goes
where it is required, and so that ALU operations occur.

Register Selector:
This block controls the use of the register stack in the example. Just a logic circuit which
switches between different registers in the set will receive instructions from Control Unit.

1.3.1 Memory organization of 8085 microprocessor

The 8085 microprocessor-based system requires both EPROM and RAM. Hence, the
available memory space has to be divided between EPROM and RAM. The 8085 has 64 kb of
addressable memory space and allotting this address space for EPROM and RAM depends on the
system designer as well as on the application for which the system is designed.
In an 8085 system, the EPROM is mapped at the beginning of memory space. (i.e., 0000H
address is allotted to the EPROM memory location). Whenever the power supply is switched ON,
the microprocessor chip will be resetted. This power-on reset will be implemented by the system
designer. When the processor is resetted all the internal registers, the flag register and the program
counter will be cleared. Hence after a reset, the program counter will have an address 0000H and
so the processor starts fetching and executing the instruction stored at 0000H.
The system designer will store the monitor program starting from the address 0000H. The
monitor program should be executed to initialize the system peripherals, whenever the system is
switched ON. To enable automatic execution of the monitor program, whenever the system is
switched ON, the EPROM should be mapped from the 0000H location in an 8085-based system.

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The monitor program is a permanent program written by the system designer to take care
of system initialization. System initialization includes the following :
1. Programming the 8279 for keyboard scanning and display refreshing.
2. Programming peripheral ICs 8259, 8257, 8255, 8251, 8254, etc.
3. Initializing stack.
4. Display a message on the LED's.
5. Initializing the interrupt vector table.

1. Implementing 64kb EPROM in 8085 system

Consider a system in which the full memory space 64 kb is utilized for the EPROM
memory. In this system, the entire 16 address lines of the processor are connected to the address
input pins of the memory IC in order to address the internal locations of the memory and the Chip
Select (CS) pin of the EPROM is permanently tied to logic low (i.e., tied to ground) as shown in
Fig. Now the range of address for EPROM is 0000H to FFFFH.

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2. Implementing 32kb EPROM and 32kb RAM in 8085 system

Consider a system in which the available 64 kb memory space is equally divided between
the EPROM and the RAM. Let us implement 32 kb memory capacity of EPROM using a single
IC 27256. Similarly, 32 kb RAM capacity is implemented using a single IC 62256. A 32 kb
memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected
to 15 address pins of both EPROM and RAM, as shown in Fig. The unused address line A15 is
used as chip select signal for selecting either EPROM or RAM. The A15 is directly connected to
the CS pin of the EPROM and it is inverted and connected to the CS pin of the RAM. Therefore,
the EPROM is selected when A15 = 0 and RAM is selected when A15 = 1. The address range of
EPROM will be 0000H to 7FFFH and that of RAM will be 8000H to FFFFH.

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3. Implementing 16kb EPROM and 16kb RAM in 8085 system

Consider a system in which 32 kb memory space is implemented using four numbers of 8
kb memory. Let two numbers of 8 kb memory be EPROM and the remaining two numbers be
RAM. Each 8 kb memory requires 13 address lines and so the address lines A0 - A12 of the
processor are connected to 13 address pins of all the memory ICs. The address lines A13 and A14
can be decoded using a 2-to-4 decoder to generate four chip select signals. These four chip select
signals can be used to select one of the four memory IC at any one time. The address line A15 is
used as enable for the decoder.

The simplified schematic of this memory organization is shown in Fig. and the addresses
allotted to each memory IC are shown in Table.

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4. Implementing 64kb memory space using 8 x 8kb in 8085 system. Consider 3

numbers of EPROM and 5 numbers of RAM:
Consider a system in which the 64 kb memory space is implemented using eight numbers
of 8 kb memory. Each 8 kb memory requires 13 address lines and so the address lines A0-A12 of
the processor are connected to 13 address pins of all the memory ICs. The address lines A13, A14
and A15 are decoded using a 3-to-8 decoder to generate eight chip select signals. These eight chip
select signals can be used to select one of the eight memory ICs at any one time.

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The 8 kb EPROM IC requires 13 address lines (213 = 8 k). The 8 kb RAM IC requires 13
address lines (213 = 8 k). The address lines A0 - A12 are connected to all the EPROMs and RAMs.
Hence, A0 - A12 will select the required memory location. The address lines A13, A14 and A15
are not used for memory address. Hence by decoding these address lines we can generate chip
select signals.
The 3-to-8 decoder, 74LS138 is employed to produce the chip-select signals for the system.
The decoder has 8-output lines which can be used as 8-chip select signals. All the 8-chip select
signals are used to select memory ICs. EPROM's are mapped at the beginning of memory space.
The decoder will select a memory IC by decoding the address lines A13, A14 and A15. The address
lines A0 - A12 will select a particular memory location in the selected IC.
In this system the full memory capacity of 64 kb is utilized for memory. Hence the
peripheral ICs and the IO ports should be IO-mapped in the system. The EPROM is mapped from

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0000H to 5FFFH. The RAM is mapped from 6000H to FFFFH. The EPROM capacity is 24 kb.
The RAM capacity is 40 kb.

1.3.2 Bus organization of 8085 microprocessor

Bus is a group of conducting wires which carries information, all the peripherals are
connected to microprocessor through Bus.

There are three types of buses.

1. Address bus:
It is a group of conducting wires which carries address only. Address bus is
unidirectional because data flow in one direction, from microprocessor to memory or from
microprocessor to Input/output devices (That is, Out of Microprocessor). Length of
Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal Digits), ranging
from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor 8085 can transfer
maximum 16 bit address which means it can address 65, 536 different memory location.

The Length of the address bus determines the amount of memory a system can address.
Such as a system with a 32-bit address bus can address 2^32 memory locations. If each memory
location holds one byte, the addressable memory space is 4 GB. However, the actual amount of
memory that can be accessed is usually much less than this theoretical limit due to chipset and
motherboard limitations.

2. Data bus:
It is a group of conducting wires which carries Data only. Data bus is bidirectional
because data flow in both directions, from microprocessor to memory or Input/Output
devices and from memory or Input/Output devices to microprocessor. Length of Data Bus
of 8085 microprocessor is 8 Bit (That is, two Hexadecimal Digits), ranging from 00 H to
FF H. (H denotes Hexadecimal). When it is write operation, the processor will put the data
(to be written) on the data bus, when it is read operation, the memory controller will get
the data from specific memory block and put it into the data bus. The width of the data bus
is directly related to the largest number that the bus can carry, such as an 8 bit bus can

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represent 2 to the power of 8 unique values, this equates to the number 0 to 255.A 16 bit
bus can carry 0 to 65535.

3. Control bus:
It is a group of conducting wires, which is used to generate timing and control
signals to control all the associated peripherals, microprocessor uses control bus to process
data, that is what to do with selected memory location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line.If the wire is low (no electricity
flowing) then the memory is read, if the wire is high (electricity is flowing) then the
memory is written.

1.4 I/O Ports and Data Transfer Concepts

IO Mapping:
The port and peripheral devices will have one logic low/high chip select pin. The processor
can access the port/peripheral device by supplying the internal address and chip select signal.
Therefore, the port and peripheral device interfacing (IO interfacing) deals with the allocation of
various internal addresses and generation of chip select signals.
There are two ways of interfacing IO devices in a microprocessor/microcontroller-based
system:
1. Memory-mapped IO device.
2. Standard IO-mapped IO device or Isolated IO mapping.

The 8085 microprocessor supports both memory-mapped IO and IO-mapped IO. The
8031/8051 microcontroller supports only memory-mapped IO. Hence in a 8031/8051-based
system, some of the memory addresses should be reserved for IO devices, and in these systems the
IO devices are interfaced similar to that of memory devices.

IO mapping in 8085-based system:

The two methods of interfacing IO devices in an 8085-based system are: Memory mapping
of IO device and Standard IO mapping of IO device or Isolated IO mapping. In memory mapping
of IO devices the ports are allotted a 16-bit address like that of memory location. Some of the chip-
select signals generated to select memory ICs are used for selecting the IO port devices. Hence,
the processor treats the IO ports as memory locations for reading and writing (i.e., the devices
which are mapped by memory mapping are accessed by executing the memory read cycle or the
memory write cycle.)
In standard IO mapping or isolated IO mapping, a separate 8-bit address is allotted for
IO ports and the peripheral ICs. The processor differentiates the IO-mapped devices from the
memory-mapped devices in the following ways:

1. For accessing the IO-mapped devices, the processor executes the IO read or write cycle.

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2. During IO read or write cycle, the 8-bit address is placed on both low order address lines and
the high order address lines.
3. IO/M is asserted high to indicate the IO operation (for read as well as write).

A 8085 processor does not provide separate read (RD) and write (WR) signals for memory
and IO devices. But it differentiates the memory and IO device accessed by an IO/M signal. The
three signals RD, WR and IO/M can be decoded as shown in Fig. 6.21 to provide separate read
and write control signals for IO devices and memory devices.

When the devices are IO-mapped, then only the IN and OUT instructions have to be used
for data transfer between the device and the processor. For IO-mapped devices, a separate decoder
should be used to generate the required chip select signals.

Comparison of Memory Mapping and I/O Mapping of I/O Devices in an 8085-Based System

Memory-Mapped I/O Interfacing I/O Mapped I/O Interfacing

The I/O devices and memory, both are treated as The I/O devices are treated as I/O devices and
memory. the memory is treated as memory.
The I/O devices are provided with 16-bit address The I/O devices are provided with 8-bit
values (in 8085) address values. (In 8085)
The interfaced devices are accessed by the The interfaced devices are accessed by the I/O
memory read or memory write cycles. read or I/O write cycles.
The peripherals or the I/O ports are treated as Only the IN and the OUT instructions can be
memory locations. Thus, all the instructions put to use for transferring information
related to the memory can be utilized for the data between the I/O device and the processor.
exchange between the processor and the I/O
device.

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In the memory-mapped ports, the information In the I/O mapped ports, the information bytes
data can be moved to the I/O devices from any can be moved around between the ports and
register or vice versa. the accumulator register only.
The full memory address space cannot be used The full memory address space can be used
solely for addressing memory for interfacing. solely for addressing memory for interfacing.
Data transfer is possible between any register and Data transfer is possible between the
I/O device. accumulator and I/O device only.
Here, a large number of I/O ports (216 ports) are Only 256 I/O ports i.e., 28 ports, are made
possible to be used for interfacing. available for interfacing.
While executing the memory, write or read While executing the I/O write or read cycles,
cycles, the IO/M` is set to low (IO/M` = 0 ). the IO/M` is set to high (IO/M` = 1 ).
There is more decoder hardware involved. There is less decoder hardware involved.
Separate control signals are not required since we Special control signals are used here since we
have a unified memory space. have separate memory spaces.
We can perform arithmetic and logical We cannot perform arithmetic and logical
operations on the data. operations on the data.

Data Transfer Concepts

1. Parallel data transfer
2. Serial data transfer

1. Parallel data transfer

 Programmed I/O
 Interrupt I/O
 DMA

Programmed I/O:
Here the processor has to check whether the I/O device is ready or not through the Ready
signal of the I/O device. If the ready signal is high then it will send the data to the I/O device.
Otherwise it will continuously check the Ready signal. The processor is busy in checking the
Ready signal. The drawback is wastage of time.

Interrupt I/O:
In this method the I/O device will interrupt the Processor through the INTR signal to
indicate to the processor that it is ready to accept the next data. Then the processor will send the
INTA signal. Then the processor stops its normal execution and start transferring the data to the
I/O device.

DMA:
Using DMA I/O device can directly transfer the data to the Memory using the Address and
Data buses of Processor.

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2. Serial data Transfer

Some of the external I/0 devices receive only the serial data. Normally serial communication
is used in the MultiProcessor environment. 8051 has two pins for serial communication.
 SID- Serial Input data.
 SOD-Serial Output data.

1.5 Interrupts in 8085 microprocessor

When microprocessor receives any interrupt signal from peripheral(s) which are requesting
its services, it stops its current execution and program control is transferred to a sub-routine by
generating CALL signal and after executing sub-routine by generating RET signal again program
control is transferred to main program from where it had stopped. When microprocessor receives
interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is requesting for
its service.
Interrupts can be classified into various categories based on different parameters:

1. Hardware and Software Interrupts:

When microprocessors receive interrupt signals through pins (hardware) of microprocessor,
they are known as Hardware Interrupts. There are 5 Hardware Interrupts in 8085
microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.

Software Interrupts are those which are inserted in between the program which means these
are mnemonics of microprocessor. There are 8 software interrupts in 8085 microprocessor.
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

2. Vectored and Non-Vectored Interrupts:

Vectored Interrupts are those which have fixed vector address (starting address of sub-
routine) and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H

3. For Software interrupts vector addresses are given by:

INTERRUPT VECTOR ADDRESS

RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H

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RST 5 28 H
RST 6 30 H
RST 7 38 H
4. Non-Vectored Interrupts:
Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting
device gives the address of sub-routine for these interrupts. INTR is the only non-vectored
interrupt in 8085 microprocessor.

5. Maskable and Non-Maskable Interrupts:

Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These
interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST
7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge
triggering and is used in critical power failure conditions.

6. Priority of Interrupts:
When microprocessor receives multiple interrupt requests simultaneously, it will execute the
interrupt service request (ISR) according to the priority of the interrupts. They are TRAP,
RST 7.5, RST 6.5, RST 5.5 and INTR. So, TRAP is the highest priority interrupt signal and
INTR is the least priority interrupt signal.

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