UNIT-2

MEMORY & COMMUNICATION INTERFACES

MEMORY:

Memory is an important part of an embedded system. The memory used in embedded system
can be either Program Storage Memory (ROM) or Data memory (RAM)
 Certain Embedded processors/controllers contain built in program memory and data
memory and this memory is known as on-chip memory
 Certain Embedded processors/controllers do not contain sufficient memory inside the
chip and requires external memory called off-chip memory or external memory.

Memory – Program Storage Memory:

The program memory or code memory of an embedded system stores the program instructions

 Retains its contents even after the power to it is turned off. It is generally known as
Nonvolatile storage memory
 Depending on the fabrication, erasing and programming techniques they are classified
into

Masked ROM (MROM)

Masked ROM is a one-time programmable memory.

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  Uses hardwired technology for storing data.
 The device is factory programmed by masking and metallization process according to
the data provided by the end user.
 The primary advantage of MROM is low cost for high volume production.
 MROM is the least expensive type of solid-state memory.
Different mechanisms are used for the masking process of the ROM, like

 Creation of an enhancement or depletion mode transistor through channel implant

 By creating the memory cell either using a standard transistor or a high threshold
transistor. In the high threshold mode, the supply voltage required to turn ON the
transistor is above the normal ROM IC operating voltage. This ensures that the
transistor is always off and the memory cell stores always logic 0.
The limitation with MROM based firmware storage is the inability to modify the device
firmware against firmware upgrades.
The MROM is permanent in bit storage, it is not possible to alter the bit information

Programmable Read Only Memory (PROM) / (OTP)

• It is not pre-programmed by the manufacturer

• The end user is responsible for Programming these devices.

• PROM/OTP has nichrome or polysilicon wires arranged in a matrix; these wires can be
functionally viewed as fuses.
• It is programmed by a PROM programmer which selectively burns the fuses according to
the bit pattern to be stored.
• Fuses which are not blown/burned represents a logic “1” whereas fuses which are
blown/burned represents a logic “0”. The default state is logic “1”.
• OTP is widely used for commercial production of embedded systems whose proto-typed
versions are proven and the code is finalized.
• It is a low-cost solution for commercial production.

• OTPs cannot be reprogrammed.

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Erasable Programmable Read Only Memory (EPROM):

• Erasable Programmable Read Only (EPROM) memory gives the flexibility to re-program
the same chip.
• During development phase, code is subject to continuous changes and using an OTP is not
economical.
• EPROM stores the bit information by charging the floating gate of an FET

• Bit information is stored by using an EPROM Programmer, which applies high voltage to
charge the floating gate
• EPROM contains a quartz crystal window for erasing the stored information. If the window
is exposed to Ultra violet rays for a fixed duration, the entire memory will be erased Even
though the EPROM chip is flexible in terms of re-programmability, it needs to be taken out
of the circuit board and needs to be put in a UV eraser device for 20 to 30 minutes

Electrically Erasable Programmable Read Only Memory (EEPROM):

• Erasable Programmable Read Only (EPROM) memory gives the flexibility to re-program
the same chip using electrical signals
• The information contained in the EEPROM memory can be altered by using electrical
signals at the register/Byte level
• They can be erased and reprogrammed within the circuit

• These chips include a chip erase mode and in this mode they can be erased in a few
milliseconds
• It provides greater flexibility for system design

• The only limitation is their capacity is limited when compared with the standard ROM (A
few kilobytes).

Program Storage Memory – FLASH

• FLASH memory is a variation of EEPROM technology.

• FALSH is the latest ROM technology and is the most popular ROM technology used in
today’s embedded designs
• It combines the re-programmability of EEPROM and the high capacity of standard ROMs

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• FLASH memory is organized as sectors (blocks) or pages

• FLASH memory stores information in an array of floating gate MOSFET transistors

• The erasing of memory can be done at sector level or page level without affecting the other
sectors or pages
• Each sector/page should be erased before re-programming

• The typical erasable capacity of FLASH is of the order of a few 1000 cycles.

Read-Write Memory/Random Access Memory (RAM)

• RAM is the data memory or working memory of the controller/processor

• RAM is volatile, meaning when the power is turned off, all the contents are destroyed

• RAM is a direct access memory, meaning we can access the desired memory location
directly without the need for traversing through the entire memory locations to reach the
desired memory position (i.e. Random Access of memory location)

Static RAM (SRAM):

• Static RAM stores data in the form of Voltage.

• They are made up of flip-flops

• In typical implementation, an SRAM cell (bit) is realized using 6 transistors (or 6

MOSFETs).
• Four of the transistors are used for building the latch (flip-flop) part of the memory cell and
2 for controlling the access.
• Static RAM is the fastest form of RAM available

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• SRAM is fast in operation due to its resistive networking and switching capabilities

• In its simplest representation an SRAM cell can be visualised as shown below:

This implementation in its simpler form can be visualised as two- cross coupled inverters with
read/write control through transistors. The four transistors in the middle form the cross-
coupled inverters.

From the SRAM implementation diagram, it is clear that access to the memory cell is controlled
by the line Word Line, which controls access transistors Q5 and Q6. It controls the connection
to bit lines B and B\.

In order to write a value to the memory cell, apply the desired value to the bit control lines

For writing 1, make B=1 and B\=0

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 For writing 0, make B=0 and B\=1

For reading, make B=1 and B\=1

The major limitations of SRAM are low capacity and high cost.

Dynamic RAM (DRAM)

• Dynamic RAM stores data in the form of charge. They are made up of MOS transistor gates

• The advantages of DRAM are its high density and low cost compared to SRAM

• The disadvantage is that since the information is stored as charge it gets leaked off with
time and to prevent this, they need to be refreshed periodically
• Special circuits called DRAM controllers are used for the refreshing operation. The refresh
operation is done periodically in milliseconds interval.

The MOSFET acts as the gate for the incoming and the outgoing data whereas the capacitor
acts as the bit storage unit.

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Non-Volatile RAM (NVRAM)

• Random access memory with battery backup

• It contains Static RAM based memory and a minute battery for providing supply to the
memory in the absence of external power supply
• The memory and battery are packed together in a single package

• NVRAM is used for the nonvolatile storage of results of operations or for setting up of
flags etc.

• The life span of NVRAM is expected to be around 10 years

DS1744 from Maxim/Dallas is an example for 32KB NVRAM

Difference between SRAM cell and DRAM cell

SRAM Cell DRAM Cell

Made up of 6 CMOS transistors (MOSFET) Made up of a MOSFET and a capacitor

Doesn’t Require refreshing Requires refreshing
Low capacity (Less dense) High Capacity (Highly dense)
More expensive Less Expensive
Fast in operation. Typical access time is 10ns Slow in operation due to refresh requirements.
Typical access time is 60ns.
Write operation is faster than read operation.

Memory According To The Type Of Interface

• The interface of memory with processor/controller may be serial, parallel.
• Parallel interfaces were used in earlier computers for connecting peripherals.
• Serial interface is commonly used for data memory like EEPROM.
• The memory density of a serial memory interface is expressed kilobits, whereas that of
a parallel memory interface is expressed in kilobytes.

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Memory Shadowing
A RAM access is 3 times as fast as ROM access. So, if program is stored in RAM, it gives
high execution speed. But RAM is volatile. i.e., its contents are lost if power supply is OFF.
On the other hand, a ROM is non-volatile memory. Its stored contents are permanent. But it
gives low execution speed. Memory shadowing technique resolves this execution speed
problem.
In computer systems (e.g., PCs) and video systems, a configuration called BIOS (Basic Input
Output System) is used to hold ROM. This information is required during boot up. Since it is
stored in ROM, it is time-consuming.
Now, manufacturers use Memory shadowing. They put a RAM behind the logical layer of
BIOS. This RAM acts as a shadow to the BIOS. While booting, BIOS is copied to shadow
RAM, write-protected and the BIOS reading operation is disabled.
Thus, information is accessed from RAM instead of from ROM.

Memory Selection For Embedded System

Selection of RAM and ROM depends on the type of ES and the application. Important factors
while selecting the RAM and ROM are: -
Need for external memory: We need to check whether the on-chip memory is sufficient or
external memory is required. Then we should estimate the memory required.
Examples:
1. A Windows mobile device needs 64 MB RAM and 128 MB ROM
2. In small applications (toys), a microcontroller with less data memory, i.e., a few
bytes of internal RAM, Flash and EEPROM (if necessary), are needed. We don’t
need external memory.
Memory size: Memory chips come in standard sizes like 512 bytes, 1024 bytes (1 kilobyte),
2048 bytes (2 kilobytes), 4 Kb, 8 Kb, 16 Kb, 32 Kb, 64 Kb, 128 Kb, 256 Kb, 1024 Kb (1
megabyte), etc. If an ES needs 20 Kb, we have to go for 32 Kb, but not 16 Kb.
(i) Address range supported by the processor: A processor with 16-bit address bus can
address a maximum of 216 (= 64 Kb) memory locations. Hence it is meaning less to
select a 128 Kb memory chip.
(ii) Word size of the memory: Word size is the number of bits that can be read/written
together at a time. 4, 8, 12, 16, 24, 32, etc., are the word sizes supported by memory

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 chips. Word size supported by the memory chip should match with the width of the data
bus of the processor/controller.

SENSORS & ACTUATORS

• Embedded system is in constant interaction with the real world

• Controlling/monitoring functions executed by the embedded system is achieved in

accordance with the changes happening to the Real World.
• The changes in the system environment or variables are detected by the sensors connected
to the input port of the embedded system.
• If the embedded system is designed for any controlling purpose, the system will produce
some changes in controlling variable to bring the controlled variable to the desired value.
• It is achieved through an actuator connected to the out port of the embedded system.

Sensors

A transducer device which converts energy from one form to another for any measurement or
control purpose. Sensors acts as input device
• Eg. Hall Effect Sensor which measures the distance between the cushion and magnet in the
Smart Running shoes from adidas
• Example: IR, humidity, PIR (passive infra-red), ultrasonic, piezoelectric, smoke sensors

Actuators

A form of transducer device (mechanical or electrical) which converts signals to corresponding

physical action (motion). Actuator acts as an output device
• Eg. Micro motor actuator which adjusts the position of the cushioning element in the Smart
Running shoes from adidas

The I/O Subsystem

• The I/O subsystem of the embedded system facilitates the interaction of the embedded
system with external world

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• The interaction happens through the sensors and actuators connected to the Input and output
ports respectively of the embedded system
• The sensors may not be directly interfaced to the Input ports, instead they may be interfaced
through signal conditioning and translating systems like ADC, Optocouplers etc

I/O Devices - Light Emitting Diode (LED):

Light Emitting Diode (LED) is an output device for visual indication in any embedded system
 LED can be used as an indicator for the status of various signals or situations.
 Typical examples are indicating the presence of power conditions like “Device ON‟,
“Battery low‟ or “Charging of battery‟ for a battery operated handheld embedded
devices

LED is a p-n junction diode and it contains an anode and a cathode.

 For proper functioning of the LED, the anode of it should be connected to +ve terminal
of the supply voltage and cathode to the –ve terminal of supply voltage
 The current flowing through the LED must limited to a value below the maximum
current that it can conduct.
 A resister is used in series between the power supply and the resistor to limit the current
through the LED

Vcc

GND

LEDs can be interfaced to the port pin of a processor/controller in two ways.

 In the first method, the anode is directly connected to the port pin and the port pin drives
the LED. In this approach the port pin 'sources' current to the LED when the port pin
is at logic High (Logic '1’).
 In the second method, the cathode of the LED is connected to the port pin of the
processor/controller and the anode to the supply voltage through a current limiting

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 resistor. The LED is turned on when the port pin is at logic Low (Logic '0'). Here the
port pin 'sinks' current.

I/O Devices – 7-Segment LED Display

The 7 – segment LED display is an output device for displaying alpha numeric characters

 It contains 8 light-emitting diode (LED) segments arranged in a special form. Out of

the 8 LED segments, 7 are used for displaying alpha numeric characters
 The LED segments are named A to G and the decimal point LED segment is named as
DP. The LED Segments A to G and DP should be lit accordingly to display numbers
and characters
 The 7 – segment LED displays are available in two different configurations, namely;
Common anode and Common cathode
o In the Common anode configuration, the anodes of the 8 segments are connected
commonly whereas in the Common cathode configuration, the 8 LED segments
share a common cathode line
 Based on the configuration of the 7 – segment LED unit, the LED segment
anode or cathode is connected to the Port of the processor/controller in
the order “A‟ segment to the Least significant port Pin and DP segment
to the most significant Port Pin.
 The current flow through each of the LED segments should be limited to
the maximum value supported by the LED display unit
 The typical value for the current falls within the range of 20mA
 The current through each segment can be limited by connecting a current
limiting resistor to the anode or cathode of each segment
7- Segment display is a popular choice for low cost embedded applications like, Public
Telephone Call monitoring devices, POS terminals, etc.,

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I/O Devices – OptoCoupler:
Optocoupler is a solid state device to isolate two parts of a circuit. Optocoupler combines an
LED and a photo-transistor in a single housing (package).
 In electronic circuits, an optocoupler is used for suppressing interference in data
communication, circuit isolation, high voltage separation, simultaneous separation and
signal intensification, etc.
 Optocouplers can be used in either input circuits or in output circuits. Figure illustrates
the usage of optocoupler in input circuit and output circuit of an embedded system with
a microcontroller as the system core.

Optocoupler is available as ICs from different semiconductor manufacturers. The MCT2M IC

from Fairchild semiconductor is an example for optocoupler IC.

I/O Devices – Stepper Motor:

Stepper motor is an electro mechanical device which generates discrete displacement (motion)
in response to dc electrical signals
 It differs from the normal dc motor in its operation. The dc motor produces continuous
rotation on applying dc voltage whereas a stepper motor produces discrete rotation in
response to the dc voltage applied to it

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  Stepper motors are widely used in industrial embedded applications, consumer
electronic products and robotics control systems
 The paper feed mechanism of a printer/fax makes use of stepper motors for its
functioning.
 Based on the coil winding arrangements, a two-phase stepper motor is classified into
o Unipolar
o Bipolar

Unipolar: A unipolar stepper motor contains two windings per phase. The direction of rotation
(clockwise or anticlockwise) of a stepper motor is controlled by changing the direction of
current flow. Current in one direction flows through one coil and in the opposite direction
flows through the other coil. It is easy to shift the direction of rotation by just switching the
terminals to which the coils are connected.

The coils are represented as A, B, C, D. Coils A and C carry current in opposite directions for
phase1 (only one of them will be carrying current at a time). Similarly, B and D carry current
in opposite directions for phase2 (only one of them will be carrying current at a time).
Bipolar: A bipolar stepper motor contains single winding per phase. For reversing the motor
rotation, the current flow through the windings is reversed dynamically. It requires complex
circuitry for current flow reversal.

The stepping of stepper motor can be implemented in different ways by changing the sequence
of activation of the stator windings.

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The different stepping modes supported by stepper motor are:
Full Step: In full step mode both the phases are energised simultaneously. It should be noted
that out of the two windings, only one winding of the phase is energised at a time. The coils are
energised in the following order:

Wave Step: In wave step mode only one phase is energised at a time and each coil of the phase
is energised alternatively. The coils are energised in the following order:

Half Step: It uses the combination of wave and full step. It has highest torque and stability .
The coils are energised in the following order:

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The rotation of the stepper motor can be reversed by reversing the order in which the coil is
energised.

The current and voltage requirements of the stepper motor is little high and hence the port pins
of a micro controller/processor may not drive them directly. Hence special driving circuits are
needed.
The following diagram illustrates the interfacing of a stepper motor

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I/O Devices – Push button switch:

Push Button switch is an input device.

 Push button switch comes in two configurations, namely “Push to Make‟ and “Push to

Break‟

o The switch is normally in the open state and it makes a circuit contact when it is
pushed or pressed in the “Push to Make‟ configuration.
o In the “Push to Break‟ configuration, the switch normally in the closed state and it
breaks the circuit contact when it is pushed or pressed
 The push button stays in the “closed‟ (For Push to Make type) or “open‟ (For Push to
Break type) state as long as it is kept in the pushed state and it breaks/makes the circuit
connection when it is released.
 Push button is used for generating a momentary pulse.
 In embedded application push button is generally used as reset and start switch and
pulse generator. The Push button is normally connected to the port pin of the host
processor/controller.
 Depending on the way in which the push button interfaced to the controller, it can
generate either a 'HIGH' pulse or a 'LOW' pulse.

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Piezo Buzzer:
Piezo buzzer is a piezoelectric device for generating audio indications in embedded
application. A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible
sound in response to the voltage applied to it.

Piezoelectric buzzers are available in two types. 'Self- driving' and 'External driving’.
 The 'Self-driving' circuit contains all the necessary components to generate sound at a
predefined tone. It will generate a tone on applying the voltage.
 External driving piezo buzzers supports the generation of different tones. The tone can
be varied by applying a variable pulse train to the piezoelectric buzzer.
A piezo buzzer can be directly interfaced to the port pin of the processor/controller.

Keyboard

Keyboard is an input device for user interfacing.

 If the number of keys required is very limited, push button switches-can be used and
they can be directly interfaced to the port pins for reading.
 However, there may be situations demanding a large number of keys for user input
(e.g. PDA device with alpha-numeric keypad for user data entry). In such situations it
may not be possible to interface each keys to a port pin due to the limitation in the
number of general purpose port pins available for the processor/controller in use and
moreover it is wastage of port pins.
 Matrix keyboard is an optimum solution for handling large key requirements. It greatly
reduces the number of interface connections.
o For example, for interfacing 16 keys, in the direct interfacing technique 16 port
pins are required, whereas in the matrix keyboard only 8 lines are required.
o The 16 keys are arranged in a 4 column x 4 Row matrix. Figure illustrates the
connection of keys in a matrix keyboard.
 In a matrix keyboard, the keys are arranged in matrix fashion (i.e. they are connected
in a row and column style). For detecting a key press, the keyboard uses the scanning
technique, where each row of the matrix is pulled low and the columns are read.

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  After reading the status of each columns corresponding to a row, the row is pulled high
and the next row is pulled low and the status of the columns are read. This process is
repeated until the scanning for all rows are completed. When a row is pulled low and
if a key connected to the row is pressed, reading the column to which the key is
connected will give logic 0.
 Since keys are mechanical devices, there is a possibility for de-bounce issues, which
may give multiple key press effect for a single key press.
 To prevent this, a proper key de-bouncing technique should be applied. Hardware key
de-bouncer circuits and software key de-bounce techniques are the key de- bouncing
techniques available.
 The software key de-bouncing technique doesn't require any additional hardware and
is easy to implement. In the software de-bouncing technique, on detecting a key-press,
the key is read again after a de-bounce delay. If the key press is a genuine one, the state
of the key will remain as 'pressed' on the second read also.
 Pull-up resistors are connected to the column lines to limit the current that flows to the
Row line on a key press.

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I/O Devices – Relay

An electro mechanical device which acts as dynamic path selectors for signals and power.

• The “Relay‟ unit contains a relay coil made up of insulated wire on a metal core and a
metal armature with one or more contacts.
“Relay‟ works on electromagnetic principle.

• When a voltage is applied to the relay coil, current flows through the coil, which in turn
generates a magnetic field.
• The magnetic field attracts the armature core and moves the contact point.

• The movement of the contact point changes the power/signal flow path.

The ‘Relays’ are available in different configurations.

 The Single Pole Single Throw configuration has only one path for information flow.
o Single pole single throw normally open relay, the circuit is normally open and
becomes closed when the relay is energised.
o Single pole single throw normally closed relay, the circuit is normally closed and
becomes open when the relay is energised.
 The Single Pole double Throw Relay has two paths for information flow.

The Relay is normally controlled using a relay driver circuit connected to the port pin of the
processor/controller

A transistor can be used as the relay driver. The transistor can be selected depending on the
relay driving current requirements.

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Programmable Peripheral Interface (PPI)

Programmable Peripheral Interface (PPI) devices are used for extending the I/O capabilities
of processors/controllers.
 Most of the processors/ controllers provide very limited number of I/O and data ports
and at times it may require more number of I/O ports than the one supported by the
controller/processor.
 A programmable peripheral interface device expands the I/O capabilities of the
processor/controller.
 82554 is a popular PPI device for 8bit processors/controllers.
o 82554 supports 24 1/O pins and these I/O pins can be grouped as either
 three 8-bit parallel ports (Port A, Port B and Port C) or
 two 8bit parallel ports (Port A and Port B) with Port C in any one of the
following configurations:
▪ As 8 individual I/O pins
▪ Two 4bit ports namely Port CUPPER (Cu) and Port CLOWER
(CL)

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EMBEDDED SYSTEM DESIGN UNIT-2
 COMMUNICATION INTERFACE

Communication interface is essential for communicating with various subsystems of the

embedded system and with the external world
The communication interface can be viewed in two different perspectives; namely;

 Device/board level communication interface (Onboard Communication Interface)

o The communication channel which interconnects the various components
within an embedded product is referred as Device/board level communication
interface (Onboard Communication Interface)
 Examples: Serial interfaces like I2C, SPI, UART, 1-Wire etc and
Parallel bus interface
 Product level communication interface (External Communication Interface)
o The “Product level communication interface‟ (External Communication
Interface) is responsible for data transfer between the embedded system and
other devices or modules. The external communication interface can be either
wired media or wireless media and it can be a serial or parallel interface.
 Examples for wireless communication interface: Infrared (IR),
Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency waves (RF),
GPRS etc.
 Examples for wired interfaces: RS-232C/RS-422/RS 485, USB,
Ethernet (TCP-IP), IEEE 1394 port, Parallel port etc.

DEVICE/BOARD LEVEL OR ON-BOARD COMMUNICATION

INTERFACES

The Communication channel which interconnects the various components within an embedded
product is referred as Device/board level communication interface (Onboard Communication
Interface)
These are classified into
 I2C (Inter Integrated Circuit) Bus
 SPI (Serial Peripheral Interface) Bus
 UART (Universal Asynchronous Receiver Transmitter)
 1-Wires Interface

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  Parallel Interface

I2C (Inter Integrated Circuit) Bus

Inter Integrated Circuit Bus (I2C - Pronounced “I square C‟) is a synchronous bi-directional
half duplex (one-directional communication at a given point of time) two wire serial interface
bus. The concept of I2C bus was developed by “Philips Semiconductors‟ in the early 1980’s.
The original intention of I2C was to provide an easy way of connection between a
microprocessor/microcontroller system and the peripheral chips in Television sets.

The I2C bus is comprised of two bus lines, namely;

Serial Clock – SCL and
Serial Data – SDA.

 SCL line is responsible for generating synchronization clock pulses

 SDA is responsible for transmitting the serial data across devices.
I2C bus is a shared bus system to which many number of I2C devices can be connected.
Devices connected to the I2C bus can act as either “Master‟ device or “Slave‟ device.
 The “Master‟ device is responsible for controlling the communication by
initiating/terminating data transfer, sending data and generating necessary
synchronization clock pulses.
 Slave devices wait for the commands from the master and respond upon receiving the
commands.
Master and “Slave‟ devices can act as either transmitter or receiver.
 Regardless whether a master is acting as transmitter or receiver, the synchronization
clock signal is generated by the “Master‟ device only.
I2C supports multi masters on the same bus.

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 SCL SDA Vcc
2 .2 K

SDA
2 .2 K
Port Pins SCL
Slave 1
SCL I 2 C Device
Master SDA ( Eg : Serial
( Microprocessor / EEPROM )
Controller )

SCL Slave 2
SDA I 2 C Device

I 2 C Bus

Figure: I2C Bus Interfacing

The sequence of operation for communicating with an I2C slave device is

1. Master device pulls the clock line (SCL) of the bus to “HIGH‟
2. Master device pulls the data line (SDA) “LOW‟, when the SCL line is at logic “HIGH‟
(This is the “Start‟ condition for data transfer)
3. Master sends the address (7 bit or 10 bit wide) of the “Slave‟ device to which it wants
to communicate, over the SDA line.
4. Clock pulses are generated at the SCL line for synchronizing the bit reception by the
slave device.
5. The MSB of the data is always transmitted first.
6. The data in the bus is valid during the “HIGH‟ period of the clock signal
7. In normal data transfer, the data line only changes state when the clock is low.
8. The master sends the Read or Write bit (1= read and 0 = write)
9. Master waits for the acknowledgement bit from the slave device whose address is sent
on the bus along with the Read/Write operation command.
10. Slave devices connected to the bus compares the address received with the address
assigned to them
11. The Slave device with the address requested by the master device responds by sending
an acknowledge bit (Bit value =1) over the SDA line
12. Upon receiving the acknowledge bit, master sends the 8bit data to the slave device over
SDA line, if the requested operation is “Write to device‟.

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 13. If the requested operation is “Read from device‟, the slave device sends data to the
master over the SDA line.
14. Master waits for the acknowledgement bit from the device upon byte transfer complete
for a write operation and sends an acknowledge bit to the slave device for a read
operation
15. Master terminates the transfer by pulling the SDA line “HIGH‟ when the clock line
SCL is at logic “HIGH‟ (Indicating the “STOP‟ condition).

In I2C Protocol there are 5-speed categories including standard mode, fast mode, fast plus
mode, high-speed mode, and ultra speed mode these speed categories range from 100 kHz to
5MHz, where standard mode is 100KHz, Fast mode is 400KHz, Fast mode plus is 1MHz, High-
Speed Mode is 3.4MHz and Ultra-fast mode is 5MHz.

Serial Peripheral Interface (SPI) Bus

The Serial Peripheral Interface Bus (SPI) is a synchronous bi-directional full duplex four wire
serial interface bus. The concept of SPI is introduced by Motorola. SPI is a single master multi-
slave system.
• It is possible to have a system where more than one SPI device can be master, provided the
condition only one master device is active at any given point of time, is satisfied.
• SPI is used to send data between Microcontrollers and small peripherals such as shift
registers, sensors, and SD cards.

Figure: SPI bus Interfacing

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SPI requires four signal lines for communication. They are:
 Master Out Slave In (MOSI): Signal line carrying the data from master to slave device.
It is also known as Slave Input/Slave Data In (SI/SDI)
 Master In Slave Out (MISO): Signal line carrying the data from slave to master device.
It is also known as Slave Output (SO/SDO)
 Serial Clock (SCLK): Signal line carrying the clock signals
 Slave Select (SS): Signal line for slave device select. It is an active low signal.

The master device is responsible for generating the clock signal.

Master device selects the required slave device by asserting the corresponding slave devices
slave select signal “LOW‟.
• The data out line (MISO) of all the slave devices when not selected floats at high
impedance state
• The serial data transmission through SPI Bus is fully configurable.

• SPI devices contain certain set of registers for holding these configurations.

• The Serial Peripheral Control Register holds the various configuration parameters like
master/slave selection for the device, baudrate selection for communication, clock signal
control etc.
• The status register holds the status of various conditions for transmission and reception.

SPI works on the principle of “Shift Register‟.

• The master and slave devices contain a special shift register for the data to transmit or
receive.
• The size of the shift register is device dependent. Normally it is a multiple of 8.

• During transmission from the master to slave, the data in the master’s shift register is
shifted out to the MOSI pin and it enters the shift register of the slave device through the
MOSI pin of the slave device.
• At the same time the shifted out data bit from the slave device’s shift register enters the
shift register of the master device through MISO pin

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I2C V/S SPI:

Universal Asynchronous Receiver Transmitter (UART)

• Universal Asynchronous Receiver Transmitter (UART) based data transmission is an

asynchronous form of serial data transmission.
• UART based serial data transmission doesn’t require a clock signal to synchronize the
transmitting end and receiving end for transmission. Instead it relies upon the pre-defined
agreement between the transmitting device and receiving device.

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• The serial communication settings (Baud rate, number of bits per byte. parity, number of
start bits and stop bit and flow control) for both transmitter and receiver should be set as
identical. The start and stop of communication is indicated through inserting special bits in
the data stream. While sending a byte of data, a start bit is added first and a stop bit is added
at the end of the bit stream.

• The least significant bit of the data byte follows the ‘start’ bit.

• The ‘start’ bit informs the receiver that a data byte is about to arrive.

• The receiver device starts polling its received line’ as per the baud rate settings.

• If the baud rate is ‘x’ bits per second, the time slot available for one bit is l /x seconds. The
receiver unit polls the receiver line at exactly half of the time slot available for the bit.
• If parity is enabled for communication, the UART of the transmitting device adds a parity
bit (bit value is l for odd number of ls in the transmitted bit stream and 0 for even number
of is the UART of the receiving device calculates the parity of the bits received and
compares it with the received parity bit for error checking.
• The UART of the receiving device discards the ‘Start’, ‘Stop’ and ‘Parity' bit from the
received bit stream and converts the received serial bit data to a word (In the case of 8
bits/byte, the byte is formed with the received 8 bits with the first received bit as the LSB
and last received data bit as MSB).

• For proper communication, the ‘Transmit line’ of the sending device should be connected
to the ‘Receive line’ of the receiving device. Figure illustrates the same.

• In addition to the serial data transmission function, UART provides hardware handshake
receiver support for controlling the serial data now. UART chips are available from
different semiconductor manufacturers. National Semiconductor’s 8250 UART chip is
considered as the standard setting UART. It was used in the original IBM PC.

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1-wire interface (protocol)
• 1-wire interface is an asynchronous half-duplex communication protocol developed by
Maxim Dallas Semiconductor. It is also known as Dallas 1-Wire® protocol. It makes use
of only a single signal line (wire) called DQ for communication and follows the masterslave
communication model.
• One of the key feature of l-wire bus is that it allows power to be sent along the signal wire
as well.
• The 12C slave devices incorporate internal capacitor (typically of the order of 800 pF) to
power the device from the signal line.
• The l-wire interface supports a Single master and one or more slave devices on the bus.
The bus interface diagram shown in Figure illustrates the connection of master and slave
devices on the l-wire bus.

• Every 1-wire device contains a globally unique 64bit identification number stored within
it. The unique identification number can be used for addressing individual devices present
on the bus in case there are multiple slave devices connected to the 1-wire bus.
• The identifier has three parts: an 8bit family code, a 48bit serial number and an 8-bit CRC
computed from the first 56 bits.
• The sequence of operation for communicating with a 1-wire slave device is listed below:

1. The master device sends a ‘Reset’ pulse on the l-wire bus.

2. The slave device(s) present on the bus respond with a ‘Presence’ pulse.

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 3. The master device sends a ROM command (Net Address Command followed by
the 64bit address of the device). This addresses the slave device(s) to which it
wants to initiate a communication.
4. The master device sends a read/write function command to read/write the internal
memory or register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device

• All communication over the l-wire bus is master initiated. The communication over the l-
wire bus divided into timeslots of 60 microseconds. The ‘Reset’ pulse occupies 8 time slots.
 For starting a communication, the master asserts the reset pulse by pulling the 1-wire
bus ‘LOW’ for at least 8 time slots ‘slave’ device is present on the bus and is ready for
communication it should respond to the master with a ‘Presence’ pulse, within 60us of the
release of the ‘Reset’ pulse by the master.
• The slave device(s) responds with a ‘Presence’ pulse by pulling the l-wire bus ‘LOW’ for
a minimum of 1 time slot (60 us).
• For writing a bit value of 1 on the l-wire bus, the bus master pulls the bus for l to l5µs and
then releases the bus for the rest of the time slot. A bit value of ‘0’ is written on the bus by
master pulling the bus for a minimum of 1 time slot (60µs) and a maximum of 2 time slots
(120µs). To Read a bit from the slave device, the master pulls the bus ‘LOW’ for l to 15us.
If the slave wants to send a bit value ‘1’ in response to the read request from the master, it
simply releases the bus for the rest of the time slot. If the slave wants to send a bit value
‘0’, it pulls the bus ‘LOW’ for the rest of the time slot.

Parallel interface

• The on-board parallel interface is normal used for communicating with peripheral devices
which are memory mapped to the host of the system.
• The host processor/controller of the embedded system contains a parallel bus and the device
which supports parallel bus can directly connect to this bus system.
• The communication through the parallel bus is controlled by the control signal interface
between the device and the host.

• The ‘Control Signals’ for communication includes ‘Read/ Write’ signal and device select
signal. The device normally contains a device select line and the device becomes active
only when this line is asserted by the host processor.
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• The direction of data transfer (Host to Device or Device to Host) can be controlled through
the control signal lines for ‘Read’ and ‘Write’. Only the host processor has control over the
‘Read’ and ‘Write’ control signals.

• The device is normally memory mapped to the host processor and a range of address is
assigned to it. An address decoder circuit is used for generating the chip select signal for
the device.
• When the address selected by the processor is within the range assigned for the device, the
decoder circuit activates the chip select line and thereby the device becomes active.
• The processor then can read or write from or to the device by asserting the corresponding
control line (RD and WR respectively). Strict timing characteristics are followed for
parallel communication.
• parallel communication is host processor initiated.

• If a device wants to initiate the communication, it can inform the same to the processor
through interrupts. For this, the interrupt line of the device is connected to the interrupt line
of the processor and the core, responding interrupt is enabled in the host processor. The
width of the parallel interbank is determined by the data bus width of the host processor. It
can be 4bit, 8bit, 16bit, 32bit or 64bit etc. The bus width supported by the device should be
same as that of the host processor.
• The bus interface diagram shown in Figure illustrates the interfacing of devices through
parallel interface.

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PRODUCT LEVEL COMMUNICATION INTERFACE (EXTERNAL
COMMUNICATION INTERFACE)
The Product level communication interface (External Communication Interface) is responsible
for data transfer between the embedded system and other devices or modules
It is classified into two types

 Wired communication interface

 Wireless communication interface:

1. Wired communication interface

Wired communication interface is an interface used to transfer information over a wired

network. It is classified into following types.
 RS-232C/RS-422/RS 485

 USB

RS-232C:

• RS-232 C (Recommended Standard number 232, revision C from the Electronic Industry

Association) is a legacy, full duplex, wired, asynchronous serial communication interface

 RS-232 extends the UART communication signals for external data communication.
• UART uses the standard TTL/CMOS logic (Logic “High‟ corresponds to bit value 1 and

Logic “LOW‟ corresponds to bit value 0) for bit transmission whereas RS232 use the EIA
standard for bit transmission.
• As per EIA standard, a logic “0‟ is represented with voltage between +3 and +25V and a
logic “1‟ is represented with voltage between -3 and -25V.
• In EIA standard, logic “0‟ is known as “Space‟ and logic “1‟ as “Mark‟.

• The RS232 interface define various handshaking and control signals for communication
apart from the “Transmit‟ and “Receive‟ signal lines for data communication
• RS-232 supports two different types of connectors, namely; DB-9: 9-Pin connector and
DB-25: 25-Pin connector.

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• RS-232 is a point-to-point communication interface and the devices involved in RS-232
communication are called “Data Terminal Equipment (DTE)‟ and “Data Communication
Equipment (DCE)‟.

• If no data flow control is required, only TXD and RXD signal lines and ground line (GND)
are required for data transmission and reception.
• The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper
data transmission.
• If hardware data flow control is required for serial transmission, various control signal lines
of the RS-232 connection are used appropriately.
• The control signals are implemented mainly for modem communication and some of them
may be irrelevant for other type of devices.
• The Request to Send (RTS) and Clear To Send (CTS) signals co-ordinate the
communication between DTE and DCE.
• Whenever the DTE has a data to send, it activates the RTS line and if the DCE is ready to
accept the data, it activates the CTS line.
• The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data.

• The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a
communication link.
• DTR should be in the activated state before the activation of DSR.

• The Data Carrier Detect (DCD) is used by the DCE to indicate the DTE that a good signal
is being received.
• Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line.
• As per the EIA standard RS-232 C supports baudrates up to 20Kbps (Upper limit
19.2Kbps).
• The commonly used baudrates by devices are 300bps, 1200bps, 2400bps, 9600bps,
11.52Kbps and 19.2Kbps.

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• The maximum operating distance supported in RS-232 communication is 50 feet at the
highest supported baudrate.
RS-232 supports only point-to-point communication and not suitable for multi-drop
communication. It uses single ended data transfer technique and thereby susceptible to noise
and it greatly reduces the operating distance.

 RS-422 is another serial interface standard that supports data rate upto 100Kbps and
distance upto 400ft. It supports multi-drop communication with one transmitter
device and receiver devices upto 10.
 RS-485 is the enhanced version of RS-422 and it supports multi-drop communication
with up to 32 transmitting devices (drivers) and 32 receiving devices on the bus. The
communication between devices in the bus uses the 'addressing' mechanism to
identify slave devices.

USB (UNIVERSAL SERIAL BUS):

Universal Serial Bus (USB) is a wired high speed serial bus for data communication.

 The first version of USB (USB1.0) was released in 1995 and was created by the USB
core group members consisting of Intel, Microsoft, IBM, Compaq, Digital and Northern
Tele- com.

The USB communication system follows a star topology with a USB host at the centre and one
or more USB peripheral devices/USB hosts connected to it.

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  A USB host can support connections up to 127, including slave peripheral devices and
other USB hosts
 USB transmits data in packet format. Each data packet has a standard format. The USB
communication is a host initiated one.
 The physical connection between a USB peripheral device and master device is
established with a USB cable

The USB standard uses two different types of connector at the ends of the USB cable for
connecting the USB peripheral device and host device.

 "Type A' connector is used for upstream connection (connection with host) and
 Type B connector is used for downstream connection (connection with slave device).

The USB connector present in desktop PCs or laptops are examples for 'Type A' USB connector.

Both Type A and Type B connectors contain 4 pins for communication.

USB uses differential signals for data transmission. USB interface has the ability to supply
power to the connecting devices. Each USB device contains a Product ID (PID) and a Vendor
ID (VID).

USB supports four different types of data transfers, namely;-

 Control transfer is used by USB system software to query, configure and issue
commands to the USB device.
 Bulk transfer is used for sending a block of data to a device. Bulk transfer supports
error checking and correction. Transferring data to a printer is an example for bulk
transfer.
 Isochronous data transfer is used for real-time data communication. In Isochronous
transfer, data is transmitted as streams in real-time. Isochronous transfer doesn't support
error checking and re-transmission of data in case of any transmission loss. All

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 streaming devices like audio devices and medical equipment for data collection make
use of the isochronous transfer.
 Interrupt transfer is used for transferring small amount of data. Interrupt transfer
mechanism makes use of polling technique to see whether the USB device has any data
to send. Devices like Mouse and Keyboard, which transmits fewer amounts of data,
uses Interrupt transfer.

Presently USB supports four different data rates namely; Low Speed (1.5Mbps), Full Speed
(12Mbps), High Speed (480Mbps) and Super Speed (4.8Gbps). The Low Speed and Full Speed
specifications are defined by USB 1.0 and the High Speed specification is defined by USB 2.0.
USB 3.0 defines the specifications for Super Speed.

IEEE 1394 (Fire wire):

• IEEE 1394 is a wired, isochronous high speed serial communication bus. It is also known
as High Performance Serial Bus (HPSB).
• The IEEE 1394 uses differential data transfer (The information is sent using differential
signals through a pair of twisted cables. It increases the noise immunity) and the interface
cable supports 3 types of connectors, namely; 4-pin connector, 6-pin connector (alpha
connector) and 9 pin connector (beta connector).
• The 6 and 9 pin connectors carry power also to support external devices It can supply
unregulated power in the range of 24 to 30V.
• There are two differential data transfer lines A and B per connector. In a 1394 cable,
normally the differential lines of A are connected to B (TPA+ to TPB+ and TPA-to TPB-)
and vice versa.
• 1394 is a popular communication interface for connecting embedded devices like Digital
Camera, Camcorder, Scanners to desktop computers for data transfer and storage.
• IEEE 1394 doesn't require a host for communicating between devices. For example, you
can directly connect a scanner with a printer for printing.

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Wireless communication interface

Wireless communication interface is an interface used to transmission of information over a

distance without help of wires, cables or any other forms of electrical conductors. They are
basically classified into following types
1. Infrared

2. Bluetooth

3. Wi-Fi

4. Zigbee

5. GPRS

INFRARED:

Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices.

 Infrared communication technique uses infrared waves of the electromagnetic

spectrum for transmitting the data.
 IrDA supports point-point and point-to-multipoint communication, provided all
devices involved in the communication are within the line of sight.
 The typical communication range for IrDA lies in the range 10 cm to 1 m.
 Depending on the speed of data transmission IR is classified into
o Serial IR (SIR),
o Medium IR (MIR),
o Fast IR (FIR),
o Very Fast IR (VFIR) and
o Ultra Fast IR (UFIR).

SIR supports transmission rates ranging from 9600bps to 115.2kbps. MIR supports
data rates of 0.576Mbps and 1.152Mbps. FIR supports data rates up to 4Mbps.
VFIR is designed to support high data rates up to 16Mbps.

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  IrDA communication involves a transmitter unit for transmitting the data over IR and
a receiver for receiving the data. Infrared Light Emitting Diode (LED) is the IR source
for transmitter and at the receiving end a photodiode acts as the receiver.

Certain devices like a TV remote control always require unidirectional communication and so
they contain either the transmitter or receiver unit

'Infra-red Data Association' is the regulatory body responsible for de- fining and licensing the
specifications for IR data communication. IrDA communication has two essential parts; a
physical link part and a protocol part.

Bluetooth:

Bluetooth is a low cost, low power, short range wireless technology for data and voice
communication.

 Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the
Frequency Hopping Spread Spectrum (FHSS) technique for communication.
 Literally it supports a data rate of up to 1Mbps and a range of approximately 30 feet
for data communication.

Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a
protocol part.

Bluetooth enabled devices essentially contain a Bluetooth wireless radio for the transmission
and reception of data.

The rules governing the Bluetooth communication is implemented in the 'Bluetooth protocol
stack'. The Bluetooth communication IC holds the stack.

Each Bluetooth device will have a 48 bit unique identification number. Bluetooth
communication follows packet based data transfer.
Bluetooth supports point-to-point (device to device) and point-to-multipoint (device to
multiple device broadcasting) wireless communication.

The point-to-point communication follows the master- slave relationship. A Bluetooth device
can function as either master or slave. When a network is formed with one Bluetooth device
as master and more than one device as slaves, it is called a Piconet.

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A Piconet supports a maximum of seven slave devices.
Bluetooth is the favourite choice for short range data communication in handheld embedded
devices. Bluetooth technology is very popular among cell phone users as they are the easiest
communication channel for transferring ringtones, music files, pictures, media files, etc.
between neighbouring Blue- tooth enabled phones.

The specifications for Bluetooth communication is defined and licensed by the standards body
'Blue- tooth Special Interest Group (SIG)'.

Wi-Fi:

• Wi-Fi is the name of a popular wireless networking technology that uses radio waves to
provide wireless high-speed Internet and network connections
• Wi-Fi follows the IEEE 802.11 standard

• Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication
• Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless
Access point to manage the communications.
• The Wi-Fi router is responsible for restricting the access to a network, assigning IP address
to devices on the network, routing data packets to the intended devices on the network.

• Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the
form of radio signals through an antenna.

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• Wi-Fi operates at 2.4GHZ or 5GHZ of radio spectrum and they co-exist with other ISM
band devices like Bluetooth.
• A Wi-Fi network is identified with a Service Set Identifier (SSID). A Wi-Fi device can
connect to a network by selecting the SSID of the network and by providing the credentials
if the network is security enabled
• Wi-Fi networks implements different security mechanisms for authentication and data
transfer.
• Wireless Equivalency Protocol (WEP), Wireless Protected Access (WPA) etc are some of
the security mechanisms supported by Wi-Fi networks in data communication.

ZIGBEE:

ZigBee is a low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard.
 ZigBee is targeted for low power, low data rate and secure applications for Wireless
Personal Area Networking (WPAN).
 ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400
to 2.484 GHz, 902 to 928 MHz and 868.0 to 868.6 MHz.
 ZigBee Supports an operating distance of up to 100 metres and a data rate of 20 to
250Kbps.
In the ZigBee terminology, each ZigBee device falls under any one of the following ZigBee
device category.

 ZigBee Coordinator (ZC)/Network Coordinator:

o The ZigBee coordinator acts as the root of the ZigBee network.
o The ZC is responsible for initiating the ZigBee network and
o it has the capability to store information about the network.

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  ZigBee Router (ZR)/Full function Device (FFD):
o Responsible for passing information from device to another device or to another
ZR.
 ZigBee End Device (ZED)/Reduced Function Device (RFD):
o End device containing ZigBee functionality for data communication.
o It can talk only with a ZR or ZC and
o doesn't have the capability to act as a mediator for transferring data from one
device to another.
Smoke detectors, heating control, lighting controls, environmental controls, etc. are examples
for applications which can make use of the Zig- Bee technology.
The specifications for ZigBee is developed and managed by the ZigBee alliance.

General Packet Radio Service (GPRS)

General Packet Radio Service (GPRS) is a communication technique for transferring data over
a mobile communication network like GSM.

Data is sent as packets in GPRS communication. The transmitting device splits the data into
several related packets. At the receiving end the data is re-constructed by combining the
received data packets.

GPRS supports a theoretical maximum transfer rate of 171.2kbps.

In GPRS communication, the radio channel is concurrently shared between several users instead
of dedicating a radio channel to a cell phone user.

The GPRS communication divides the channel into 8 timeslots and transmits data over the
available channel. GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25
protocols for communication.

GPRS is mainly used by mobile enabled embedded devices for data communication. The device
should support the necessary GPRS hardware like GPRS modem and GPRS radio. To
accomplish GPRS based communication, the carrier network also should have support for
GPRS communication.

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