SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

DATA TYPES PART-1

SCALAR

 A scalar is a single bit or a single value.

 It represents a single piece of data, such as a single bit (bit), a single 4-state value
(logic), or a single integer (int, integer).

Examples of scalar types in SystemVerilog:

 bit: A single binary bit (0 or 1).

 logic: A single 4-state value (0, 1, X, or Z).

 int: A 32-bit signed integer.

 integer: A 32-bit signed integer (similar to int but with some differences in
usage).

bit a; // Scalar: single bit

logic b; // Scalar: single 4-state value

int c; // Scalar: 32-bit signed integer

VECTOR

 A vector is a collection of bits or values grouped together into a single entity.

 It represents multiple bits or values, such as a bus, a multi-bit signal, or an array of bits.
 Vectors are typically used to represent multi-bit data, such as addresses, data buses, or registers.
 In systemverilog, vectors are declared using a range specification, e.g., [7:0] for an 8-bit vector.

Examples of vector types in systemverilog:

 Bit [7:0]: an 8-bit vector of binary bits.

 Logic [15:0]: a 16-bit vector of 4-state values.
 Reg [31:0]: a 32-bit vector of register values.

Bit [7:0] data; // vector: 8-bit binary value

Logic [15:0] addr; // vector: 16-bit 4-state value

Reg [31:0] counter; // vector: 32-bit register

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

LOGIC:
 Why logic in system verilog.
 reg is used in Procedural Logic for defining variables that need to hold their value
within procedural blocks.
 Wire is used in Sequential Logic for connecting signals, especially between sequential
elements like flip-flops or memory elements.
 Logic can be used as reg and wire

X UNKNOWN
Z HIGH IMPEDENCE

Aspect Procedural Logic Sequential Logic

wire (used for connections in sequential
Data Type reg (used for procedural blocks like always) logic)
Assignment Non-blocking (<=), usually for
Type Blocking (=) /Non-blocking (<=) registers

Usage Context Used in always, initial, or final blocks Used in always_ff blocks with clocking

Updates in response to clock edges

Signal Update Updates in response to simulation events (posedge/negedge)

Procedurally driven (sequential logic, not Stateful, stores values between clock
Behavior stored between clock cycles) cycles

Common Counter, State machine (inside always

Example block) Flip-flops, Registers, Clocked logic

SIMPLE CODE:
 Logic data type used for sequential assignment
 Logic data type used for procedural assignment
 Logic used for module & gates

EDA EXAMPLE:
https://edaplayground.com/x/vyxH

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

DEFAULT/RESET/INITIAL VALUES:

Data Type Default Value

int 0
reg x (unknown)
wire z (high impedance)
logic x (unknown)
bit 0
byte 8'bxxxxxxxx (unknown)
shortint 0
longint 0
real 0
string "" (empty string)
time 0

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EDA EXAMPLE:

https://edaplayground.com/x/iG47

Result
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 03:36 2025
Default value of 'i' (int): 0
Default value of 'b' (reg): x
Default value of 'w' (wire): z
Default value of 'l' (logic): x
Default value of 'bt' (bit): 0
Default value of 'by' (byte): 00000000
Default value of 'si' (shortint): 0
Default value of 'li' (longint): 0
Default value of 'r' (real): 0.000000
Default value of 'str' (string): ""
Default value of 't' (time): 0
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

2 STATE AND 4 STATE DATA TYPES

Data Default Bit Width Signed/Unsigned

Type Value
int 0 32 bits Signed
reg x (unknown) Depends on size Can be signed or unsigned
(commonly 32 bits)
wire z (high Depends on size Can be signed or unsigned
impedance) (commonly 1 bit)
logic x (unknown) Depends on size Can be signed or unsigned
(commonly 1 bit)
bit 0 1 bit Unsigned

byte 8'bxxxxxxxx 8 bits Unsigned

(unknown)

shortint 0 16 bits Signed

longint 0 64 bits Signed
real 0 64 bits N/A (Floating-point)

string "" (empty Dynamic (variable N/A (Strings are not

string) length) signed/unsigned)

time 0 64 bits Unsigned

2-State vs 4-State Data Types

 2-State means the variable can only represent two values, typically 0 and 1.
o Examples: bit, int, shortint, longint, time, real (and floating-point types in
general).
o These types cannot hold unknown (x) or high-impedance (z) states.
o Signed and unsigned versions of these types exist (like int being signed, and
bit being unsigned by default).
 4-State means the variable can represent four values: 0, 1, x (unknown), and z (high
impedance).
o Examples: reg, wire, logic.
o These types can represent a wider range of logic states, which is essential for
modeling digital circuits where certain conditions may be undefined or
disconnected.
o Signed and unsigned versions of these types also exist (like reg signed [3:0] or
wire [7:0]).

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

HOW TO DETECT UNKNOWN VALUE:

EDA EXAMPLE:

https://edaplayground.com/x/ngS5

Result:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 04:22 2025
Data value: xx01
The register 'data' contains an unknown value (x or z).
The wire 'signal' contains an unknown value (x or z).
VCS Simulation Report

Explanation:

1. $isunknown(): This is the SystemVerilog system function used to check if a signal (of
any type like reg or wire) contains an unknown value (x or z). It returns 1 (true) if the
signal contains an unknown value, and 0 (false) if it does not.
2. Test Setup:
o We assign an unknown value (4'bx01) to the data register. The x in 4'bx01
represents an unknown value.
o We assign a high-impedance value (4'bz) to the signal wire, which is also an
unknown value.
3. Detection:
o We use $isunknown(data) to check if the data register contains any unknown
value (x or z).
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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

o Similarly, we use $isunknown(signal) to check if the signal wire contains any

unknown value.

SIGNED AND UNSIGNED

 Signed data types allow for both positive and negative values (using two's
complement representation).
 Unsigned data types only allow non-negative values.
 SystemVerilog uses signed and unsigned keywords to control the interpretation of the
variables.

Key Points:

1. Unsigned:
o Used for variables that should only hold non-negative values.
o Example: reg [7:0] unsigned_data;
2. Signed:
o Used for variables that can hold both positive and negative values.
o Example: reg signed [7:0] signed_data;
3. Two's Complement Representation:
o SystemVerilog uses two's complement to represent negative numbers in
signed types.
o The MSB (Most Significant Bit) determines the sign: 0 for positive and 1 for
negative.
4. No Implicit Sign:
o If you declare a variable with no explicit signed or unsigned, SystemVerilog
assumes unsigned by default.

Data Type Signed/Unsigned Value Range Example (2^n)

bit Unsigned 0 to 1 2^0 = 1
byte Unsigned 0 to 255 2^8 - 1 = 255
shortint Signed -2^15 to 2^15 - -2^15 to 2^15 - 1
1
int Signed -2^31 to 2^31 - -2^31 to 2^31 - 1
1
longint Signed -2^63 to 2^63 - -2^63 to 2^63 - 1
1
reg Can be Depends on the Dependent on the
signed/unsigned declaration bit width
wire Can be Depends on the Dependent on the
signed/unsigned declaration bit width

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EDA EXAMPLE: https://edaplayground.com/x/ZmqF

Result:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 04:34 2025
Unsigned data (8'b11111111): 255
Unsigned negative example (-5): 251
Signed data (8'b11111111): -1
Signed negative example (-5): -5
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

FINAL CONCLUSION:

Data Default Bit Width Signed/Unsigned 2-State / Floating

Type Value 4-State Point
int 0 32 bits Signed 2-state No
reg x (unknown) Depends on Can be signed or 4-state No
size unsigned
(commonly
32 bits)
wire z (high Depends on Can be signed or 4-state No
impedance) size unsigned
(commonly 1
bit)
logic x (unknown) Depends on Can be signed or 4-state No
size unsigned
(commonly 1
bit)
bit 0 1 bit Unsigned 2-state No
byte 8'bxxxxxxxx 8 bits Unsigned 4-state No
(unknown)
shortint 0 16 bits Signed 2-state No
longint 0 64 bits Signed 2-state No
real 0 64 bits N/A (Floating-point) 2-state Yes

string "" (empty Dynamic N/A (Strings are not N/A No

string) (variable signed/unsigned) (Variable
length) length)

time 0 64 bits Unsigned 2-state No

1. Integer and Logic Literals

In Verilog, to assign a value to all the bits of a vector, the user had to specify the value
explicitly for each bit. SystemVerilog simplifies this by introducing unsized single-bit
literals using a preceding apostrophe (').

Unsized Single-Bit Literals

 '0: Sets all bits to 0.
 '1: Sets all bits to 1.
 'x or 'X: Sets all bits to x (unknown).
 'z or 'Z: Sets all bits to z (high impedance).

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 07:33 2025
a = 11111111111111111111111111111111
b = 0000000000000000
c = xxxxxxxx
d = zzzz
VCS Simulation Report

Equivalents in Verilog-2001:
 'x is equivalent to 'bx.
 'z is equivalent to 'bz.
 '1 is equivalent to assigning all 1s.
 '0 is equivalent to assigning all 0s.

2. Time Literals

Time literals represent time values and are used in timing constructs. They are written in
integer or fixed-point format, followed by a time unit (fs, ps, ns, us, ms, s, step).

EXAMPLE:

RESULT :

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 07:31 2025

0.1ns delay completed.
40ps delay completed.
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Behavior:

 Time literals are interpreted as real-time values scaled to the current time unit and
rounded to the current time precision.

3. Array Literals

Array literals are used to initialize arrays. They are syntactically similar to C initializers but
include the replicate operator ({{}}) for repeating values.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 07:29 2025

n[1][1] = 0
n[1][2] = 1
n[1][3] = 2
n[2][1] = 4
n[2][2] = 4
n[2][3] = 4

VCS Simulation Report

Key Points:
 The nesting of braces must match the number of dimensions in the array.
 The replicate operator ({{}}) can be used to repeat values within a dimension.
 Replicate operators can be nested, but the inner pair of braces in a replication is
removed.

Summary of Literals

Literal Type Example Description

Unsized single-bit
literals for setting all
Integer and Logic '1, '0, 'x, 'z bits
Time 0.1ns, 40ps Time values with units
Array initialization with
Array '{'{0,1,2}, '{3{4}}} replicate operator

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Key Enhancements in SystemVerilog

1. Unsized Single-Bit Literals:

o Simplify assigning values to all bits of a vector.
o Example: reg [31:0] a = '1; sets all 32 bits to 1.
2. Time Literals:
o Support fixed-point notation and time units.
o Example: #0.1ns; waits for 0.1 nanoseconds.
3. Array Literals:
o Support multi-dimensional initialization and replicate operators.
o Example: int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

ARRAY
Fixed size array: size is fixed
Single dimension array

byte array [4];

Index 0 1 2 3

Length of array is 4

INDEX 0 1 2 3
ELEMENTS 5 2 5 2

Another way to write elements

RESULT:
-------displaying array1-------
array1[0] = 5
array1[1] = 4
array1[2] = 3
array1[3] = 2
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

MULTIDIMENSIONAL ARRAY
2 DIMENSIONAL ARRAYS:

int array[3][2];

RESULT:

-------displaying array2-------
array[0][0] = 1
array[0][1] = 5
array[1][0] = 2
array[1][1] = 6
array[2][0] = 3
array[2][1] = 7
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
EXAMPLE 2:

Result

------displaying array2-------
array[0][0] = 1
array[0][1] = 5
array[1][0] = 2
array[1][1] = 6
array[2][0] = 3
array[2][1] = 7
VCS Simulation Report

0 1
0 1 5
1 2 6
2 3 7

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

3 DIMENSIONAL ARRAY:

int array[2][3][4];

2*3*4=24 element

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 13:03 2025

Displaying the 3D array:
array[0][0][0] = 100
array[0][0][1] = 101
array[0][0][2] = 102
array[0][0][3] = 103
array[0][1][0] = 110
array[0][1][1] = 111
array[0][1][2] = 112
array[0][1][3] = 113
array[0][2][0] = 120
array[0][2][1] = 121
array[0][2][2] = 122
array[0][2][3] = 123

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
array[1][0][0] = 200
array[1][0][1] = 201
array[1][0][2] = 202
array[1][0][3] = 203
array[1][1][0] = 210
array[1][1][1] = 211
array[1][1][2] = 212
array[1][1][3] = 213
array[1][2][0] = 220
array[1][2][1] = 221
array[1][2][2] = 222
array[1][2][3] = 223
VCS Simulation Report

ANOTHER WAY

0 1 2 3
0 0 100 101 102 103
1 110 111 112 113
2 120 121 122 123

1 0 200 201 202 203

1 210 211 212 213
2 220 221 222 223

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

PACKED ARRAY:
Packed arrays can be defined from single bit data types ( bit, logic, reg ), enumerated types,
and other packed arrays or packed structures

A packed array refers to the dimension mentioned before the variable or object name. This is
also known as the vector width.

bit [3] array;

2 1 0
ARRAY0

bit [2][3] array;

3 2 1 0 3 2 1 0 3 2 1 0
ARRAY2 ARRAY1 ARRAY0

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 1:

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 14:30 2025

byte_array = 10101010
byte_array[3] = 1
word_array = abcd 1234 5678 9abc
Displaying word_array using foreach loop:
word_array[3] = 9abc
word_array[2] = 5678
word_array[1] = 1234
word_array[0] = abcd
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

UNPACKED ARRAY:

 Unpacked array can be defined as any kind of data type.

 The fixed-size dimension of an unpacked array can be declared using an address
range, or it can be declared by specifying a size.
 Unpacked arrays shall be declared by specifying the element ranges after the identifier
name.

bit [7:0] array4[2:0];

Total elements =21

7 6 5 4 3 2 1 0
0
1
2

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Unpacked array example 2

bit [7:0] matrix[2:0][2:0];

3x3 matrix

0 1 2
0 8’h1 8’h2 8’h3
1 8’h4 8’h5 8’h6
2 8’h7 8’h8 8’h9

Result:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jan 29 15:00 2025

Displaying 3x3 matrix using for loop:
01 02 03
04 05 06
07 08 09
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 2:

bit [7:0] matrix[2:0][3:0];

0 1 2 3
0
1
2

EXAMPLE 3

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

DYNAMIC ARRAY IN SYSTEMVERILOG

 Verilog does not allow changing the dimensions of the array once it is declared
Fixed size array as its size is set at compile time
 If you store the transaction in an fixed size array it would have to be large enough to
hold the maximum number of transaction wasting memory
 Dynamic array that can be allocated and resized during simulation time so your
simulation consume minimum amount of memory
 A dynamic array is one dimension of an unpacked array whose size can be set or
changed at run-time.
 Dynamic array is declared using an empty word subscript [ ].
 The size of an array can be specified during run-time by using new [ ].
 By default, the size of a dynamic array is 0 unless a new [ ] is used.
 Dynamic arrays require fixed-size elements, so you cannot use bit or logic directly.
Instead, use a fixed-size vector type (e.g., typedef logic [7:0] byte_t).

 Limitations:
o You can only access elements using integer indices.
o Searching for a specific value (e.g., finding an element by its
content) can be slow (O(n) in the worst case).

SCALAR VS. VECTOR IN DYNAMIC ARRAYS

 When you declare a dynamic array, SystemVerilog needs to know the size of each
element in the array so it can allocate memory efficiently.
 Scalar types like int and integer have a fixed size (e.g., 32 bits), so they can be used
directly in dynamic arrays.
 Vector types like bit or logic can represent a single bit or a multi-bit vector, which
introduces ambiguity. For example:
o Is bit a single bit or a vector of bits?
o Is logic a single 4-state value or a vector of 4-state values?
 Because of this ambiguity, SystemVerilog does not allow dynamic arrays
of bit or logic directly. Instead, you must define a fixed-size vector (e.g., bit
[7:0] or logic [15:0]) and then use that type in the dynamic array.

Example: Scalar vs. Vector in Dynamic Arrays

Scalar Dynamic Array (Allowed)

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Vector Dynamic Array (Allowed with Fixed-Size Vector)

DYNAMIC ARRAY METHODS IN SYSTEMVERILOG

1. New
2. Size
3. Delete

1. NEW [] (ALLOCATION)
 Allocates memory for the dynamic array.

 You can specify the size of the array during allocation.

 If no size is specified, the array is initially empty.

int array[];

array = new[10]; // Allocate memory for 10 elements

2. SIZE()
 Returns the current size of the dynamic array.

 If the array is empty, it returns 0.

int size;

size = array.size(); // Get the size of the array

3. DELETE()

 Deallocates the memory of the dynamic array, making it empty.

 After calling delete(), the array size becomes 0.

array.delete(); // Delete the array and free memory

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 1:

Before Memory Allocation

Size of Dynamic array 0
After Memory Allocation
Size of Dynamic array 5
--- Dynamic array Values are ---
dyn[0] = 2
dyn[1] = 3
dyn[2] = 4
dyn[3] = 5
dyn[4] = 6
---------------------------------
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 2:

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
RESULT :
Before Memory Allocation
Size of Dynamic array 0
After Memory Allocation
Size of Dynamic array 5
dyn[0] = 100
dyn[1] = 200
dyn[2] = 300
dyn[3] = 400
dyn[4] = 500
Increasing the size by overriding previous values
Size of Dynamic array 10
dyn[0] = 88
dyn[1] = 11
dyn[2] = 22
dyn[3] = 33
dyn[4] = 44
dyn[5] = 55
dyn[6] = 66
dyn[7] = 77
dyn[8] = 99
dyn[9] = 12
Increasing the size by retaining previous values
Size of Dynamic array 10
dyn[0] = 88
dyn[1] = 11
dyn[2] = 22
dyn[3] = 33
dyn[4] = 44
dyn[5] = 55
dyn[6] = 66
dyn[7] = 77
dyn[8] = 99
dyn[9] = 12
Copy dyn to dyn1
dyn1[0] = 88
dyn1[1] = 11
dyn1[2] = 22
dyn1[3] = 33
dyn1[4] = 44
dyn1[5] = 55
dyn1[6] = 66
dyn1[7] = 77
dyn1[8] = 99
dyn1[9] = 12
After Array Delete
Size of dyn 0
Size of dyn1 10
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.2Mb
Sat Feb 1 03:57:01 2025

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Associative array
 Associative array stores entries in a sparse matrix. This means that while you can
address a very large address space ,system verilog only allocates memory for an
element when you write on it.
 When the size of the collection is unknown or the data space is sparse, an associative
array is a better option.
 An associative array (also called a map, dictionary, or hash table) stores key-value
pairs, where keys can be of any data type (e.g., strings, numbers, objects). Values are
accessed using their corresponding keys.
 Use Case:
o When you need to associate data with specific keys (e.g., storing user
information by username).
o When you need fast lookups by key (O(1) on average for hash-based
implementations).
o When the keys are not integers or are not sequential.
o When you need to store and retrieve data in a way that doesn't rely on order.
 Advantages:
o Flexibility in key types (e.g., strings, objects, etc.).
o Efficient lookups, insertions, and deletions by key.
o Ideal for scenarios where you need to map one piece of data to another (e.g.,
phone books, configuration settings, etc.).

When to Use Associative Arrays over Dynamic Arrays

1. Non-Integer Keys:
o If you need to use keys that are not integers (e.g., strings, objects), associative
arrays are necessary.
o Example: Storing user data by username (userData["john_doe"] = {age: 30,
email: "[email protected]"}).
2. Fast Lookups by Key:
o If you need to frequently look up values based on a specific key, associative
arrays are more efficient than dynamic arrays.
o Example: Checking if a username exists in a database.
3. Sparse Data:
o If your data is sparse (i.e., you don't need to store values for every possible
index), associative arrays save memory by only storing the key-value pairs
that exist.
4. Mapping Relationships:
o If you need to represent relationships between two pieces of data (e.g., word
frequencies, graph edges), associative arrays are ideal.
o Example: Counting word occurrences in a text (wordCounts["hello"] = 5).
5. Configuration or Settings:
o Associative arrays are great for storing configuration settings where keys are
meaningful names (e.g., config["theme"] = "dark").

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE SCENARIOS

1. Dynamic Array:
o Storing a list of numbers: [10, 20, 30, 40].
o Iterating over elements in order.
2. Associative Array:
o Storing user information: {"john_doe": {age: 30, email:
"[email protected]"}, "jane_doe": {age: 25, email: "[email protected]"}}.
o Looking up a user's email by their username.

Sparse Data in Arrays

 In a dense array, most or all of the indices are occupied by meaningful values.
o Example: [1, 2, 3, 4, 5] (every index is filled).
 In a sparse array, only a few indices contain meaningful values, and the rest are empty
or default (e.g., 0, null, or undefined).
o Example: [1, null, null, 4, null] (only indices 0 and 3 have meaningful values).

Declaration of Associative Arrays

The general syntax for declaring an associative array in SystemVerilog is:

data_type array_name [index_type];

 data_type: The type of data stored in the array (e.g., int, bit, string, logic, etc.).
 array_name: The name of the associative array.
 index_type: The type of the index (key) used to access elements in the array
(e.g., int, string, bit, etc.).

Valid Types for data_type Data

The data_type can be any valid SystemVerilog data type, including:

 Integer types: int, integer, byte, shortint, longint

 Bit types: bit, logic, reg
 Other types: string, real, shortreal, user-defined types (e.g., structs, enums)

The index_type can be:

 Integer types: int, integer, byte, shortint, longint

 String type: string
 Bit types: bit, logic, reg
 Other types: User-defined types (e.g., enums, structs)

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Examples of associative array declarations are:

 int array_name[*];//Wildcard index. can be indexed by any integral datatype. //

associative array of integer (unspecified index)
 int array_name [ string ];// String index
 int array_name [ some_Class ];// Class index
 int array_name [ integer ];// Integer index
 typedef bit signed [4:1] Nibble;
 int array_name [ Nibble ]; // Signed packed array
 Elements in associative array elements can be accessed like those of one dimensional
 arrays. Associative array literals use the '{index:value} syntax with an optional
default
 index.
 //associative array of 4-state integers indexed by strings, default is '1.
 integer tab [string] = '{"Peter":20, "Paul":22, "Mary":23, default:-1 };

METHODS:
Method Description

num() returns the number of entries in the associative array

delete(index) removes the entry at the specified index.exa_array.delete(index)

exists(index) returns 1 if an element exists at the specified index else returns 0

first(var) assigns the value of first index to the variable var

last(var) assigns the value of last index to the variable var

next(var) assigns the value of next index to the variable var

prev(var) assigns the value of previous index to the variable var

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE:

RESULT:
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

Number of entries in a_array is 3

--- Associative array mem entries and Values are ---
mem[5] =2
mem[6] =3
mem[7] =4
--------------------------------------------------------
First entry is a_array[5] = 2
Last entry is a_array[7] = 4
VCS Simulation Report

31
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 2:

32
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:

(Specify +UVM_NO_RELNOTES to turn off this notice)

--------------------------------------------------------
Number of entries in mem is 3
--- Associative array mem entries and Values are ---
mem[BLUE] =3
mem[ORANGE] =4
mem[RED] = 2
--------------------------------------------------------
First entry is mem[BLUE] = 3
--------------------------------------------------------
Last entry is mem[RED] = 2
--------------------------------------------------------
mem.exists("RED")
--------------------------------------------------------
Number of entries in mem after deletion is 2
--- Associative array mem entries and Values are ---
mem[BLUE] =3
mem[RED] = 2
--------------------------------------------------------
First entry is at index BLUE
--------------------------------------------------------
Next entry is at index RED after the first index
VCS Simulation Report
Time: 0 ns
CPU Time: 0.420 seconds; Data structure size: 0.2Mb

RESULT OF BELOW EXAMPLE 3:

Number of elements in assoc_aar: 4
------------------------------------------------------
Exists 'banana': 1
------------------------------------------------------
Exists 'grape': 0
------------------------------------------------------
Deleting 'banana'...
------------------------------------------------------
Exists 'banana' after deletion: 0
------------------------------------------------------
First element: key = apple, value = 10
------------------------------------------------------
Next element: key = cherry, value = 30
------------------------------------------------------
Last element: key = date, value = 40
------------------------------------------------------
Prev element: key = cherry, value = 30
------------------------------------------------------
VCS Simulation Report

33
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Example 3 : Declare An Associative Array Where The Key Is Of Type String

And Value Is Of Type Int

34
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

QUEUE:
 Queue are like fifo
 A Queue is analogous to one dimensional unpacked array that grows and shrinks
automatically
 Queues can be used to model a last in, first out buffer or first in, first out buffer.
 Queues support insertion and deletion of elements from random locations using an
Index.
 Queues can be passed to tasks / functions as ref or non-ref arguments. Type Checking
is also done.
 Queues are declared using the same syntax as unpacked arrays, but specifying $ as the
array size. In queue 0 represents the first, and $ representing the last entries.
 Which combines the best of an linked list and array A queue can be bounded or
unbounded
bounded queue – queue with the number of entries limited or queue size specifiedun
bounded queue – queue with unlimited entries or queue size not specified

data_type queue_name[$];
where:
data_type – data type of the queue elements.
queue_name – name of the queue.

Common Data Types for Queues

The data_type can be any valid SystemVerilog data type.

Some common data types used in queues include:

1. INTEGER TYPES:
o bit: Single-bit unsigned value.
o logic: Single-bit or multi-bit value (4-state: 0, 1, X, Z).
o reg: Legacy type, similar to logic.
o byte: 8-bit signed integer.
o shortint: 16-bit signed integer.
o int: 32-bit signed integer.

o longint: 64-bit signed integer.

o integer: 32-bit signed integer (legacy type).

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Queue Methods

Method Description

size() returns the number of items in the queue

insert() inserts the given item at the specified index position

delete() deletes the item at the specified index position

push_front() inserts the given element at the front of the queue

push_back() inserts the given element at the end of the queue

pop_front() removes and returns the first element of the queue

pop_back() removes and returns the last element of the queue

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

bit queue_1[$]; // queue of bits (unbound queue)

int queue_2[$]; // queue of int
byte queue_3[$:255]; // queue of byte (bounded queue with 256 entries)
string queue_4[$]; // queue of strings

https://edaplayground.com/x/VZz7

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

38
SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT :
----------------------------------------------------------------

*********** IMPORTANT RELEASE NOTES ************

You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.

You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

Initial Queues:
bit_queue: '{'h1, 'h0}
logic_queue: '{'ha, 'hX}
reg_queue: '{'haa, 'hbb}
byte_queue: '{127, -128}
shortint_queue: '{32767, -32768}
int_queue: '{2147483647, -2147483648}
longint_queue: '{9223372036854775807, -9223372036854775808}
integer_queue: '{2147483647, -2147483648}

Queues after push_front:

bit_queue: '{'h1, 'h1, 'h0}
logic_queue: '{'hf, 'ha, 'hX}
reg_queue: '{'hcc, 'haa, 'hbb}
byte_queue: '{0, 127, -128}

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
shortint_queue: '{0, 32767, -32768}
int_queue: '{0, 2147483647, -2147483648}
longint_queue: '{0, 9223372036854775807, -9223372036854775808}
integer_queue: '{0, 2147483647, -2147483648}

Queues after pop_back:

bit_queue: '{'h1, 'h1}
logic_queue: '{'hf, 'ha}
reg_queue: '{'hcc, 'haa}
byte_queue: '{0, 127}
shortint_queue: '{0, 32767}
int_queue: '{0, 2147483647}
longint_queue: '{0, 9223372036854775807}
integer_queue: '{0, 2147483647}

Queues after pop_front:

bit_queue: '{'h1}
logic_queue: '{'ha}
reg_queue: '{'haa}
byte_queue: '{127}
shortint_queue: '{32767}
int_queue: '{2147483647}
longint_queue: '{9223372036854775807}
integer_queue: '{2147483647}

Queues after insert:

bit_queue: '{'h0, 'h1}
logic_queue: '{'ha, 'h5}
reg_queue: '{'hdd, 'haa}
byte_queue: '{127, 85}
shortint_queue: '{4660, 32767}
int_queue: '{2147483647, -559038737}
longint_queue: '{81985529216486895, 9223372036854775807}
integer_queue: '{2147483647, -889275714}

Queues after delete:

bit_queue: '{'h1}
logic_queue: '{'ha}
reg_queue: '{'haa}
byte_queue: '{127}
shortint_queue: '{32767}
int_queue: '{2147483647}
longint_queue: '{9223372036854775807}
integer_queue: '{2147483647}

Queue Sizes:
bit_queue size: 1
logic_queue size: 1
reg_queue size: 1
byte_queue size: 1
shortint_queue size: 1
int_queue size: 1

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
longint_queue size: 1
integer_queue size: 1

Queues after emptying:

bit_queue: '{}
logic_queue: '{}
reg_queue: '{}
byte_queue: '{}
shortint_queue: '{}
int_queue: '{}
longint_queue: '{}
integer_queue: '{}
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.2Mb

43
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

LINKED L

in-progress

The List package implements a classic list data-structure, and is analogous to the STL
(Standard Template Library) List container that is popular with C++ programmers. The
container is defined as a parameterized class, meaning that it can be customized to
hold data of any type. The List package supports lists of any arbitrary predefined
type, such as integer, string, or class object. First declare the Linked list type and
then take instances of it. SystemVerilog has many methods to operate on these
instances.
A double linked list is a chain of data structures called nodes. Each node has 3
members, one points to the next item or points to a null value if it is last node, one
points to the previous item or points to a null value if it is first node and other has the
data.

The disadvantage of the linked list is that data can only be accessed sequentially and
not in random order. To read the 1000th element of a linked list, you must read the
999 elements that precede it.

List Definitions:
list :- A list is a doubly linked list, where every element has a predecessor and
successor. It is a sequence that supports both forward and backward traversal, as well
as amortized constant time insertion and removal of elements at the beginning, end,
or middle.
container :- A container is a collection of objects of the same type .Containers are
objects that contain and manage other objects and provide iterators that allow the
contained objects (elements) to be addressed. A container has methods for accessing
its elements. Every container has an associated iterator type that can be used to
iterate through the container´s elements.
iterator :- Iterators provide the interface to containers. They also provide a means to
traverse the container elements. Iterators are pointers to nodes within a list. If an
iterator points to an object in a range of objects and the iterator is incremented, the
iterator then points to the next object in the range.

Procedure To Create And Use List:

1. include the generic List class declaration
`include <List.vh>
2. Declare list variable
List#(integer) il; // Object il is a list of integer
3. Declaring list iterator

44
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

List_Iterator#(integer) itor; //Object s is a list-of-integer iterator

List_iterator Methods

The List_Iterator class provides methods to iterate over the elements of lists.
The next() method changes the iterator so that it refers to the next element in the
list.
The prev() method changes the iterator so that it refers to the previous element in
the list.
The eq() method compares two iterators and returns 1 if both iterators refer to the
same list element.
The neq() method is the negation of eq().
The data() method returns the data stored in the element at the given iterator
location.

List Methods
The List class provides methods to query the size of the list; obtain iterators to the
head or tail of the list;
retrieve the data stored in the list; and methods to add, remove, and reorder the
elements of the list.
The size() method returns the number of elements stored in the list.
The empty() method returns 1 if the number elements stored in the list is zero and 0
otherwise.
The push_front() method inserts the specified value at the front of the list.
The push_back() method inserts the specified value at the end of the list.
The front() method returns the data stored in the first element of the list.
The back() method returns the data stored in the last element of the list.
The pop_front() method removes the first element of the list.
The pop_back() method removes the last element of the list.
The start() method returns an iterator to the position of the first element in the list.
The finish() method returns an iterator to a position just past the last element in the
list.
The insert() method inserts the given data into the list at the position specified by the
iterator.
The insert_range() method inserts the elements contained in the list range specified
by the iterators first and last at the specified list position.
The erase() method removes from the list the element at the specified position.
The erase_range() method removes from a list the range of elements specified by the
first and last iterators.
The set() method assigns to the list object the elements that lie in the range specified
by the first and last iterators.
The swap() method exchanges the contents of two equal-size lists.
The clear() method removes all the elements from a list, but not the list itself.
The purge() method removes all the list elements (as in clear) and the list itself.

45
SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

FEATURE PACKED ARRAY UNPACKED ARRAY

Definition A contiguous collection of bits A collection of elements stored in
stored as a single unit. separate memory locations.
Memory Layout Stored as a single block of Stored as individual elements in
memory. memory.
Data Types Can only contain single-bit data Can contain any data type,
types (bit, logic, reg, wire). including complex types
(struct, enum, etc.).
Usage Used for bit-level operations, Used for storing collections of data,
arithmetic, and modeling such as arrays of integers or structs.
hardware signals.
Indexing Accessed using bit indices Accessed using element indices
(e.g., array[3:0]). (e.g., array[0]).
Size Size must be known at compile Size can be dynamic (for dynamic
time (static). arrays) or static.
Limitations - Cannot store complex data - Cannot perform bitwise
types. operations directly.
- Limited to single-bit elements. - Less efficient for bit-level
operations.
Example logic [7:0] packed_array; (8-bit int unpacked_array [0:7]; (8-
packed array) element unpacked array of
integers)
Memory More memory-efficient for bit- Less memory-efficient for bit-level
Efficiency level operations. operations due to overhead.
Operations Supports bitwise operations Does not directly support bitwise
operations.
Memory Layout Elements are contiguous (bit- Elements are not contiguous (word-
level) level)
Element Size Fixed width for all elements Elements can vary in type and size
Usage Hardware modeling (e.g., register, Software modeling (e.g., dynamic
wires) arrays)
Flexibility Less flexible (fixed size and width) More flexible (dynamic sizes,
associative)
Performance More efficient for hardware More efficient for software
simulation simulation
Dynamic Size Cannot resize during simulation Can be dynamically resized at
runtime
Associative Array Not allowed Can have associative arrays
Example logic [7:0] arr[10]; int arr[5];

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Memory Layout Elements are stored contiguously in Elements are stored non-contiguously
memory. in memory.
Memory Efficiency Efficient: No memory wasted since Less efficient: Memory may be wasted
all bits are contiguous. due to non-contiguous element
storage.
Fixed vs Dynamic Fixed size, defined at compile-time. Dynamic size, can be resized at
Size runtime.
Memory Waste for None: Memory is allocated for the Possible waste: If the array is resized,
Dynamic Size exact size at compile-time. memory allocation may lead to
fragmentation or unused memory.
Variable Element No: All elements must have the same Yes: Elements can be of different types
Width size. and sizes.
Memory Waste for None: All elements have the same Possible waste: Different element sizes
Varying Widths width, so no waste. could lead to unused or wasted
memory (e.g., if elements require
more space than necessary).
Access Time for Faster: Elements are contiguous, so Slower: Access times may be slower
Large Arrays memory access is fast. for non-contiguous elements.
Memory Allocation Fixed Memory: Memory is allocated Heap Memory: Dynamic allocation
for Large Arrays for the exact size at compile-time. may lead to fragmentation or unused
memory if not properly managed.
Used for Hardware Yes: Suitable for representing No: Not ideal for hardware modeling
Modeling hardware (e.g., registers, buses) with due to non-contiguous storage and
no wasted space. potential memory waste.
Use of Memory for Limited: Cannot store elements of Flexible: Can store complex types such
Complex Types varying types (only scalars with fixed as objects, classes, or structs with
widths). potentially wasteful memory allocation
if not managed properly.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

FEATURE DYNAMIC ARRAY ASSOCIATIVE ARRAY QUEUE

Definition An array with a size that can An array indexed by any data A collection of
be changed at runtime. type (e.g., integer, string). elements with FIFO
(First-In-First-Out)
behavior.
Memory Memory is allocated when the Memory is allocated only Memory is allocated
Allocation array is resized. when a key-value pair is dynamically as
added. elements are added
or removed.
Indexing Integer-based indexing Can use any data type as an Integer-based
(e.g., array[0]). index (e.g., array["key"]). indexing
(e.g., queue[0]).
Size Size can be changed at Size is dynamic and grows as Size is dynamic and
runtime using new[]. key-value pairs are added. grows/shrinks as
elements are
added/removed.

Usage Used when the size of the Used for sparse arrays or Used for FIFO
array is not known at compile when non-integer indexing is operations or when
time. needed. elements need to
be added/removed
frequently.
Limitations - Size must be explicitly - Slower access time - No random access
resized using new[]. compared to dynamic arrays. (only FIFO
operations).
- Wastes memory if oversized. - Higher memory overhead. - Limited to integer
indexing.
Memory Wastes memory if allocated Efficient for sparse arrays but Efficient for FIFO
Efficiency size is larger than needed. has higher overhead for key- operations but
value storage. wastes memory if
elements are not
removed.
Compile/Ru Size is determined at runtime. Size is determined at runtime. Size is determined
ntime at runtime.
Operations - new[] to resize. - exists() to check if a key - push_back() to
exists. add.
- size() to get the size. - delete to remove a key- - pop_front() to
value. remove.
- delete to clear. - size() to get size.
Example int dynamic_array[]; int associative_array[string];
dynamic_array = new[10]; associative_array["key"] = 10;

Memory Dynamically allocated, size can Dynamically allocated, Dynamically

Allocation be changed at runtime memory grows as keys are allocated, grows or
added shrinks as elements
are added or
removed

49
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Fixed vs Size can change dynamically at Size dynamically managed by Size dynamically
Dynamic runtime adding/removing keys changes as
Size elements are added
or removed
Access Indexed access (by integer Key-based access (using FIFO access (First In
Method index) string, int, etc.) First Out)
Memory Memory usage is proportional Memory usage is sparse, only Memory usage
Efficiency to the current size allocated for stored keys proportional to the
number of elements
in the queue
Memory Possible memory waste during Sparse, but may have Memory wasted if
Waste resizing overhead for key lookup and elements are added
hash tables without being
removed; potential
fragmentation
Performanc Low overhead for accessing Higher overhead for key- No random access,
e Overhead elements by index based access only FIFO access,
but quick
insertion/removal
Limitations Cannot have non-integer Key-based lookup overhead, No random access,
indices, resizing may incur cannot use negative indices memory overhead
overhead for dynamic resizing
Best For Arrays with a known type and Sparse data structures with FIFO or dynamic
size (resizable) key-based access ordered storage
(e.g., queues)
Key new(size), delete, size() num(), delete(index), size(), insert(index,
Methods exists(index), first(var), item), delete(index),
last(var), next(var), prev(var) push_front(item),
push_back(item),
pop_front(),
pop_back()
Method - new(size): Allocates the array - num(): Returns the number - size(): Returns the
Description with the specified size. of entries in the associative number of elements
s array. in the queue.
- delete: Deallocates the - delete(index): Removes the - insert(index, item):
dynamic array. entry at the specified key. Inserts the given
item at the specified
index.
- size(): Returns the number of - exists(index): Returns 1 if an - delete(index):
elements in the dynamic element exists at the specified Removes the item
array. key, otherwise returns 0. at the specified
index.
- first(var): Assigns the value - push_front(item):
of the first index to the Inserts the given
variable var. element at the front
of the queue.
- last(var): Assigns the value of - push_back(item):
the last index to the variable Inserts the given
var. element at the end
of the queue.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

- next(var): Assigns the value - pop_front():

of the next index to the Removes and
variable var. returns the first
element of the
queue.
- prev(var): Assigns the value - pop_back():
of the previous index to the Removes and
variable var. returns the last
element of the
queue.

ARRAY METHODS

 Array querying functions

 Array Locator Methods
 Array ordering methods
 Array reduction methods
 Iterator index querying

ARRAY QUERYING FUNCTIONS

METHOD DESCRIPTION EXAMPLE OUTPUT

$left Returns the left bound (MSB) of the array's dimension. 1

$right Returns the right bound (LSB) of the array's dimension. 4

$low Returns the minimum of $left and $right of the array's dimension. 1

$high Returns the maximum of $left and $right of the array's 4

dimension.
$increment Returns 1 if $left >= $right, and -1 if $left < $right. 1 (since 1 <= 4)

$size Returns the number of elements in the dimension ($high - $low + 4 (4 - 1 + 1 = 4)

1).
$dimensions Returns the total number of dimensions in the array. 2 (for a 2D array)

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 08:19 2025
Left bound of arr[1:4]: 1
Right bound of arr[1:4]: 4
Low bound of arr[1:4]: 1
High bound of arr[1:4]: 4
Increment of arr[1:4]: -1
Size of arr[1:4]: 4
Dimensions of arr: 3

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

ARRAY LOCATOR METHODS

METHOD DESCRIPTION EXAMPLE OUTPUT

find() Returns all elements satisfying the given find() found: 20 at
expression. index 1
find_index() Returns the indexes of all elements satisfying find_index() found
the given expression. index: 1
find_first() Returns the first element satisfying the given find_first() found: 20
expression.
find_first_index() Returns the index of the first element satisfying find_first_index()
the given expression. found at index: 1

find_last() Returns the last element satisfying the given find_last() found: 20
expression.
find_last_index() Returns the index of the last element satisfying find_last_index()
the given expression. found at index: 3

min() Returns the element with the minimum value min() found: 10
or whose expression evaluates to a minimum.

max() Returns the element with the maximum value max() found: 40
or whose expression evaluates to a maximum.

unique() Returns all elements with unique values or unique() found unique
whose expression is unique. element: 10 at index 0

unique_index() Returns the indexes of all elements with unique unique_index() found
values or whose expression is unique. at index: 0

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 08:55 2025
find: 13 43 36 39 237
-------------------------------------------------------->
find_index: 2
-------------------------------------------------------->
find_first: Bob
-------------------------------------------------------->
find_last: Henry
-------------------------------------------------------->
find_last_index:
-------------------------------------------------------->
min: 3
-------------------------------------------------------->
max:
-------------------------------------------------------->
unique: Bob Abc Henry John
-------------------------------------------------------->
unique with tolower: Bob Abc Henry John
-------------------------------------------------------->
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

ARRAY ORDERING METHODS:

Method Description Example Input Example out

Reverses the order of elements in the
reverse() array. {9, 5, 1, 7, 3} {3, 7, 1, 5, 9}

sort() Sorts the array in ascending order. {9, 5, 1, 7, 3} {1, 3, 5, 7, 9}

rsort() Sorts the array in descending order. {9, 5, 1, 7, 3} {9, 7, 5, 3, 1}

Randomizes the order of elements in

shuffle() the array (results vary each time). {9, 5, 1, 7, 3} {5, 3, 9, 1, 7}

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 13:06 2025
Original numbers: '{10, 40, 30, 20}
Original fruits: '{"apple", "kiwi", "banana"}

After reverse(): '{20, 30, 40, 10}

After sort(): '{10, 20, 30, 40}
Fruits sorted by length: '{"kiwi", "apple", "banana"}
After rsort(): '{40, 30, 20, 10}
Fruits reverse-sorted by length: '{"banana", "apple", "kiwi"}

After shuffle(): '{20, 10, 30, 40}

After another shuffle(): '{30, 20, 40, 10}
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

ARRAY REDUCTION METHODS:

Method Description Syntax Syntax Example Output

sum() Returns sum of array.sum() array.sum() with my_array.sum() = 15
all elements (condition ? item :
neutral)
product() Returns array.product() array.product() my_array.product() =
product of all with (filter ? item : 120
elements 1)
and() Returns bitwise array.and() array.and() with my_array.and() = 0
AND (&) of all (item & mask)
elements
or() Returns bitwise array.or() array.or() with my_array.or() = 7
OR (|) of all (item | mask)
elements
xor() Returns bitwise array.xor() array.xor() with my_array.xor() = 1
XOR (^) of all (item ^ mask)
elements

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 12:54 2025
sum() result: 15
sum(evens) result: 6
product() result: 120
product(>3) result: 20
and() result: 0
and(LSB) result: 0
or() result: 7
or(>3) result: 5
xor() result: 1
xor(LSB flip) result: 0
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

ITERATOR INDEX QUERYING:

 The expressions used by array manipulation methods sometimes need the actual array
 indexes at each iteration, not just the array element.
 The index method of an iterator
 returns the index value of the specified dimension.
// find all items equal to their position (index)
q = arr.find with ( item == item.index );
// find all items in mem that are greater than corresponding item in mem2
q = mem.find( x ) with ( x > mem2[x.index(1)][x.index(2)] );

RESULT “
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 13:21 2025
Items equal to their index in arr:
Index: 0, Value: 0
Index: 1, Value: 1
Index: 2, Value: 2
Index: 3, Value: 3
Index: 4, Value: 4
Index: 5, Value: 5
Index: 6, Value: 6
Index: 7, Value: 7
Index: 8, Value: 8
Index: 9, Value: 9
-------------------------------------------------------->
Items in mem greater than corresponding items in mem2:
Index: (0, 1), Value in mem: 2, Value in mem2: 1
Index: (0, 2), Value in mem: 3, Value in mem2: 1
Index: (0, 3), Value in mem: 4, Value in mem2: 1

60
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS
Index: (0, 4), Value in mem: 5, Value in mem2: 1
Index: (1, 0), Value in mem: 6, Value in mem2: 2
Index: (1, 1), Value in mem: 7, Value in mem2: 2
Index: (1, 2), Value in mem: 8, Value in mem2: 2
Index: (1, 3), Value in mem: 9, Value in mem2: 2
Index: (1, 4), Value in mem: 10, Value in mem2: 2
Index: (2, 0), Value in mem: 11, Value in mem2: 3
Index: (2, 1), Value in mem: 12, Value in mem2: 3
Index: (2, 2), Value in mem: 13, Value in mem2: 3
Index: (2, 3), Value in mem: 14, Value in mem2: 3
Index: (2, 4), Value in mem: 15, Value in mem2: 3
Index: (3, 0), Value in mem: 16, Value in mem2: 4
Index: (3, 1), Value in mem: 17, Value in mem2: 4
Index: (3, 2), Value in mem: 18, Value in mem2: 4
Index: (3, 3), Value in mem: 19, Value in mem2: 4
Index: (3, 4), Value in mem: 20, Value in mem2: 4
Index: (4, 0), Value in mem: 21, Value in mem2: 5
Index: (4, 1), Value in mem: 22, Value in mem2: 5
Index: (4, 2), Value in mem: 23, Value in mem2: 5
Index: (4, 3), Value in mem: 24, Value in mem2: 5
Index: (4, 4), Value in mem: 25, Value in mem2: 5
-------------------------------------------------------->
VCS Simulation Report
Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb

61
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

STRING

METHOD DESCRIPTION EXAMPLE USAGE

len() Returns the length of the string. str.len() - Returns the length of the
string str.
putc(i, c) Replaces the character at the str.putc(7, "X") - Replaces the 7th
specified index i with the character character of the string str with X.
c.
getc(i) Returns the ASCII code of the str.getc(2) - Returns the ASCII value of
character at the specified index i. the character at index 2 in the string str.
toupper() Converts all characters in the string str.toupper() - Converts the string str to
to uppercase and returns the uppercase.
modified string.
tolower() Converts all characters in the string str.tolower() - Converts the string str to
to lowercase and returns the lowercase.
modified string.
compare(s) Compares the current string with str.compare(s) - Compares the string str
string s (case-sensitive). Returns 0 if with s.
equal, otherwise non-zero.
icompare(s) Compares the current string with str.icompare(s) - Compares the string
string s (case-insensitive). Returns 0 str with s ignoring case.
if equal, otherwise non-zero.
substr(i, j) Returns a substring from index i to j str.substr(0, 5) - Extracts a substring
(inclusive). from index 0 to 5 of the string str.
atoi() Converts a string representing a str.atoi() - Converts the string str to an
number to an integer. integer (if it represents a valid number).
atoreal() Converts a string representing a str.atoreal() - Converts the string str to
real number to a real value. a real number (if it represents a valid
real number).
itoa(i) Converts an integer i to its string string int_str = $sformatf("%0d", num) -
representation. Converts integer num to a string and
stores it in int_str.
hextoa(i) Converts an integer i to its string hex_str = $sformatf("%h", 255) -
hexadecimal string representation. Converts integer 255 to its hexadecimal
string representation.
bintoa(i) Converts an integer i to its binary string bin_str = $sformatf("%b", 10) -
string representation. Converts integer 10 to its binary string
representation.

62
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

1. str.len():
o Returns the number of characters in the string.
o Example: "VIKRAM RENESAS" has a length of 14.
2. str.putc(i, c):
o Replaces the ith character in the string with the character c.
o Example: Replacing the 7th character (' ') with 'X' results
in "VIKRAMXRENESAS".
3. str.getc(i):
o Returns the ASCII code of the ith character in the string.
o Example: The 3rd character ('K') has an ASCII code of 75.
4. str.toupper():
o Converts all characters in the string to uppercase.
o Example: "VIKRAMXRENESAS" remains the same since it is already in
uppercase.
5. str.tolower():
o Converts all characters in the string to lowercase.
o Example: "vikramxrenesas".
6. str.compare(s):
o Compares two strings case-sensitively.
o Returns 0 if equal, a negative value if str < s, and a positive value if str > s.
7. str.icompare(s):
o Compares two strings case-insensitively.
o Returns 0 if equal, regardless of case.
8. str.substr(i, j):
o Extracts a substring from index i to j.
o Example: str.substr(0, 5) returns "VIKRAM".
9. str.atoi():
o Converts a string representing a decimal number to an integer.
o Example: "12345" is converted to 12345.
10. str.atoreal():
o Converts a string representing a floating-point number to a real number.
o Example: "123.45" is converted to 123.45.
11. str.itoa(i):
o Converts an integer to its ASCII decimal representation.
o Example: 6789 is converted to "6789".
12. str.hextoa(i):
o Converts an integer to its ASCII hexadecimal representation.
o Example: 255 is converted to "ff".
13. str.bintoa(i):
o Converts an integer to its ASCII binary representation.
o Example: 10 is converted to "1010".

63
SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

64
SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

65
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 13:42 2025

Length of str: 14
After replacing 7th character: VIKRAM XENESAS
ASCII value of 3rd character: 82
Uppercase: VIKRAM RENESAS
Lowercase: vikram renesas
Comparing with 'VIKRAM RENESAS': 0
Case-insensitive compare with 'vikram renesas': 0
Substring from 0 to 5: VIKRAM
Convert string to integer: 12345
Convert string to real: 123.450000
Integer to ASCII: 9876
Integer to Hex ASCII: ff
Integer to Binary ASCII: 0101
VCS Simulation Report

66
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

USER DEFINED DATATYPES

System verilog allows the user to define data types. There are different ways to define u ser
defined data types. They are

1. Class.
2. Enumerations.
3. Struct.
4. Union.
5. Typedef.

ENUMERATIONS (ENUM)

Enum (short for enumeration) is used to define a type with a set of named values. It allows
you to define a variable that can take only one of the predefined values, improving code
readability and reducing errors.

Declaration:
enum <type> { <value1>, <value2>, ..., <valueN> };

Where:

 <type> is the underlying data type of the enumeration (typically int, logic, etc.)
 <value1>, <value2>, ..., <valueN> are the possible values the enumeration can take.

// Define an enum type 'color'

enum logic [2:0] { RED = 3'b000, GREEN = 3'b001, BLUE = 3'b010 } color_t;

 Strong Typing: When you define an enumerated type, variables of that type can only
take values from the enumerated set, which helps prevent invalid values.
 Default Behavior: By default, enumerated data types are assigned integer values
starting from 0.
 If you don't explicitly assign a value to an enumerator, the next value will be
automatically incremented from the previous value.
 Enum as String: You can also print enum values as strings in SystemVerilog.

1. // Enum with implicit increment for 'c'

enum {a=3, b=7, c} alphabet1; c will be 8
2. // Enum with explicit assignment for 'd' enum {a=0, b=7, c, d=8} alphabet2; //error
because c & d same
3. // Enum with mixed explicit and implicit values enum {a, b=7, c} alphabet3; // a ==0
4. In SystemVerilog, enum (short for "enumeration") is a user-defined type that allows
you to define a set of named constants. Enums often used for state machines or
representing a set of related values.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Below are the key rules and guidelines for using enums in SystemVerilog:

1. Defining Enums

You can define an enum with specific named constants, optionally assigning integer values to
them. If no values are explicitly given, SystemVerilog will automatically assign sequential
integers starting from 0.

Syntax:

enum [size] {name1 = value1, name2 = value2, ...} enum_name;

Example:

enum {RED = 1, GREEN = 2, BLUE = 3} color;

Here, the color enum type has three named constants: RED, GREEN, and BLUE.

2. Implicit Increment

If you do not assign specific values to enum elements, SystemVerilog will automatically
assign incremental integer values starting from 0.

Example:

enum {a, b, c} alphabet;

 a=0
 b=1
 c=2

3. Explicit Values

You can explicitly assign integer values to some or all elements of the enum. If one element
is explicitly assigned a value, the following elements will continue from the last assigned
value unless otherwise specified.

Example:

enum {a=10, b=20, c} alphabet;

 a = 10
 b = 20
 c = 21 (implicitly assigned the next value)

4. Scoped Enums

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Enum names should be unique within a given scope. If you have multiple enums, you cannot
reuse the same name (e.g., a, b, etc.) unless they are scoped differently (e.g., inside different
modules or classes).

Example:

enum {a, b} enum1;

enum {c, d} enum2;

This works because enum1 and enum2 are scoped separately.

5. Enum Values Can Be Used Like Integers

Enum values can be used in assignments and comparisons just like integer constants.

EXAMPLE:

color = GREEN; // Assigning enum value to a variable

if (color == RED) begin
// some code
end

6. SIZE OF ENUM

By default, SystemVerilog will allocate just enough bits to represent all the enum values.
However, you can specify a size for the underlying integer type if needed.

Example:

enum [3:0] {a=0, b=1, c=2, d=3} alphabet; // 4-bit integer representation

The size [3:0] indicates a 4-bit representation.

7. FORWARD REFERENCES

Enums in SystemVerilog are processed in the order they appear. You cannot reference an
enum member before it is defined.

Example:

enum {a, b=5, c} alphabet;

 a=0
 b=5
 c=6

8. Enum Variables and Assignments

Enum variables are of the type specified by the enum, and they can be assigned values from
the list of named constants.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Example:

enum {START, STOP, PAUSE} state;

state = START; // Valid assignment

9. ENUM AND TYPE KEYWORD

You can also define an enum as a type using the typedef keyword.

Example:

typedef enum {SINGLE, DOUBLE, TRIPLE} size_t;

size_t size;
size = DOUBLE;

10. COMPARISON BETWEEN ENUMS

Enums can be compared using relational operators like ==, !=, <, >, etc.

Example:

if (state == STOP) begin

// Do something
end

11. Assigning Integer to Enum

You can assign an integer directly to an enum variable, but the value must be within the
defined enum range.

Example:

state = 2; // This assigns PAUSE (since it's the 2nd member)

12. Enum with Mixed Implicit and Explicit Values

You can mix explicit and implicit values in the same enum definition.

Example:

enum {a=3, b=7, c} alphabet; // c is assigned 8

13. Error if Values Conflict

If you define enums with conflicting values, you'll get an error. For example, you cannot
assign two members of the same enum the same value unless you're intentionally using the
same value.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Example:

enum {a=5, b=5, c} alphabet; // Error: two values have the same value

SUMMARY OF KEY RULES:

1. Enum names must be unique within the same scope.

2. Enum elements can be assigned explicit integer values or left to be assigned
incrementally.
3. You can mix explicit and implicit values in an enum.
4. Enums can be scoped using modules, classes, or typedefs.
5. Enum values can be compared and assigned as integers.
6. Enum variables can be assigned values directly or using the named constants.

Methods

METHOD DESCRIPTION EXAMPLE OUTPUT EXAMPLE

first() Returns first enum value day.first() MON

last() Returns last enum value day.last() SUN

next() Next value (1 step) day.next() TUE → WED

next(N) Nth next value day.next(2) WED → FRI

prev() Previous value (1 step) day.prev() FRI → THU

prev(N) Nth previous value day.prev(3) SAT → WED

name() String name of value day.name() "SUN"

day = 7;
name() error Empty string for invalid values day.name() ""

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

72
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 14:12 2025
First day: MON
------------------------------->
Last day: SUN
------------------------------->
Next day after TUE: WED
------------------------------->
Next 2 days after WED: FRI
------------------------------->
Previous day before FRI: THU
------------------------------->
Previous 3 days before SAT: WED
------------------------------->
Name of day: SUN
------------------------------->
Invalid enum name: ''
------------------------------->
VCS Simulation Report
Time: 0 ns
CPU Time: 0.400 seconds; Data structure size: 0.0Mb

EXAMPLE 2:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 14:41 2025

red
blue
green
blue
VCS Simulation Report

73
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 3

74
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Example of Enum with X and Z Values in SystemVerilog:

Chronologic VCS simulator copyright 1991-2023

Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 14:50 2025
Initial state: XX
Next state: S1
Next state: S2
Next state: XX
Next state: IDLE
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.0Mb

75
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE: Enum with Queue and Associative Array

RESULT :
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 14:50 2025
Initial state: XX
Next state: S1
Next state: S2
Next state: XX
Next state: IDLE
VCS Simulation Report
Time: 0 ns
CPU Time: 0.440 seconds; Data structure size: 0.0Mb

76
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

STRUCTURES AND UNIOUNS

STRUCT:
 The disadvantage of arrays is that all the elements stored in then are to be of the Same
data type.
 If we need to use a collection of different data types, it is not possible using an array.
 When we require using a collection of different data items of different data types we
can use a structure.
 Structure is a method of packing data of different types. A structure is a convenient

MEMORY ALLOCATION

Memory Breakdown:

1. int a:
o Size: 4 bytes.
o Offset: 0.
2. byte b:
o Size: 1 byte.
o Offset: 4 (immediately after int a).
3. bit [7:0] c:
o Size: 1 byte.
o Offset: 5 (immediately after byte b).
4. Padding:
o To align the struct to a 4-byte boundary, 2 bytes of padding are added at the
end.
o Offset: 6.

Total Memory Assigned

 Without Padding: 4 (int) + 1 (byte) + 1 (bit) = 6 bytes.

 With Padding: 4 (int) + 1 (byte) + 1 (bit) + 2 (padding) = 8 bytes.

Why Padding is added

 The int type (4 bytes) requires alignment to a 4-byte boundary for efficient memory
access.
 After the int and byte fields, the struct size is 5 bytes, which is not a multiple of 4.
 To ensure proper alignment, 2 bytes of padding are added, making the total size 8
bytes.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

RESULT:
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 15:31 2025
Struct Field Values:
a = deadbeef
b = a5
c = 10101010

Memory Layout:
Field 'a' (int): Size = 4 bytes, Offset = 0
Field 'b' (byte): Size = 1 bytes, Offset = 4
Field 'c' (bit): Size = 1 bytes, Offset = 5
Total Size: 6 bytes (with padding)
VCS Simulation Report
Time: 0 ns
CPU Time: 0.400 seconds; Data structure size: 0.0Mb

78
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

UNIONS

In SystemVerilog, a union is a data structure that allows multiple variables to share the same
memory location. A union can hold one of its members at a time, and all members share the
same memory space. This is useful when you want to store different types of data but do not
need them all to exist simultaneously. The size of the union will be determined by the largest
member.

RESULT “
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 15:51 2025
Integer value: 42
Byte value: ff
Byte array: 01 02 03 04
Integer value after byte array assignment: 131073
VCS Simulation Report

79
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Explanation of the Example:

1. Union Definition: The data union is defined with three members:

o i is a 32-bit integer.
o b is an 8-bit byte.
o byte_arr is an array of 4 bytes.
2. Memory Sharing:
o The union will share the same memory location for i, b, and byte_arr. This
means that when we assign a value to one of the members, the other members
are overwritten.
o For example, after storing a byte array in data.byte_arr, the integer data.i will
hold an undefined value (since it's overwritten by the byte array's memory
location).
3. Display Statements: We display the values of each member of the union one at a time.
Since the union members share the same memory, assigning a value to one member
affects the others.

FEATURE UNION STRUCTURE

Memory Usage Shared memory for all members Separate memory for each member

Size Size of the largest member Sum of sizes of all members

Overwriting Writing to one member overwrites others Members are independent

Use Case Interpret memory in multiple ways Group related data together

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

CAST:
In SystemVerilog, casting refers to converting one data type into another, which can be
important when working with different sizes or types of variables. There are two main kinds
of casting: implicit and explicit.
Convert data type

1. IMPLICIT CASTING

This happens automatically when the data type is compatible, and SystemVerilog will handle
it for you. For example, when you assign a bit (1 bit) to a logic (multiple bits), the conversion
happens implicitly.

bit a;

logic [3:0] b;

a = 1; // Implicit casting from 'bit' to 'logic'

b = a; // Implicit casting

2. EXPLICIT CASTING

Explicit casting is when you need to manually convert one type to another, often using the
cast operator or casting functions like $cast or $signed/$unsigned.

int unsigned a = 8;

shortint b;

b = shortint'(a); // Explicit casting from unsigned int to shortint

Example: Using $cast

This function is used when you want to convert one type to another, and it returns a boolean
indicating success or failure:

Example: Using $signed or $unsigned

You can cast a variable to signed or unsigned types using the $signed or $unsigned system
functions:

logic [7:0] data;

int signed s_data;

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

s_data = $signed(data); // Explicit cast to signed integer

Example: Using $cast

This function is used when you want to convert one type to another, and it returns a boolean
indicating success or failure:

int a = 10;

real b;

if ($cast(b, a)) begin

// Successfully casted

end else begin

// Cast failed

End

Overview of Casting in SystemVerilog

 Loosely Typed Nature of Verilog:

o Verilog allows assignments between different data types based on predefined
rules.
o Compiler only checks if the source and destination are scalars; no strict type
checking is performed.
 Stricter Typing in SystemVerilog:
o SystemVerilog introduces complex data types (e.g., structures, unions,
classes).
o Requires stricter type conversions to ensure data integrity.
 Casting Operator ('):
o Used to explicitly specify the type of an expression.
o Allows assigning values to variables that might not ordinarily be valid due to
differing data types.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

2. TYPES OF CASTING

 Static
 Dynamic

SystemVerilog supports two types of casting:

 If the layout of the bits between source and destination variables are same such as int
& enum cast b/w two values
 if bit layout are different such as array of bytes & words use the streming operators to
rearrange them

STATIC CASTING:
o Performed at compile time.
o Static cast operation converts between two types with n o checking of value
o Uses the casting operator (').
o Syntax: casting_type'(expression).
o Example: int'(2.5) converts the floating-point value 2.5 to an integer.

EXAMPLE:

RESULT
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2 02:53 2025

-------------------------------------------->>>
Static Cast: real 5.700000 -> int 6
-------------------------------------------->>>

VCS Simulation Report

Time: 0 ns
CPU Time: 0.380 seconds; Data structure size: 0.0Mb

Example 2:

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2 03:03 2025

Implicit Casting: a = 1, b = 0001

-------------------------------------------->>>
Explicit Casting: x = 1000, y = 1000

-------------------------------------------->>>
Casting using $signed: s_data = -43

-------------------------------------------->>>
$cast result: r = 123.000000 (success)

-------------------------------------------->>>
VCS Simulation Report
Time: 0 ns
CPU Time: 0.350 seconds; Data structure size: 0.0Mb

84
 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

2. DYNAMIC CASTING:
o Performed at runtime.
o Uses the $cast system task or function.
o Allows handling invalid assignments gracefully.
o Will cover during class explanation

FEATURE STATIC CASTING DYNAMIC CASTING

Timing Compile-time Runtime
Syntax casting_type'(expression) $cast(dest_var, source_exp)
Compile-time error if
Error Handling invalid Runtime error or return value
Complex type conversions (e.g., class
Use Case Basic type conversions hierarchies)

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

OPERATORS
Assignment Operators

Operator Name Example

= Binary assignment int a = 5;
+= Add and assign a += 3; // a = 8
-= Subtract and assign a -= 2; // a = 6
*= Multiply and assign a *= 2; // a = 12
/= Divide and assign a /= 3; // a = 4
%= Modulus and assign a %= 3; // a = 1
&= Bitwise AND and assign a &= 1; // a = 1
` =` Bitwise OR and assign
^= Bitwise XOR and assign a ^= 1; // a = 2
>>= Right shift and assign a >>= 1; // a = 1
<<= Left shift and assign a <<= 1; // a = 2
Arithmetic right shift and
>>>= assign a >>>= 1; // a = 1
Arithmetic left shift and
<<<= assign a <<<= 1; // a = 2

2. Conditional Operator

Operator Name Example

?: Ternary conditional int b = (a > 0) ? 1 : 0; // b = 1

3. Unary Operators

Operator Name Example

+ Unary plus int c = +5; // c = 5

- Unary minus int d = -5; // d = -5

! Logical NOT bit e = !0; // e = 1

~ Bitwise NOT bit f = ~1; // f = 0

& Reduction AND bit g = &4'b1111; // g = 1

~& Reduction NAND bit h = ~&4'b1111; // h = 0

` ` Reduction OR

`~ ` Reduction NOR

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

^ Reduction XOR bit k = ^4'b1010; // k = 0

~^ Reduction XNOR bit l = ~^4'b1010; // l = 1

4. Binary Arithmetic Operators

Operator Name Example

+ Addition int m = 5 + 3; // m = 8

- Subtraction int n = 5 - 3; // n = 2

* Multiplication int o = 5 * 3; // o = 15

/ Division int p = 15 / 3; // p = 5

** Exponentiation int q = 2 ** 3; // q = 8

% Modulus int r = 5 % 3; // r = 2

5. Bitwise Operators

Operator Name Example

bit s = 4'b1010 & 4'b1100; // s

& Bitwise AND = 4'b1000

` ` Bitwise OR

bit u = 4'b1010 ^ 4'b1100; // u

^ Bitwise XOR = 4'b0110

bit v = 4'b1010 ^~ 4'b1100; // v

^~ Bitwise XNOR = 4'b1001

6. Shift Operators

Operator Name Example

bit w = 4'b1010 >> 1;

>> Logical right shift // w = 4'b0101

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

bit x = 4'b1010 << 1;

<< Logical left shift // x = 4'b0100

bit y = 4'sb1010 >>>

>>> Arithmetic right shift 1; // y = 4'sb1101

bit z = 4'sb1010 <<<

<<< Arithmetic left shift 1; // z = 4'sb0100

7. Logical Operators

Operator Name Example

bit aa = 1 && 0;
&& Logical AND // aa = 0

` `

8. Relational Operators

Operator Name Example

bit ac = 5 < 3; //
< Less than ac = 0

bit ad = 5 <= 5; //
<= Less than or equal ad = 1

bit ae = 5 > 3; //
> Greater than ae = 1

bit af = 5 >= 5; //
>= Greater than or equal af = 1

9. Equality Operators

Operator Name Example

bit ag = 5 == 5; //
== Logical equality ag = 1

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bit ah = 5 != 5; //
!= Logical inequality ah = 0

bit ai = 4'b1010
=== 4'b1010; // ai
=== Case equality =1

bit aj = 4'b1010
!== 4'b1010; // aj
!== Case inequality =0

bit ak = 4'b1010
==? 4'b1x1x; // ak
==? Wildcard equality =1

bit al = 4'b1010
!=? 4'b1x1x; // al
!=? Wildcard inequality =0

10. Increment/Decrement Operators

Operator Name Example

int am = 5; am++;
++ Increment // am = 6

int an = 5; an--; //
-- Decrement an = 4

11. Set Membership Operator

Operator Name Example

bit ao = 5 inside
inside Set membership {1, 3, 5}; // ao = 1

12. Distribution Operator

Operator Name Example

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

int ap =
$dist_uniform(1,
10); // ap =
random value
between 1 and
dist Distribution 10

13. Concatenation and Replication Operators

Operator Name Example

bit [7:0] aq =
{4'b1010,
4'b1100}; // aq =
{} Concatenation 8'b10101100

bit [7:0] ar =
{2{4'b1010}}; //
{{}} Replication ar = 8'b10101010

14. Stream Operators

Operator Name Example

bit [7:0] as =
{<<{4'b1010}}; //
{<<{}} Left stream as = 8'b10100000

bit [7:0] at =
{>>{4'b1010}}; //
{>>{}} Right stream at = 8'b00001010

Operator Operation Description

+ Unary Plus No change, used for positive
numbers
- Unary Minus Negates the operand
! Logical NOT Inverts the boolean value (0 -
> 1, non-zero -> 0)

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~ Bitwise NOT Inverts each bit of the
operand
& Bitwise AND AND operation on each bit

` ` Bitwise OR
^ Bitwise XOR XOR operation on each bit
^~ Bitwise XNOR XNOR operation on each bit

<< Logical Left Shift Shifts bits left, fills with 0s

>> Logical Right Shift Shifts bits right, fills with 0s

>>> Arithmetic Right Shift Shifts bits right, preserves

the sign
<<< Arithmetic Left Shift Shifts bits left, preserves the
sign

SUMMARY

 Assignment Operators: Modify and assign values.

 Conditional Operator: Ternary operator for conditional assignments.
 Unary Operators: Operate on a single operand.
 Binary Operators: Perform arithmetic, bitwise, logical, and relational operations.
 Shift Operators: Shift bits left or right.
 Equality Operators: Compare values for equality or inequality.
 Increment/Decrement: Increase or decrease values.
 Set Membership: Check if a value is in a set.
 Concatenation/Replication: Combine or repeat values.
 Stream Operators: Stream bits in a specific direction.

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DIFFERENCE IN BITWISE AND LOGIC

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2 03:38 2025

Bitwise AND: a & b = 00000000000000000000000000001000
Logical AND: c && d = 0

-------------------------------------------->>>
Bitwise OR: a | b = 00000000000000000000000000001110
Logical OR: c || d = 1

-------------------------------------------->>>
Bitwise XOR: a ^ b = 00000000000000000000000000000110
Logical XOR: c ^ d = 1

-------------------------------------------->>>
Bitwise NOT: ~a = 11111111111111111111111111110101

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Logical NOT: !c = 0

-------------------------------------------->>>
Bitwise AND with assignment: a &= b, a = 1000
Logical AND with assignment: c = 0

-------------------------------------------->>>
Bitwise OR with assignment: a |= b, a = 1100
Logical OR with assignment: c = 0

-------------------------------------------->>>
Bitwise XOR with assignment: a ^= b, a = 0000
Logical XOR with assignment: c = 0

-------------------------------------------->>>
Bitwise NOT with assignment: a = ~a, a = 0101
Logical NOT with assignment: c = 1

-------------------------------------------->>>
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

EXAMPLE 2: https://edaplayground.com/x/WtZx

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

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RESULT

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2 03:38 2025

Bitwise AND: a & b = 00000000000000000000000000001000
Logical AND: c && d = 0

-------------------------------------------->>>
Bitwise OR: a | b = 00000000000000000000000000001110
Logical OR: c || d = 1

-------------------------------------------->>>
Bitwise XOR: a ^ b = 00000000000000000000000000000110
Logical XOR: c ^ d = 1

-------------------------------------------->>>
Bitwise NOT: ~a = 11111111111111111111111111110101
Logical NOT: !c = 0

-------------------------------------------->>>
Bitwise AND with assignment: a &= b, a = 1000
Logical AND with assignment: c = 0

-------------------------------------------->>>
Bitwise OR with assignment: a |= b, a = 1100
Logical OR with assignment: c = 0

-------------------------------------------->>>
Bitwise XOR with assignment: a ^= b, a = 0000
Logical XOR with assignment: c = 0

-------------------------------------------->>>
Bitwise NOT with assignment: a = ~a, a = 0101
Logical NOT with assignment: c = 1

-------------------------------------------->>>
VCS Simulation Report

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SYSTEMVERILOG OPERATOR PRECEDENCE (HIGHEST TO LOWEST)

Parentheses () (Highest Precedence):

 Parentheses have the highest precedence and are used to explicitly specify the order of
operations.

Example:

result = (a + b) * c; // The addition is done first because of parentheses

Increment and Decrement Operators (++, --):

 These operators are used to increase or decrease the value of a variable by 1. They
have higher precedence than most operators.

Example:

a++; // Post-increment
++a; // Pre-increment

Bitwise NOT (~), AND (&), OR (|), XOR (^), and their respective Negations (~&, ~|, ~^):

 These are unary and binary bitwise operators. They perform operations at the bit level
and have higher precedence than arithmetic and relational operators.

Example:

result = ~a; // Bitwise NOT of 'a'

result = a & b; // Bitwise AND of 'a' and 'b'
result = a ^ b; // Bitwise XOR of 'a' and 'b'
result = ~&a; // NAND operation

Multiplication (*), Division (/), and Modulus (%):

 These arithmetic operators have higher precedence than addition and subtraction.

Example:

result = a * b; // Multiplication
result = a % b; // Modulus

Addition (+), Subtraction (-):

 These are basic arithmetic operators, and they come after the multiplication, division,
and modulus operators in precedence.

Example:

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result = a + b; // Addition
result = a - b; // Subtraction

Shift Operators (<<, >>):

 These operators perform bitwise shifts (left or right) and have precedence just below
arithmetic operators.

Example:

result = a << 2; // Logical Left Shift

result = a >> 1; // Logical Right Shift

Relational Operators (<, <=, >, >=, in, !in, dist):

 These operators are used to compare values and are evaluated after the arithmetic and
shift operators.

Example:

result = a < b; // Less than comparison

result = a in {1, 2, 3}; // Set membership check

Equality Operators (==, !=, ===, !==, =?=, !?=, ==?, !=?):

 These operators are used to check for equality or inequality. The === and !== are
used for case-sensitive comparison (where x and z values are considered), while ==
and != are more standard.

Example:

result = a == b; // Equality check

result = a !== b; // Case inequality check

Bitwise AND (&), Bitwise AND NOT (&~), XOR (^), XOR NOT (^~), OR (|), OR NOT
(|~):

 These operators are bitwise and have precedence after the relational and equality
operators.

Example:

result = a & b; // Bitwise AND

result = a ^ b; // Bitwise XOR
result = a | b; // Bitwise OR

Logical AND (&&):

 This operator is used for logical comparisons (e.g., in conditional statements) and has
lower precedence than the bitwise AND (&).

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Example:

if (a && b) begin
// Execute code if both 'a' and 'b' are non-zero
end

Logical OR (||):

 This operator performs logical OR and has a lower precedence than logical AND
(&&).

Example:

if (a || b) begin
// Execute code if either 'a' or 'b' is non-zero
end

Ternary Conditional Operator (?:):

 This operator is used to perform conditional assignments or decisions. It has relatively

low precedence.
 Example:

systemverilog
Copy
result = (a > b) ? 1 : 0; // If a > b, result = 1; otherwise 0

Assignment Operators (=, +=, -=, *=, /=, %= etc.):

 These operators are used to assign values and have the lowest precedence.

Example:

a = b; // Simple assignment
a += 5; // Add and assign

Operator Description Precedence Level

() Parentheses (highest 1
precedence)
++, -- Post-increment, pre-increment 2
&, ~&, ` ,~ , ^, ^, ><, -`
*, /, % Multiplication, division, 4
modulus
+, - Addition, subtraction 5
<<, >> Logical left shift, right shift 6
<, <=, >, >=, in, !in, Relational operators (less than, 7
dist greater than)

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=?=, !?=, ==, !=, ===, Equality and inequality 8

!==, ==?, !=? operators
&, &~, ^, ^~, ` , ~`
&& Logical AND 10
` `
?: Conditional (ternary) 12
=, +=, -=, *=, /=, %= Assignment operators 13 (lowest precedence)

EXAMPLE:

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RESULT
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
04:08 2025
Result with parentheses: 16
Post-increment a: 6
Pre-increment b: 4
Bitwise AND: 4
Bitwise OR: 6
Bitwise XOR: 2
Addition with multiplication precedence: 14
Logical Left Shift: 12
Logical Right Shift: 3
Arithmetic Right Shift: 3
a > b: 1
a == b: 0
Logical AND: 1
Logical OR: 1
Ternary conditional (a > b): 1
VCS Simulation Report

Streaming Operators in SystemVerilog

In SystemVerilog, streaming operators are used to manage and manipulate the flow of
bitstreams. These operators allow you to pack and unpack multiple variables into a single
bitstream, and also to reverse the order of the streamed data.

There are two key streaming operators:

1. << (left stream)

2. >> (right stream)

Reordering of the Generic Stream

The order in which blocks of data are streamed is controlled by these streaming operators:

 >>: This operator streams data from left to right, following the usual order of data.
For example, when applied to an array or multiple variables, the values will be packed
or streamed in the original order.
 <<: This operator streams data from right to left, causing a reversal in the order of the
data. It's often used to simulate little-endian packing or to reverse the bits of a data
stream.

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Packing Using Streaming Operators

 Packing is done by using the streaming operators to combine multiple variables into
one single stream. Here, the order of variables can be customized by choosing
between << or >>.

Unpacking Using Streaming Operators

 Unpacking is performed by using the streaming operator on the left-hand side (LHS)
of an expression. This allows you to retrieve multiple values from a single packed
stream of bits.

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Streaming Dynamically Sized Data

When dealing with dynamically sized data, you can pack and unpack content using the
streaming operator. You can specify the size of the streamed data and the specific portions of
the object to include.

 << (left shift/streaming): Streams data in right-to-left order.

 >> (right shift/streaming): Streams data in left-to-right order.
 Unpacking allows extracting multiple variables from a packed stream.
 Dynamic packing/unpacking allows dealing with variable-sized data structures, with
advanced syntax like slicing and with [0 +: n] for specific ranges of data.

These streaming operators provide an elegant and powerful way to manage data transfer,
packing, and unpacking in hardware designs, and they are highly useful in situations where
you need to work with data streams and bit manipulation.

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EVENTS

SystemVerilog Events Overview

 In SystemVerilog, events are primarily used to synchronize different processes, tasks,

or threads in simulation. Events are essential for waiting for specific conditions to
occur and are often used for testbenches, synchronizing signals, and inter-thread
synchronization in complex designs.
 An identifier declared as an event data type is called a named event. Named event is a
data type which has no storage. In verilog, a named event can be triggered explicitly
using "->" . Verilog Named Event triggering occurrence can be recognized by using
the event control "@" . Named events and event control give a powerful and efficient
means of describing the communication between, and synchronization of, two or
more concurrently active processes.
 SystemVerilog named events support the same basic operations as verilog named
event, but enhance it in several ways.

TRIGGERED

 The "triggered" event property evaluates to true if the given event has been triggered
in the current time-step and false otherwise. If event_identifier is null, then the
triggered event property evaluates to false. Using this mechanism, an event trigger
shall unblock the waiting process whether the wait executes before or at the same
simulation time as the trigger operation.

In the following example, event "e" is triggered

Event Declaration and Triggering

 Event Declaration: Events are declared using the event keyword.

 Event Triggering: The -> operator is used to trigger events, which changes the event
status to triggered.

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RESULT :

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb

2 04:51 2025

--------------------------------------->
Event 'my_event' triggered at time 0

--------------------------------------->

VCS Simulation Report

WAITING FOR EVENTS

 SystemVerilog allows a process to wait for an event to be triggered. The @ operator

is used to wait for an event to occur.

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
04:55 2025

--------------------------------------->
Waiting for 'my_event' to be triggered...
Event 'my_event' triggered at time 10
--------------------------------------->

VCS Simulation Report

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The process will block until the event is triggered by another part of the simulation.

TRIGGERED PROPERTY

The .triggered property can be used to check if an event has been triggered during the current
time-step. This property returns true if the event has been triggered, and false otherwise.

Explanation:

 The event e is triggered at time 10.

 We display the status of .triggered at time 15 to show that the event was not triggered
during the time step 15.

1. -> Operator (Event Triggering)

The -> operator triggers the event immediately at the current simulation time. Once triggered,
the event becomes active, and processes waiting on this event can resume.
-> my_event; // Trigger the event 'my_event'

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2

04:59 2025
############################################
Event 'my_event' triggered at time 0

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2. ->> Operator (Event Triggering with a Delay)

The ->> operator also triggers an event, but with a delayed trigger. The event is scheduled to
be triggered at the end of the current simulation time step, allowing other operations in the
same time-step to finish before the event is activated.

->> my_event; // Trigger the event at the end of the current time step

->> my_event; // Trigger the event at the end of the current time step

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
05:02 2025

############################################
Event 'my_event' triggered at time 5
############################################

VCS Simulation Report

The difference between -> and ->> is subtle, but the second operator is used when you want
the event to be triggered after all actions within the current time step are completed.

WAITING FOR AN EVENT TO BE TRIGGERED

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Once an event is triggered, processes or threads can wait for the event to occur. There are
several ways to wait for an event in SystemVerilog:

1. @ Operator (Wait for Event)

The @ operator is used to wait for an event. The process will pause at the @event_name
statement and will only continue execution once the event is triggered.
@my_event; // Wait until 'my_event' is triggered

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
05:04 2025

############################################
Waiting for 'my_event' to be triggered...
Event 'my_event' triggered at time 10
############################################

VCS Simulation Report

Time: 10 ns
CPU Time: 0.470 seconds; Data structure size: 0.0Mb

2. WAIT OPERATOR (WAIT FOR CONDITION)

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The wait operator is used to pause a process until a certain condition (typically an event or a
boolean expression) becomes true. It can be used for both events and other conditions.

wait(my_event.triggered); // Wait until the event 'my_event' is triggered

In this example, the wait operator will pause the process until the .triggered property of
my_event evaluates to true.

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
05:06 2025

############################################
Event 'my_event' triggered at time 10

############################################
VCS Simulation Report

3. WAIT_ORDER() FUNCTION (WAIT FOR MULTIPLE EVENTS)

SystemVerilog provides the wait_order() function to wait for a set of events in a specified
order. This is useful when you need to ensure that certain events are triggered in a specific
order.

wait_order(event1, event2); // Wait for event1 to trigger, then event2

The process will wait until event1 is triggered, and only after that will it proceed to wait for
event2. This is useful when there is a strict order in which events should occur.

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RESULT:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2
05:08 2025
Both events triggered in order.
VCS Simulation Report

MERGING EVENTS IN SYSTEMVERILOG

Merging events means combining multiple events and waiting for all of them to be triggered.
The @ operator can be used for merging multiple events, where the process will block until
all of the listed events are triggered.

@ (event1 or event2 or event3); // Wait for any of these events to be triggered

@ (event1 and event2); // Wait for both event1 and event2 to trigger

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2

05:09 2025

############################################
One of the events triggered at time 5
VCS Simulation Report
Time: 5 ns
CPU Time: 0.400 seconds; Data structure size: 0.0Mb

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Event Example 1: Event Waiting with @ Operator

This example demonstrates how a process waits for an event using the @ operator.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2

05:13 2025
Waiting for the event to be triggered...
Event triggered, continuing execution.
VCS Simulation Report
Time: 10 ns
CPU Time: 0.400 seconds; Data structure size: 0.0Mb

Explanation:

 The first process waits for the event e to be triggered using @e.
 The second process triggers e at time 10.
 When e is triggered, the first process resumes and displays the message that the event
has been triggered.

EVENT EXAMPLE 2: Trigger First, And then Wait for Trigger

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 This example demonstrates how an event can be triggered first and then the process
waits for it to be triggered again

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2

05:15 2025
Event 'e' triggered at time 0
VCS Simulation Report
Time: 0 ns
CPU Time: 0.530 seconds; Data structure size: 0.0Mb

Explanation:

 The event e is triggered immediately using -> e.

 The first $display shows the event was triggered.
 The process then waits for the same event e to be triggered again using @e.
 Once triggered, the second $display shows the event has been triggered a second time.

EVENT SYNCHRONIZATION EXAMPLE

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You can also use events to synchronize different parts of your design. Here’s an example of
two processes that synchronize using events:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 2

05:16 2025
Triggering start event...
Start event triggered, now doing work...
End event triggered, process finished.
VCS Simulation Report
Time: 10 ns
CPU Time: 0.540 seconds; Data structure size: 0.0Mb
Explanation:

 Process 1 waits for the start_event, does some work (simulated with a delay), and then
triggers the end_event.

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 Process 2 triggers the start_event and waits for the end_event.

WORK IN PROGRESS
In progress :
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
Procedural Statements and Flow Control
Index
Blocking

Non-Blocking assignments
Unique-If

Priority-If
while, do-while

foreach

enhanced for loop

repeat,
forever break and continue

Named Blocks,
Statement Labels
disable block and disable statements
Event Control

Processes
Index
fork-join
fork-join_any
fork-join_none

wait-fork
disable-fork

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Tasks and Functions

Index
Tasks
Functions
Argument passing

Import & Export Functions

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Queue for class

Result :

CPU time: .340 seconds to compile + .387 seconds to elab + .321 seconds to link
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 06:19 2025
Packet: id=1, name=Packet1
Packet: id=2, name=Packet2
VCS Simulation Report

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Associative array for class

Result:

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Feb 1 06:23 2025
Key: first
Packet: id=1, name=Packet1
Key: second
Packet: id=2, name=Packet2
VCS Simulation Report

119