SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

DATA TYPES PART-1

LOGIC:

Why logic in system verilog.

 reg is used in Procedural Logic for defining variables that need to hold
their value within procedural blocks.
 Wire is used in Sequential Logic for connecting signals, especially between
sequential elements like flip-flops or memory elements.
 Logic can be used as reg and wire

X UNKNOWN
Z HIGH IMPEDENCE

Aspect Procedural Logic Sequential Logic

reg (used for procedural blocks wire (used for connections in
Data Type like always) sequential logic)
Non-blocking (<=), usually for
Assignment Type Blocking (=) /Non-blocking (<=) registers
Used in always, initial, or final Used in always_ff blocks with
Usage Context blocks clocking

Updates in response to simulation Updates in response to clock

Signal Update events edges (posedge/negedge)

Procedurally driven (sequential

logic, not stored between clock Stateful, stores values between
Behavior cycles) clock cycles

Common Counter, State machine (inside Flip-flops, Registers, Clocked

Example always block) logic

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

SIMPLE CODE:
 Logic data type used for sequential assignment
 Logic data type used for procedural assignment
 Logic used for module & gates

EDA EXAMPLE:
https://edaplayground.com/x/vyxH

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

DEFAULT/RESET/INITIAL VALUES:

Data Type Default Value

int 0
reg x (unknown)
wire z (high impedance)
logic x (unknown)
bit 0
byte 8'bxxxxxxxx
(unknown)
shortint 0
longint 0
real 0
string "" (empty string)
time 0

EDA EXAMPLE:
https://edaplayground.com/x/iG47

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Result

Contains Synopsys proprietary information.

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-
SP2_Full64; Jan 29 03:36 2025
Default value of 'i' (int): 0
Default value of 'b' (reg): x
Default value of 'w' (wire): z
Default value of 'l' (logic): x
Default value of 'bt' (bit): 0
Default value of 'by' (byte): 00000000
Default value of 'si' (shortint): 0
Default value of 'li' (longint): 0
Default value of 'r' (real): 0.000000
Default value of 'str' (string): ""
Default value of 't' (time): 0
VCS Simulation Report

2 STATE AND 4 STATE DATA TYPES

Data Default Bit Width Signed/Unsigned

Type Value

int 0 32 bits Signed

reg x (unknown) Depends on size Can be signed or
(commonly 32 bits) unsigned

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

wire z (high Depends on size Can be signed or

impedance) (commonly 1 bit) unsigned

logic x (unknown) Depends on size Can be signed or

(commonly 1 bit) unsigned

bit 0 1 bit Unsigned

byte 8'bxxxxxxxx 8 bits Unsigned

(unknown)

shortint 0 16 bits Signed

longint 0 64 bits Signed
real 0 64 bits N/A (Floating-point)

string "" (empty Dynamic (variable N/A (Strings are not

string) length) signed/unsigned)

time 0 64 bits Unsigned

2-State vs 4-State Data Types

 2-State means the variable can only represent two values, typically 0 and
1.
o Examples: bit, int, shortint, longint, time, real (and floating-point
types in general).
o These types cannot hold unknown (x) or high-impedance (z) states.
o Signed and unsigned versions of these types exist (like int being
signed, and bit being unsigned by default).
 4-State means the variable can represent four values: 0, 1, x (unknown),
and z (high impedance).
o Examples: reg, wire, logic.
o These types can represent a wider range of logic states, which is
essential for modeling digital circuits where certain conditions may
be undefined or disconnected.

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

o Signed and unsigned versions of these types also exist (like reg
signed [3:0] or wire [7:0]).

How to detect unknown value:

EDA EXAMPLE:

https://edaplayground.com/x/ngS5

Result:
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-
SP2_Full64; Jan 29 04:22 2025
Data value: xx01
The register 'data' contains an unknown value (x or z).
The wire 'signal' contains an unknown value (x or z).
VCS Simulation Report

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Explanation:

1. $isunknown(): This is the SystemVerilog system function used to check

if a signal (of any type like reg or wire) contains an unknown value (x or
z). It returns 1 (true) if the signal contains an unknown value, and 0
(false) if it does not.
2. Test Setup:
o We assign an unknown value (4'bx01) to the data register. The x
in 4'bx01 represents an unknown value.
o We assign a high-impedance value (4'bz) to the signal wire, which
is also an unknown value.
3. Detection:
o We use $isunknown(data) to check if the data register contains any
unknown value (x or z).
o Similarly, we use $isunknown(signal) to check if the signal wire
contains any unknown value.

SIGNED AND UNSIGNED

 Signed data types allow for both positive and negative values (using
two's complement representation).
 Unsigned data types only allow non-negative values.
 SystemVerilog uses signed and unsigned keywords to control the
interpretation of the variables.

Key Points:

1. Unsigned:
o Used for variables that should only hold non-negative values.
o Example: reg [7:0] unsigned_data;
2. Signed:
o Used for variables that can hold both positive and negative values.
o Example: reg signed [7:0] signed_data;
3. Two's Complement Representation:
o SystemVerilog uses two's complement to represent negative
numbers in signed types.
o The MSB (Most Significant Bit) determines the sign: 0 for positive
and 1 for negative.
4. No Implicit Sign:
o If you declare a variable with no explicit signed or unsigned,
SystemVerilog assumes unsigned by default.

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Data Type Signed/Unsigned Value Range Example

(2^n)
bit Unsigned 0 to 1 2^0 = 1
byte Unsigned 0 to 255 2^8 - 1 = 255
shortint Signed -2^15 to 2^15 -2^15 to 2^15
-1 -1
int Signed -2^31 to 2^31 -2^31 to 2^31
-1 -1
longint Signed -2^63 to 2^63 -2^63 to 2^63
-1 -1
reg Can be Depends on Dependent on
signed/unsigned the the bit width
declaration
wire Can be Depends on Dependent on
signed/unsigned the the bit width
declaration

EDA EXAMPLE: https://edaplayground.com/x/ZmqF

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 SYSTEM VERILOG DATA TYPES BY VIKRAM RENESAS

Result:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-

SP2_Full64; Jan 29 04:34 2025
Unsigned data (8'b11111111): 255
Unsigned negative example (-5): 251
Signed data (8'b11111111): -1
Signed negative example (-5): -5
VCS Simulation Report

FINAL CONCLUSION:
Data Default Bit Width Signed/Unsigned 2-State / Floating
Type Value 4-State Point
int 0 32 bits Signed 2-state No
reg x (unknown) Depends Can be signed or 4-state No
on size unsigned
(commonly
32 bits)
wire z (high Depends Can be signed or 4-state No
impedance) on size unsigned
(commonly
1 bit)
logic x (unknown) Depends Can be signed or 4-state No
on size unsigned
(commonly
1 bit)
bit 0 1 bit Unsigned 2-state No
byte 8'bxxxxxxxx 8 bits Unsigned 4-state No
(unknown)
shortint 0 16 bits Signed 2-state No
longint 0 64 bits Signed 2-state No
real 0 64 bits N/A (Floating- 2-state Yes
point)
string "" (empty Dynamic N/A (Strings are N/A No
string) (variable not (Variable
length) signed/unsigned) length)

time 0 64 bits Unsigned 2-state No