NAIL APB PROTOCOL

INTERVIEWS WITH THIS CHEAT

SHEET !!

IMPORTANT INTERVIEW QUESTIONS

CHALLENGING PROGRAMMING QUESTIONS
USEFUL INTERVIEW TIPS
PROJECT IMPLEMENTATION

Prasanthi Chanda
1. Write a Verilog module for an APB Slave interface.

module apb_slave (
input logic PCLK, // APB Clock
input logic PRESETn, // Active low reset
input logic PSEL, // Slave select
input logic PENABLE, // Enable signal
input logic PWRITE, // Write enable
input logic [7:0] PADDR, // Address bus
input logic [31:0] PWDATA, // Write data
output logic [31:0] PRDATA, // Read data
output logic PREADY, // Ready signal
output logic PSLVERR // Error signal
);

logic [31:0] memory [0:255];

always_ff @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn) begin
PRDATA <= 32'b0;
PREADY <= 1'b0;
PSLVERR <= 1'b0;
end else if (PSEL && PENABLE) begin
PREADY <= 1'b1; // Always ready
if (PWRITE)
memory[PADDR] <= PWDATA;
else
PRDATA <= memory[PADDR];
end else begin
PREADY <= 1'b0;
end
end
endmodule
2. Write a UVM monitor to observe APB transactions.

class apb_monitor extends uvm_monitor;

`uvm_component_utils(apb_monitor)

virtual apb_interface vif;

uvm_analysis_port#(apb_transaction) mon_ap;

function new(string name = "apb_monitor", uvm_component

parent);
super.new(name, parent);
mon_ap = new("mon_ap", this);
endfunction

task run_phase(uvm_phase phase);

apb_transaction tr;
forever begin
tr = apb_transaction::type_id::create("tr", this);
@(posedge vif.PCLK);
if (vif.PSEL && vif.PENABLE) begin
tr.addr = vif.PADDR;
tr.write = vif.PWRITE;
tr.data = vif.PWRITE ? vif.PWDATA : vif.PRDATA;
mon_ap.write(tr);
end
end
endtask
endclass
3. Implement an APB Master in Verilog

module apb_master (
input logic PCLK, // Clock
input logic PRESETn, // Active low reset
output logic PSEL, // Slave select
output logic PENABLE, // Enable signal
output logic PWRITE, // Write enable
output logic [7:0] PADDR, // Address bus
output logic [31:0] PWDATA, // Write data
input logic [31:0] PRDATA, // Read data
input logic PREADY, // Ready signal
input logic PSLVERR // Error signal
);
typedef enum logic [1:0] {IDLE, SETUP, ACCESS} state_t;
state_t state, next_state;
always_ff @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn)
state <= IDLE;
else
state <= next_state;
end
always_comb begin
case (state)
IDLE: next_state = PSEL ? SETUP : IDLE;
SETUP: next_state = ACCESS;
ACCESS: next_state = PREADY ? IDLE : ACCESS;
default: next_state = IDLE;
endcase
end
 always_ff @(posedge PCLK) begin
if (state == IDLE) begin
PSEL <= 1'b0;
PENABLE <= 1'b0;
end else if (state == SETUP) begin
PSEL <= 1'b1;
PENABLE <= 1'b0;
end else if (state == ACCESS) begin
PENABLE <= 1'b1;
end
end
endmodule

4. Explain APB timeout handling using Verilog

module apb_timeout (
input logic PCLK, PRESETn, PSEL, PENABLE, PREADY,
output logic timeout
);
int count;
always_ff @(posedge PCLK or negedge PRESETn) begin
if (!PRESETn)
count <= 0;
else if (PSEL && PENABLE && !PREADY)
count <= count + 1;
else
count <= 0;
end
assign timeout = (count > 10); // Timeout if wait exceeds 10
cycles
endmodule
5. What are the key differences between APB, AHB, and AXI?

FEATURE APB AHB AXI

Single cycle per Pipelined, burst-

Data Transfer Burst-based
transaction based

Complexity Simple Moderate High

Throughput Low Medium High

Uses PSEL,
Uses Uses AWVALID,
Handshake PENABLE,
HREADY WVALID, BVALID
PREADY

Medium- High-
Usage Peripherals speed performance
memory memory

APB should be used for low-speed peripherals like UART, I2C,

GPIO, and timers where high throughput is not required.

6. What are the conditions for a successful APB transfer?

A transfer is successful when:
PSEL = 1 (Peripheral is selected).
PENABLE = 1 (Access phase is active).
PREADY = 1 (Peripheral is ready to complete the transaction).
PSLVERR = 0 (No error in the transfer).
7. Write SystemVerilog Assertions (SVA) for APB Protocol
Compliance.
module apb_sva #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32)
(
input logic PCLK,
input logic PRESETn,
input logic PSEL,
input logic PENABLE,
input logic PWRITE,
input logic [ADDR_WIDTH-1:0] PADDR,
input logic [DATA_WIDTH-1:0] PWDATA,
input logic [DATA_WIDTH-1:0] PRDATA,
input logic PREADY,
input logic PSLVERR
);

// Assertion 1: PREADY should be LOW in the setup phase

property pready_low_in_setup;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && !PENABLE) |-> !PREADY;
endproperty
assert property (pready_low_in_setup) else $error("PREADY is
HIGH in setup phase");
 // Assertion 2: PREADY should be HIGH in the access phase if the
transfer is successful
property pready_high_in_access;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && PENABLE) |-> ##1 PREADY;
endproperty
assert property (pready_high_in_access) else $error("PREADY did
not go HIGH in access phase");

// Assertion 3: If PWRITE is HIGH, PWDATA must be stable during

the access phase
property stable_write_data;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && PENABLE && PWRITE) |=> $stable(PWDATA);
endproperty
assert property (stable_write_data) else $error("PWDATA changed
during the access phase");

// Assertion 4: If PWRITE is LOW, PRDATA must be stable during

the access phase
property stable_read_data;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && PENABLE && !PWRITE) |=> $stable(PRDATA);
endproperty
assert property (stable_read_data) else $error("PRDATA changed
during the access phase");
 // Assertion 5: If PREADY is LOW, PENABLE must remain HIGH
until PREADY is HIGH
property penable_hold_till_pready;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && PENABLE && !PREADY) |=> PENABLE;
endproperty
assert property (penable_hold_till_pready) else $error("PENABLE
deasserted before PREADY went HIGH");

// Assertion 6: PENABLE should be LOW during the setup phase

property penable_low_in_setup;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && !PENABLE) |-> !PENABLE;
endproperty
assert property (penable_low_in_setup) else $error("PENABLE is
HIGH in the setup phase");

// Assertion 7: A valid APB transaction should have PSEL = HIGH

and PREADY = HIGH in the access phase
property valid_apb_transaction;
@(posedge PCLK) disable iff (!PRESETn)
(PSEL && PENABLE) |-> ##1 PREADY;
endproperty
assert property (valid_apb_transaction) else $error("APB
transaction did not complete properly");
 // Assertion 8: PSLVERR should only be HIGH when PREADY is
HIGH (error should be valid only when ready)
property pslverr_valid_with_pready;
@(posedge PCLK) disable iff (!PRESETn)
PSLVERR |-> PREADY;
endproperty
assert property (pslverr_valid_with_pready) else $error("PSLVERR
asserted without PREADY HIGH");

endmodule

EXPLANATION OF ASSERTIONS:
PREADY should be LOW during the setup phase.
PREADY should be HIGH during the access phase for a
successful transfer.
PWDATA must remain stable when writing during the access
phase.
PRDATA must remain stable when reading during the access
phase.
PENABLE should remain HIGH if PREADY is LOW (ensures
transfer completion).
PENABLE should be LOW in the setup phase (ensures correct
handshake).
A valid APB transaction should have PSEL=1, PENABLE=1, and
PREADY=1.
PSLVERR should only be HIGH when PREADY is HIGH (ensures
proper error handling).
8. What are the main challenges in verifying an APB interface in a
complex SoC?
Ensuring timing correctness with various slave latencies.
Handling corner cases like unexpected PSEL deassertion.
Debugging protocol violations using assertions (SVA).
Managing multiple masters in multi-layer APB systems.

9. How do you debug an APB protocol violation using waveform

analysis?
Check PSEL, PENABLE, and PREADY timing: Should follow the
two-phase protocol.
Look for glitches in PWDATA during writes (should be stable in
access phase).
Ensure PADDR remains valid when PENABLE=1.
Verify PSLVERR asserts only when PREADY=1.

10. What are the key corner cases in APB verification?

PSEL toggling before transaction completion.

Unexpected deassertion of PENABLE in the middle of a transfer.
PREADY high before PENABLE is asserted.
Consecutive read/write transactions without an idle cycle.

11. What would happen if PSEL is high but PENABLE is never

asserted?
The slave would never complete the transaction.
The system could hang indefinitely.
A timeout mechanism is required in real implementations.
12. Write an APB Read-Write Test Sequence in UVM.

class apb_rw_sequence extends uvm_sequence#(apb_transaction);

`uvm_object_utils(apb_rw_sequence)

function new(string name = "apb_rw_sequence");

super.new(name);
endfunction

virtual task body();

apb_transaction txn;

// Write Transaction
txn = apb_transaction::type_id::create("write_txn");
txn.addr = 8'h20;
txn.wdata = 32'h12345678;
txn.write = 1;
start_item(txn);
finish_item(txn);

// Read Transaction
txn = apb_transaction::type_id::create("read_txn");
txn.addr = 8'h20;
txn.write = 0;
start_item(txn);
finish_item(txn);
endtask
endclass
13. Implement an APB Error-Handling Slave Model.

module apb_err_slave (
input logic PCLK,
input logic PRESETn,
input logic PSEL,
input logic PENABLE,
input logic PWRITE,
input logic [7:0] PADDR,
input logic [31:0] PWDATA,
output logic [31:0] PRDATA,
output logic PREADY,
output logic PSLVERR
);
logic [31:0] mem [0:255];

always_ff @(posedge PCLK or negedge PRESETn) begin

if (!PRESETn) begin
PREADY <= 0;
PSLVERR <= 0;
end else if (PSEL && PENABLE) begin
if (PADDR >= 8'h80) // Invalid Address
PSLVERR <= 1;
else
PSLVERR <= 0;

if (!PWRITE)
PRDATA <= mem[PADDR];
end
end
endmodule
14. How would you handle APB bus contention in a multi-master
environment?
APB is inherently a single-master bus, so direct contention is
not possible.
In a multi-master system, an arbiter must select which master
gets control of the APB bridge.
Arbitration mechanisms include fixed priority, round-robin, and
time-sliced scheduling.

15. How does APB handle clock domain crossing (CDC) issues?

APB typically operates in a single clock domain, but crossing to

other domains requires:
Dual flip-flop synchronizers for single-bit signals (e.g., PSEL,
PREADY).
Asynchronous FIFOs for data transfers between clock
domains.
Handshake protocols when moving control signals.

16. How would you modify APB to support burst transactions?

Introduce a burst counter and allow multiple consecutive

writes/reads.
Add a burst flag to indicate ongoing transactions.
Ensure the slave pre-fetches or prepares data accordingly.
17. What are common APB protocol violations and their root
causes?

VIOLATION ROOT CAUSE

PENABLE asserted
Master design issue (state machine bug).
before PSEL

PADDR changes after

Incorrect address handling in the master.
PENABLE

PREADY stays LOW Slave not responding or incorrect PSEL

indefinitely timing.

PSLVERR asserted Incorrect slave address decoding or

incorrectly invalid access.

18. How do you add a pipelined APB transfer?

Traditional APB is non-pipelined (one transaction at a time).

To pipeline it:
Use pre-fetching: The slave prepares data before PENABLE
assertion.
Use buffered writes: APB master sends multiple write requests
without waiting for PREADY.
Implement a "look-ahead" address decode for faster response.
19. How can you implement a low-latency APB transaction
system?
Reduce slave response time: Optimize PREADY logic to avoid
unnecessary delays.
Use parallel APB bridges: Allow simultaneous transactions.
Optimize APB slave logic: Use zero-wait state memory for faster
read/write.

20. How do you reduce dynamic power consumption in an APB-

based system?
Reduce switching activity: Gate PCLK when APB is idle.
Use low-power APB peripherals: Ensure PSEL and PENABLE
remain low when idle.
Use clock domain gating: Disable PCLK for unused peripherals.

21. How do you implement an APB power management unit

(PMU)?

Add power control registers in APB slaves to enable/disable

functional blocks.
Implement clock gating logic to stop PCLK when no transactions
are happening.
Use voltage scaling: Reduce the supply voltage when the APB
bus is inactive.

22. How do you implement APB transaction priority handling?

Use an APB arbiter that assigns priorities to master requests.
Implement preemption logic: Higher-priority masters interrupt
ongoing low-priority transactions.
23. How do you handle APB bus congestion?
Use multiple APB bridges to distribute traffic.
Implement transaction queuing in the master to handle pending
requests.
Reduce transaction latency by pre-decoding address mapping in
the slave.

24. How would you verify an APB interface using UVM?

Create an APB agent with driver, monitor, and sequencer.

Use a scoreboard to check expected vs actual results.
Write SystemVerilog Assertions (SVA) for APB protocol
compliance.

25. How do you secure APB transactions against unauthorized

access?

Implement access control registers to restrict certain

transactions.
Use an authentication mechanism (e.g., APB register locks).
Add transaction logging to detect illegal memory access.

26. What is the minimum number of cycles required for an APB

write?

Cycle 1: Assert PSEL, PWRITE, and PADDR.

Cycle 2: Assert PENABLE, and wait for PREADY.
27. How do you debug APB protocol violations?

DEBUGGING
VIOLATION POSSIBLE CAUSE
STEPS

PENABLE asserted Master state machine Check FSM

before PSEL bug transitions

PADDR changes Ensure address

Incorrect address latch
after PENABLE is stable

PREADY never
Slave not responding Verify slave logic
asserts

28. What are the methods to handle APB transaction errors?

Use PSLVERR to indicate invalid transactions.
Implement timeout detection if PREADY remains LOW beyond a
certain number of clock cycles.
Generate an interrupt when an invalid address or unsupported
command is detected.
29. How do you design an APB-based real-time clock (RTC)
module?
Store seconds, minutes, hours, and date in APB-mapped
registers.
Use an APB write transaction to set time.
Implement an interrupt mechanism for alarms.
 FINAL NOTE
This document has provided detailed and advanced APB interview
questions along with full solutions, focusing on both theoretical
concepts and practical implementations.

INTERVIEW TIPS:
✅ Understand APB’s role as a simple peripheral bus in AMBA
architecture.
✅ Explain timing diagrams clearly with signal transitions.
✅ Know the handshake mechanism using PSEL, PENABLE, and
PREADY.
✅ Compare APB with AHB and AXI in terms of performance and
use cases.
✅ Demonstrate debugging techniques for APB protocol violations.
CONTACT DETAILS:
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contact ProV Logic :
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Phone : +91 91822 80927
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