Digital IC Design

Combinational MOS Logic Ciruits

Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOH : Va and Vb are low

Solution of this eqn., gives VOH = VDD

Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL :

Assumption: Threshold voltage of the driver transistors are identical

Possible cases for conduction path are:

1. Va = VOH Vb = VOL

2. Va = VOL Vb = VOH

3. Va = VOH Vb = VOH
Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL :

Assumption: Threshold voltage of two transistors are identical

Possible cases for conduction path are:

1. Va = VOH Vb = VOL

2. Va = VOL Vb = VOH

3. Va = VOH Vb = VOH

Case1: Va = VOH Vb = VOL

Driver A ON
Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL : Threshold voltage of two transistors are identical

Possible cases for conduction path are:

1. Va = VOH Vb = VOL

2. Va = VOL Vb = VOH

3. Va = VOH Vb = VOH

For driver A ON case (i)

For driver B ON case (ii)

Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL : Threshold voltage of two transistors are identical

For each driver: We know that

If (W/L) ratios of both drivers are identical i.e., (W/L)A = (W/L)B,

the output voltage VOL for case1 and case 2 will be identical.
Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL : Threshold voltage of two transistors are identical

For case (iii) when both the drivers are ON (linear):

The saturation current in load is the sum of 2 linear region driver current,
i.e.,

Since, VA = VB= VOH , an equivalent driver-to-load ration can be written as:

Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL : Threshold voltage of two transistors are identical

For case (iii) when both the drivers are ON (linear) and load (saturation):

Since, VA = VB= VOH , an equivalent driver-to-load ration can be written as:

Thus, in a 2 input NOR gate circuit with both the inputs tied to logic ‘1’ is replaced
by an nMOS depletion load inverter whose driver-to-load ratio is defined as above.
The output voltage level in this case is then
Digital IC Design

Combinational MOS Logic: Two input depletion load NOR Gate

Calculation of VOL : Threshold voltage of two transistors are identical

Case (iii) : when both the drivers are ON (linear) and load (saturation):

Note that VOL in this case is lower than case (i) and case (ii) where only one input
is logic “1” and gives the worst case condition i.e., the highest possible VOL value.

For the worst case calculations, set

Digital IC Design

Combinational MOS Logic: n input depletion load NOR Gate

Assuming that all input voltages of all driver transistors are identical, i.e.,
VGS,K = VGS for k = 1,2,3 , …….n
Digital IC Design

Combinational MOS Logic

N- input depletion load NOR Gate (Equivalent ckt.)

Digital IC Design

Combinational MOS Logic

Two input depletion load NOR Gate: Transients Analysis
Digital IC Design

Combinational MOS Logic

Two input depletion load NOR Gate: Transients

Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

Note: Substrate bias effect here

as source is not at 0V
Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

When both drivers are high (VOH):

Note: Substrate bias effect

Here as source is not at 0V
Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

When both drivers are high (VOH):

Assuming VT,A = VT,B = VT0 Note: Substrate bias effect

and also neglecting the substrate bias effect Here as source is not at 0V
for transistor A.
Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

When both drivers are high (VOH):

If

Then since
Note: Substrate bias effect here
VOL = VDS, A + VDS,B as source is not at 0V
Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

If we assume VT,A = VT,B = VT0

The linear driver currents:

Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

If we assume VT,A = VT,B = VT0

The linear driver currents:

Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

If we assume VT,A = VT,B = VT0

The linear driver currents:

Since
Digital IC Design

Combinational MOS Logic : Two input depletion load NAND Gate

If we assume VT,A = VT,B = VT0

The linear driver currents:

Since

Final drain current:

Two n-MOS in series with same gate

voltage behaves like one nMOS with
keq= 0.5 kdriver
Digital IC Design

Combinational MOS Logic

N- input depletion load NAND Gate

Digital IC Design

Combinational MOS Logic: Two- input depletion load NAND Gate: Transient

When VA = VOH and

VB changes from
VOH to VOL
Digital IC Design

Combinational MOS Logic: Two- input depletion load NAND Gate: Transient

When VB = VOH and

VA changes from
VOH to VOL
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

Series connection

Parallel connection
Digital IC Design

CMOS Logic: Understanding Series and Parallel connection

Scale both W and L
– no effective change in W/L
– increases gate capacitance

Inputs must be at same value

• Series Transistors
– increases effective L

• Parallel Transistors
– increases effective W
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

Series connection

Parallel connection

Either n-MOS network is ON and pMOS network is OFF, or the pMOS network is ON and nMOS network is OFF
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

Series connection

Parallel connection

When either one or both inputs are high → nMOS ON → VOUT = 0V

Digital IC Design

Combinational MOS Logic: CMOS NOR Gate

Series connection

Parallel connection

When either one or both inputs are high → nMOS ON → VOUT = 0V

When both inputs are low → nMOS OFF pMOS ON → VOUT = VDD
Digital IC Design

Combinational MOS Logic: CMOS NOR Gate

Series connection

Parallel connection

When either one or both inputs are high → nMOS ON → VOUT = 0V

VOL = 0V
When both inputs are low → nMOS OFF pMOS ON → VOUT = VDD
VOH = VDD
Digital IC Design

Combinational MOS Logic: CMOS NOR Gate

Let us have

❑ all aspect ratios to be same

❑ Substrate bias of pMOS is negligible.

Digital IC Design

Combinational MOS Logic: CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

Saturation

saturation
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

Saturation

saturation
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

For nMOS: Saturation

saturation
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

For nMOS: Saturation

Therefore the switching threshold:

saturation
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

For pMOS: Saturation

saturation
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

The output voltage = input voltage at the switching threshold

Linear

For pMOS: Saturation

As
saturation
Thus:
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate
The output voltage = input voltage at the switching threshold

Linear
For pMOS:
Saturation

As

Thus: saturation

Combining both the Vth gives the switching threshold of NOR2,

Digital IC Design

Combinational MOS Logic

CMOS NOR Gate

Difference between switching threshold of CMOS and NOR

inverter Linear

Saturation
For NOR:

saturation
For CMOS:
Digital IC Design

Combinational MOS Logic

CMOS NOR Gate
Linear
Difference between switching threshold of CMOS and NOR inverter,
assuming Saturation

saturation
For NOR:

For CMOS:
Digital IC Design

Combinational MOS Logic: CMOS NOR Gate: Equivalent Circuit

The switching threshold voltage of the NOR2 gate can also be obtained by using the equivalent-
inverter approach. When both inputs are identical, the parallel-connected nMOS transistors can be
represented by a single nMOS transistor with 2kn. Similarly, the series-connected pMOS transistors
are represented by a single pMOS transistor with kP/2.

Switching threshold under such condition is

A CMOS NOR2 gate and its inverter equivalent.

Simple design guidelines: In order to achieve a switching threshold voltage of VDD/2 for
simultaneous switching, we have to set VTn = |VTP| and kp = 4 kn.
Digital IC Design

Combinational MOS Logic

CMOS NAND Gate

Digital IC Design

Combinational MOS Logic

CMOS NAND Gate

A CMOS NAND2 gate and its inverter equivalent.

Digital IC Design

Combinational MOS Logic: CMOS NAND Gate

Digital IC Design

Combinational MOS Logic

MOS Layout
Digital IC Design

Combinational MOS Logic

CMOS NOR2 Layout: N-well technology

Digital IC Design

Combinational MOS Logic

CMOS NOR2 Layout

CMOS NOR2 Stick Diagram

Digital IC Design

Combinational MOS Logic

CMOS NAND2 Layout

Digital IC Design

Combinational MOS Logic: CMOS 2 Input XOR gate

F is not complemented and some of the I\P’s are complemented. We need to do some logic
transformations:

Operator PMOS NMOS

Dot (.) Parallel Series
Plus (+) Series Parallel