Analog Circuits Test 4

Number of Questions: 25 Time: 60 min.

Directions for questions 1 to 25: Select the correct alterna- (A) Voltage series feedback
tive from the given choices. (B) Voltage shunt feedback
1. At higher frequency (>1MHz), the phase shift of an (C) Current series feedback
RC-coupled amplifier is (D) Current shunt feedback
(A) equal to 180o (B) above 180o 6. The cascode amplifier is a multistage configuration of
(C) below 180o (D) None of the above (A) CE-CC (B) CE-CB
2. An amplifier with open loop voltage gain AV = 800 ± 50 (C) CC-CB (D) CB-CC
is available. It is required to have an amplifier whose 7. For FET shown in below figure has VTN = 1.5V,
gain varies by not more than ±0.5%. Find reverse trans- kn = 2 mA/V2. The FET is in saturation and ID = 1mA
mission factor β of the feedback network. then small signal voltage gain AV is
(A) 1.43% (B) 2.5% 10V
(C) 4% (D) 3.7%
3. Below network represents a
8kΩ
C

R +–
VG = 2.5V
–
Vi/p C Vo
+ (A) –64 (B) –32
R (C) 16 D) 48
(A) low pass filter (B) high pass filter 8. Find out output voltage (Vo), assume that the op-Amps
(C) band pass filter (D) band stop filter in below circuit are ideal.
4. Match List-I with List-II where List-I contains type of 20kΩ 80kΩ
+
feedback and List-II have input impedance (Zi/p) and VS = 0.1V
–
output impedance (Zo/p)
80kΩ
List-I List-II –

(p) current series (1) Zi/p increases and Zo/p decreases

V
(q) current shunt (2) Zi/p increases and Zo/p increases +
20kΩ
(r) voltage series (3) Zi/p decreases and Zo/p decreases
(s) voltage shunt (4) Zi/p decreases and Zo/p increases

(A) p–2, q–4, r–1, s–3 (B) p–4, q–2, r–3, s–1
(C) p–3, q–1, r–2, s–4 (D) p–2, q–3, r–4, s–1 (A) 2 V (B) 0.5 V
5. Below circuit configuration indicates which type of (C) –0.5 V (D) –2V
feedback connection? 9. Find output voltage Vo at Vi = 4V for below circuit.
+VCC [Assume that diodes are ideal.]
D1
12kΩ
RB RC

VO
C 8kΩ
D2
–

4kΩ Vo
+
VC ∼ Vi
RE
(A) –12V (B) 16V
(C) 4V (D) –8V
 Analog Circuits Test 4 | 3.169

10. In below Op-Amp circuit, the output voltage (Vo) for (A) –40.5 V (B) 12.5 V
Vi > 0, is proportional to (C) 42.5 V (D) 35 V
15. Find fβ where junction capacitances are Cπ = 25 pF,
Cµ = 8 pF, Cce = 2 pF and β = 150.
R1
Vi – VCC = 12V
Vo
+

30kΩ R1 RC = 4kΩ
R2

1
10 µF
RL
(A) Vi (B) Vi
kV
(C) ln(k Vi) (D) e
i

500Ω 2.5 µF
+ R
11. Differential amplifier is invariably used in input stage ∼
V 20kΩ
of all Op-Amps. This is done to provide the Op-Amp
–
with a very high
(A) open-loop gain (B) Bandwidth
(C) CMRR (D) slew rate
(A) 9.1 MHz (B) 11.13 MHz
12. If the frequency of operation is 0.5 MHz and Op-Amp slew
(C) 30 MHz (D) 20.5 MHz
rate is 0.8 V/µs. Then output Vo is
120kΩ
16. An Op-amp having the following parameters is con-
nected as a non inverting amplifier, A = 2 × 105,
Ri = 5 MΩ, Ro = 150 Ω, fo = 10Hz. Then output imped-
– +15V ance after feedback (R0F) is
Vi 10kΩ Vo
(0.1V) + + VO
–15V + –
(A) more distorted (B) 15V Vin ∼
– 24 kΩ
(C) No distortion (D) –15V 250 Ω

13. Plot gm versus VGS for the JFET, find drain current ID at
2 kΩ
VGS = –4V
gm(S)

5mS

(A) 7.8 mΩ (B) 9.75 mΩ

(C) 2.3 mΩ (D) 3.25 mΩ
17. A dc analysis of the source follower network has
VGSQ = –2.5 V and IDQ = 2.36 mA. Then find voltage
–6V 0 VGS(V) gain AV. [IDSS = 12 mA, VP = –5 V, YOS = 74 μs]
(A) 30 mA (B) 20 mA
+10 V
(C) 1.67 mA (D) 15 mA
14. Output voltage of below circuit is
2kΩ 8kΩ 0.5 µF
+ 0.1 µF +
–5V ∼ 500 kΩ V
Vi
10kΩ 2.2 kΩ –
–

–
Vo
+
(A) 0.48 (B) 0.84
(C) 0.24 (D) 1.2
3.170 | Analog Circuits Test 4

18. For the common-base amplifier, output impedance is 10V

0.5
Io Vo
C M1
4 kΩ 4 kΩ 3 kΩ

+ 6V 12 V M2
VS ∼
–
V2
M3

[∵ hib = 15 Ω, hrb = 88.3 × 10–6, hfb = – 0.9, hob = 0.18 ms]

(A) 5 MΩ (B) 6 MΩ (A) 4.16 (B) 3.67
(C) 7 MΩ (D) 4 MΩ (C) 2.82 (D) 5.32
19. Find total current gain for the system 23. In the following circuit, transistors Q1 and Q2 has the
5 kΩ following parameters. [Transistors are in saturation]
+ Zi = 40 kΩ Zi = 10 kΩ
+5V +5 V
V ∼ Zo = 10 kΩ Zo = 50 kΩ 10 kΩ
AVNL = 250 AVNL = 0.9
50 kΩ 50 kΩ

(A) –497.5 (B) 277.7

(C) –208 (D) 187 Q1 Q2
20. An amplifier with a lower cut-off frequency of
50Hz is to be employed for amplification of square
waves for the tilt on the output waveform not to Va
exceed 5%. The lowest input frequency that can be ↓ 300 µA
amplified is
(A) 2.5 kHz
(B) 3.14 kHz
(C) 10 kHz W  W 
(D) 17.5 kHz   =   = 15
L 1 L 2
21. In below circuit the transistor parameters are (VTh)1 = (VTh)2 = 1 V
VTh = –1.2V and Kn = 0.8 mA/V2 then find drain
current (k ) = (k )
1
n 1
1
n 2 = 75 µA/V2
Then find Va.
+5
(A) 1.365 V (B) –2.14 V
(C) 2.14 V (D) –1.516 V
10 kΩ 1 kΩ 24. The transistor in below circuit is in
Vgsi = 0.7V ,Vgred = 1.8V 

+5 V
5 kΩ 0.8 kΩ

+1 V
–5 V Si

(A) 1.27 mA (B) 1.75 mA

–5 V
(C) 1.55 mA (D) 1.97 mA
22. In below circuit, the EMOSFET parameters are (A) active region
VTh = 1V, VGS = 3V and kn1= 30 µA/V2. If ID = 1 mA, (B) saturation region
V2 = 2V. Then width to length ratio required in (C) cut-off region
EMOSFET M1, is (D) None of the above
 Analog Circuits Test 4 | 3.171

25. Determine the value of VC in above given

20 V network?
(A) 4 V
(B) 6 V
2.2 kΩ (C) 8 V
80 kΩ (D) zero V
IDSS= 8mA
Vp = –8V

10 MΩ Vc

β = 150

20 kΩ 1.8 kΩ

Answer Keys
1. C 2. A 3. C 4. A 5. C 6. B 7. B 8. D 9. B 10. C
11. C 12. A 13. C 14. C 15. A 16. B 17. B 18. A 19. A 20. B
21. B 22. A 23. D 24. A 25. C

Hints and Explanations

1. If f → ∞, capacitors will short circuited then n/w looks
Q like
270

180
–

90° Vi/p 0V
V
100 Hz 0.1 MHz f +
10 Hz

Phase plot for an R-C coupled amplifier Choice (C) R

2. AV = 800 ± 50
∂AF ∂AF ∂A  1  So it represents a band pass filter Choice (C)
= ±0.5% ; =
AF AF A  1 + b A  4. Choice (A)
0.5 50  1  5. The current through RE results in a feedback voltage
⇒ =
100 800  1 + b (800) 
 that opposes the source signal applied, so that Vo is
reduced. It has current series feedback connection.
⇒ β = 1.43%. Choice (A)  Choice (C)
3. If f → 0, capacitor is open circuited then n/w looks 6. CASCODE amplifier is CE – CB configuration.
like  Choice (B)
R 7. AV = –gm RD
⇒ gm = 2k(VGS – VTh)
– ⇒ VGS = 2.5V
Vo So Vo = 0
+ ⇒ gm = 2 × 2 × 10-3 [2.5 – 1.5]
= 4ms
R
AV = –4 × 10-3 × 8 × 103
= –32 Choice (B)
3.172 | Analog Circuits Test 4

8. 2
 4
0.1V ⇒ I D = 15 × 10 −3 1 − 
+ V1 20kΩ 80kΩ  6
Vs
– 15
= × 10 −3 = 1.67mA  Choice (C)
80kΩ 9
0.1V –
14.
Vo 5kΩ
+ 2kΩ 0V V1 8kΩ V0
20kΩ –5V

10k

V1 × 20
0.1V =
80 + 20 –
Vo
V1 = 0.5V +
− RF
⇒ V0 = × V1 = –2V Choice (D)
R1
9. Input is given to positive terminal so output Vo is +ve. 0 − ( −5) 0 − V1 25
KCL at Node 0V is + =0; = V1
The D1 is on and D2 is off 2 5 2
V1 − 0 V1 V1 − V0
12kΩ ⇒ KCL at Node V1 is + + =0
5 10 8
–
4kΩ Vo 1 1 1 V
⇒ V1  + +  = 0
+  5 10 8  8
⇒ Vo = 42.5V Choice (C)
 12 
Vo = Vi 1 +  = 16V Choice (B) 1
 4 15. f b =
2pb re (Cbe + Cbe )
10. Given circuit is logarithmic amplifier
 V  12V
Vo = VT ln  i 
 RS I S 
4kΩ
So Vo a ln(kVi) Choice (C)
11. Differential amplifier reduced common mode gain then
CMRR will increases. Choice (C) β = 150
+
 120  0.7V 500Ω
12. ACL = –  –12 (30//20) kΩ –
 10 
4.8V
SR ≥ ω|ACL|Vi
0.8
10 −6 × 12 × 0.1
≥ω VT
re =
IE
2
⇒w≤ MHz ⇒ fmax = 0.106MHZ
3 IE = 7.0 7mA
Frequency of operation is greater than maximum fre- 25mV
⇒ re = = 3.53
quency so output has distortion. Choice (A) 7.07mA

2 I DSS  VGS  1
fb = = 9.1 MHz
13. gm = 1 −  2p × 150 × 3.53 × (25 + 8) × 10 −12
VP  VP 
 Choice (A)
from graph VP = –6 at VGS = 0V
2 2
5 × 10 −3 × 6 16. Feedback factor is = =
⇒ I DSS = = 15mA 2 + 24 26
2
 VGS 
2 Ro 150
ROF = = = 9.75 mΩ Choice (B)
ID = IDSS 1 −  1 + Ab 1 + 2 × 105 × 2
 VP  26
 Analog Circuits Test 4 | 3.173

2 I DSS  VGSQ  2 × 12  ( −2.5)  5V

17. gm = 1 −  = 5 1 − ( −5)  = 2.4 mS
VP  VP   
1kΩ
g R 2.4 × 10 −3 × 2.2 × 103
AV = m s = VG
1 + g m Rs 1 + 2.4 × 10 −3 × 2.2 × 103
5.28 VS
= = 0.84. Choice (B)
6.28 (10//5)kΩ 0.8kΩ
1
18. ZO = ZL|| Z O 5
V
3
1 –5V
Where Z o =
1
–5V
hob −  h fb hrb (h ib + Rs ) 

VS + 5
1 ID = = k n [VGS ( on ) − VT )2
Zo = = 5 MΩ 0.8k Ω
 ( −0.9) (88.3 × 10 −6 ) 
−6 2
0.18 × 10 −   (VS + 5)  −10 
 ( 0.015 + 4) × 10  = 0.8  − VS + 1.2
3

0.8  3 
 Choice (A) ⇒ VS = –3.6
19. ( −3.6 + 5)10
⇒ ID = mA = 1.75 mA Choice (B)
5k 8
Zo= 10k Zo = 50 kΩ 22.
+ + + + +
AVNL = 250 AVNL = 0.9 10V
Vs ∼ Vi1 Vo1 Vi2 Vo2 10kΩ
– – – – –

M1
Zi1 Z01 Zi2 Zo2
V1 = 5V

Vo1 Zi2 10 × 10 × 250

3
M2
AV1 = = AVNL1 = = 125 V1 +
Vi1 Zi2 + Z o1 (10 + 10) ×103 VGS –
2V
4
RL 10
AV2 = AVNL 2 = 4 × 0.9 = 0.99 M3
RL + Z o2 10 + 50
AVT = AV1 . AV2 = 124.37
40 For every EMOSFET in given problem VGS = VDS and
Zi
⇒ AiT = − AVT = 124.37 × 10 = –497.5 VDS > VGS – VTh so all are in saturation region
RL
VGS 2 = 3 = VDS 3
 Choice (A)
p fL 5 VGS 1 = VGS 2 + 2 = 5V
20. <
f 100 ⇒ VGS 1 = 5V
100p × 50 30 × 10 −6 W 
⇒ < f; 3.14 kHz < f Choice (B) 1mA = ID = [5 − 1]2  
5 2  L 1

5×5 5 W 
21. Vth = = V 1 × 10–3 = 15 × 10–6 × 16 ×  
15 3  L 1
5 W 
5 + VG = ⇒ 4.16 =    Choice (A)
3  L 1
−10
VG = V 23. Va = –VGS
3 Both transistors have same parameters so current flow
VGS = VG – VS in each transistor is equal to 150 µA
3.174 | Analog Circuits Test 4

+5V +5V 25. Reducing the network to

20V
50kΩ 50kΩ
2.2k

Q1 Q2
+
VGS – Vc
10MΩ
Va +
↓ 300µA
VB –

16kΩ
1.8kΩ

−6
(k )  WL 
1
n 4V
I D = 150 × 10 = (VGS − 1)2
2
4 − 0.7
⇒ 300 × 10 = 75 × 10–6 × 15 (VGS – 1)2
–6
βRE > 10R2 so IC =
1.8k Ω
20
⇒ + 1 = VGS = 1.516 = –Va 3.3
75 = mA = 1.83mA
1.8
⇒ Va = –1.516. Choice (D) IC = ID = IS = 1.83 mA
24. Si diode is ON but other diode is off 2
 VGS 
5V ID = IDSS 1 − 
off  VP 
2
 V 
1V red ⇒ 1.8 = 8 1 + GS 
0.7V  8 
on
-5V ⇒ VGS = –4.02 ⇒ KVL at VB to VC
VGS + VC = VB
So transistor is in active region Choice (A) VC = 4 + 4.02 ≃ 8V. Choice (C)