RT1719

Sink Only USB Type-C PD Controller

General Description Features
⚫ PD 2.0 and 3.0 Compatible
The RT1719 is a USB Type-C controller that complies
⚫ Attach/Detach Detection as Device
with the latest USB Type-C and PD standards. It does
⚫ Current Capability Definition
the USB Type-C detection including attach and
⚫ Data Role Support
orientation. The RT1719 integrates the physical layer of
⚫ Dead Battery Support
the USB BMC power delivery protocol to allow up to
⚫ Simple I2C Interface with AP or EC
100W of power. The BMC PD block supports the full
⚫ BIST Mode Supported
Type-C specification.

Ordering Information Applications

⚫ Cameras
RT1719 ⚫ Printers
Package Type ⚫ Toys
QW : WQFN-20L 3.5x3.5 (W-Type) ⚫ Drones
Lead Plating System ⚫ Handheld Devices
G : Green (Halogen Free and Pb Free) ⚫ Sink Devices

Note :
Richtek products are :
 RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes.

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RT1719
Marking Information Pin Configuration
29= : Product Code
(TOP VIEW)
YMDNN : Date Code
29=YM

Table_SEL
DNN

IRQB
SCL
NC

NC
20 19 18 17 16

SDA 1 15 PATH_EN
NC 2 14 Indication
PSEL2 3 GND 13 USB_SET
PSEL1 4 12 ADDR
21
Path_Opt 5 11 VBUS

6 7 8 9 10

GND
CC1
VBIAS
CC2
VCAP
WQFN-20L 3.5x3.5

Functional Pin Description

Pin No. Pin Name Pin Function
I2Cserial data signal to be connected to the I2C master.
1 SDA Please connect 1k to GND if I2C is not used.
2, 17, 19 NC No internal connection.
Power selection 2 for power data object. Please use the 1% resistor for
3 PSEL2
setting.
Power selection 1 for power data object. Please use the 1% resistor for
4 PSEL1
setting.
5 Path_Opt Power path option. Please use the 1% resistor for setting.
6, Ground pin. The exposed pad must be connected to GND and be well
GND
21 (Exposed Pad) soldered to a large copper PCB for maximum power dissipation.
Type-C connector configuration channel (CC) pins. Initially used to
7 CC1
determine when an attach has occurred and what the orientation detected.
8 VBIAS Put a 0.1F (0402/50V) capacitor. This pin cannot drive external load.
Type-C connector configuration channel (CC) pins. Initially used to
9 CC2
determine when an attach has occurred and what the orientation detected.
10 VCAP Put a 1F capacitor. This pin cannot drive external load.
11 VBUS VBUS input pin for attach/detach detection and supply input.
Address selection node when used with multiple Type-C ports. Please use
12 ADDR
the 1% resistor for setting.
13 USB_SET USB ability setting node. Please use the 1% resistor for setting.
14 Indication The power data object does not match the indication pin.
15 PATH_EN Open-drain gate driver. which may be used to drive an PMOS.
Interrupt output, active-low open-drain, to prompt the processor to read the
16 IRQB
registers. Please connect 1k to GND if IRQB is not used.

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 RT1719
Pin No. Pin Name Pin Function
18 Table_SEL Power data object table selection
I2C serial clock signal to be connected to the I2C master.
20 SCL
Please connect 1k to GND if I2C is not used.

Typical Application Circuit

Q1
To System
R10 C7

VBUS R11
C6 R12
To VCAP or
C5 C2 3.3V
4.7μF 1μF/10V
Type-C Receptacle

11 15 10 R8
VBUS PATH_EN VCAP 1MΩ
VBUS
16
IRQB
CC1 7 20
CC1 SCL To MCU R9
C3 1
SDA
330pF D1

RT1719 14 Q2
CC2 9 Indication
CC2 R6
C4 5
Path_Opt R7
330pF
R5 1MΩ
6, 13
USB_SET
21 (Exposed Pad) R4
GND 12
ADDR
PSEL1 PSEL2 Table_SEL VBIAS
4 3 18 8 C1
R3 0.1μF
R1 R2
10kΩ 50V/0402

To VCAP or
GND

Note :
1. R1, R2, R4, R5 and R6 depend on system design. Please use the 1% resistor for setting.
2. R9 depends on the D1 at VBUS = 5V.
3. R10, R11, R12, C6 and C7 depend on the soft-start for power path.

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RT1719
Functional Block Diagram

VBUS VCAP SCL SDA IRQB ADDR USB_SET

Regulator USB
Setting
2
I C & IRQ
Vbus Detection
and Discharge

PATH_EN
CC1 CC Logic and
PHY
CC2 Sink Power Setting Indication

Path_Opt
ESD Bias

VBIAS GND PSEL1 PSEL2 Table_SEL

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 RT1719
Absolute Maximum Ratings (Note 1)
⚫ VBUS -------------------------------------------------------------------------------------------------------------------- −0.3V to 28V
⚫ CC1, CC2, PATH_EN,VBIAS ------------------------------------------------------------------------------------- −0.3V to 24V
⚫ VCAP, Indication, Path_Opt, USB_SET, ADDR -------------------------------------------------------------- −0.3V to 6V
⚫ SDA, SCL, IRQB, PSEL1, PSEL2, Table_SEL --------------------------------------------------------------- −0.3V to 6V
⚫ Power Dissipation, PD @ TA = 25°C
WQFN-20L 3.5x3.5 -------------------------------------------------------------------------------------------------- 3.5W
⚫ Package Thermal Resistance (Note 2)
WQFN-20L 3.5x3.5, θJA -------------------------------------------------------------------------------------------- 28.5C/W
WQFN-20L 3.5x3.5, θJC -------------------------------------------------------------------------------------------- 7.2C/W
⚫ Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260C
⚫ Junction Temperature ----------------------------------------------------------------------------------------------- 150C
⚫ Storage Temperature Range -------------------------------------------------------------------------------------- −65C to 150C
⚫ ESD Susceptibility (Note 3)
HBM (Human Body Model)
VBUS, CC1, CC2 ----------------------------------------------------------------------------------------------------- ±4kV
Other Pins -------------------------------------------------------------------------------------------------------------- ±2kV
VBUS, CC1, CC2 (IEC 61000-4-2 Contact Discharge) ----------------------------------------------------- ±8kV
VBUS, CC1, CC2 (IEC 61000-4-2 Air Discharge) ------------------------------------------------------------ ±15kV
VBUS, CC1, CC2 (IEC 61000-4-5 Surge) ---------------------------------------------------------------------- ±28V

Recommended Operating Conditions (Note 4)

⚫ VBUS Input Voltage ----------------------------------------------------------------------------------------------- 3V to 22V
⚫ Ambient Temperature Range------------------------------------------------------------------------------------ −40C to 85C
⚫ Junction Temperature Range ----------------------------------------------------------------------------------- −40C to 125C

Electrical Characteristics
(TA = 25C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Common Normative Signaling Requirements
Bit Rate fBitRate VBUS = 3V to 22V 270 300 330 kbps
Common Normative Signaling Requirements for Transmitter
Maximum difference
between the bit-rate
during the part of the
pBitRate VBUS = 3V to 22V -- -- 0.25 %
packet following the
Preamble and the
reference bit-rate
Time from the end of last
bit of a Frame until the
tInterFrameGap VBUS = 3V to 22V 25 -- -- s
start of the first bit of the
next Preamble

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RT1719
Parameter Symbol Test Conditions Min Typ Max Unit
Time before the start of
the first bit of the
Preamble when the tStartDrive VBUS = 3V to 22V −1 -- 1 s
transmitter shall start
driving the line
BMC Common Normative Requirements
Time to cease driving the
line after the end of the tEndDriveBMC VBUS = 3V to 22V -- -- 23 s
last bit of the Frame
VBUS = 3V to 22V
10% and 90% amplitude points,
Fall Time tFall 300 -- -- ns
minimum is under an unloaded
condition.
Time to cease driving the
line after the final high-to- tHoldLowBMC VBUS = 3V to 22V 1 -- -- s
low transition
VBUS = 3V to 22V
10% and 90% amplitude points,
Rise Time tRise 300 -- -- ns
minimum is under an unloaded
condition.
Voltage Swing VSwing VBUS = 3V to 22V 1.05 1.125 1.2 V
Transmitter Output
zDriver VBUS = 3V to 22V 33 -- 75 
Impedance
Receiver Input Impedance zBmcRx VBUS = 3V to 22V 1 -- -- M
Power Consumption
VBUS = 3V to 22V. I2C and IRQB
-- 130 180
are not used.
Idle Mode IiIdle_Sink A
VBUS = 3V to 22V. I2C and IRQB
-- 160 300
pull high voltage is 3.3V.
Sink current consumption in
cable attached and CC send
BIST
BIST Mode IBIST -- 5.5 6.5 mA
VBUS = 3V to 22V.
I2C and IRQB pull high voltage is
3.3V.
Type-C Port Control
UFP Rd Rd VBUS = 3V to 22V 4.59 5.10 5.61 k
UFP Pull-Down Voltage in
Dead Battery under DFP VDB_80A 0.25 -- 1.5 V
80A
UFP Pull-Down Voltage in
Dead Battery under DFP VDB_180A 0.45 -- 1.5 V
180A
UFP Pull-Down Voltage in
Dead Battery under DFP VDB_330A 0.85 -- 2.45 V
330A

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 RT1719
Parameter Symbol Test Conditions Min Typ Max Unit
VBUS Port Control
VBUS High Voltage Bound
VHV20 21.85 23 24.15 V
for 20V
VBUS Low Voltage Bound
VLV20 15.975 16.9 17.75 V
for 20V
VBUS High Voltage Bound
VHV15 16.15 17 17.85 V
for 15V
VBUS Low Voltage Bound
VLV15 11.7 12.35 13 V
for 15V
VBUS High Voltage Bound
VHV12 13.3 14 14.7 V
for 12V
VBUS Low Voltage Bound
VLV12 9.135 9.6 10.18 V
for 12V
VBUS High Voltage Bound
VHV09 9.975 10.5 11.025 V
for 9V
VBUS Low Voltage Bound
VLV09 6.57 6.93 7.36 V
for 9V
VBUS High Voltage Bound
VHV05 5.7 6 6.3 V
for 5V
VBUS_PRESENT Voltage VBUS_PRESENT
VBUS rising 3.7 3.85 4 V
Rising Threshold _rising

VBUS_PRESENT Voltage VBUS_PRESENT

VBUS falling 3.4 3.5 3.6 V
Falling Threshold _Falling

IRQB Low-Level Output Voltage

IRQB Low-Level Output
VIRQB_OL IIRQB_OL = 4mA -- -- 0.4 V
Voltage
VCAP
Voltage at VCAP VCAP2 VBUS ≥ 5V, no load. 4.3 -- 5 V
Indication
VCAP
Output Voltage High-Level VOH With 1M resistance load -- VCAP V
-1
Output Voltage Low-Level VOL IOL = 4mA -- -- 0.4 V
Table_SEL
VCAP
Input Voltage High-Level VIH -- -- V
x 0.75
VCAP
Input Voltage Low-Level VIL -- -- V
x 0.25
Input Leakage Current IIN_Leakage −1 -- 1 A
PATH_EN
PATH_EN Low-Level
VPATHE_EN OL IPATH_EN_OL = 800A -- -- 0.4 V
Output Voltage
I2C Electrical Characteristics
I2C Bus Pulled Voltage VI2C_Hi 1.8 -- 3.6 V

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RT1719
Parameter Symbol Test Conditions Min Typ Max Unit
Low-Level Input Voltage VIL VBUS = 3V to 22V -- -- 0.4 V
High-Level Input Voltage VIH VBUS = 3V to 22V 1.26 -- -- V
Low-Level Output Voltage VOL VBUS = 3V to 22V, open-drain -- -- 0.4 V
VBUS = 3V to 22V
Input Current Each IO Pin II −10 -- 10 A
0.1VDD < VI < 0.9VDDMAX
SCL Clock Frequency fSCL VBUS = 3V to 22V 100 -- 2000 kHz
Pulse width of spikes that
must be suppressed by tSP VBUS = 3V to 22V -- -- 50 ns
the input filter
Data Hold Time tHD:DAT VBUS = 3V to 22V 30 -- -- ns
Data Set-Up Time tSU:DAT VBUS = 3V to 22V 50 -- -- ns

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-
conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. JC is measured at the exposed pad
of the package.
Note 3. Devices are ESD sensitive. Handling precautions are recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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 RT1719
Register Map

Register
Address Length Bit Bit Name Default Type Description
Name
PD_CC1/PD_CC2 VDET resistor force
off control for CMP detection
CMPEN_
7 1 RW 0 : Turn off CMPEN_VDET_CCx
VDET_CC
1 : Keep HW behavior, turn on when
present normal mode RD. (default)
Enable VBUS short to CC1 and CC2
detection. Individual interrupt is
generated when CC1 or CC2
CMPEN_
voltage is > 3.45V.
6 VBUS_TO_ 0 RW
0 : Disable CC1 and CC2 short to
CC
VBUS detection. (default)
1 : Enable CC1 and CC2 short to VBUS
detection.
PATH_CTRL pin from register setting.
0 : PATH_CTRL pin from HW control
PATHCTRL_M
5 0 RW (default)
ODE
1 : PATH_CTRL pin from register
setting.
PATH_CTRL pin's register setting.
0x00 1 CC_CTRL PATHCTRL_E
4 0 RW 0 : Disable VBUS power path (default)
N
1 : Enable VBUS power path
CC control from register setting.
0 : CC control from HW control.
3 CC_MODE 0 RW
(default)
1 : CC control from register setting
Orientation setting when CC_MODE =
1
0 : Monitor the CC1 pin for BMC
PLUG_ communications if PD messaging is
2 0 RW
ORIENT enabled. (default)
1 : Monitor the CC2 pin for BMC
communications if PD messaging is
enabled.
CC2 role setting when CC_MODE = 1
1 CC2 1 RW 0 : Open (Disconnect or don’t care)
1 : Rd (default)
CC1 role setting when CC_MODE = 1
0 CC1 1 RW 0 : Open (Disconnect or don’t care)
1 : Rd (default)

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RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
FORCE_DISC 0 : Disable forced discharge (default)
7 0 RW
_EN 1 : Enable forced discharge of VBUS.
BLEED_DISC_ 0 : Disable bleed discharge (default)
6 0 RW
EN 1 : Enable bleed discharge of VBUS
Auto enable Force Discharge when CC
detach and VBUS <
VBUSDISC VBUS_SNK_DISCONNECT till
0x01 1
_CTRL AUTO_DISC_ 650ms timeout or FORCE_DISC_EN =
5 1 RW
EN 1 (0x01[7]) or VBUS_PRESENT go
High
0 : Disable
1 : Enable (default)
4 Reserved 0 R Reserved
3:0 Reserved 0000 RW Reserved
Initiated Date Role Swap request to
source. To request change data role
from DFP to UFP or UFP to
DFP is controlled by MCU.
Requesting Data Role Swap when
USBSET configuration to not a dual
role data will trigger
7 TX_DRSWAP 0 RW
INT_I2C_ERR.
Requesting Data Role Swap when
TXNG(RP 1.5A) and negotiated at
PD3.0 will trigger INT_I2C_ERR.
0 : No DR_Swap sent. (default)
1 : DR_Swap sent and then 0x03[7]
returns to 0b.
6:5 Reserved 01 RW Reserved
Enable Source Cap evaluation based
0x03 1 TX_CTRL1 on the REQ_SRCPDO_NO (0x03[2:0])
or MCU selected capability
EVASCAP_
4 0 RW instead of PSEL.
MODE
0 : Evaluation per PSEL setting.
(default)
1 : Evaluation per register setting.
3 Reserved 0 RW Reserved
Selected SRCPDO number in the
request message which is initiated by
TX_SPDO_REQ.
Set to 000 or invalid object number will
REQ_ trigger INT_I2C_ERR when set
2:0 000 RW
SRCPDO_NO TX_SPDO_REQ = 1
000 : No PDO selected (default)
001 : Select the first PDO.
…
111 : Select the seventh PDO.

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 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Set EVASCAP_MODE = 1 (0x03[4])
when try to initiate Request message to
source.
Initiated Fixed power supply Request of
select SRCPDO (0x03[2:0]) to source.
When initiated, it will update Sink
Capabilities to 2 objects which contain
5V/PSEL_5V current and selected SRC
PDO's voltage/current when
TX_SPDO_
7 0 RW REQ_SRCPDO_NO not 1. Or update
REQ
Sink Capabilities to 1
object which is the same as 1st SRC
PDO when REQ_SRCPDO_NO = 1.
Requesting TX_SPDO_REQ when
TXNG (RP 1.5A) and negotiated at
PD3.0 will trigger INT_I2C_ERR.
0 : No Request sent. (default)
0x04 1 TX_CTRL2 1 : Request sent and then 0x04[7]
returns to 0b.
Initiated Get_Source_Cap request to
source.
Requesting Get_Source_Cap when
TX_SRCCAP_ TXNG(RP 1.5A) and negotiated at
6 0 RW
REQ PD3.0 will trigger INT_I2C_ERR.
0 : No Get_Source_Cap sent. (default)
1 : Get_Source_Cap sent and then
0x04[6] returns to 0b.
5:1 Reserved 00000 R Reserved
HIGHER_CAP field in the Request
message which is initiated by
REQ_
0 0 RW TX_SPDO_REQ (0x04[7]).
HIGHER_ CAP
0 : No higher cap needed (default)
1 : Higher cap needed

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RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
7:5 Reserved 000 RW Reserved
4 Reserved 0 R Reserved
ADDR pin de-bounce result after power
on.
LAT_ADR_
3 0 R 0 : De-bounce timeout. The slave ID is
RDY
0x40 in 7-bit. (default)
1 : De-bounce success
Path_Opt pin de-bounce result after
power on.
LAT_PATH_
2 0 R 0 : De-bounce timeout. PATH_EN in off
RDY
state (default)
1 : De-bounce success
PINDEB_
0x0D 1 USB_SET pin de-bounce result after
INFO
power on.
LAT_USB_ 0 : De-bounce timeout. USB Comm
1 0 R
RDY capability and Dual Data Role are not
supported (default)
1 : De-bounce success
PSEL1/PSEL2/TABLE_SET pin de-
bounce result after power on.
0 : De-bounce timeout. PD Comm
LAT_PSEL_ capability is not supported and
0 0 R
RDY PATH_EN is off if Path_Opt is 0 or 1.
(Table_SEL, PSEL2, PSEL1) =
(0,111,111) (default)
1 : De-bounce success
7:4 Reserved 0000 R Reserved
Indication of No-RP Source attached.
And it's current capability (5V/500mA)
POLICY_ VBUSONLY_
0x0E 1 3 0 R not meet Sink requirement.
INFO MIS
0 : No No-RP Source attached (default)
1 : No-RP Source attached
2:0 Reserved 000 R Reserved

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 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Indication of how many Source PDOs is
7:5 SPDO_NUM 000 R
received.
Indication of VBUS only attached last
over 300ms.
ATTACH_
4 0 R 0 : Not in attached VBUS state.
VBUS
(default)
1 : In attached VBUS state.
3 Reserved 0 R Reserved
Indication of Type-C is in Attached as
Debug Accessory State.
TYPECATT ATTACH_
0x0F 1 2 0 R 0 : Not in debug accessory state
ACH_INFO DBG
(default)
1 : In debug accessory State
Indication of Type-C is in Attached as
Sink State.
ATTACH_
1 0 R 0 : Not in attached as Sink state
SNK
(default)
1 : In attached as Sink State
Indication of Type-C current capability
not meet Sink requirement.
0 TYPEC_MIS 0 R
0 : No mismatch with Source (default)
1 : Mismatch with Type-C-Only Source
Attached polarity, updated when enter
entered into attached_snk state from
attachedwait_state.
7 POLARITY 0 R
Detection apply for signal RP only.
0 : CC1 (default)
1 : CC2
current data role after Type-C attached.
6 DATA_ROLE 0 R 0 : UFP (default)
PDATTACH 1 : DFP
0x10 1
_INFO Negotiated PD SPEC
00 : Revision 1.0 (default)
USBPD_SPEC
5:4 00 R 01 : Revision 2.0
REV
10 : Revision 3.0
11 : Reserved
3 SPDO_MIS 0 R Indication of capability mismatch.
Indication of which SRCPDO is been
2:0 SPDO_SEL 000 R
used.
Received SRCCAP message and
SRCPDO1_
0x11 1 7:0 SRCPDO1_0 00000000 R stored OBJ1 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO1_
0x12 1 7:0 SRCPDO1_1 00000000 R stored OBJ1 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO1_
0x13 1 7:0 SRCPDO1_2 00000000 R stored OBJ1 content, reset when Type-
2
C detached.

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RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Received SRCCAP message and
SRCPDO1_
0x14 1 7:0 SRCPDO1_3 00000000 R stored OBJ1 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO2_
0x15 1 7:0 SRCPDO2_0 00000000 R stored OBJ2 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO2_
0x16 1 7:0 SRCPDO2_1 00000000 R stored OBJ2 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO2_
0x17 1 7:0 SRCPDO2_2 00000000 R stored OBJ2 content, reset when Type-
2
C detached.
Received SRCCAP message and
SRCPDO2_
0x18 1 7:0 SRCPDO2_3 00000000 R stored OBJ2 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO3_
0x19 1 7:0 SRCPDO3_0 00000000 R stored OBJ3 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO3_
0x1A 1 7:0 SRCPDO3_1 00000000 R stored OBJ3 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO3_
0x1B 1 7:0 SRCPDO3_2 00000000 R stored OBJ3 content, reset when Type-
2
C detached.
Received SRCCAP message and
SRCPDO3_
0x1C 1 7:0 SRCPDO3_3 00000000 R stored OBJ3 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO4_
0x1D 1 7:0 SRCPDO4_0 00000000 R stored OBJ4 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO4_
0x1E 1 7:0 SRCPDO4_1 00000000 R stored OBJ4 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO4_
0x1F 1 7:0 SRCPDO4_2 00000000 R stored OBJ4 content, reset when Type-
2
C detached.
Received SRCCAP message and
SRCPDO4_
0x20 1 7:0 SRCPDO4_3 00000000 R stored OBJ4 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO5_
0x21 1 7:0 SRCPDO5_0 00000000 R stored OBJ5 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO5_
0x22 1 7:0 SRCPDO5_1 00000000 R stored OBJ5 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO5_
0x23 1 7:0 SRCPDO5_2 00000000 R stored OBJ5 content, reset when Type-
2
C detached.

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 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Received SRCCAP message and
SRCPDO5_
0x24 1 7:0 SRCPDO5_3 00000000 R stored OBJ5 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO6_
0x25 1 7:0 SRCPDO6_0 00000000 R stored OBJ6 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO6_
0x26 1 7:0 SRCPDO6_1 00000000 R stored OBJ6 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO6_
0x27 1 7:0 SRCPDO6_2 00000000 R stored OBJ6 content, reset when Type-
2
C detached.
Received SRCCAP message and
SRCPDO6_
0x28 1 7:0 SRCPDO6_3 00000000 R stored OBJ6 content, reset when Type-
3
C detached.
Received SRCCAP message and
SRCPDO7_
0x29 1 7:0 SRCPDO7_0 00000000 R stored OBJ7 content, reset when Type-
0
C detached.
Received SRCCAP message and
SRCPDO7_
0x2A 1 7:0 SRCPDO7_1 00000000 R stored OBJ7 content, reset when Type-
1
C detached.
Received SRCCAP message and
SRCPDO7_
0x2B 1 7:0 SRCPDO7_2 00000000 R stored OBJ7 content, reset when Type-
2
C detached.
Received SRCCAP message and
SRCPDO7_
0x2C 1 7:0 SRCPDO7_3 00000000 R stored OBJ7 content, reset when Type-
3
C detached.
0 : Interrupt masked (default)
7 M_VBUS_HV 0 RW
1 : Interrupt unmasked
M_VBUS_ 0 : Interrupt masked (default)
6 0 RW
DCT 1 : Interrupt unmasked
M_VBUS_ 0 : Interrupt masked (default)
5 0 RW
PRESENT 1 : Interrupt unmasked
M_VBUS_TO_ 0 : Interrupt masked (default)
4 0 RW
CC2 1 : Interrupt unmasked
0x2D 1 MASK1 M_VBUS_TO_ 0 : Interrupt masked (default)
3 0 RW
CC1 1 : Interrupt unmasked
M_PE_SNK_R 0 : Interrupt masked (default)
2 0 RW
DY 1 : Interrupt unmasked
M_TYPC_
0 : Interrupt masked (default)
1 ATTACH_ 0 RW
1 : Interrupt unmasked
SNK
M_CC_ 0 : Interrupt masked (default)
0 0 RW
CHANGE 1 : Interrupt unmasked

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15
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
M_DRSW_ 0 : Interrupt masked (default)
7 0 RW
ACCEPT 1 : Interrupt unmasked
M_DRSW_ 0 : Interrupt masked (default)
6 0 RW
REJECT 1 : Interrupt unmasked
M_DRSW_ 0 : Interrupt masked (default)
5 0 RW
WAIT 1 : Interrupt unmasked
M_DRSW_ 0 : Interrupt masked (default)
4 0 RW
TIMEOUT 1 : Interrupt unmasked
0x2E 1 MASK2
M_REQ_ 0 : Interrupt masked (default)
3 0 RW
ACCEPT 1 : Interrupt unmasked
M_REQ_ 0 : Interrupt masked (default)
2 0 RW
REJECT 1 : Interrupt unmasked
M_REQ_ 0 : Interrupt masked (default)
1 0 RW
WAIT 1 : Interrupt unmasked
M_GSRCCAP 0 : Interrupt masked (default)
0 0 RW
_SENT 1 : Interrupt unmasked
M_RX_DRSW 0 : Interrupt masked (default)
7 0 RW
_ACCEPT 1 : Interrupt unmasked
M_RX_DRSW 0 : Interrupt masked (default)
6 0 RW
_REJECT 1 : Interrupt unmasked
M_RX_ 0 : Interrupt masked (default)
5 0 RW
SRCCAP 1 : Interrupt unmasked
0x2F 1 MASK3 M_RX_ 0 : Interrupt masked (default)
4 0 RW
NOTSUPT 1 : Interrupt unmasked
M_RX_ 0 : Interrupt masked (default)
3 0 RW
HARDRST 1 : Interrupt unmasked
M_RX_ 0 : Interrupt masked (default)
2 0 RW
PSRDY 1 : Interrupt unmasked
1:0 Reserved 00 R Reserved
0 : Interrupt masked (default)
7 M_REQ_SENT 0 RW
1 : Interrupt unmasked
M_TX_ 0 : Interrupt masked (default)
6 0 RW
SUCCESS 1 : Interrupt unmasked
M_TX_ 0 : Interrupt masked (default)
5 0 RW
0x30 1 MASK4 DISCARD 1 : Interrupt unmasked
0 : Interrupt masked (default)
4 M_TX_FAIL 0 RW
1 : Interrupt unmasked
3:1 Reserved 000 RW Reserved
0 : Interrupt masked (default)
0 M_I2C_ERR 0 RW
1 : Interrupt unmasked

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16
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0 : Cleared (default)
INT_VBUS_
7 0 WC 1 : VBUS_HV_FLAG go High (VBUS
HV
reach over-voltage threshold)
0: Cleared (default)
INT_VBUS_
6 0 WC 1: VBUS_DCT_FLAG go High (VBUS
DCT
reach disconnect threshold)
0: Cleared (default)
INT_VBUS_
5 0 WC 1: VBUS_PRESENT_FLAG go High
PRESENT
(VBUS reach present threshold)
0 : Cleared (default)
INT_VBUS_
4 0 WC 1 : The voltage at CC2 is higher than
TO_CC2
3.45V.
0x33 1 RT_INT1
0 : Cleared (default)
INT_VBUS_
3 0 WC 1 : The voltage at CC1 is higher than
TO_CC1
3.45V.
0 : Cleared (default)
INT_PE_SNK_
2 0 WC 1 : Policy Engine Enter PE_SNK_RDY
RDY
state.
INT_TYPC_ 0 : Cleared (default)
1 ATTACH_ 0 WC 1 : Type-C Attached_SNK state is
SNK entered.
0 : Cleared (default)
INT_CC_
0 0 WC 1 : CC1_ST or CC2_ST (0x38[3:0]) has
CHANGE
changed.

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17
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0 : No DR_Swap transmitted, or Accept
INT_DRSW_ not received. Cleared. (default)
7 0 WC
ACCEPT 1 : Transmit DR_Swap and Accept
received.
0 : No DR_Swap transmitted, or Reject
INT_DRSW_R not received. Cleared. (default)
6 0 WC
EJECT 1 : Transmit DR_Swap and Reject
received.
0 : No DR_Swap transmitted, or Wait
INT_DRSW_W not received. Cleared. (default)
5 0 WC
AIT 1 : Transmit DR_Swap and Wait
received.
0 : No DR_Swap transmitted. Cleared.
INT_DRSW_ (default)
4 0 WC
TIMEOUT 1 : Transmit DR_Swap and no any
response.
0x34 1 RT_INT2
0 : No Request transmitted, or Accept
INT_REQ_ not received. Cleared. (default)
3 0 WC
ACCEPT 1 : Transmit Request and Accept
received.
0 : No Request transmitted, or Reject
INT_REQ_ not received. Cleared. (default)
2 0 WC
REJECT 1 : Transmit Request and Reject
received.
0 : No Request transmitted, or Wait not
INT_REQ_ received. Cleared. (default)
1 0 WC
WAIT 1 : Transmit Request and Wait
received.
0 : No Get_SRC_CAP transmitted or no
INT_
GoodCRC response. Cleared. (default)
0 GSRCCAP_ 0 WC
1 : Transmit Get_SRC_CAP and
SENT
GoodCRC received.

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18
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0 : No DR_Swap received or no Accept
INT_RX_
transmitted. Cleared. (default)
7 DRSW_ 0 WC
1 : DR_Swap received and Accept
ACCEPT
transmitted.
0 : No DR_Swap received or no Reject
INT_RX_
transmitted. Cleared. (default)
6 DRSW_ 0 WC
1 : DR_Swap received and Reject
REJECT
transmitted.
0 : No Source_Cap received. Cleared.
(default)
INT_RX_
5 0 WC 1 : Source_Cap received in
SRCCAP
PE_SNK_READY state or
0x35 1 RT_INT3
PE_SNK_WAIT_FOR_CAP state.
0 : No Not_Supported received.
INT_RX_
4 0 WC Cleared. (default)
NOTSUPT
1 : Not_Supported received.
0 : No Hard Reset received. Cleared.
INT_RX_
3 0 WC (default)
HARDRST
1 : Hard Reset received.
0 : No PS_RDY received. Cleared.
INT_RX_
2 0 WC (default)
PSRDY
1 : PS_RDY received.
1:0 Reserved 00 R Reserved

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19
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0 : No Request transmitted or no
INT_REQ_ GoodCRC response. Cleared. (default)
7 0 WC
SENT 1 : Transmit Request and GoodCRC
received.
0 : No PD message transmitted or no
GoodCRC response. Cleared. (default)
INT_TX_ 1 : Reset or SOP message
6 0 WC
SUCCESS transmission successful. GoodCRC
response received on SOP message
transmission.
0 : PD message transmitted. Cleared.
(default)
INT_TX_
5 0 WC 1 : Reset or SOP message
DISCARD
transmission not sent due to an
incoming receive message.
0 : No PD message transmitted or
0x36 1 RT_INT4 GoodCRC response. Cleared. (default)
1 : SOP* message transmission not
4 INT_TX_FAIL 0 WC
successful, no GoodCRC response
received on SOP* message
transmission.
3:2 Reserved 00 R Reserved
1 Reserved 0 WC Reserved
0 : Cleared (default)
1 : Transmit "Request" with invalid
Object setting. E.g. Obj = 0, or Not
Existing Obj number.
0 INT_I2C_ERR 0 WC Transmit "DR_Swap" when Pins are
configured to not a dual role data.
Transmit "Request", "DR_Swap" and
"Get_Source_Cap" when RP level is
1.5A in PD 3.0 communication.

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20
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0 : VBUS is not at vHV (default)
7 VBUS_HV 0 R
1 : VBUS is at vHV
VBUS_ 0 : VBUS is not at vSNKDisc (default)
6 0 R
SNKDISC 1 : VBUS is at vSNKDisc
VBUS_ 0 : VBUS is not at vPRESENT (default)
5 0 R
PRESENT 1 : VBUS is at vPRESENT
0 : The voltage at CC2 is lower than
VBUS_TO_ 3.45V. (default)
4 0 R
CC2 1 : The voltage at CC2 is higher than
3.45V.
0x37 1 RT_ST1 0 : The voltage at CC1 is lower than
VBUS_TO_ 3.45V. (default)
3 0 R
CC1 1 : The voltage at CC1 is higher than
3.45V.
0 : Not in Policy Sink Ready State
PE_SNK_
2 0 R (default)
RDY
1 : In Policy Sink Ready State
TYPC_ 0 : Not in Type-C attached sink state
1 ATTACH_ 0 R (default)
SNK 1 : In Type-C attached sink state
0 Reserved 0 R Reserved

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21
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
7:5 Reserved 000 R Reserved
0 : PD2.0 communication or RP level is
3A in PD3.0 communication. (default)
1 : Indication of connected CCx pin is in
RP1P5A level after PD3.0 power
4 PD3_TXNG 0 R
contract is established (Explicit
contract). Apply for attached as sink
only, not available for debug accessory
plugin.
If (ROLE_CONTROL.CC2 = Rd)
00 : SNK.Open (Below maximum vRa)
(default)
01 : SNK.Default (Above minimum vRd-
Connect)
10 : SNK.Power1.5 (Above minimum
3:2 CC2_ STATUS 00 R
vRd-Connect) Detects Rp 1.5A
0x38 1 RT_ST2 11 : SNK.Power3.0 (Above minimum
vRd-Connect) Detects Rp 3.0A

If ROLE_CONTROL.CC2 = Open, this

field is set to 00.
If (ROLE_CONTROL.CC1 = Rd)
00 : SNK.Open (Below maximum vRa)
(default)
01 : SNK.Default (Above minimum vRd-
Connect)
10 : SNK.Power1.5 (Above minimum
1:0 CC1_ STATUS 00 R
vRd-Connect) Detects Rp-1.5A
11 : SNK.Power3.0 (Above minimum
vRd-Connect) Detects Rp-3.0A

If ROLE_CONTROL.CC1 = Open, this

field is set to 00.
7:3 Reserved 00000 R Reserved
Limit Fault (VBUS reach High Voltage
threshold) handling (PATH_EN turns
off) times to FAULT_CNT.
FAULT_ After reach FAULT_CNT, PATH_EN
0x3B 1 remains off till new plugin.
CTRL 2:0 FAULT_CNT 111 RW
Set 0 to disable Limit Fault function.
000 : Disable
001 : 1 time
…
111 : 7 times (default)

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22
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
7 Reserved 0 R Reserved
Latched TABLE_SEL result during
LAT_TABLE_ power on sequence. With 0x0D[0]
6 1 R
SELL indicate de-bounce success or timeout
(30ms)
PSEL_
0x3C 1 Latched PSEL2 result during power on
DEBINFO1
5:3 LAT_PSEL2 111 R sequence. With 0x0D[0] indicate de-
bounce success or timeout (30ms)
Latched PSEL1 result during power on
2:0 LAT_PSEL1 111 R sequence. With 0x0D[0] indicate de-
bounce success or timeout (30ms)
7:2 Reserved 000000 R Reserved
USBSET_ Latched USB_SET result during power
0x3E 1
DEBINFO 1:0 LAT_USB 00 R on sequence. With 0x0D[1] indicate de-
bounce success or timeout (30ms)
7:3 Reserved 00000 R Reserved
PATHOPT_ Latched PATH_OPT result during
0x3F 1 LAT_ power on sequence. With 0x0D[2]
DEBINFO 2:0 000 R
PATHOPT indicate de-bounce success or timeout
(30ms)
PRO_
0x50 1 SNKCAP_ 7:0 VID[7:0] 00000000 RW A unique 16-bit unsigned integer.
EXT1 Assigned by the USB-IF to the Vendor.
0x51 1 7:0 VID[15:8] 00000000 RW
PRO_
0x52 1 SNKCAP_ 7:0 PID[7:0] 00000000 RW A unique 16-bit unsigned integer.
EXT2 Assigned uniquely by the Vendor to
identify the product.
0x53 1 7:0 PID[15:8] 00000000 RW
PRO_
0x54 1 SNKCAP_ 7:0 XID[7:0] 11111111 RW
EXT3
A unique 32-bit unsigned integer.
0x55 1 7:0 XID[15:8] 11111111 RW Assigned by the USB-IF to the Vendor.
0x56 1 7:0 XID[23:16] 11111111 RW
0x57 1 7:0 XID[31:24] 11111111 RW
PRO_
0x58 1 SNKCAP_ 7:0 FW_VER 00000000 RW Firmware version number
EXT4
PRO_
0x59 1 SNKCAP_ 7:0 HW_VER 00000000 RW Hardware version number
EXT5
PRO_
0x5A 1 SNKCAP_ 7:0 SKEDB_VER 00000001 RW SKEDB version = 1
EXT6
0 : 150mA/s (default)
PRO_
1 : 500mA/s
0x5B 1 SNKCAP_ 7:0 LOAD_STEP 00000000 RW
Bit1 to Bit7 are reserved and shall not
EXT7
be used.
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23
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Bit[4:0] Percent overload in 10%
increments Values higher than 25
PRO_
SNK_LOAD (11001b) are
0x5C 1 SNKCAP_ 7:0 00000000 RW
[7:0] clipped to 250%. 00000b is the default.
EXT8
Bit[7:5] Overload period in 20ms when
bits 0-4 non-zero.
Bit[1:0] Overload period in 20ms when
bits 0-4 non-zero.
SNK_LOAD
0x5D 1 7:0 10000000 RW Bit[6:2] Duty cycle in 5% increments
[15:8]
when bits 0-4 are non-zero
Bit[7] Can tolerate VBUS Voltage droop
Bit 0 Requires LPS Source when set
PRO_ Bit 1 Requires PS1 Source when set
0x5E 1 SNKCAP_ 7:0 COMPLIANCE 00000000 RW Bit 2 Requires PS2 Source when set
EXT9 3…7 bits are Reserved and Shall be
set to zero
Temperature conforms to :
00000000 = Not applicable (default)
PRO_
TOUCH_ 00000001 = [IEC 60950-1]
0x5F 1 SNKCAP_ 7:0 00000000 RW
TEMP 00000010 = [IEC 62368-1] TS1
EXT10
00000011 = [IEC 62368-1] TS2
Note : All other values Reserved
Upper Nibble = Number of Hot
PRO_
BATTERY_ Swappable Battery Slots (0…4)
0x60 1 SNKCAP_ 7:0 00000000 RW
INFO Lower Nibble = Number of Fixed
EXT11
Batteries (0…4)
Bit 0 1 : PPS charging supported
Bit 1 1 : VBUS powered
Bit 2 1 : Mains powered
PRO_
Bit 3 1 : Battery powered
0x61 1 SNKCAP_ 7:0 SNK_MODES 00000010 RW
Bit 4 1 : Battery essentially unlimited
EXT12
Bit 5 1 : AVS supported
Bit 6 and 7 are reserved and shall be
set to zero
Manual setting for Sink Cap Extended
message.
Bit 0 to Bit 6 : The Minimum PDP
PRO_SNKC required by the Sink to operate without
0x62 1 7:0 SNK_PDP 00000000 RW
AP_EXT13 consuming any power from its
Battery(s) should it have one.
Bit 7 is reserved and shall be set to
zero
Sink Cap Extended message's content
0 : From the default values of 0x50 to
PRO_ SNKCAPEXT_ 0x61 no matter what 0x50 to 0x61 are
7 0 RW
0x65 1 SNKCAP_ CTRL_EN modified. The Sink PDP is from 0x62.
CTRL (default)
1: From the values of 0x50 to 0x62.
6:0 Reserved 0000000 RW Reserved

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24
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Manual determined operating current.
0x73[7] = 0b :
0x72 and 0x73[1:0] will be zero.
PSEL_MCU_
0x72 1 SNKCAP1 7:0 00000000 R
CUR_L 0x73[7] = 1b :
0x72 and 0x73[1:0] are from Received
SRCPDO of selected OBJ number
(0x10[2:0]). The current step is 10mA.
Indication of
PSEL_MCU_VOLT/PSEL_MCU_CUR
is used for SNKCAP message and
evaluation of
7 PSEL_MCU 0 R
power with Source.
0 : MCU Selected SNKCAP is not in
used. (default)
1 : MCU Selected SNKCAP is in used.
Reveal PDP information in sink cap ext
message.
0x65[7] = 0b :
0x73[6:2] and 0x75[4:2] are determined
PSEL_PDP
0x73 1 SNKCAP2 6:2 00000 R by PSEL1/PSEL2/TABLE_SET setting.
[4:0]
0x65[7] = 1b :
0x73[6:2] and 0x75[4:2] are determined
by control register 0x62.
Manual determined operating current.
0x73[7] = 0b :
0x72 and 0x73[1:0] will be zero.
PSEL_MCU_
1:0 00 R
CUR_H 0x73[7] = 1b :
0x72 and 0x73[1:0] are from Received
SRCPDO of selected OBJ number
(0x10[2:0]). The current step is 10mA.
Manual determined operating voltage.
0x73[7] = 0b :
0x74 and 0x75[1:0] are zero.
PSEL_MCU_
0x74 1 SNKCAP3 7:0 00000000 R 0x73[7] = 1b :
VOLT_L
0x74 and 0x75[1:0] are from the
received SRCPDO of selected OBJ
number (0x10[2:0]). The voltage step is
50mV.

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25
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
Determination of which sink capabilities
is from and used for evaluation of
source PDO.
0 : PSEL1/PSEL2/TABLE_SET
determined (default)
1 : MCU selected VOL/CUR from
SRCPDOs
MCU selected method is entered when
MCU initiated TX Request (0x04[7] =
1b) with correct setting (0x03[4] = 1b
EVASCAP_
7 0 R and selected object (0x03[2:0]) is not
CTRL_EN
zero or larger than received SPDO
number).
MCU selected method is cleared when
Source detached, unchanged response
from source (Wait, Reject) for
"Request" message is received, or the
updated sink cap by MCU selected
VOL/CUR evaluated is capability
mismatched with new Source
0x75 1 SNKCAP4 Capabilities received.
6:5 Reserved 00 R Reserved
Reveal PDP information in sink cap ext
message.
0x65[7] = 0b :
0x73[6:2] and 0x75[4:2] are determined
PSEL_PDP
4:2 000 R by PSEL1/PSEL2/TABLE_SET setting.
[7:5]
0x65[7] = 1b :
0x73[6:2] and 0x75[4:2] are determined
by control register 0x62.
Manual determined operating voltage.
0x73[7] = 0b :
0x74 and 0x75[1:0] are zero.
PSEL_MCU_
1:0 00 R 0x73[7] = 1b :
VOLT_H
0x74 and 0x75[1:0] are from the
received SRCPDO of selected OBJ
number (0x10[2:0]). The voltage step is
50mV.
0x73[7] = 0b :
0x76 and 0x77[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.

0x73[7] = 1b :
PSEL_5V_ If OBJ1 is selected (0x10[2:0] = 1),
0x76 1 SNKCAP5 7:0 00000000 R
CUR_L 0x76 and 0x77[1:0] are from the
received SRCPDO OBJ1.
If OBJ1 is not selected (0x10[2:0]! = 1),
0x76 and 0x77[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
The current step is 10mA.

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26
 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0x73[7] = 0b :
0 : 5V Sink PDO is not the candidate
for the evaluation of Source PDO.
(default)
1 : 5V Sink PDO is the candidate for
7 PSEL_5V 0 R the evaluation of Source PDO.

0x73[7] = 1b :
5V Sink PDO is not used for the
evaluation of Source PDO. 0x77[7] =
0b.
Indication of transmit bytes for
PSEL_ SNK_CAP message.
6:2 00000 R
0x77 1 SNKCAP6 TXBYTE 0x77[6:2] = 4 * Sink PDO number + 2.
2 bytes are Header.
0x73[7] = 0b :
0x76 and 0x77[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.

0x73[7] = 1b :
PSEL_5V_ If OBJ1 is selected (0x10[2:0] = 1),
1:0 00 R
CUR_H 0x76 and 0x77[1:0] are from the
received SRCPDO OBJ1.
If OBJ1 is not selected (0x10[2:0]! = 1),
0x76 and 0x77[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
The current step is 10mA.
0x73[7] = 0b :
0x78 and 0x79[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_9V_
0x78 1 SNKCAP7 7:0 00000000 R
CUR_L
0x73[7] = 1b :
0x78 = 00h and 0x79[1:0] = 00b. The
current step is 10mA.

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27
RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0x73[7] = 0b :
0 : 9V Sink PDO is not the candidate
for the evaluation of Source PDO.
(default)
1 : 9V Sink PDO is the candidate for
7 PSEL_9V 0 R the evaluation of Source PDO.

0x73[7] = 1b :
9V Sink PDO is not used for the
evaluation of Source PDO. 0x79[7] =
0x79 1 SNKCAP8
0b.
6:2 Reserved 00000 R Reserved
0x73[7] = 0b :
0x78 and 0x79[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_9V_
1:0 00 R
CUR_H
0x73[7] = 1b :
0x78 = 00h and 0x79[1:0] = 00b. The
current step is 10mA.
0x73[7] = 0b :
0x7A and 0x7B[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_12V_
0x7A 1 SNKCAP9 7:0 00000000 R
CUR_L
0x73[7] = 1b :
0x7A = 00h and 0x7B[1:0] = 00b. The
current step is 10mA.
0x73[7] = 0b :
0 : 12V Sink PDO is not the candidate
for the evaluation of Source PDO.
(default)
1 : 12V Sink PDO is the candidate for
7 PSEL_12V 0 R the evaluation of Source PDO.

0x73[7] = 1b :
12V Sink PDO is not used for the
0x7B 1 SNKCAP10 evaluation of Source PDO. 0x7B[7] =
0b.
6:2 Reserved 00000 R Reserved
0x73[7] = 0b :
0x7A and 0x7B[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_12V_
1:0 00 R
CUR_H
0x73[7] = 1b :
0x7A = 00h and 0x7B[1:0] = 00b. The
current step is 10mA.
0x73[7] = 0b :
0x7C and 0x7D[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_15V_
0x7C 1 SNKCAP11 7:0 00000000 R
CUR_L
0x73[7] = 1b :
0x7C = 00h and 0x7D[1:0] = 00b. The
current step is 10mA.
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 RT1719
Register
Address Length Bit Bit Name Default Type Description
Name
0x73[7] = 0b :
0 : 15V Sink PDO is not the candidate
for the evaluation of Source PDO.
(default)
1 : 15V Sink PDO is the candidate for
7 PSEL_15V 0 R the evaluation of Source PDO.

0x73[7] = 1b :
15V Sink PDO is not used for the
evaluation of Source PDO. 0x7D[7] =
0x7D 1 SNKCAP12
0b.
6:2 Reserved 00000 R Reserved
0x73[7] = 0b :
0x7C and 0x7D[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_15V_
1:0 00 R
CUR_H
0x73[7] = 1b :
0x7C = 00h and 0x7D[1:0] = 00b. The
current step is 10mA.
0x73[7] = 0b :
0x7E and 0x7F[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_20V_
0x7E 1 SNKCAP13 7:0 00000000 R
CUR_L
0x73[7] = 1b :
0x7E = 00h and 0x7F[1:0] = 00b. The
current step is 10mA.
0x73[7] = 0b :
0 : 20V Sink PDO is not the candidate
for the evaluation of Source PDO.
(default)
1 : 20V Sink PDO is the candidate for
7 PSEL_20V 0 R the evaluation of Source PDO.

0x73[7] = 1b :
20V Sink PDO is not used for the
0x7F 1 SNKCAP14 evaluation of Source PDO. 0x7F[7] =
0b.
6:2 Reserved 00000 R Reserved
0x73[7] = 0b :
0x7E and 0x7F[1:0] are from
PSEL1/PSEL2/TABLE_SET settings.
PSEL_20V_
1:0 00 R
CUR_H
0x73[7] = 1b :
0x7E = 00h and 0x7F[1:0] = 00b. The
current step is 10mA.
0x80 1 DEVICE_ID 7:0 DID[7:0] 10010001 R
DEVICE ID
0x81 1 7:0 DID[15:8] 01000110 R
PRODUCT_
0x82 1 7:0 PID[7:0] 00011001 R
ID PRODUCT ID
0x83 1 7:0 PID[15:8] 00010111 R

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RT1719
Application Information

Richtek’s component specification does not include the following information in the Application Information section.
Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their
own designs and reserve suitable design margin to ensure the functional suitability of their components and systems.

USB_PD Dead Battery Mode

The PD function of the RT1719 complies with USB Power When VBUS is off, RT1719 shall apply Rd on both CC1
Delivery spec 3.0-controller. and CC2 and follow all Sink rules. When it is connected
to a Source, DRP or Sourcing Device, the system will
Type-C Detection
receive the default VBUS. Circuitry to present Rd in this
The USB_PD implements multiple comparators which case only needs to guarantee the voltage on CC is
can be used by software to determine the state of the pulled within the same range as the voltage clamp
CC1, CC2 pins. This status information provides the implementation of Rd in order for a Source to recognize
host processor all of the information required to the Sink and provide VBUS.
determine attach and detach status of the cable.
The USB_PD has three threshold comparators, which
match the USB Type-C specification for the three charge
current levels, which can be detected by a Type-C device.

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 RT1719
I2C Interface
The RT1719 can be configured to four slave addresses by setting the resistance between ADDR (pin 12) and GND.

I2C Address in 7bit Resistance between ADDR and GND (unit : k)
0x40 0
0x41 309
0x42 649
0x43 open

The I2C interface bus must be connect a resistor 1k to power node and independent connection to processor, individually.
The I2C timing diagrams are listed below.

⚫ Read and Write Function

Read single byte of data from Register
Slave Address Register Address Slave Address MSB Data LSB

S 0 A A Sr 1 A A P

R/W Assume Address = m Data for Address = m

Read N bytes of data from Registers

Slave Address Register Address Slave Address MSB Data 1 LSB

S 0 A A Sr 1 A A

R/W Assume Address = m Data for Address = m

MSB Data 2 LSB MSB Data N LSB

A A P
Data for Address = m + 1 Data for Address = m + N - 1

Write single byte of data to Register

Slave Address Register Address MSB Data LSB

S 0 A A A P
Assume Address = m Data for Address = m
R/W

Write N bytes of data to Registers

Slave Address Register Address MSB Data 1 LSB MSB Data 2 LSB

S 0 A A A A
Assume Address = m Data for Address = m Data for Address = m + 1
R/W
MSB Data N LSB

A P
Data for Address = m + N - 1

Driven by Master, Driven by Slave, P Stop, S Start, Sr Repeat Start

⚫ I2C Waveform Information

SDA

tLOW tBUF
tF tR tSU;DAT tF tHD;STA tSP tR

SCL

tHD;STA tSU;STA tSU;STO

S tHD;DAT tHIGH Sr P S

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RT1719
USB Setting

The USB ability of RT1719 can be set by USB_SET (pin 13).

Resistance
between
USB Setting USB_SET 0x3E[1:0] Behavior
and GND
(unit : k)
1. Respond “DR_Swap” by sending “Accept,” and 0x35[7] will be 1b
USB Ability,
if “DR_Swap” is received.
Data Role Open 11b
2. USB Communications Capable in “Sink_Capabilities” is 1b.
Swap
3. MCU can send “DR_Swap” by 0x03[7] = 1b.
USB Ability,
1. Respond “DR_Swap” by sending “Reject,” and 0x35[6] will be 1b
No Data Role
309 01b if “DR_Swap” is received.
Swap
2. USB Communications Capable in “Sink_Capabilities” is 1b.
(UFP Only)
1. Respond “DR_Swap” by sending “Reject,” and 0x35[6] will be 1b
No USB
0 00b if “DR_Swap” is received.
Ability
2. USB Communications Capable in “Sink_Capabilities” is 0b.

The RT1719 will respond DR Swap from port partner according to the setting of US_SET and report the result in the
register 0x35[7:6].

Address Bit Bit Name Default Type Description

0 : Interrupt masked (default)
7 M_RX_DRSW_ACCEPT 0 RW
1 : Interrupt unmasked
0x2F
0 : Interrupt masked (default)
6 M_RX_DRSW_REJECT 0 RW
1 : Interrupt unmasked
0 : No DR_Swap received or no
Accept transmitted. Cleared.
7 INT_RX_DRSW_ACCEPT 0 WC (default)
1 : DR_Swap received and Accept
transmitted.
0x35
0 : No DR_Swap received or no
Reject transmitted. Cleared.
6 INT_RX_DRSW_REJECT 0 WC (default)
1 : DR_Swap received and Reject
transmitted.

Table Select

There are 128 Sink_Capabilities to be able to configure. There are 64 Sink_Capabilities in Table 1. The sink currents
of each Sink PDO in the Sink capability are the same. There are the other 64 Sink_Capabilities in Table 0. The sink
powers of each Sink PDO in the Sink capability are the same except for the one which the sink current is over 5A.

Table Setting Configure in Pin 18 0x3C[6]

Table 1 10k to VCAP (pin 10) 1b
Table 0 10k to GND 0b

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 RT1719
PSEL

PSEL2 (pin 3) and PSEL1 (pin 4) can configure 64 settings. The sink capability can be configured according to Table
select, PSEL2, and PSEL1.

Resistance between
PSEL2 Setting PSEL2 and GND 0x3C[5:3]
(unit : k)
111 Open 111b
110 887 110b
101 649 101b
100 453 100b
011 324 011b
010 143 010b
001 56.2 001b
000 0 000b

Resistance between
PSEL1 Setting PSEL1 and GND 0x3C[2:0]
(unit : k)
111 Open 111b
110 887 110b
101 649 101b
100 453 100b
011 324 011b
010 143 010b
001 56.2 001b
000 0 000b

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RT1719
The Min V in the following 2 tables means that the sink system cannot operate if VBUS is under than the Min V.
Taking (Table_Sel, PSEL2, PSEL1) = (1,101,011) as example, the PDO1 (5V/1000mA) will not be the candidate to
match with Source PDO or Rp level.

Table 1
PDO1 PDO2 PDO3 PDO4 PDO5
Table_Sel PSEL2 PSEL1
Min. V Max. V V I V I V I V I V I
Setting Setting Setting
(V) (mA) (V) (mA) (V) (mA) (V) (mA) (V) (mA)
1 111 111 5 9 5 500 9 500 NA NA
1 111 110 5 9 5 1000 9 1000 NA NA
1 111 101 5 9 5 1500 9 1500 NA NA
1 111 100 5 9 5 2000 9 2000 NA NA
1 111 011 5 9 5 2500 9 2500 NA NA
1 111 010 5 9 5 3000 9 3000 NA NA
1 111 001 5 9 5 3500 9 3500 NA NA
1 111 000 5 9 5 4000 9 4000 NA NA
1 110 111 5 9 5 4500 9 4500 NA NA
1 110 110 5 9 5 5000 9 5000 NA NA
1 110 101 5 12 5 500 9 500 12 500 NA NA
1 110 100 5 12 5 1000 9 1000 12 1000 NA NA
1 110 011 5 12 5 1500 9 1500 12 1500 NA NA
1 110 010 5 12 5 2000 9 2000 12 2000 NA NA
1 110 001 5 12 5 2500 9 2500 12 2500 NA NA
1 110 000 5 12 5 3000 9 3000 12 3000 NA NA
1 101 111 5 12 5 3500 9 3500 12 3500 NA NA
1 101 110 5 12 5 4000 9 4000 12 4000 NA NA
1 101 101 5 12 5 4500 9 4500 12 4500 NA NA
1 101 100 5 12 5 5000 9 5000 12 5000 NA NA
1 101 011 12 12 5 1000 12 1000 NA NA
1 101 010 12 12 5 1500 12 1500 NA NA
1 101 001 12 12 5 2000 12 2000 NA NA
1 101 000 12 12 5 2500 12 2500 NA NA
1 100 111 12 12 5 3000 12 3000 NA NA
1 100 110 12 12 5 3500 12 3500 NA NA
1 100 101 12 12 5 4000 12 4000 NA NA
1 100 100 12 12 5 4500 12 4500 NA NA
1 100 011 12 12 5 5000 12 5000 NA NA
1 100 010 5 15 5 500 9 500 12 500 15 500 NA NA
1 100 001 5 15 5 1000 9 1000 12 1000 15 1000 NA NA
1 100 000 5 15 5 1500 9 1500 12 1500 15 1500 NA NA

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 RT1719
PDO1 PDO2 PDO3 PDO4 PDO5
Table_Sel PSEL2 PSEL1
Min. V Max. V V I V I V I V I V I
Setting Setting Setting
(V) (mA) (V) (mA) (V) (mA) (V) (mA) (V) (mA)
1 011 111 5 15 5 2000 9 2000 12 2000 15 2000 NA NA
1 011 110 5 15 5 2500 9 2500 12 2500 15 2500 NA NA
1 011 101 5 15 5 3000 9 3000 12 3000 15 3000 NA NA
1 011 100 5 15 5 3500 9 3500 12 3500 15 3500 NA NA
1 011 011 5 15 5 4000 9 4000 12 4000 15 4000 NA NA
1 011 010 5 15 5 4500 9 4500 12 4500 15 4500 NA NA
1 011 001 5 15 5 5000 9 5000 12 5000 15 5000 NA NA
1 011 000 15 15 5 1000 15 1000 NA NA
1 010 111 15 15 5 1500 15 1500 NA NA
1 010 110 15 15 5 2000 15 2000 NA NA
1 010 101 15 15 5 2500 15 2500 NA NA
1 010 100 15 15 5 3000 15 3000 NA NA
1 010 011 15 15 5 3500 15 3500 NA NA
1 010 010 15 15 5 4000 15 4000 NA NA
1 010 001 15 15 5 4500 15 4500 NA NA
1 010 000 15 15 5 5000 15 5000 NA NA
1 001 111 5 20 5 1000 9 1000 12 1000 15 1000 20 1000
1 001 110 5 20 5 2000 9 2000 12 2000 15 2000 20 2000
1 001 101 5 20 5 2500 9 2500 12 2500 15 2500 20 2500
1 001 100 5 20 5 3000 9 3000 12 3000 15 3000 20 3000
1 001 011 5 20 5 3500 9 3500 12 3500 15 3500 20 3500
1 001 010 5 20 5 4000 9 4000 12 4000 15 4000 20 4000
1 001 001 5 20 5 4500 9 4500 12 4500 15 4500 20 4500
1 001 000 5 20 5 5000 9 5000 12 5000 15 5000 20 5000
1 000 111 20 20 5 1000 20 1000 NA NA
1 000 110 20 20 5 2000 20 2000 NA NA
1 000 101 20 20 5 2500 20 2500 NA NA
1 000 100 20 20 5 3000 20 3000 NA NA
1 000 011 20 20 5 3500 20 3500 NA NA
1 000 010 20 20 5 4000 20 4000 NA NA
1 000 001 20 20 5 4500 20 4500 NA NA
1 000 000 20 20 5 5000 20 5000 NA NA

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RT1719
Table 0
PDO1 PDO2 PDO3 PDO4 PDO5
Table_Sel PSEL2 PSEL1
Min. V Max. V V I V I V I V I V I
Setting Setting Setting
(V) (mA) (V) (mA) (V) (mA) (V) (mA) (V) (mA)
0 111 111 5 5 5 500 NA NA
0 111 110 5 5 5 1500 NA NA
0 111 101 5 5 5 2000 NA NA
0 111 100 5 5 5 3000 NA NA
0 111 011 5 9 5 1500 9 830 NA NA
0 111 010 5 9 5 2000 9 1110 NA NA
0 111 001 5 9 5 3000 9 1660 NA NA
0 111 000 5 9 5 4000 9 2220 NA NA
0 110 111 5 9 5 5000 9 2770 NA NA
0 110 110 5 12 5 1500 9 830 12 620 NA NA
0 110 101 5 12 5 2000 9 1110 12 830 NA NA
0 110 100 5 12 5 3000 9 1660 12 1250 NA NA
0 110 011 5 12 5 4000 9 2220 12 1660 NA NA
0 110 010 5 12 5 5000 9 2770 12 2080 NA NA
0 110 001 5 15 5 1500 9 830 12 620 15 500 NA NA
0 110 000 5 15 5 2000 9 1110 12 830 15 660 NA NA
0 101 111 5 15 5 3000 9 1660 12 1250 15 1000 NA NA
0 101 110 5 15 5 4000 9 2220 12 1660 15 1330 NA NA
0 101 101 5 15 5 5000 9 2770 12 2080 15 1660 NA NA
0 101 100 5 20 5 1500 9 830 12 620 15 500 20 370
0 101 011 5 20 5 2000 9 1110 12 830 15 660 20 500
0 101 010 5 20 5 3000 9 1660 12 1250 15 1000 20 750
0 101 001 5 20 5 4000 9 2220 12 1660 15 1330 20 1000
0 101 000 5 20 5 5000 9 2770 12 2080 15 1660 20 1250
0 100 111 9 12 5 1800 9 1000 12 750 NA NA
0 100 110 9 12 5 2400 9 1330 12 1000 NA NA
0 100 101 9 12 5 3600 9 2000 12 1500 NA NA
0 100 100 9 12 5 4800 9 2660 12 2000 NA NA
0 100 011 9 12 5 5000 9 3000 12 2250 NA NA
0 100 010 9 12 5 5000 9 4000 12 3000 NA NA
0 100 001 9 12 5 5000 9 5000 12 3750 NA NA
0 100 000 9 15 5 1800 9 1000 12 750 15 600 NA NA
0 011 111 9 15 5 3000 9 1660 12 1250 15 1000 NA NA
0 011 110 9 15 5 4000 9 2220 12 1660 15 1330 NA NA
0 011 101 9 15 5 5000 9 3000 12 2250 15 1800 NA NA
0 011 100 9 15 5 5000 9 4000 12 3000 15 2400 NA NA
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 RT1719
PDO1 PDO2 PDO3 PDO4 PDO5
Table_Sel PSEL2 PSEL1
Min. V Max. V V I V I V I V I V I
Setting Setting Setting
(V) (mA) (V) (mA) (V) (mA) (V) (mA) (V) (mA)
0 011 011 9 15 5 5000 9 5000 12 3750 15 3000 NA NA
0 011 010 9 20 5 1800 9 1000 12 750 15 600 20 450
0 011 001 9 20 5 3000 9 1660 12 1250 15 1000 20 750
0 011 000 9 20 5 4000 9 2220 12 1660 15 1330 20 1000
0 010 111 9 20 5 5000 9 3000 12 2250 15 1800 20 1350
0 010 110 9 20 5 5000 9 4000 12 3000 15 2400 20 1800
0 010 101 9 20 5 5000 9 5000 12 3750 15 3000 20 2250
0 010 100 12 15 5 2000 12 830 15 660 NA NA
0 010 011 12 15 5 3000 12 1250 15 1000 NA NA
0 010 010 12 15 5 4800 12 2000 15 1600 NA NA
0 010 001 12 15 5 5000 12 2500 15 2000 NA NA
0 010 000 12 15 5 5000 12 3000 15 2400 NA NA
0 001 111 12 15 5 5000 12 3750 15 3000 NA NA
0 001 110 12 15 5 5000 12 5000 15 4000 NA NA
0 001 101 12 20 5 2000 12 830 15 660 20 500 NA NA
0 001 100 12 20 5 3000 12 1250 15 1000 20 750 NA NA
0 001 011 12 20 5 4800 12 2000 15 1600 20 1200 NA NA
0 001 010 12 20 5 5000 12 3000 15 2400 20 1800 NA NA
0 001 001 12 20 5 5000 12 3750 15 3000 20 2250 NA NA
0 001 000 12 20 5 5000 12 5000 15 4000 20 3000 NA NA
0 000 111 15 20 5 2000 15 660 20 500 NA NA
0 000 110 15 20 5 3000 15 1000 20 750 NA NA
0 000 101 15 20 5 4000 15 1330 20 1000 NA NA
0 000 100 15 20 5 5000 15 1660 20 1250 NA NA
0 000 011 15 20 5 5000 15 2000 20 1500 NA NA
0 000 010 15 20 5 5000 15 3000 20 2250 NA NA
0 000 001 15 20 5 5000 15 4000 20 3000 NA NA
0 000 000 15 20 5 5000 15 5000 20 3750 NA NA

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RT1719
Path Option
Resistance
Path between
Option Path_Opt 0x3F[2:0] Behavior HV Bound LV Bound
Setting and GND
(unit : k)
The same with The same with Path
Option 7 Open 111b The same with Path option = 000
Path option 0 option 0
PATHEN is low no matter if Sink
Option 6 887 110b 20V 5V
PDO is matched with Source DPO.
PATHEN is low no matter if Sink
Option 5 649 101b 15V 5V
PDO is matched with Source DPO.
PATHEN is low no matter if Sink
Option 4 453 100b 12V 5V
PDO is matched with Source DPO.
PATHEN is low no matter if Sink
Option 3 324 011b 9V 5V
PDO is matched with Source DPO.
PATHEN is low no matter if Sink
Option 2 143 010b 5V 5V
PDO is matched with Source DPO.
1. Match :
Depending on Depending on
PATHEN is low no matter if Sink
Option 1 56.2 001b Max. V of the the requested
PDO is matched with Source DPO.
Sink capability PDO.
2. Mismatch : 5V
1. Match :
Depending on Depending on
1. Match : PATHEN is low.
Option 0 0 000b Max. V of the the requested
2. Mismatch : PATHEN is high.
Sink capability PDO.
2. Mismatch : 5V

The RT1719 will compare the source ability with the sink capability according to Table_Sel, PSEL2, and PSEL1. The
match condition is that the one voltage in source ability exactly meets the one in sink capability and the current of the
voltage in source ability is higher or equal to the current of the voltage in sink capability.

Source Type No Rp (VBUS Only) Type-C Only PD

Source Voltage 5V 5V Depending on “Source_Capabilities”

Ability Current 500mA Depending on Rp Depending on “Source_Capabilities”

HV Bound and LV Bound

When VBUS is higher than HV bound, PATHEN will be floating to turn off PMOS for power path, CC pins will be open
and INT_VBUS_HV will be 1b (0x33[7] = 1b). When VBUS is lower than LV bound, PATHEN will be floating to turn
off PMOS for power path and INT_VBUS_LV will be 1b (0x33[6] = 1b).

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 RT1719
MCU Control

The system master can get port information and access PD message through I 2C bus. The followings introduce CC
status, DR Swap, reading Source Capability, Request Source PDO, and editing Sink Capability Extend.
⚫ CC Status

The CC status is reported in register 0x38[3:0]. Please refer to the register map for more detail information.

⚫ DR Swap

Except for responding to DR Swap automatically according to USB setting (at pin 13), the system master can
initiate DR Swap by writing 0x03[7] = 1b. Please make sure that the DR Swap is supported (0x3E[1:0] = 11b)
before initiate DR Swap (0x03[7] = 1b) or I2C error will be triggered (0x30[0] = 1b.) If Rp = 1.5A at PD3.0, initiating
DR Swap (0x30[7] = 1b) will also trigger I2C error (0x30[0] = 1b). After initiating DR Swap successfully, there will
be four results as reported in 0x34[7:4].

Address Bit Bit Name Default Type Description

Initiated Date Role Swap request to
source. To request change data role
from DFP to UFP or UFP to
DFP is controlled by MCU.
Requesting Data Role Swap when
USBSET configuration to not a dual
0x03 7 TX_DRSWAP 0 RW role data will trigger INT_I2C_ERR.
Requesting Data Role Swap when
TXNG(RP 1.5A) and negotiated at
PD3.0 will trigger INT_I2C_ERR.
0 : No DR_Swap sent. (default)
1 : DR_Swap sent and then 0x03[7]
returns to 0b.
0 : Interrupt masked (default)
7 M_DRSW_ACCEPT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
6 M_DRSW_REJECT 0 RW
1 : Interrupt unmasked
0x2E
0 : Interrupt masked (default)
5 M_DRSW_WAIT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
4 M_DRSW_TIMEOUT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
0x30 0 M_I2C_ERR 0 RW
1 : Interrupt unmasked

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RT1719
Address Bit Bit Name Default Type Description
0 : No DR_Swap transmitted, or
Accept not received. Cleared. (default)
7 INT_DRSW_ACCEPT 0 WC
1 : Transmit DR_Swap and Accept
received.
0 : No DR_Swap transmitted, or
Reject not received. Cleared. (default)
6 INT_DRSW_REJECT 0 WC
1 : Transmit DR_Swap and Reject
received.
0x34
0 : No DR_Swap transmitted, or Wait
not received. Cleared. (default)
5 INT_DRSW_WAIT 0 WC
1 : Transmit DR_Swap and Wait
received.
0 : No DR_Swap transmitted. Cleared.
(default)
4 INT_DRSW_TIMEOUT 0 WC
1: Transmit DR_Swap and no any
response.
0 : Cleared (default)
1 : Transmit "Request" with invalid
Object setting. E.g. Obj = 0, or Not
Existing Obj number.
0x36 0 INT_I2C_ERR 0 WC Transmit "DR_Swap" when Pins are
configured to not a dual role data.
Transmit "Request", "DR_Swap" and
"Get_Source_Cap" when RP level is
1.5A in PD 3.0 communication.

⚫ Reading Source Capability

The RT1719 can record the source cap in the register from 0x11 to 0x2C. There is one Source PDO with VBUS =
5V at least and seven Source PDO at most in the Source Capability. Register 0x0F[7:5] shows how many Source
PDO in the Source Capability.
Please note that RT1719 will only compare the fixed supply of Source PDO with Sink PDO.
The selected Source PDO is recorded in register 0x10[2:0].
PDO Information Register Description
00b : Fixed supply
01b : Battery supply
Power Type 0x14[7:6]
10b : Variable supply
1st PDO 11b : Programmable power supply
Vbus Voltage 0x13[3:0] (MSB) and 0x12[7:2] (LSB) Unit : 50mV
Current 0x12[1:0] (MSB) and 0x11[7:0] (LSB) Unit : 10mA
00b : Fixed supply
01b : Battery supply
Power Type 0x18[7:6]
10b : Variable supply
2nd PDO 11b : Programmable power supply
Vbus Voltage 0x17[3:0] (MSB) and 0x16[7:2] (LSB) Unit : 50mV
Current 0x16[1:0] (MSB) and 0x15[7:0] (LSB) Unit : 10mA

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 RT1719
PDO Information Register Description
00b : Fixed supply
01b : Battery supply
Power Type 0x1C[7:6]
10b : Variable supply
3rd PDO 11b : Programmable power supply
Vbus Voltage 0x1B[3:0] (MSB) and 0x1A[7:2] (LSB) Unit : 50mV
Current 0x1A[1:0] (MSB) and 0x19[7:0] (LSB) Unit : 10mA
00b : Fixed supply
01b : Battery supply
Power Type 0x20[7:6]
10b : Variable supply
4th PDO 11b : Programmable power supply
Vbus Voltage 0x1F[3:0] (MSB) and 0x1E[7:2] (LSB) Unit : 50mV
Current 0x1E[1:0] (MSB) and 0x1D[7:0] (LSB) Unit : 10mA
00b : Fixed supply
01b : Battery supply
Power Type 0x24[7:6]
10b : Variable supply
5th PDO 11b : Programmable power supply
Vbus Voltage 0x23[3:0] (MSB) and 0x22[7:2] (LSB) Unit : 50mV
Current 0x22[1:0] (MSB) and 0x21[7:0] (LSB) Unit : 10mA
00b : Fixed supply
01b : Battery supply
Power Type 0x28[7:6]
10b : Variable supply
6th PDO 11b : Programmable power supply
Vbus Voltage 0x27[3:0] (MSB) and 0x26[7:2] (LSB) Unit : 50mV
Current 0x26[1:0] (MSB) and 0x25[7:0] (LSB) Unit : 10mA
00b : Fixed supply
01b : Battery supply
Power Type 0x2C[7:6]
10b : Variable supply
7th PDO 11b : Programmable power supply
Vbus Voltage 0x2B[3:0] (MSB) and 0x2A[7:2] (LSB) Unit : 50mV
Current 0x2A[1:0] (MSB) and 0x29[7:0] (LSB) Unit : 10mA

⚫ Request Source PDO

After reading Source Capability, the system master can request the other source PDO through I 2C.
Set the evaluation mode as evaluating per register setting by 0x03[4] = 1b.
Set the PDO number in 0x03[2:0].
Initiate a Request for the source PDO by 0x04[7] = 1b.
Please note that 0x03[2:0] = 000b or the invalid values (0x03[2:0] = 110b but only five source PDOs) will trigger
I2C error (0x36[0] = 1b).
After initiating Request successfully, there will be three results as reported in 0x34[3:1].
Besides the response to message, the sink capability will be modified. If the system master requests the first PDO
(5V), the sink capability will be modified to 5V/(current is according to 5V Source PDO).
If the system master requests the other valid PDO (9V for example), the sink capability will be modified to
5V/(current is according to Table_SEL, PSEL2 and PSLE1) and 9V/(current is according to 5V Source PDO).

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RT1719
The following table shows the update result of related registers.
Currents of other PDO
MCU Select MCU Select
5V Current 0x79[1:0] (MSB) and 0x78 (LSB)
MCU Current Voltage
0x77[1:0] (MSB) 0x7B[1:0] (MSB) and 0x7A (LSB)
Selection 0x73[1:0] (MSB) 0x75[1:0] (MSB)
and 0x76 (LSB) 0x7D[1:0] (MSB) and 0x7C (LSB)
and 0x72 (LSB) and 0x74 (LSB)
0x7F[1:0] (MSB) and 0x7E (LSB)
According to the According to the
The 1st PDO requested Source 5V requested Source 0A
PDO PDO
According to
According to the According to the
The other valid Table_SEL,
requested Source requested Source 0A
PDO PSEL2 and
PDO PDO
PSEL1

After the sink capability is updated according to MCU selection, the request scenario is shown as the following flow.
Please note that if the mismatch happens with the source capability received again, the sink capability will be updated
according to (Table_SEL, PSEL2, and PSLE1) and then the RT1719 will compare the sink capability and source
capability again.

Sink PDOs
updated due to
MCU selection

Source Capability
received again

Yes Sink PDO is updated again

Mismatch according to Table_SEL,
PSEL2, and PSEL1.

No

TheRT1719 requests the Yes The RT1719 requests the

PDO with highest voltage Mismatch 5V sourcd PDO and the
which matches the Indication (pin 14) is high.
updated Sink Capability.

No

The RT1719 requests the

PDO with highest voltage
which matches the Sink
Capability according to
Table_SEL, PSEL2, and
PSEL1.

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 RT1719
Address Bit Bit Name Default Type Description
Enable Source Cap evaluation based
on the REQ_SRCPDO_NO(0x03[2:0])
or MCU selected capability
4 EVASCAP_MODE 0 RW instead of PSEL.
0 : Evaluation per PSEL setting.
(default)
1 : Evaluation per register setting.
Selected SRCPDO number in the
0x03 request message which is initiated by
TX_SPDO_REQ.
Set to 000 or invalid object number will
trigger INT_I2C_ERR when set
2:0 REQ_SRCPDO_NO 000 RW
TX_SPDO_REQ = 1
000 : No PDO selected (default)
001 : Select the first PDO.
…
111 : Select the seventh PDO.
Set EVASCAP_MODE = 1 (0x03[4])
when try to initiate Request message to
source.
Initiated Fixed power supply Request of
select SRCPDO (0x03[2:0]) to source.
When initiated, it will update Sink
Capabilities to 2 objects which contain
5V/PSEL_5V current and
selected SRC PDO's voltage/current
0x04 7 TX_SPDO_REQ 0 RW when REQ_SRCPDO_NO not 1. Or
update Sink Capabilities to 1
object which is the same as 1st SRC
PDO when REQ_SRCPDO_NO = 1.
Requesting TX_SPDO_REQ when
TXNG(RP 1.5A) and negotiated at
PD3.0 will trigger INT_I2C_ERR.
0 : No Request sent. (default)
1 : Request sent and then 0x04[7]
returns to 0b.
0 : Interrupt masked (default)
3 M_REQ_ACCEPT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
0x2E 2 M_REQ_REJECT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
1 M_REQ_WAIT 0 RW
1 : Interrupt unmasked
0 : Interrupt masked (default)
0x30 0 M_I2C_ERR 0 RW
1 : Interrupt unmasked

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RT1719
Address Bit Bit Name Default Type Description
0 : No DR_Swap transmitted, or Accept
not received. Cleared. (default)
3 INT_REQ_ACCEPT 0 WC
1 : Transmit DR_Swap and Accept
received.
0 : No DR_Swap transmitted, or Reject
not received. Cleared. (default)
0x34 2 INT_REQ_REJECT 0 WC
1 : Transmit DR_Swap and Reject
received.
0 : No DR_Swap transmitted, or Wait
not received. Cleared. (default)
1 INT_REQ_WAIT 0 WC
1 : Transmit DR_Swap and Wait
received.
0 : Cleared (default)
1 : Transmit "Request" with invalid
Object setting. E.g. Obj = 0, or Not
Existing Obj number.
0x36 0 INT_I2C_ERR 0 WC Transmit "DR_Swap" when Pins are
configured to not a dual role data.
Transmit "Request", "DR_Swap" and
"Get_Source_Cap" when RP level is
1.5A in PD 3.0 communication.

⚫ Editing Sink Capability Extend

The system master can modify the Sink Capabilities Extended (0x50 to 0x62) through I 2C (0x65[7] = 1b).

Content of Sink
Capabilities Extended Sink PDP
(except for Sink PDP)
From the default values of According to the
0x65[7] = 0b 0x50 to 0x61 no matter if Table_SEL, PSEL2, and
0x50 to 0x61 are modified. PSEL1.
From the register values of From the register value of
0x65[7] = 1b
0x50 to 0x61. 0x62

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 RT1719
Thermal Considerations 5.0

Maximum Power Dissipation (W)1

Four-Layer PCB
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed 4.0

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power 3.0

dissipation depends on the thermal resistance of the IC

2.0
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
1.0
temperatures. The maximum power dissipation can be
calculated using the following formula :
0.0
PD(MAX) = (TJ(MAX) - TA) / JA 0 25 50 75 100 125
Ambient Temperature (°C)
where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and JA is the junction-to- Figure 1. Derating Curve of Maximum Power
ambient thermal resistance.
Dissipation
For continuous operation, the maximum operating
junction temperature indicated under Recommended
Operating Conditions is 125C. The junction-to-ambient
thermal resistance, JA, is highly package dependent.
For a WQFN-20L 3.5x3.5 package, the thermal
resistance, JA, is 28.5C/W on a standard JEDEC 51-
7 high effective-thermal conductivity four-layer test
board. The maximum power dissipation at TA = 25C
can be calculated as below :
PD(MAX) = (125C − 25C) / (28.5C/W) = 3.5W for a
WQFN-20L 3.5x3.5 package.
The maximum power dissipation depends on the
operating ambient temperature for the fixed TJ(MAX) and
the thermal resistance, JA. The derating curves in
Figure 1 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.

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RT1719
Outline Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 3.400 3.600 0.134 0.142
D2 2.000 2.100 0.079 0.083
E 3.400 3.600 0.134 0.142
E2 2.000 2.100 0.079 0.083
e 0.500 0.020
L 0.350 0.450 0.014 0.018

W-Type 20L QFN 3.5x3.5 Package

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 RT1719
Footprint Information

Number of Footprint Dimension (mm)

Package Tolerance
Pin P Ax Ay Bx By C D Sx Sy
V/W/U/XQFN3.5*3.5-20 20 0.50 4.30 4.30 2.60 2.60 0.85 0.35 2.15 2.15 ±0.05

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RT1719
Packing Information
Tape and Reel Data

Tape Size Pocket Pitch Reel Size (A) Units Trailer Leader Reel Width (W2)
Package Type (mm) (mm)
(W1) (mm) (P) (mm) per Reel Min./Max. (mm)
(mm) (in)

QFN/DFN
12 8 180 7 1,500 160 600 12.4/14.4
3.5x3.5

C, D and K are determined by component size.

The clearance between the components and

the cavity is as follows:

- For 12mm carrier tape: 0.5mm max.

W1 P B F ØJ H
Tape Size
Max. Min. Max. Min. Max. Min. Max. Min. Max. Max.

12mm 12.3mm 7.9mm 8.1mm 1.65mm 1.85mm 3.9mm 4.1mm 1.5mm 1.6mm 0.6mm

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 RT1719
Tape and Reel Packing

Step Photo/Description Step Photo/Description

1 4

Reel 7” 3 reels per inner box Box A

2 5

HIC & Desiccant (1 Unit) inside 12 inner boxes per outer box

3 6

Caution label is on backside of Al bag Outer box Carton A

Container Reel Box Carton

Package Size Units Item Size(cm) Weight(Kg) Reels Units Item Size(cm) Boxes Unit

QFN/DFN Box A 18.3*18.3*8.0 0.1 3 4,500 Carton A 38.3*27.2*38.3 12 54,000

7” 1,500
3.5x3.5 Box E 18.6*18.6*3.5 0.03 1 1,500 For Combined or Partial Reel.

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RT1719
Packing Material Anti-ESD Property

Surface
Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band
Resistance
/cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable.
However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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 RT1719
Datasheet Revision History
Version Date Description Item
Functional Pin Description on P2
Typical Application Circuit on P2
01 2023/5/10 Modify Electrical Characteristics on P6
Application Information on P30, 40, 41
Packing Information on P48, 49, 50

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