Module - III

Memory System
Dr. Ashfaq Ahmad Najar
Faculty, SCSE
VIT Bhopal University
Contents

Locality
Memory systems hierarchy
Memory Types
Main memory organization
 Locality
Principle of Locality:
◼ Programs tend to reuse data and instructions near those they have used recently,
or that were recently referenced themselves.
◼ Temporal locality: Recently referenced items are likely to be referenced in the near
future.
◼ Spatial locality: Items with nearby addresses tend to be referenced close together
in time.
sum = 0;
for (i = 0; i < n; i++)
Locality Example: sum += a[i];
return sum;
• Data
– Reference array elements in succession (stride-1 reference pattern): Spatial locality
– Reference sum each iteration: Temporal locality
• Instructions
– Reference instructions in sequence: Spatial locality
– Cycle through loop repeatedly: Temporal locality
3
Memory Hierarchies
Some fundamental and enduring properties of hardware and software:
◼ Fast storage technologies cost more per byte and have less capacity.
◼ The gap between CPU and main memory speed is widening.
◼ Well-written programs tend to exhibit good locality.

These fundamental properties complement each other beautifully.

They suggest an approach for organizing memory and storage systems

known as a memory hierarchy.

4
Memory hierarchy was developed on a program behaviour known as
locality of reference.

The references are generated by CPU for accessing data or instructions.

These accesses tend to be clustered in certain regions in time, space
and ordering.

5
 An Example Memory Hierarchy

Smaller, CPU registers hold words retrieved from

L0: L1 cache.
faster, registers
and
L1: on-chip L1 L1 cache holds cache lines retrieved
costlier from the L2 cache memory.
(per byte) cache (SRAM)
storage off-chip L2 L2 cache holds cache lines retrieved
L2: from main memory.
devices cache (SRAM)
Main memory holds disk
L3: main memory blocks retrieved from local
Larger, (DRAM) disks.
slower,
and Local disks hold files
cheaper L4: local secondary storage retrieved from disks on
(per byte) (local disks) remote network servers.
storage
devices
L5: remote secondary storage
(distributed file systems, Web servers)

6
 Internal Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access Electrically, byte-

Read-write memory Electrically Volatile
memory (RAM) level

Read-only
Masks
memory (ROM)
Read-only memory Not possible
Programmable
ROM (PROM)

Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile
Electrically
Electrically Erasable Read-mostly memory Electrically, byte-
PROM (EEPROM) level

Electrically, block-
Flash memory
level
7
Types of Memory based on Access
• Sequential Access
To find the required piece of information, the system must search the
device from beginning of the memory. Memory devices that supports
such access are called sequential access.
Example: Magnetic tape
• Direct Access
Refers to the condition when system can go directly to the information that
is needed is known as direct access.
Example: Magnetic disk or optical disk.

8
Memory Access Methods
1. Sequential Access:
• Start at the beginning and read through in order
• Access time depends on location of data and previous location
2. Random Access:
• Individual addresses identify locations exactly
• Access time is consistent across all locations and is independent previous
access
3. Direct Access:
• Individual blocks have unique address
• Access is by jumping to vicinity then performing a sequential search
• Access time depends on location of data within "block" and previous location
9
4. Associative Access
• Addressing information must be stored with data in a general data
location
• A specific data element is located by a comparing desired address with
address portion of stored elements
• Access time is independent of location or previous access
Example: cache

10
Contents
- Types of Main memory (RAM) :
- SRAM
- DRAM
- Characteristics and Performance
- Latency
- Cycle time
- Bandwidth
- memory interleaving

11
Random-Access Memory (RAM): Types
Key features
◼ RAM is packaged as a chip.
◼ Basic storage unit is a cell (one bit per cell).
◼ Multiple RAM chips form a memory.
Static RAM (SRAM)
◼ Each cell stores bit with a six-transistor circuit.
◼ Retains value indefinitely, as long as it is kept powered.
◼ Relatively insensitive to disturbances such as electrical noise.
◼ Faster and more expensive than DRAM.
◼ Uses: Used in L2 and L3 cache, wearables, tablets etc.
Dynamic RAM (DRAM)
◼ Each cell stores bit with a capacitor and transistor.
◼ Value must be refreshed every 10-100 ms.
◼ Sensitive to disturbances.
◼ Slower and cheaper than SRAM.
◼ Uses: As RAM in Computers.

12
Memories: Review
SRAM:
◼ value is stored on a pair of inverting gates

◼ very fast but takes up more space than DRAM (4 to 6 transistors).

Access times: 5 - 25ns
DRAM:
◼ value is stored as a charge on capacitor (must be refreshed)
◼ very small but slower than SRAM (factor of 5 to 10)

Word line word

0 1 (row select)
Pass transistor

Capacitor

0 1
DRAM Bit line
bit SRAM bit
13
 DRAM SRAM

Type of device Analog Digital

Electricity Needed to No need to

refresh refresh
Speed Slow Fast

Construction Simple Complicated

Capacity More Less

Cost Low High

Application Main Memory Cache Memory

By: Prof. Anand Motwani, Faculty SCSE, VIT Bhopal University 14

 Classical DRAM Organization (square)
bit (data) lines

r
o Each intersection represents
w a 1-T DRAM Cell

d RAM Cell
e Array
c
o
d word (row) select
e
r

row Column Address Selector &

I/O Circuits Column
Address selector Address
Row and Column Address together:
data ◼ Select 1 bit a time

15
16
17
18
DIMM: a PCB with DRAM chips on the back and front
• Rank: a collection of DRAM chips that work together to respond to a
request and keep the data bus full
• A 64-bit data will need 8 x8 DRAM chips or 4 x16 DRAM chips or..
• Bank: a subset of a rank that is busy during one request
• Row buffer: the last row (say, 8 KB) read from a bank, acts like a cache
Dual In-line Memory Module: DIMM
DDR: Double Data Rate

19
20
Each rank has 64-bit wide data bus
If a rank is of width x8 then # DRAM chips ??
What about x4, # DRAM chips ??
If a rank is of width x8 then # DRAM chips ?? 8
What about if rank is of width x4, # DRAM chips ?? 16

21
Nonvolatile Memories
DRAM and SRAM are volatile memories
◼ Lose information if powered off.
Nonvolatile memories retain value even if powered off.
◼ Generic name is read-only memory (ROM).
◼ Misleading because some ROMs can be read and modified.
Types of ROMs
◼ Programmable ROM (PROM)
◼ Eraseable programmable ROM (EPROM)
◼ Electrically eraseable PROM (EEPROM)
◼ Flash memory
Firmware
◼ Program stored in a ROM
⚫ Boot time code, BIOS (basic input/ouput system)
⚫ graphics cards, disk controllers.

22
Characteristics of Memory
• Capacity: It is global volume of information (in bits) that the memory can
store.
• Access time: The time interval between the read request and the
availability of data.
• Cycle time: It is the minimum time interval between two successive
access.
• Throughput: It is the volume of information exchanged per unit of time,
expressing in bits/second.
• Non-Volatility: The ability of a memory to store data when it is not being
supplied with electricity

23
Memory Performance Metrics
Latency: Time to access one word
◼ Access time: time between the request and when the data is available (or written)
◼ Cycle time: time between requests
◼ Usually cycle time > access time
◼ Typical read access times for SRAMs in 2004 are 2 to 4 ns for the fastest parts to 8
to 20ns for the typical largest parts

Bandwidth: How much data from the memory can be supplied to the
processor per unit time
◼ width of the data channel * the rate at which it can be used

Size: DRAM to SRAM 4 to 8

Cost/Cycle time: SRAM to DRAM 8 to 16

24