Overview

Introduction
Block Diagram and Pin Description of the
8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timers
Interrupts & Applications
 Why do we need to learn
Microcontrollers ?
■ Its not an exaggeration if I say that, today
there is no electronic gadget on the earth
which is designed without a Microcontroller.
Ex: communication devices, digital
entertainment, portable devices etc…

Not believable ??? See the next slide

■ Personal information products: Cell phone, pager,
watch, pocket recorder, calculator
■ Laptop components:mouse, keyboard, modem,
fax card, sound card, battery charger
■ Home appliances:door lock, alarm clock,
thermostat, air conditioner, TV remote, VCR,
small refrigerator, exercise equipment,
washer/dryer, microwave oven
■ Industrial equipment: Temperature/pressure
controllers, Counters, timers, RPM Controllers
■ Toys: video games, cars, dolls, etc.
 Then What is a Microcontroller ?
■ A smaller computer
■ On-chip RAM, ROM, I/O ports...
■ Example: Motorola’s 6811, Intel’s 8051,
Zilog’s Z8 and PIC 16X
CPU RAM ROM

I/O
Serial A single chip
Timer COM
Port Microcontroller
Port
 How it is different from a
Microprocessor ??
■ General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example ： Intel’s x86, Motorola’s 680x0
Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
■ CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
■ designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and I/ RAM, I/O ports
O ports.
• Highly bit addressable
■ expansive
• for applications in which cost,
■ versatility
power and space are critical
■ general-purpose
• single-purpose
 EVOLUTION

Flashback !!!!
In 1970 and 1971, about the same time Intel was inventing its
microprocessor, Gary Boone, an engineer at Texas Instruments was working on
a similar idea. This extraordinary breakthrough was given the rather humdrum
name of the TMS1802NC. It is named as microcontroller.

The INTEL bagged the credit of producing the first

Microcontroller 8048 with a CPU and 1K bytes of
EPROM, 64 Bytes of RAM an 8-Bit Timer and 27 I/O
pins in 1976.
 Evolution contd…
■ Then followed the most popular controller 8051
in the year 1980 with 4K bytes of ROM,128
Bytes of RAM , a serial port, two 16-bit Timers ,
and 32 I/O pins.
■ The 8051 family has many additions and
improvements over the years and remains a
most soughtafter tool for todays circuit
designers.
■ The same INTEL introduced a 16 bit controller
8096 in the year 1982
 Important Features of
8051
■ 4K bytes ROM
■ 128 bytes RAM
■ Four 8-bit I/O ports
■ Two 16-bit timers
■ Serial interface
■ 64K external code memory space
■ 64K data memory space
“Original” 8051 Microcontroller
Oscillator 4096 Bytes 128 Bytes Two 16 Bit
and timing Program Memory Data Memory Timer/Event
(ROM) (RAM) Counters

8051 Internal data bus

CPU

64 K Byte Bus Programmable

Programmable I/O
Expansion Serial Port Full
Control Duplex UART
Synchronous Shifter
subsystem interrupts

External interrupts Control Parallel ports Serial

Address Data Bus Serial Input
Output
I/O
pins
 Pin Description of the 8051

■ The 8051 is a 40 pin

device, but out of
these 40 pins, 32 are
used for I/O.

■ 24 of these are dual

purpose, i.e. they can
operate as I/O or a
control line or as part
of address or date
bus.
https://www.tutorialspoint.com/microprocessor/microcontrollers_8051_pin_description.htm
Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. Using this Pins,
external address can be separated from data (as they are multiplexed by 8051).

During Flash Programming, this pin acts as program pulse input (PROG).

Pin 31 (EA/VPP): Pin 31 is the External Access Enable Pin i.e. allows external
program Memory. Code from external program memory can be fetched only if this pin
is LOW. Else internal program memory and external program memory is used.

During Flash Programming, this Pin receives 12V Programming Enable Voltage
(VPP).

Flash memory is just like EEPROM: Electrically erasable programmable read only
memory.

PSEN: This is an output pin. PSEN stands for “program store enable.” This pin is
used to read external program memory when ‘0’ else external data memory. If we use
an external ROM for storing the program, then logic 0 appears on it, which indicates
Microcontroller to read data from the memory.

https://www.electronicshub.org/8051-microcontroller-memory-organization/
EA :
 Memory Organization
• 8051 has 2 types of memory
– Program memory (ROM)
– Data memory (RAM)
• Few KB of ROM and 128 or 256 bytes of RAM
• 16 address bus capable of addressing 64KB of
memory
• External memory can also be used
 ▪ Almost all modern variants of 8051 Microcontroller have 256B of RAM. In this 256B, the
first 128B i.e. memory addresses from 00H to 7FH is divided into Working Registers
(organized
almost all modern as variants
RegisterofBanks), Bit – Addressable
8051 Microcontroller have Area
256B ofandRAM.
General
In thisPurpose
256B, theRAM first(also
128B
known as
i.e. memory Scratchpad
addresses from area).
00H Into the
7FHfirst 128B in
is divided of to
RAM (fromRegisters
Working 00H to 7FH), the first
(organized 32B i.e.
as Register
memory
Banks), from addresses
Bit – Addressable Area00H
andtoGeneral
1FH consists
Purpose ofRAM
32 Working Registers
(also known that are organized
as Scratchpad area). as
four
In the firstbanks
128Bwith 8 Registers
of RAM (from 00H in each Bank.
to 7FH), the first 32B i.e. memory from addresses 00H to 1FH
consists of 32 Working Registers that are organized as four banks with 8 Registers in each Bank.

• DATA registers
• CONTROL
registers
• Timers
• Serial ports
• Interrupt system
•Analog to Digital converter
Addresses 80h – FFh
•Digital to Analog converter
etc.. Direct Addressing is used to
access SFRs
 RAM memory space allocation in the 8051

7FH

Third Scratch pad RAM

block
30H

Second 2FH
block Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
First block Register Bank 2
10H
0FH Register Bank 1
08H
07H
Register Bank 0
00H
8051 Register bank
 Second block
• 16 bit addressable register
each of 8 bits
• Total 128 bits
• Address 20h to 2Fh
• Both bit addressable and
byte addressable
 Third block
• Address 30 to 7Fh
• 80 locations
• Do not have any special function
• Scratch pad RAM
 Special Function Registers -SFR
• 8051 microcontroller has a dedicated SFR that
controls various functionalities and peripheral
devices. These registers are essential for
programming the microcontroller’s behavior.
• Direct Addressing
• 80h to FFh
 Accumulator
• The Register A is located at the address E0H in
the SFR memory space. The Accumulator is
used to hold the data for almost all the ALU
Operations
 B Register
• The B Register is used along with the ACC in
Multiplication and Division operations.

• Register B is located at the address F0H of the

SFR Address Space.
 Program Status word
• The PSW or Program Status Word Register is also
called as Flag Register and is one of the important
SFRs. The PSW Register consists of Flag Bits, which
help the programmer in checking the condition of the
result and also make decisions.
Data pointer
Stack pointer
I/O Port
https://www.electronicshub.org/8051-microcontroller-special-function-registers/
List of Registers
(*Denotes the SFRs)
Contd…
PSW REGISTER
 PORTS OF 8051
■ 8051 has 4 Ports. Port 0, Port1, Port2 , Port3
■ Port 0 is a dual purpose port, it is located from
pin 32 to pin 39 (8 pins). To use this port as both
input/output ports each pin must be connected
externally to a 10 k ohm pull-up resistor.This is
because Port 0 is an open drain.
Simple ex: MOV A, #22
BACK MOV P0 ,A
ACALL DELAY
CPL A
SJMP BACK
Alternate functions of P3
 Addressing
Addressing
Modes Modes
♦ Eight modes of addressing are available with
the C8051F020
♦ The different addressing modes determine how the
operand byte is selected

Addressing Modes Instruction

Register MOV A, B
Direct MOV 30H,A
Indirect ADD A,@R0
Immediate Constant ADD A,#80H
Relative* SJMP AHEAD
Absolute* AJMP BACK
Long* LJMP FAR_AHEAD
Indexed MOVC A,@A+PC

* Related to program branching

instructions
 Register Addressing
♦ The register addressing instruction involves
information transfer between registers

♦ Example:
MOV R0, A

♦ The instruction transfers the accumulator content into the

R0 register. The register bank (Bank 0, 1, 2 or 3) must be
specified prior to this instruction.
 Direct Addressing
♦ This mode allows you to specify the operand by giving
its actual memory address (typically specified in
hexadecimal format) or by giving its abbreviated name
(e.g. P3)
Note: Abbreviated SFR names are defined in the “C8051F020.inc” header file

♦ Example:

MOV A, P3 ;Transfer the contents

of
MOV A, 020H ;Port 3 to the
accumulator
location 20H to the
;Transfer the contents
accumulator
of RAM
 Indirect Addressing
♦ This mode uses a pointer to hold the effective address of
the operand
♦ Only registers R0, R1 and DPTR can be used as the
pointer registers
♦ The R0 and R1 registers can hold an 8-bit address,
whereas DPTR can hold a 16-bit address

♦ Examples:
;Store the content of
;accumulator into the memory
MOV @R0,A ;location pointed to by
;register R0. R0 could have an
;8-bit address, such as 60H.

;Transfer the contents from

MOVX A,@DPTR
;the memory location
;pointed to by DPTR into the
;accumulator. DPTR could
have a
;16-bit address, such as 1234H.
 Immediate Constant Addressing
♦ This mode of addressing uses either an 8- or
16-bit constant value as the source operand
♦ This constant is specified in the instruction, rather than
in a register or a memory location
♦ The destination register should hold the same data
size which is specified by the source operand

♦ Examples:
ADD A,#030H ;Add 8-bit value of 30H to
;the accumulator register
;(which is an 8-bit register).

MOV ;Move 16-bit data constant

DPTR,#0FE00H ;FE00H into the 16-bit Data
;Pointer Register.
 Relative Addressing
♦ This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
♦ These instructions transfer control from one part of
a program to another
♦ The destination address must be within -128 and +127
bytes from the current instruction address because an
8-bit offset is used (28 = 256)
♦ Example:

GoBack: DEC A ;Decrement A

JNZ GoBac ;If A is not zero,
k loop back
 Absolute Addressing
♦ Two instructions associated with this mode of addressing
are ACALL and AJMP instructions
♦ These are 2-byte instructions where the 11-bit absolute
address is specified as the operand
♦ The upper 5 bits of the 16-bit PC address are not modified.
The lower 11 bits are loaded from this instruction. So, the
branch address must be within the current 2K byte page of
program memory (211 = 2048)
♦ Example: ;PORT_INIT
should be
ACALL PORT_INIT
;located within 2k
bytes.

PORT_INIT: P0, #0FH ;PORT_INIT

MOV subroutine
 Long Addressing
♦ This mode of addressing is used with the LCALL and
LJMP instructions
♦ It is a 3-byte instruction and the last 2 bytes specify a
16-bit destination location where the program branches
♦ It allows use of the full 64 K code space
♦ The program will always branch to the same location
no matter where the program was previously
♦ Example:
LCALL TIMER_INIT ;TIMER_INIT address
(16-bits
;long) is specified as
the
;operand; In C, this
TIMER_INIT: ORL ;TIMER_INIT will be a
TMOD,#01H subroutine

;function call:
Timer_Init().
 Indexed Addressing

♦ The Indexed addressing is useful when there is a need to retrieve

data from a look-up table
♦ A 16-bit register (data pointer) holds the base address and
the accumulator holds an 8-bit displacement or index
value
♦ The sum of these two registers forms the effective address for a
JMP or MOVC instruction
♦ Example: ;Offset from table
MOV A,#08H start
MOV DPTR,#01F ;Table start
MOVC 00H
A,@A+DPTR address
;Gets target value from the
table;start address + offset and puts it
;in A.

♦ After the execution of the above instructions, the program will branch to
address 1F08H (1F00H+08H) and transfer into the accumulator the data
byte retrieved from that location (from the look-up table)
Keil software introduction:

Download: https://www.keil.com/download/product/

Product: C51

Device: AT89C51ED2

Demo: https://www.youtube.com/watch?v=mhHJV21CDjs.
 Instruction Types
♦ The C8051F020 instructions are divided into five functional
groups:
Arithmetic operations
Logical operations
Data transfer operations
Boolean variable operations
Program branching operations

53
 Arithmetic Operations

♦ [@Ri] implies contents

of memory location
pointed to by R0 or R1

♦ Rn refers to registers
R0-R7 of the currently
selected register bank

54
 ADD A,<source-byte> ADDC A,<source-byte>
♦ ADD adds the data byte specified by the source operand to
the accumulator, leaving the result in the accumulator
♦ ADDC adds the data byte specified by the source operand,
the carry flag and the accumulator contents, leaving the
result in the accumulator
♦ Operation of both the instructions, ADD and ADDC, can
affect the carry flag (CY), auxiliary carry flag (AC) and the
overflow flag (OV)
CY=1 If there is a carryout from bit 7; cleared otherwise
AC =1 If there is a carryout from the lower 4-bit of A i.e. from bit 3;
cleared otherwise
OV=1 If the signed result cannot be expressed within the number
of bits in the destination operand; cleared otherwise

55
 SUBB A,<source-byte>
♦ SUBB subtracts the specified data byte and the carry flag together from
the accumulator, leaving the result in the accumulator
CY=1 If a borrow is needed for bit 7; cleared otherwise
AC =1 If a borrow is needed for bit 3, cleared otherwise
OV=1 If a borrow is needed into bit 6, but not into bit 7, or into bit 7,
but not into bit 6.
♦ Example:
The accumulator holds 0C1H (11000001B), Register1 holds 40H
(01000000B) and the CY=1.The instruction,

SUBB A, R1

gives the value 70H (01110000B) in the accumulator, with the CY=0 and
AC=0 but OV=1

56
 INC <byte>
♦ Increments the data variable by 1. The instruction is used in register,
direct or register direct addressing modes
♦ Example:
INC6FH
If the internal RAM location 6FH contains 30H, then the instruction
increments this value, leaving 31H in location 6FH
♦ Example:
MOVR1, #5E
INCR1
INC@R1
♦ If R1=5E (01011110) and internal RAM location 5FH contains 20H, the
instructions will result in R1=5FH and internal RAM location 5FH to
increment by one to 21H

57
 DEC <byte>
♦ The data variable is decremented by 1

♦ The instruction is used in accumulator, register, direct or

register direct addressing modes

♦ A data of value 00H underflows to FFH after the operation

♦ No flags are affected

58
 INC DPTR
♦ Increments the 16-bit data pointer by 1

♦ DPTR is the only 16-bit register that can be incremented

♦ The instruction adds one to the contents of DPTR directly

59
 MUL AB
♦ Multiplies A & B and the 16-bit result stored in [B15-8], [A7-0]

♦ Multiplies the unsigned 8-bit integers in the accumulator and the B

register

♦ The Low order byte of the 16-bit product will go to the accumulator
and the High order byte will go to the B register

♦ If the product is greater than 255 (FFH), the overflow flag is set;
otherwise it is cleared. The carry flag is always cleared.

♦ If ACC=85 (55H) and B=23 (17H), the instruction gives the product
1955 (07A3H), so B is now 07H and the accumulator is A3H. The
overflow flag is set and the carry flag is cleared.

60
 DIV AB
♦ Divides A by B

♦ THE INTEGER PART OF THE QUOTIENT IS STORED IN

A AND THE REMAINDER GOES TO THE B REGISTER

♦ If ACC=90 (5AH) and B=05(05H), the instruction leaves 18

(12H) in ACC and the value 00 (00H) in B, since 90/5 = 18
(quotient) and 00 (remainder)

♦ Carry and OV are both cleared

♦ If B contains 00H before the division operation, then the

values stored in ACC and B are undefined and an overflow
flag is set. The carry flag is cleared.

61
 DA A
♦ This is a decimal adjust instruction
♦ It adjusts the 8-bit value in ACC resulting from operations
like ADD or ADDC and produces two 4-bit digits (in packed
Binary Coded Decimal (BCD) format)
♦ Effectively, this instruction performs the decimal conversion
by adding 00H, 06H, 60H or 66H to the accumulator,
depending on the initial value of ACC and PSW
♦ If ACC bits A3-0 are greater than 9 (xxxx1010-xxxx1111), or
if AC=1, then a value 6 is added to the accumulator to
produce a correct BCD digit in the lower order nibble
♦ If CY=1, because the high order bits A7-4 is now exceeding
9 (1010xxxx-1111xxxx), then these high order bits will be
increased by 6 to produce a correct proper BCD in the high
order nibble but not clear the carry
62
 Logical Operations

♦ Logical instructions perform Boolean operations (AND, OR,

XOR, and NOT) on data bytes on a bit-by-bit basis
63
 ANL <dest-byte>,<source-byte>
♦ This instruction performs the logical AND operation on the
source and destination operands and stores the result in the
destination variable

♦ No flags are affected

♦ Example:
ANLA,R2
If ACC=D3H (11010011) and R2=75H (01110101), the
result of the instruction is ACC=51H (01010001)

♦ The following instruction is also useful when there is a need

to mask a byte

♦ Example:
ANLP1,#10111001B
64
 ORL <dest-byte>,<source-byte>
♦ This instruction performs the logical OR operation on the
source and destination operands and stores the result in the
destination variable

♦ No flags are affected

♦ Example:
ORLA,R2
If ACC=D3H (11010011) and R2=75H (01110101), the
result of the instruction is ACC=F7H (11110111)

♦ Example:
ORLP1,#11000010B
This instruction sets bits 7, 6, and 1 of output Port 1

65
 XRL <dest-byte>,<source-byte>
♦ This instruction performs the logical XOR (Exclusive OR)
operation on the source and destination operands and
stores the result in the destination variable

♦ No flags are affected

♦ Example:
XRLA,R0
If ACC=C3H (11000011) and R0=AAH (10101010), then the
instruction results in ACC=69H (01101001)

♦ Example:
XRLP1,#00110001
This instruction complements bits 5, 4, and 0 of
output Port 1
66
 CLR A and CPL A

CLR A
♦ This instruction clears the accumulator (all bits set to 0)
♦ No flags are affected
♦ If ACC=C3H, then the instruction results in ACC=00H

CPL A
♦ This instruction logically complements each bit of the accumulator (one’s
complement)
♦ No flags are affected
♦ If ACC=C3H (11000011), then the instruction results in ACC=3CH (00111100)

67
 RL A
♦ The 8 bits in the accumulator are rotated one bit to the left.
Bit 7 is rotated into the bit 0 position.

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction results in

ACC=87H (10000111) with the carry unaffected

68
 RLC A
♦ The instruction rotates the accumulator contents one bit to
the left through the carry flag

♦ Bit 7 of the accumulator will move into carry flag and the
original value of the carry flag will move into the Bit 0
position

♦ No other flags are affected

♦ If ACC=C3H (11000011), and the carry flag is 1, the

instruction results in ACC=87H (10000111) with the carry
flag set

69
 RR A
♦ The 8 bits in the accumulator are rotated one bit to the right.
Bit 0 is rotated into the bit 7 position.

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction results in

ACC=E1H (11100001) with the carry unaffected

70
 RRC A
♦ The instruction rotates the accumulator contents one bit to
the right through the carry flag

♦ The original value of carry flag will move into Bit 7 of the
accumulator and Bit 0 rotated into carry flag

♦ No other flags are affected

♦ If ACC=C3H (11000011), and the carry flag is 0, the

instruction results in ACC=61H (01100001) with the carry
flag set

71
 SWAP A
♦ This instruction interchanges the low order 4-bit nibbles
(A3-0) with the high order 4-bit nibbles (A7-4) of the ACC

♦ The operation can also be thought of as a 4-bit rotate

instruction

♦ No flags are affected

♦ If ACC=C3H (11000011), then the instruction leaves

ACC=3CH (00111100)

72
 Data Transfer Instructions
Mnemonic Description
MOV @Ri, direct [@Ri] = [direct]
MOV @Ri, #data [@Ri] = immediate data
MOV DPTR, #data 16 [DPTR] = immediate data
MOVC A,@A+DPTR A = Code byte from [@A+DPTR]
MOVC A,@A+PC A = Code byte from [@A+PC]
MOVX A,@Ri A = Data byte from external ram [@Ri]
MOVX A,@DPTR A = Data byte from external ram [@DPTR]
MOVX @Ri, A External[@Ri] = A
MOVX @DPTR,A External[@DPTR] = A
PUSH direct Push into stack
POP direct Pop from stack
XCH A,Rn A = [Rn], [Rn] = A
XCH A, direct A = [direct], [direct] = A
XCH A, @Ri A = [@Rn], [@Rn] = A
XCHD A,@Ri Exchange low order digits

73
 MOV <dest-byte>,<source-byte>
♦ This instruction moves the source byte into the destination location
♦ The source byte is not affected, neither are any other registers or flags
♦ Example:

MOVR1,#60;R1=60H
MOVA,@R1 ;A=[60H]
MOVR2,#61;R2=61H
ADDA,@R2 ;A=A+[61H]
MOVR7,A ;R7=A

♦ If internal RAM locations 60H=10H, and 61H=20H, then after the

operations of the above instructions R7=A=30H. The data contents of
memory locations 60H and 61H remain intact.

74
 MOV DPTR, #data 16
♦ This instruction loads the data pointer with the 16-bit
constant and no flags are affected

♦ Example:
MOVDPTR,#1032

♦ This instruction loads the value 1032H into the data pointer,
i.e. DPH=10H and DPL=32H.

75
 MOVC A,@A + <base-reg>
♦ This instruction moves a code byte from program memory into ACC
♦ The effective address of the byte fetched is formed by adding the original 8-bit
accumulator contents and the contents of the base register, which is either the
data pointer (DPTR) or program counter (PC)
♦ 16-bit addition is performed and no flags are affected
♦ The instruction is useful in reading the look-up tables in the program memory
♦ If the PC is used, it is incremented to the address of the following instruction
before being added to the ACC
♦ Example:
CLRA
LOC1: INCA
MOVC A,@A + PC
RET
Look_up DB 10H
DB 20H
DB 30H
DB 40H
♦ The subroutine takes the value in the accumulator to 1 of 4 values
defined by the DB (define byte) directive
♦ After the operation of the subroutine it returns ACC=20H
76
 MOVX <dest-byte>,<source-byte>
♦ This instruction transfers data between ACC and a byte of external data
memory

♦ There are two forms of this instruction, the only difference between them
is whether to use an 8-bit or 16-bit indirect addressing mode to access
the external data RAM

♦ The 8-bit form of the MOVX instruction uses the EMI0CN SFR to
determine the upper 8 bits of the effective address to be accessed and
the contents of R0 or R1 to determine the lower 8 bits of the effective
address to be accessed

♦ Example:
MOV EMI0CN,#10H ;Load high byte of
;address into EMI0CN.
MOV R0,#34H ;Load low byte of
;address into R0(or R1).
MOVX A,@R0 ;Load contents of 1034H
;into ACC.

77
 MOVX <dest-byte>,<source-byte>
♦ The 16-bit form of the MOVX instruction accesses the memory location
pointed to by the contents of the DPTR register

♦ Example:
MOVDPTR,#1034H ;Load DPTR with 16 bit
;address to read (1034H).
MOVX A,@DPTR ;Load contents of 1034H
;into ACC.

♦ The above example uses the 16-bit immediate MOV DPTR instruction to
set the contents of DPTR

♦ Alternately, the DPTR can be accessed through the SFR registers DPH,
which contains the upper 8 bits of DPTR, and DPL, which contains the
lower 8 bits of DPTR

78
 PUSH Direct
♦ This instruction INCREMENTS THE STACK POINTER (SP) BY 1

♦ The contents of Direct, which is an internal memory location or a SFR,

are copied into the internal RAM location addressed by the stack pointer

♦ No flags are affected

♦ Example:
PUSH 22H
PUSH 23H

♦ Initially the SP points to memory location 4FH and the contents of

memory locations 22H and 23H are 11H and 12H respectively. After the
above instructions, SP=51H, and the internal RAM locations 50H and
51H will store 11H and 12H respectively.

79
 POP Direct
♦ This instruction reads the contents of the internal RAM location
addressed by the stack pointer (SP) and decrements the stack pointer
by 1. The data read is then transferred to the Direct address which is an
internal memory or a SFR. No flags are affected.

♦ Example:
POPDPH
POPDPL

♦ If SP=51H originally and internal RAM locations 4FH, 50H and 51H
contain the values 30H, 11H and 12H respectively, the instructions
above leave SP=4FH and DPTR=1211H

POPSP
♦ If the above line of instruction follows, then SP=30H. In this case, SP is
decremented to 4EH before being loaded with the value popped (30H)

80
 XCH A,<byte>
♦ This instruction swaps the contents of ACC with the contents
of the indicated data byte

♦ Example:
XCHA,@R0

♦ Suppose R0=2EH, ACC=F3H (11110011) and internal RAM

location 2EH=76H (01110110). The result of the above
instruction leaves RAM location 2EH=F3H and ACC=76H.

81
 XCHD A,@Ri
♦ This instruction exchanges the low order nibble of ACC (bits
0-3), with that of the internal RAM location pointed to by Ri
register

♦ The high order nibbles (bits 7-4) of both the registers remain
the same

♦ No flags are affected

♦ Example:
XCHDA,@R0

If R0=2EH, ACC=76H (01110110) and internal RAM location

2EH=F3H (11110011), the result of the instruction leaves
RAM location 2EH=F6H (11110110) and
ACC=73H (01110011)
82
 Boolean Variable Instructions
♦ The C8051F020 processor
Mnemonic Description
CLR C Clear C
can perform single bit
CLR bit Clear direct bit
operations SETB C Set C

SETB bit Set direct bit

♦ The operations include set, CPL C Complement c

clear, as well as and, or and CPL bit Complement direct bit

complement instructions ANL C, bit AND bit with C

ANL C, bit AND NOT bit with C

ORL C, bit OR bit with C

♦ Also included are bit–level ORL C, bit OR NOT bit with C
moves or conditional jump MOV C, bit MOV bit to C
instructions MOV bit, C MOV C to bit

JC rel Jump if C set

♦ All bit accesses use direct JNC rel Jump if C not set

JB bit, rel Jump if specified bit set

addressing
JNB bit, rel Jump if specified bit not set
if specified bit set then clear it and
JBC bit, rel
jump
83
 CLR <bit>
♦ This operation clears (reset to 0) the specified bit indicated
in the instruction

♦ No other flags are affected

♦ CLR instruction can operate on the carry flag or any

directly-addressable bit

♦ Example:
CLRP2.7
If Port 2 has been previously written with DCH (11011100),
then the operation leaves the port set to 5CH (01011100)

84
 SETB <bit>
♦ This operation sets the specified bit to 1

♦ SETB instruction can operate on the carry flag or any

directly-addressable bit

♦ No other flags are affected

♦ Example:
SETB C
SETB P2.0
♦ If the carry flag is cleared and the output Port 2 has the
value of 24H (00100100), then the result of the instructions
sets the carry flag to 1 and changes the Port 2 value to 25H
(00100101)

85
 CPL <bit>
♦ This operation complements the bit indicated by the operand

♦ No other flags are affected

♦ CPL instruction can operate on the carry flag or any

directly-addressable bit

♦ Example:
CPLP2.1
CPLP2.2
♦ If Port 2 has the value of 53H (01010011) before the start of
the instructions, then after the execution of the instructions it
leaves the port set to 55H (01010101)

86
 ANL C, <source-bit>
♦ This instruction ANDs the bit addressed with the Carry bit and stores the result in
the Carry bit itself

♦ If the source bit is a logical 0, then the instruction clears the carry flag; else the
carry flag is left in its original value

♦ If a slash (/) is used in the source operand bit, it means that the logical
complement of the addressed source bit is used, but the source bit itself is not
affected

♦ No other flags are affected

♦ Example:
MOVC,P2.0;Load C with input pin
;state of P2.0.
ANLC,P2.7;AND carry flag with ;bit 7
of P2.
MOVP2.1,C;Move C to bit 1 of Port 2.
ANLC,/OV ;AND with inverse of OV flag.

♦ If P2.0=1, P2.7=0 and OV=0 initially, then after the above instructions,
P2.1=0, CY=0 and the OV remains unchanged, i.e. OV=0
87
 ORL C, <source-bit>
♦ This instruction ORs the bit addressed with the Carry bit and stores the result in
the Carry bit itself

♦ It sets the carry flag if the source bit is a logical 1; else the carry is left in its
original value

♦ If a slash (/) is used in the source operand bit, it means that the logical
complement of the addressed source bit is used, but the source bit itself is not
affected

♦ No other flags are affected

♦ Example:
MOV C,P2.0 ;Load C with input pin
;state of P2.0.
ORL C,P2.7 ;OR carry flag with
;bit 7 of P2.
MOV P2.1,C ;Move C to bit 1 of
;port 2.
ORL C,/OV ;OR with inverse of OV
;flag.

88
 MOV <dest-bit>,<source-bit>
♦ The instruction loads the value of source operand bit into the destination
operand bit

♦ One of the operands must be the carry flag; the other may be any
directly-addressable bit

♦ No other register or flag is affected

♦ Example:
MOVP2.3,C
MOVC,P3.3
MOVP2.0,C

♦ If P2=C5H (11000101), P3.3=0 and CY=1 initially, then after the above
instructions, P2=CCH (11001100) and CY=0.

89
 JC rel
♦ This instruction branches to the address, indicated by the label, if the
carry flag is set, otherwise the program continues to the next instruction

♦ No flags are affected

♦ Example:
CLRC
SUBB A,R0
JC ARRAY1
MOVA,#20H

♦ The carry flag is cleared initially. After the SUBB instruction, if the value
of A is smaller than R0, then the instruction sets the carry flag and
causes program execution to branch to ARRAY1 address, otherwise it
continues to the MOV instruction.

90
 JNC rel
♦ This instruction branches to the address, indicated by the label, if the
carry flag is not set, otherwise the program continues to the next
instruction

♦ No flags are affected. The carry flag is not modified.

♦ Example:
CLRC
SUBB A,R0
JNCARRAY2
MOVA,#20H

♦ The above sequence of instructions will cause the jump to be taken if the
value of A is greater than or equal to R0. Otherwise the program will
continue to the MOV instruction.

91
 JB <bit>,rel
♦ This instruction jumps to the address indicated if the
destination bit is 1, otherwise the program continues to the
next instruction

♦ No flags are affected. The bit tested is not modified.

♦ Example:
JB ACC.7,ARRAY1
JB P1.2,ARRAY2

♦ If the accumulator value is 01001010 and Port 1=57H

(01010111), then the above instruction sequence will cause
the program to branch to the instruction at ARRAY2

92
 JNB <bit>,rel
♦ This instruction jumps to the address indicated if the
destination bit is 0, otherwise the program continues to the
next instruction

♦ No flags are affected. The bit tested is not modified.

♦ Example:
JNBACC.6,ARRAY1
JNBP1.3,ARRAY2

♦ If the accumulator value is 01001010 and Port 1=57H

(01010111), then the above instruction sequence will cause
the program to branch to the instruction at ARRAY2

93
 JBC <bit>,rel
♦ If the source bit is 1, this instruction clears it and branches to
the address indicated; else it proceeds with the next
instruction

♦ The bit is not cleared if it is already a 0. No flags are

affected.

♦ Example:
JBCP1.3,ARRAY1
JBCP1.2,ARRAY2

♦ If P1=56H (01010110), the above instruction sequence will

cause the program to branch to the instruction at
ARRAY2, modifying P1 to 52H (01010010)
94
 Program Branching Instructions
♦ Program branching Mnemonic Description

ACALL addr11 Absolute subroutine call

instructions are used to
LCALL addr16 Long subroutine call
control the flow of actions in RET Return from subroutine
a program RETI Return from interrupt

AJMP addr11 Absolute jump

♦ Some instructions provide

LJMP addr16 Long jump

SJMP rel Short jump

decision making JMP @A+DPTR Jump indirect

capabilities and transfer JZ rel Jump if A=0

control to other parts of the JNZ rel Jump if A NOT=0

program, e.g. conditional CJNE A,direct,rel

and unconditional branches CJNE A,#data,rel

Compare and Jump if Not Equal
CJNE Rn,#data,rel

CJNE @Ri,#data,rel

DJNZ Rn,rel
Decrement and Jump if Not
Zero
DJNZ direct,rel

NOP No Operation

95
 ACALL addr11
♦ This instruction unconditionally calls a subroutine indicated by the
address
♦ The operation will cause the PC to increase by 2, then it pushes the
16-bit PC value onto the stack (low order byte first) and increments the
stack pointer twice
♦ The PC is now loaded with the value addr11 and the program execution
continues from this new location
♦ The subroutine called must therefore start within the same 2 kB block of
the program memory

♦ No flags are affected

♦ Example:
ACALL LOC_SUB

♦ If SP=07H initially and the label “LOC_SUB” is at program memory

location 0567H, then executing the instruction at location 0230H,
SP=09H, internal RAM locations 08H and 09H will contain 32H
and 02H respectively and PC=0567H

96
 LCALL addr16
♦ This instruction calls a subroutine located at the indicated address

♦ The operation will cause the PC to increase by 3, then it pushes the

16-bit PC value onto the stack (low order byte first) and increments the
stack pointer twice

♦ The PC is then loaded with the value addr16 and the program execution
continues from this new location

♦ Since it is a Long call, the subroutine may therefore begin anywhere in

the full 64 kB program memory address space

♦ No flags are affected

♦ Example:
LCALL LOC_SUB

♦ Initially, SP=07H and the label “LOC_SUB” is at program memory

location 2034H. Executing the instruction at location 0230H,
SP=09H, internal RAM locations 08H and 09H contain 33H
and 02H respectively and PC=2034H
97
 RET
♦ This instruction returns the program from a subroutine

♦ RET pops the high byte and low byte address of PC from
the stack and decrements the SP by 2

♦ The execution of the instruction will result in the program to

resume from the location just after the “call” instruction

♦ No flags are affected

♦ Suppose SP=0BH originally and internal RAM locations 0AH

and 0BH contain the values 30H and 02H respectively. The
instruction leaves SP=09H and program execution will
continue at location 0230H

98
 RETI
♦ This instruction returns the program from an interrupt
subroutine
♦ RETI pops the high byte and low byte address of PC from
the stack and restores the interrupt logic to accept additional
interrupts
♦ SP decrements by 2 and no other registers are affected.
However the PSW is not automatically restored to its
pre-interrupt status
♦ After the RETI, program execution will resume immediately
after the point at which the interrupt is detected
♦ Suppose SP=0BH originally and an interrupt is detected
during the instruction ending at location 0213H
Internal RAM locations 0AH and 0BH contain the values 14H and
02H respectively
The RETI instruction leaves SP=09H and returns
99
program execution to location 0234H
 AJMP addr11
♦ The AJMP instruction transfers program execution to the
destination address which is located at the absolute short
range distance (short range means 11-bit address)

♦ The destination must therefore be within the same 2kB block

of program memory

♦ Example:
AJMP NEAR

♦ If the label NEAR is at program memory location 0120H, the

AJMP instruction at location 0234H loads the PC with 0120H

10
 LJMP addr16
♦ The LJMP instruction transfers program execution to the
destination address which is located at the absolute long
range distance (long range means 16-bit address)

♦ The destination may therefore be anywhere in the full 64 kB

program memory address space

♦ No flags are affected

♦ Example:
LJMP FAR_ADR

♦ If the label FAR_ADR is at program memory location 3456H,

the LJMP instruction at location 0120H loads the PC
with 3456H
10
 SJMP rel
♦ This is a short jump instruction, which increments the PC by 2
and then adds the relative value ‘rel’ (signed 8-bit) to the PC

♦ This will be the new address where the program would branch
to unconditionally

♦ Therefore, the range of destination allowed is from -128 to

+127 bytes from the instruction

♦ Example:
SJMP RELSRT

♦ If the label RELSRT is at program memory location 0120H

and the SJMP instruction is located at address 0100H,
after executing the instruction, PC=0120H.
10
 JMP @A + DPTR
♦ This instruction adds the 8-bit unsigned value of the ACC to the 16-bit
data pointer and the resulting sum is returned to the PC

♦ Neither ACC nor DPTR is altered

♦ No flags are affected

♦ Example:
MOVDPTR, #LOOK_TBL
JMP@A + DPTR
LOOK_TBL:AJMP LOC0
AJMP LOC1
AJMP LOC2
If the ACC=02H, execution jumps to LOC1

♦ AJMP is a two byte instruction

10
 JZ rel
♦ This instruction branches to the destination address if
ACC=0; else the program continues to the next instruction

♦ The ACC is not modified and no flags are affected

♦ Example:
SUBB A,#20H
JZ LABEL1
DECA

♦ If ACC originally holds 20H and CY=0, then the SUBB

instruction changes ACC to 00H and causes the program
execution to continue at the instruction identified by
LABEL1; otherwise the program continues to the DEC
instruction

10
 JNZ rel
♦ This instruction branches to the destination address if any bit
of ACC is a 1; else the program continues to the next
instruction

♦ The ACC is not modified and no flags are affected

♦ Example:
DECA
JNZLABEL2
MOVRO, A

♦ If ACC originally holds 00H, then the instructions change

ACC to FFH and cause the program execution to continue at
the instruction identified by LABEL2; otherwise the program
continues to MOV instruction

10
 CJNE <dest-byte>,<source-byte>,rel
♦ This instruction compares the magnitude of the dest-byte and the
source-byte and branches if their values are not equal

♦ The carry flag is set if the unsigned dest-byte is less than the unsigned
integer source-byte; otherwise, the carry flag is cleared

♦ Neither operand is affected

♦ Example:
CJNE R3,#50H,NEQU
… … ;R3 = 50H
NEQU: JC LOC1 ;If R3 < 50H
… … ;R7 > 50H
LOC1: … … ;R3 < 50H

10
 DJNZ <byte>,<rel-addr>
♦ This instruction is ”decrement jump not zero”
♦ It decrements the contents of the destination location and if the resulting
value is not 0, branches to the address indicated by the source operand
♦ An original value of 00H underflows to FFH
♦ No flags are affected

♦ Example:
DJNZ 20H,LOC1
DJNZ 30H,LOC2
DJNZ 40H,LOC3

♦ If internal RAM locations 20H, 30H and 40H contain the values 01H,
5FH and 16H respectively, the above instruction sequence will cause a
jump to the instruction at LOC2, with the values 00H, 5EH, and 15H in
the 3 RAM locations.
Note, the first instruction will not branch to LOC1 because the [20H] = 00H,
hence the program continues to the second instruction
Only after the execution of the second instruction (where the
location [30H] = 5FH), then the branching takes place

10
 NOP
♦ This is the no operation instruction
♦ The instruction takes one machine cycle operation time
♦ Hence it is useful to time the ON/OFF bit of an output port
♦ Example:
CLRP1.2
NOP
NOP
NOP
NOP
SETB P1.2

♦ The above sequence of instructions outputs a low-going output pulse on

bit 2 of Port 1 lasting exactly 5 cycles.
Note a simple SETB/CLR generates a 1 cycle pulse, so four additional
cycles must be inserted in order to have a 5-clock
pulse width

10
However, the relation between machine cycle and clock cycle depends upon the
manufacturer. Ex: AT89C51 by Atmel consider 12 clock cycles per machine cycle. But,
other 8051 manufactured by Dallas consider 1 clock cycles per machine cycle.

Instruction cycle: Fetch, decode, execute, write back into memory and etc.
• Note: Mnemonic will occupy 1
byte memory.

• No register will occupy memory

of ROM.

• Address will occupy memory

depending upon the number of bits.

• Data also occupy memory

depending upon number of bits.