Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology ⇒ Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors ⇒ 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology ⇒ Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors ⇒ 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors ⇒ 16 pins nesting
8 and 16 bit processors ⇒ 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 1
multiplexed Intel 8085 (8 bit processor)
General Microprocessor Functional blocks

Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations information to the timing and
of the microprocessor control unit 2
8086 Microprocessor

Overview
First 16 - bit processor released by
INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory ⇒ can

address up to 220 = 1 megabytes of
memory space.

3
8086 Microprocessor
Common signals

Pins and Signals AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

https://www.geeksforgeeks.org/pin-diagram-8086-microprocessor/ 4
8086 Microprocessor
Common signals

Pins and Signals BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
6
8086 Microprocessor
Common signals

Pins and Signals

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 7

 8086 Microprocessor
Common signals

Pins and Signals RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
The 8086 does not have on-chip clock
interrupt acknowledge cycle.
generation circuit. Hence the clock
generator chip, 8284 is connected to the This signal is active high and internally
synchronized. 8
CLK pin of 8086.
8086 Microprocessor
Min/ Max Pins

Pins and Signals

The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

9
8086 Microprocessor
Minimum mode signals

Pins and Signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers.

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
10
DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
8086 Microprocessor
Minimum mode signals

Pins and Signals

HOLD Input signal to the processor from the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

12
8086 Microprocessor
Maximum mode signals

Pins and Signals

Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

13
8086 Microprocessor
Maximum mode signals

Pins and Signals

(Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

▪ These signals provide the status of instruction queue. 14

8086 Microprocessor
Maximum mode signals

Pins and Signals

15
 Inside The 8088/8086…pipelining
• Pipelining
– Two ways to make CPU process information faster:
• Increase the working frequency – technology dependent
• Change the internal architecture of the CPU

– Pipelining is to allow CPU to fetch and execute at the

same time
8086 Microprocessor
Architecture
Dedicated Adder to
generate 20 bit address

Four 16-bit
segment
registers

Code Segment
(CS)
Data Segment
(DS)
Stack Segment
(SS)
Extra Segment
(ES)

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
22
 Bus Interface Unit (BIU)

• It provides the interface of 8086 to external memory and I/O devices

through the System Bus. It performs various machine cycles such as
memory read, I/O read, etc. to transfer data between memory and
I/O devices.
• BIU performs the following functions:
• It generates the 20-bit physical address for memory access.

• It fetches instructions from the memory.

• It transfers data to and from the memory and I/O.

• Maintains the 6-byte pre-fetch instruction queue(supports

pipelining).

• BIU mainly contains the 4 Segment registers, the Instruction

Pointer, a pre-fetch queue, and an Address Generation Circuit.
 Instruction Pointer (IP):
• It is a 16-bit register. It holds the offset of the next instructions in
the Code Segment (CS).
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20-bit physical address of the
Code Segment.
• The address of the next instruction is calculated by using the
formula CS x 10H + IP

Example: If CS = 4321H and IP = 1000H

then CS x 10H = 43210H + offset = 44210H, the address of
the next instruction
Here Offset = Instruction Pointer(IP)
• Code Segment register: (16 Bit
register): CS holds the base address for the
Code Segment. All programs are stored in
the Code Segment and accessed via the IP.
• Data Segment register: (16 Bit
register): DS holds the base address for the
Data Segment.
• Stack Segment register: (16 Bit
register): SS holds the base address for the
Stack Segment.
• Extra Segment register: (16 Bit register):
ES holds the base address for the Extra
• Address Generation Circuit:
• The BIU has a Physical Address Generation
Circuit.
• It generates the 20-bit physical address using
Segment and Offset addresses using the
formula:
• Physical Address = Segment Address x 10H +
Offset Address
 Execution Unit (EU)
• The main components of the EU are General purpose registers, the
ALU, Special purpose registers, the Instruction Register and
Instruction Decoder, and the Flag/Status Register.
• Functions are:
1. Fetches instructions from the Queue in BIU, decodes, and executes
arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the
microprocessor.
3. Send request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine
cycles
• 8086 has four 16-bit general purpose registers: AX, BX, CX,
and DX which store intermediate values during execution.
Each of these has two 8-bit parts (higher and lower).
• AX register: (Combination of AL and AH Registers)
It holds operands and results during multiplication and
division operations. Also an accumulator during String
operations.

• BX register: (Combination of BL and BH Registers)

It holds the memory address (offset address) in indirect
addressing modes.

• CX register: (Combination of CL and CH Registers)

It holds the count for instructions like a loop, rotates, shifts
and string operations.

• DX register: (Combination of DL and DH Registers)

It is used with AX to hold 32-bit values during multiplication
• Arithmetic Logic Unit (16-bit): Performs 8 and
16-bit arithmetic and logic operations.
• Special purpose registers (16-bit): Special purpose
registers are called Offset registers also. Which points to
specific memory locations under each segment.
• Stack Pointer: Points to Stack top. Stack is in Stack
Segment, used during instructions like PUSH, POP, CALL,
RET etc.
• Base Pointer: BP can hold the offset addresses of any
location in the stack segment. It is used to access random
locations of the stack.
• Source Index: It holds offset address in Data Segment
during string operations.
• Destination Index: It holds offset address in Extra
Segment during string operations.
• Instruction Register and Instruction Decoder:
• The EU fetches an opcode from the queue into the instruction
register. The instruction decoder decodes it and sends the
information to the control circuit for execution.
• Flag/Status register (16 bits): It has 9 flags that help change or
recognize the state of the microprocessor.
• 6 Status flags:
Carry flag(CF) Parity flag(PF) Auxiliary carry flag(AF) Zero
flag(Z) Sign flag(S) Overflow flag (O)
• Status flags are updated after every arithmetic and logic
operation.
• 3 Control flags:
Trap flag(TF) Interrupt flag(IF) Direction flag(DF)
• These flags can be set or reset using control instructions
Memory segmentation
 8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment
Registers

• 8086’s 1-megabyte • The 8086 can directly • Programs obtain access to

memory is divided address four segments (256 code and data in the
into segments of up K bytes within the 1 M byte segments by changing the
to 64K bytes each. of memory) at a particular segment register content
time. to point to the desired
segments.
32
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Code Segment Register
Registers
• 16-bit

• CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.

• BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.

• That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.

33
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Data Segment Register
Registers
• 16-bit

• Points to the current data segment; operands for most instructions are fetched
from this segment.

• The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a
16-bit displacement are used as offset for computing the 20-bit physical
address.

34
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Stack Segment Register
Registers
• 16-bit

• Points to the current stack.

• The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.

• In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).

35
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment
Registers
Extra Segment Register

• 16-bit

• Points to the extra segment in which data (in excess of 64K pointed to by the
DS) is stored.

• String instructions use the ES and DI to determine the 20-bit physical address
for the destination.

36
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment
Registers Instruction Pointer

• 16-bit

• Always points to the next instruction to be executed within

the currently executing code segment.

• So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64KB of the code
segment area.

• Its content is automatically incremented as the execution

of the next instruction takes place.

37
8086 Microprocessor
Bus Interface Unit (BIU)

Instruction queue

• A group of First-In-First-Out (FIFO) in

which up to 6 bytes of instruction
code are pre fetched from the
memory ahead of time.

• This is done in order to speed up the

execution by overlapping instruction
fetch with execution.

• This mechanism is known as

pipelining.

Architecture
38
8086 Microprocessor
Execution Unit (EU)

EU decodes and Architecture

executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 39
DX can be used as DH and DL
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Accumulator Register (AX)
Registers

• Consists of two 8-bit registers AL and AH, which can be

combined together and used as a 16-bit register AX.

• AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

• The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

• Multiplication and Division instructions also use the AX or

AL.

40
8086 Microprocessor
Execution Unit (EU)
Architecture
EU Base Register (BX)
Registers
• Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

• BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

• This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

• All memory references utilizing this register content for

addressing use DS as the default segment register.

41
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Counter Register (CX)
Registers
• Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

• When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

• Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

42
8086 Microprocessor
Execution Unit (EU)
Architecture
EU
Registers

43
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
• SP and BP are used to access data in the stack segment.

• SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

• SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

• BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

44
8086 Microprocessor
Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

45
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 46
 8086 Microprocessor
Addressing Modes
• Every instruction of a program has to operate on a data.
• The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for register and
2. Immediate Addressing immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for memory data
6. Indexed Addressing

7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for I/O ports
10. Indirect I/O port Addressing

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

47
 8086 Microprocessor Group I : Addressing modes for register and

1. Register Addressing
Addressing Modes
The instruction will specify the name of the
immediate data

register which holds the data to be operated by

2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL) ← (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

48
 8086 Microprocessor Group I : Addressing modes for register and
immediate data

1. Register Addressing
Addressing Modes
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL) ← 08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) ← 0A9FH
12. Implied Addressing

49
8086 Microprocessor

Addressing Modes : Memory Access

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

50
8086 Microprocessor

Addressing Modes : Memory Access

• 20 Address lines ⇒ 8086 can address up to 220 = 1M bytes
of memory

• However, the largest register is only 16 bits

• Physical Address will have to be calculated Physical Address :

Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.

• Memory Address represented in the form – Seg : Offset (Eg

- 89AB:F012)

• Each time the processor wants to access memory, it takes the

contents of a segment register, shifts it one hexadecimal place to
the left (same as multiplying by 1610), then add the required
offset to form the 20- bit address
16 bytes of contiguous
memory

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
51
8086 Microprocessor

Addressing Modes : Memory Access

• To access memory, we use these four registers: BX, SI, DI, BP

• Combining these registers inside [ ] symbols, we can get different

memory locations (Effective Address, EA)

• Supported combinations:

[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI] [BP + DI + d8]
[BX]

[SI + d8] [BX + SI + d16] [SI + d16]

[DI + d8] [BX + DI + d16] [DI + d16]
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16]

BX SI
+ disp
BP DI 52
 8086 Microprocessor Group II : Addressing modes for memory data

1. Register Addressing Addressing Modes

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

53
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA +1)
54
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes
In Based Addressing, BX or BP is used to hold the
data

1. Register Addressing
base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H ← 08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX) ← (MA) or,

(AL) ← (MA)
55
(AH) ← (MA + 1)
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned
2. Immediate Addressing 16-bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H ← A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX) ← (MA) or,

(CL) ← (MA)
(CH) ← (MA + 1)
56
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH ← 0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX) ← (MA) or,

11. Relative Addressing (DL) ← (MA)

(DH) ← (MA + 1)
12. Implied Addressing

57
 8086 Microprocessor Group II : Addressing modes for memory

Addressing Modes Employed in string operations to operate on string

data

1. Register Addressing
data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of the (MAE) ← (MA)

Extra segment register
If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI)58+ 1
 8086 Microprocessor Group III : Addressing modes for I/O

Addressing Modes
These addressing modes are used to access data
ports

1. Register Addressing
from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL) ← (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT) ← (AX)

Content of AX is moved to port

whose address is specified by DX
register. 59
 8086 Microprocessor Group IV : Relative Addressing
mode

1. Register Addressing Addressing Modes

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH ← 0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA

12. Implied Addressing If ZF = 1, then the program control jumps to

new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
60
 8086 Microprocessor Group IV : Implied Addressing
mode

1. Register Addressing
Addressing Modes
2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

61
8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

https://www.tutorialspoint.com/assembly_programming/assembly_logical_instructions.ht
m

62
8086 Microprocessor

Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to registers, memory

locations and I/O ports.

Generally involve two operands: Source operand and Destination operand of the
same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be
moved to 16-bit register/ memory.

63
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2) ← (reg1)

MOV mem, reg1 (mem) ← (reg1)
MOV reg2, mem (reg2) ← (mem)

MOV reg/ mem, data

MOV reg, data (reg) ← data

MOV mem, data (mem) ← data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2) ↔ (reg1)

XCHG mem, reg1 (mem) ↔ (reg1)

64
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (reg16)

PUSH mem (SP) ← (SP) – 2

MA S = (SS) x 16 10 + SP
(MA S ; MA S + 1) ← (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 16 10 + SP

(reg16) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2

POP mem MA S = (SS) x 16 10 + SP

(mem) ← (MA S ; MA S + 1)
(SP) ← (SP) + 2
65
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORT addr = (DX) OUT [DX], AL PORT addr = (DX)
(AL) ← (PORT) (PORT) ← (AL)

IN AX, [DX] PORT addr = (DX) OUT [DX], AX PORT addr = (DX)
(AX) ← (PORT) (PORT) ← (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL) ← (addr8) OUT addr8, AL (addr8) ← (AL)

IN AX, addr16 (AX) ← (addr16) OUT addr16, AX (addr16) ← (AX)

66
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2) ← (reg1) + (reg2)

ADD reg2, mem (reg2) ← (reg2) + (mem)
ADD mem, reg1 (mem) ← (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg) ← (reg)+ data

ADD mem, data (mem) ← (mem)+data

ADD A, data

ADD AL, data8 (AL) ← (AL) + data8

ADD AX, data16 (AX) ← (AX) +data16

67
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2) ← (reg1) + (reg2)+CF

ADC reg2, mem (reg2) ← (reg2) + (mem)+CF
ADC mem, reg1 (mem) ← (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg) ← (reg)+ data+CF

ADC mem, data (mem) ← (mem)+data+CF

ADC A, data

ADC AL, data8 (AL) ← (AL) + data8+CF

ADC AX, data16 (AX) ← (AX) +data16+CF

68
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2) ← (reg2) - (reg1)

SUB reg2, mem (reg2) ← (reg2) - (mem)
SUB mem, reg1 (mem) ← (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg) ← (reg) - data

SUB mem, data (mem) ← (mem) - data

SUB A, data

SUB AL, data8 (AL) ← (AL) - data8

SUB AX, data16 (AX) ← (AX) - data16

69
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2) ← (reg2) - (reg1) - CF

SBB reg2, mem (reg2) ← (reg2) - (mem)- CF
SBB mem, reg1 (mem) ← (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg) ← (reg) – data - CF

SBB mem, data (mem) ← (mem) - data - CF

SBB A, data

SBB AL, data8 (AL) ← (AL) - data8 - CF

SBB AX, data16 (AX) ← (AX) - data16 - CF

70
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8) ← (reg8) + 1

INC reg16 (reg16) ← (reg16) + 1

INC mem (mem) ← (mem) + 1

DEC reg/ mem

DEC reg8 (reg8) ← (reg8) - 1

DEC reg16 (reg16) ← (reg16) - 1

DEC mem (mem) ← (mem) - 1

71
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

MUL mem For byte : (AX) ← (AL) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX) ← (AL) x (reg8)

For word : (DX)(AX) ← (AX) x (reg16)

IMUL mem For byte : (AX) ← (AL) x (mem8)

For word : (DX)(AX) ← (AX) x (mem16)

72
8086 Microprocessor

Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL) ← (AX) :- (reg8) AL:Quotient; AH:Remainder
(AH) ← (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (reg16) Quotient AX: Quotient, DX: Remainder
(DX) ← (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL) ← (AX) :- (mem8) Quotient
(AH) ← (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX) ← (DX)(AX) :- (mem16) Quotient
(DX) ← (DX)(AX) MOD(mem16) Remainder

73
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags ← (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags ← (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags ← (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

74
8086 Microprocessor

Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags ← (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags ← (mem) – (data)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

75
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags ← (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags ← (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

76
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

77
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

78
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

79
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL
The TEST instruction
works same as the AND
operation, but unlike
AND instruction, it does
not change the first
operand. So, if we need
to check whether a
number in a register is
even or odd, we can also
do this using the TEST
instruction without
changing the original
number.

80
8086 Microprocessor

Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

81
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

82
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

83
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL … ROR, ROL

84
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions

❑ String : Sequence of bytes or words

❑ 8086 instruction set includes instruction for string movement, comparison, scan, load and store.

❑ REP instruction prefix : used to repeat execution of string instructions

❑ String instructions end with S or SB or SW. S represents string, SB string byte and SW string word.

❑ Offset or effective address of the source operand is stored in SI register and that of the destination
operand is stored in DI register.

❑ Depending on the status of DF, SI and DI registers are automatically updated.

❑ DF = 0 ⇒ SI and DI are incremented by 1 for byte and 2 for word.

❑ DF = 1 ⇒ SI and DI are decremented by 1 for byte and 2 for word.

85
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP Result should be zero for condition true

REPZ/ REPE While CX ≠ 0 and ZF = 1, repeat execution of string instruction

and
(Repeat CMPS or SCAS until ZF = 0) (CX) ← (CX) – 1

Result should not be zero for condition true

REPNZ/ REPNE
While CX ≠ 0 and ZF = 0, repeat execution of string instruction
(Repeat CMPS or SCAS until ZF = 1) and
(CX) ← (CX) - 1

Ex: rep movsb

Note: Always ‘REPZ’ instruction can be used in association with the string related
operations.
86
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E) ← (MA)

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1

If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

MOVSW MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1) ← (MA; MA + 1)

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2

If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

87
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 16 10 + (SI)

MAE = (ES) x 16 10 + (DI)

Modify flags ← (MA) - (MA E)

If (MA) > (MA E), then CF = 0; ZF = 0; SF = 0

If (MA) < (MA E), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MA E), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI) ← (DI) + 1; (SI) ← (SI) + 1
If DF = 1, then (DI) ← (DI) - 1; (SI) ← (SI) - 1

For word operation

If DF = 0, then (DI) ← (DI) + 2; (SI) ← (SI) + 2
If DF = 1, then (DI) ← (DI) - 2; (SI) ← (SI) - 2

88
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AL) > (MA E), then CF = 0; ZF = 0; SF = 0

If (AL) < (MA E), then CF = 1; ZF = 0; SF = 1
If (AL) = (MA E), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

SCASW MAE = (ES) x 16 10 + (DI)

Modify flags ← (AL) - (MA E)

If (AX) > (MA E ; MA E + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MA E ; MA E + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MA E ; MA E + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI) ← (DI) + 2

89
If DF = 1, then (DI) ← (DI) – 2
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 16 10 + (SI)

(AL) ← (MA)

If DF = 0, then (SI) ← (SI) + 1

If DF = 1, then (SI) ← (SI) – 1

LODSW MA = (DS) x 16 10 + (SI)

(AX) ← (MA ; MA + 1)

If DF = 0, then (SI) ← (SI) + 2

If DF = 1, then (SI) ← (SI) – 2

90
8086 Microprocessor

Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 16 10 + (DI)

(MA E) ← (AL)

If DF = 0, then (DI) ← (DI) + 1

If DF = 1, then (DI) ← (DI) – 1

STOSW MAE = (ES) x 16 10 + (DI)

(MA E ; MA E + 1 ) ← (AX)

If DF = 0, then (DI) ← (DI) + 2

If DF = 1, then (DI) ← (DI) – 2

91
8086 Microprocessor

Instruction Set
5. Processor Control Instructions
Mnemonics Explanation
STC Set CF ← 1

CLC Clear CF ← 0

CMC Complement carry CF ← CF /

STD Set direction flag DF ← 1

CLD Clear direction flag DF ← 0

STI Set interrupt enable flag IF ← 1

CLI Clear interrupt enable flag IF ← 0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086
LOCK Lock bus during next instruction
92
8086 Microprocessor
Instruction Set
6. Control Transfer Instructions

• Transfer the control to a specific destination or target instruction

• Do not affect flags

❑ 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

93
8086 Microprocessor

Instruction Set
6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch

instructions instructions

• Checks flags

• If conditions are true, the program control is transferred to the new

memory location in the same segment by modifying the content of IP

94
 8086 Microprocessor

Instruction Set
6. Control Transfer Instructions

❑ 8086 signed conditional branch ❑ 8086 unsigned conditional branch

instructions instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or equal Jump if above Jump if not below or
equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less JAE disp8 JNB disp8
equal Jump if above or equal Jump if not below
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not greater than Jump if below Jump if not above or
or equal equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater JBE disp8 JNA disp8
equal Jump if below or equal Jump if not above

Note: Before these instructions comparison instruction is to be used for comparing two operands. 95
8086 Microprocessor
Instruction Set
6. Control Transfer Instructions

❑ 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, ZF = 1

JNZ disp8 Jump if result is not zero, i.e, ZF = 0

96
Iteration Control Instructions
These instructions are used to execute the given instructions for number of times.
Following is the list of instructions under this group −

LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0

LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0

LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0

JCXZ − Used to jump to the provided address if CX = 0

Mov cx, 06h

label: add al, bl
Loop label
8086 Microprocessor

Assemble Directives
• Instructions to the Assembler regarding the program being executed.

• Control the generation of machine codes and organization of the program; but no
machine codes are generated for assembler directives.

• Also called ‘pseudo instructions’

• Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

98
8086 Microprocessor

DB
Assemble Directives
• Define Byte

DW • Define a byte type (8-bit) variable

SEGMENT • Reserves specific amount of memory locations to each

ENDS variable

ASSUME • Range : 00H – FFH for unsigned value; 00H – 7FH for
positive value and 80H – FFH for negative value
ORG
END • General form : variable DB value/ values
EVEN
EQU

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for the variable LIST
SHORT and each data specified in the instruction are stored as initial value in
the reserved memory location
MACRO
ENDM 99
8086 Microprocessor

DB
Assemble Directives
• Define Word

DW • Define a word type (16-bit) variable

SEGMENT • Reserves two consecutive memory locations to each variable

ENDS
• Range : 0000H – FFFFH for unsigned value; 0000H –
ASSUME 7FFFH for positive value and 8000H – FFFFH for negative
value
ORG
END • General form : variable DW value/ values
EVEN
EQU

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for the variable ALIST
SHORT and each 16-bit data specified in the instruction is stored in two
consecutive memory location.
MACRO
ENDM 100
8086 Microprocessor

DB
Assemble Directives
• SEGMENT : Used to indicate the beginning of a code/ data/
stack segment
DW
• ENDS : Used to indicate the end of a code/ data/ stack
SEGMENT segment
ENDS
• General form:
ASSUME

ORG
END Seg_nam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Seg_nam ENDS

SHORT

MACRO User defined name of the

segment
ENDM 101
8086 Microprocessor

DB
Assemble Directives
• Informs the assembler the name of the program/ data
segment that should be used for a specific segment.
DW
• General form:
SEGMENT
ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of the
END Segment Register
segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the instructions of the
ENDP program are stored in the segment ACODE and
data are stored in the segment ADATA

SHORT

MACRO
ENDM 102
8086 Microprocessor
Assemble Directives
• ORG (Origin) is used to assign the starting address (Effective address)
DB
for a program/ data segment

DW • END is used to terminate a program; statements after END will be

ignored
SEGMENT
ENDS • EVEN : Informs the assembler to store program/ data segment
starting from an even address
ASSUME
• EQU (Equate) is used to attach a value to a variable

ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements following
EQU ORG 1000H should be stored in memory starting with
effective address 1000H

PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of memory
SHORT ORG 1200H location assigned to A will be 1200H and that of B will
A DB 4CH be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 103
LENGTH: LENGTH is an operator, which tells the assembler to determine the number of
elements in some named data item, such as a string or an array. When the assembler reads
the statement MOV CX, LENGTH STRING1, for example, will determine the number of
elements in STRING1 and load it into CX. If the string was declared as a string of bytes,
LENGTH will produce the number of bytes in the string. If the string was declared as a word
string, LENGTH will produce the number of words in the string.
LENGTH: Byte length of a label: This is used to refer to the length of a data array or a
string. Ex : MOV CX, LENGTH ARRAY
OFFSET: offset of a label: When the assembler comes across the OFFSET operator along
with a label, it first computing the 16-bit offset address of a particular label and replace
the string ‘OFFSET LABEL’ by the computed offset address. Ex : MOV SI, offset list

LEA : Load Effective address : loads the address of variable.

Ex: Test DB 23H, 40H, 44H

LEA AX, Test
8086 Microprocessor

Assemble Directives
• PROC Indicates the beginning of a procedure
DB
• ENDP End of procedure
DW
• FAR Intersegment call
SEGMENT
ENDS • NEAR Intrasegment call

• General form
ASSUME

ORG
Proc_name PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the procedure
EQU
…
Last statement of the procedure
PROC RET
ENDP
FAR Proc_name ENDP
NEAR

SHORT User defined name of the

procedure
MACRO
ENDM 105
8086 Microprocessor

DB
Assemble Directives
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is declared
ENDS as NEAR and so the assembler will code the CALL
… and RET instructions involved in this procedure as
… near call and return
ASSUME …

RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT is
declared as FAR and so the assembler will code the
… CALL and RET instructions involved in this
PROC … procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM 106
8086 Microprocessor

Assemble Directives
DB • Reserves one memory location for 8-bit signed displacement
in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT AHEAD The directive will reserve one memory
location for 8-bit displacement named
ORG AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 107
8086 Microprocessor

Assemble Directives
DB • MACRO Indicate the beginning of a macro

DW • ENDM End of a macro

SEGMENT • General form:

ENDS

ASSUME Macro_name MACRO[Arg1, Arg2 ...]

Program statements
… in the macro
ORG …
END …
EVEN
EQU ENDM

PROC
ENDP
FAR
NEAR User defined name of the macro

SHORT

MACRO
ENDM 108
 Procedures and Macros:
http://www.snjb.org/polytechnic/up-images/downloads/chapter%206-MAPupFile_058d4fa990abaa.pdf.

Define procedure : A procedure is a group of instructions that usually performs one task. It
is a reusable section of a software program stored in memory once but can be used as often
as necessary. A procedure can be of two types. 1) Near Procedure 2) Far Procedure

Near Procedure: A procedure is known as NEAR procedure if is written(defined) in the

same code segment that is calling that procedure. Only Instruction Pointer(IP register)
contents will be changed in NEAR procedure.

FAR procedure : A procedure is known as FAR procedure if it is written (defined) in the

different code segment than the calling segment. In this case both Instruction Pointer (IP)
and the Code Segment (CS) register content will be changed.

Directives used for procedure :

PROC directive: The PROC directive is used to identify the start of a procedure. The PROC
directive follows a name given to the procedure. After that the term FAR and NEAR is used to
specify the type of the procedure.
ENDP Directive: This directive is used along with the name of the procedure to indicate the
end of a procedure to the assembler. The PROC and ENDP directive are used to bracket a
procedure.
CALL instruction and RET instruction :

CALL instruction : The CALL instruction is used to transfer execution to a procedure. It

performs two operation. When it executes, first it stores the address of instruction after the
CALL instruction on the stack. Second it changes the content of IP register in case of Near call
and changes the content of IP register and CS register in case of FAR call.

There are two types of calls. 1)Near Call or Intra segment call. 2) Far call or Inter Segment call

Operation for Near Call : When 8086 executes a near CALL instruction, it decrements the
stack pointer by 2 and copies the IP register contents on to the stack. Then it copies address
of first instruction of called procedure.

Operation of FAR CALL: When 8086 executes a far call, it decrements the stack pointer by 2
and copies the contents of CS register to the stack. It the decrements the stack pointer by 2
again and copies the content of IP register to the stack. Finally it loads CS register with base
address of segment having procedure and IP with address of first instruction in procedure.
 8086 INTERRUPTS
Sources of Interrupts in 8086:

•Three types of interrupts sources are there in 8086:

• 1. An external signal applied to NMI or INTR
input pin (Hardware interrupt)

2. Execution of INTn (n=00H-FFH)

instruction (Software interrupt)
3. Interrupt caused by some error condition
produced in 8086 instruction execution process.

(Divide by zero, overflow errors etc)

 8086 Interrupt Processing Steps
If an interrupt has been requested, the 8086 Microprocessor processes it by
performing the following series of steps:
1. Pushes the content of the flag register onto the stack to preserve the status
of IF and TF flags, by decrementing the stack pointer (SP) by 2

2. Disables the INTR interrupt by clearing IF in the flag register

3. Resets TF in the flag register, to disable the single step or trap interrupt
4. Pushes the content of the code segment (CS) register onto
the stack by decrementing SP by 2
5. Pushes the content of the instruction pointer (IP)onto the stack by
decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service routine
(ISR) corresponding to the received interrupt.
 cesso
Executes the Interrupt
r instruction
Jumps to the Interrupt Vector Table

Takes the CS and IP in the Vector Table

Pushes the existing CS and IP on the Stack

Loads the new CS and IP

Jumps to the ISR

Executes ISR

Comes back and continues the Main

Program
Steps involved in processing an interrupt instruction by the
processor
 Processing of an Interrupt by the
8086
Main Push flags Interrupt
Program Service
register Clear IF
Routine (ISR)
and TF Push CS Interrupt
Interrupt and IP Load CS program:
and IP :
Pop IP and CS :
Pop flags :
register :
IRE
T :
Interrupt Vector Table
 2 bytes 00002H
CS LSB C S 00003H
CS MSB
Type 0 or
INT 00
2 bytes 00000H
IP LSB I P 00001H
IP MSB Interrupt
CS LSB MSB

Given a vector, where is the ISR address stored in memory ?

Offset = Type number X 4

Example:- INT 02H

Offset = 02 x 4 = 08
= 00008H
 256 Interrupts of 8086 are Divided into 3 Groups
1. Type 00 to Type 04 interrupts -
These are used for fixed operations and hence are
called dedicated interrupts

2. Type 05 to Type 31 interrupts

Not used by 8086,reserved for higher processors like
80286 80386 etc.

3. Type 32 to Type 255 interrupts

Available for user, called user defined interrupts. These can
be either H/W interrupts and activated through INTR line
or can be S/W interrupts.
¬
Type – 0 :- Divide by Zero Error Interrupt
Quotient is large, cant be fit in AL/AX or divide by zero
¬
Type –1:- Single step or Trap Interrupt
Used for executing the program in single step mode by
setting trap flag.

¬
Type – 2:- Non-Maskable Interrupt
This interrupt is used for executing ISR of NMI pin
(positive edge signal), NMI can’t be masked by S/W.

¬
Type – 3:- One-byte INT instruction interrupt
Used for providing break points in the program
¬
An example of an interrupt generated
due to overflow error in an 8086 system
ASSUME CS:CODE, DS:DATA, SS:STACK_SEG CALL SUBTRACTION
MOV AH, 4CH
DATA SEGMENT INT 21H
NUM1 DB 50H Procedure Example
NUM2 DB 20H ADDITION PROC NEAR
ADD_RES DB ?
program: MOV AL, NUM1
SUB_RES DB ? MOV BL, NUM2
DATA ENDS ADD AL, BL
MOV ADD_RES, AL
STACK_SEG SEGMENT RET
ADDITION ENDP
DW 40 DUP(0) ; stack of 40 words, all initialized to zero
TOS LABEL WORD SUBTRACTION PROC
STACK_SEG ENDS MOV AL, NUM1
MOV BL, NUM2
CODE SEGMENT SUB AL, BL
MOV SUB_RES, AL
START: MOV AX, DATA ; initialize data segment RET
MOV DS, AX SUBTRACTION ENDP
MOV AX, STACK_SEG ; initialize stack segment
MOV SS, AX CODE ENDS
MOV SP, OFFSET TOS ; initialize stack pointer to TOS END START
CALL ADDITION
ASSUME CS:CODE, DS:DATA

DATA SEGMENT
NUM1 DW 1000H
NUM2 DW 2000H
RES DW ?
DATA ENDS MACRO program
CODE SEGMENT Example
ADDITION MACRO NO1, NO2, RESULT
MOV AX, NO1
MOV BX, NO2
ADD AX, BX
MOV RESULT, AX
ENDM

START: MOV AX, DATA ; initialize data segment

MOV DS, AX
ADDITION NUM1, NUM2, RES
MOV AH, 4CH
INT 21H

CODE ENDS
END START