Computer Aided Digital Design

Introduction to the Course

Vinay Reddy
Department of Electronics & Communication Engineering

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COMPUTER AIDED DIGITAL DESIGN
Course Flow

 Strat with Number System – Boolean Algebra

 Learn to design Combinational Circuits and write SV codes for
combinational circuits
 Learn to design Sequential Circuits and write SV codes for
Sequential circuits
 Digital Building Blocks

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COMPUTER AIDED DIGITAL DESIGN
Course - Text Book

“Digital Design and Computer Architecture”, David Money Harris and Sarah L
Harris, Elsevier, 2nd Edition, 2019.

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COMPUTER AIDED DIGITAL DESIGN
EDA Tools that can be used for the Course

Xilinx Tool
FPGA Boards
Software

Hardware
Basys 3 FPGA Board
Arty 35T FPGA Board
Arty 100T FPGA Board

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Computer Aided Digital Design
Unit 1 : Number System
Vinay Reddy
Department of Electronics & Communication Engineering

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System

Topic 1 : Levels of abstraction for an electronic computing system

At the lowest level of abstraction is the physics, the motion of electrons.

Our system is constructed from electronic devices such as transistors

The next level of abstraction is analog circuits, in which devices are assembled to
create components such as amplifiers. Analog circuits input and output a
continuous range of voltages.

Digital circuits such as logic gates restrict the voltages to discrete ranges, which
we will use to indicate 0 and 1.

In logic design, we build more complex structures, such as adders or memories,

from digital circuits.

Microarchitecture links the logic and architecture levels of abstraction.

The architecture level of abstraction describes a computer from the

programmer’s perspective

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System

Levels of abstraction for an electronic computing system

The operating system handles low level details such as accessing a hard drive or
managing memory.

Finally, the application software uses these facilities provided by the operating system
to solve a problem for the user.

The critical technique for managing complexity is

abstraction

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Decimal Numbers

Decimal digits : 0, 1, 2, …, 9.

Decimal numbers are referred to as base 10.

Representation of a decimal number

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Binary Numbers
Bits represent one of two values, 0 or 1, and are joined together to form binary numbers.

Binary numbers are base 2

Conversion of a binary number to decimal

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

DECIMAL TO BINARY CONVERSION

Convert 84 to Binary Number

84 ÷ 2 = 42 with 0 remainder
42 ÷ 2 = 21 with 0 remainder
21 ÷ 2 = 10 with 1 remainder
10 ÷ 2 = 5 with 0 remainder
5 ÷ 2 = 2 with 1 remainder
2 ÷ 2 = 1 with 0 remainder
1 ÷ 2 = 0 with 1 remainder

Then, when we put the remainders together in reverse order, we get the answer. The decimal number 84 converted to
binary is therefore:

1010100 13
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System & Logic Gates
Topic 2 : Number System

Hexadecimal Numbers
Hexadecimal numbers use the digits 0 to 9 along
with the letters A to F

Hexadecimal numbers are base 16

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Hexadecimal Numbers
HEXADECIMAL TO BINARY AND DECIMAL CONVERSION

Convert the hexadecimal number 2ED to binary and to decimal.

Conversion between hexadecimal and binary is easy because each hexadecimal digit directly corresponds to four binary digits.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Hexadecimal Numbers

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Hexadecimal Numbers

Using the above steps, here is the work involved in the solution for converting 333 to hexadecimal
number:
333 / 16 = 20 with remainder 13 (D)
20 / 16 = 1 with remainder 4
1 / 16 = 0 with remainder 1

Then just write down the remainders in the reverse order to get the answer, The decimal number
333 converted to hexadecimal is therefore equal to :

14D

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System
Bytes, Nibbles
A group of eight bits is called a byte.

A group of four bits, or half a byte, is called a nibble.

Within a group of bits, the bit in the 1’s column is called the least significant bit (lsb), and the bit at the other end is called
the most significant bit (msb).

Least and most significant bits and bytes

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

1024 bytes is called a kilobyte (KB). 1024 bits is called a kilobit (Kb or Kbit).
Similarly, MB, Mb, GB, and Gb are used for millions and billions of bytes and bits.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System
Binary Addition

0+0=0
1+0=1
0+1=1
1 + 1 = 10 (0 with a carry 1)

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Signed Binary Numbers

Sign/Magnitude Numbers

An N-bit sign/magnitude number uses the most significant bit as the sign and the remaining N−1 bits as the
magnitude (absolute value).

A sign bit of 0 indicates positive and a sign bit of 1 indicates negative.

Unfortunately, ordinary binary addition does not work for sign/ magnitude numbers
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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

Two’s Complement Numbers

Two’s complement numbers are identical to unsigned binary numbers except that the most significant bit position
has a weight of −2^(N-1) instead of 2^(N−1) -1.

They overcome the shortcomings of sign/magnitude numbers:

zero has a single representation, and ordinary addition works.

The process consists of inverting all of the bits in the number, then adding 1 to the least
significant bit position.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System
Topic 2 : Number System

sign extension
When a two’s complement number is extended to more bits, the sign bit must be copied into the most
significant bit positions.

This process is called sign extension. For example, the numbers 3 and −3 are written as 4-bit two’s
complement numbers 0011 and 1101, respectively.

They are sign-extended to seven bits by copying the sign bit into the three new upper bits to form
0000011 and 1111101, respectively.

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Unit 1 : Number System
Topic 2 : Number System

Comparison of Number Systems

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Unit 1 : Number System
Topic 2 : Number System

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Unit 1 : Number System
Topic 2 : Number System

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Number System & Logic Gates
Topic 2 : Number System

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Computer Aided Digital Design
Unit 1 : Combinational Logic Design
Vinay Reddy
Department of Electronics & Communication Engineering

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

Circuit as a black box with inputs, outputs, and specifications

A circuit can be viewed as a black box with

▶ one or more discrete-valued input terminals

▶ one or more discrete-valued output terminals
▶ a functional specification describing the relationship between inputs and outputs
▶ a timing specification describing the delay between inputs changing and outputs responding.
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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

Elements and nodes

Peering inside the black box, circuits are composed of nodes and elements

▶ An element is itself a circuit with inputs, outputs, and a specification.

▶ A node is a wire, whose voltage conveys a discrete-valued variable.
▶ Nodes are classified as input, output, or internal.
▶ Inputs receive values from the external world.
▶ Outputs deliver values to the external world.
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▶ Wires that are not inputs or outputs are called internal nodes.
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

Digital circuits

Combinational Circuits Sequential Circuits

▶ A combinational circuit’s outputs depend only ▶ A sequential circuit’s outputs depend on

on the current values of the inputs. both current and previous values of the
▶ It combines the current input values to compute inputs.
the output. ▶ It depends on the input sequence
▶ A combinational circuit is memoryless. ▶ Sequential circuit has memory.

For example, a logic gate is a combinational circuit.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

CL – Combinational Logic
Combinational logic circuit
Two OR implementations

▶ The symbol CL inside the box indicates that it is implemented using only
combinational logic.
▶ In this example, the function F is specified to be OR: Y = F(A, B) = A + B.
▶ In words, we say the output Y is a function of the two inputs, A and B,
namely Y = A OR B.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

represents a block of combinational

logic with three inputs and two
outputs.

If the number of bits is unimportant or

obvious from the context, the slash may
be shown without a number.

Multiple-output combinational circuit

Slash notation for multiple signals

▶ This particular combinational circuit is called a full adder.

▶ To simplify drawings, we often use a single line with a slash through it and
a number next to it to indicate a bus, a bundle of multiple signals.
▶ The number specifies how many signals are in the bus.
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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction

Combinational Composition

A circuit is combinational if it consists of interconnected circuit elements such that

▶ Every circuit element is itself combinational.

▶ Every node of the circuit is either designated as an input to the circuit or
connects to exactly one output terminal of a circuit element.
▶ The circuit contains no cyclic paths: every path through the circuit visits each
circuit node at most once.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction
Which of the circuits in Figure are combinational circuits according to the rules of
combinational composition?

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 COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 1 : Introduction
Which of the circuits in Figure are combinational circuits according to the rules of
combinational composition?

(a) is combinational. It is constructed from two (c) is combinational.

combinational circuit elements (inverters I1 and I2).

(b) is not combinational,

because there is a cyclic path.

(e) is combinational (f) does not obey the rules of combinational

composition because it has a cyclic path
(d) is not combinational, because
through the two elements.
node n6 connects to the output
terminals of both I3 and I4. 10
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Hardware Reduction

Multilevel combinational circuits may use less hardware than their two-level counterparts.
Three-input XOR: (a) functional specification and (b) two-level logic implementation

Which implementation is better ?

Option 1 – (a)
Option 1 – (b)

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic

Similarly, an eight-input XOR would require 128 eight-input AND gates and one 128-input
OR gate for a two-level sum-of-products implementation.

A much better option is to use a tree of two-input XOR gates.

Three-input XOR using two-input XORs

Eight-input XOR using seven two-input XORs

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Bubble Pushing

Bubble pushing is a helpful way to redraw these circuits so that the bubbles
cancel out and the function can be more easily determined.

The guidelines for bubble pushing are as follows:

▶ Begin at the output of the circuit and work toward the inputs.

▶ Push any bubbles on the final output back toward the inputs so that you can read an
equation in terms of the output (for example, Y) instead of the complement of the output (~Y).

▶ Working backward, draw each gate in a form so that bubbles cancel. If the current gate has
an input bubble, draw the preceding gate with an output bubble. If the current gate does not
have an input bubble, draw the preceding gate without an output bubble. 13
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Bubble Pushing

▶ Begin at the output of the circuit.

▶ Push any bubbles on the final output back toward the inputs.

▶ Working backward, draw each gate in a form so that bubbles cancel.

Multilevel circuit using NANDs and NORs

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Bubble Pushing

Multilevel circuit using NANDs and NORs

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Bubble Pushing
BUBBLE PUSHING FOR CMOS LOGIC

suppose you would like to implement the circuit in CMOS

logic, which favors NAND and NOR gates.

Use bubble pushing to convert the circuit to NANDs, NORs,

and inverters.

Circuit using ANDs and ORs

Step 1 : Replace AND gates to NAND gates with a inverter.

Replace OR gates to NOR gates with a inverter.

Step 2 : Perform Bubble Pushing

Poor circuit using NANDs and NORs

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 2 : Multilevel Combinational Logic Bubble Pushing
No of gates = 8

Poor circuit using NANDs and NORs

No of gates = 4 No of gates = 5

Better circuit using NANDs and NORs 17

COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S

Boolean algebra is limited to 0’s and 1’s. However, real circuits can also have illegal and floating values,
represented symbolically by X and Z.

▶ This commonly happens if it is being driven to both 0 and 1 at the same time.
Illegal Value: X

▶ This situation, called contention, is considered to be an error and must be

avoided. Contention also can cause large amounts of power to flow between
the fighting gates, resulting in the circuit getting hot and possibly damaged.

▶ X values are also sometimes used by circuit simulators to indicate an

uninitialized value.

▶ Digital designers also use the symbol X to indicate “don’t care” values in truth
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tables.
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S

▶ When X appears in a truth table, it indicates that the value of the variable in
the truth table is unimportant (can be either 0 or 1).

▶ When X appears in a circuit, it means that the circuit node has an unknown
or illegal value.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S
Floating Value: Z

▶ The symbol Z indicates that a node is being driven neither HIGH nor LOW.

▶ The node is said to be floating, high impedance, or high Z.

▶ A floating node does not always mean there is an error in the circuit, so long as some other

circuit element does drive the node to a valid logic level when the value of the node is

relevant to circuit operation.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S
Floating Value: Z

▶ The tristate buffer, has three possible output states: HIGH (1),
LOW (0), and floating (Z).

▶ The tristate buffer has an input A, output Y, and enable E.

▶ When the enable is TRUE, the tristate buffer acts as a simple

buffer, transferring the input value to the output.

▶ When the enable is FALSE, the output is allowed to float (Z).

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S
Floating Value: Z Tristate buffer with active low enable

When the enable is LOW (0), the buffer is enabled.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 3 : X’S AND Z’S
Floating Value: Z Tristate bus connecting multiple chips

▶ Tristate buffers are commonly used on busses that connect multiple chips.

For example, a microprocessor, a video controller, and an Ethernet controller might all
need to communicate with the memory system in a personal computer.

▶ Each chip can connect to a shared memory bus using tristate buffers.

▶ Only one chip at a time is allowed to assert its enable signal to drive a value onto
the bus.

▶ The other chips must produce floating outputs so that they do not cause
contention with the chip talking to the memory.

▶ Any chip can read the information from the shared bus at any time.
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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

Karnaugh maps (K-maps) are a graphical method for simplifying Boolean equations.

They were invented in 1953 by Maurice Karnaugh, a telecommunications engineer at Bell Labs.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

The top row of the K-map gives the four possible values for the A
and B inputs.

The left column gives the two possible values for the C input.

Each square in the K-map corresponds to a row in the truth table

and contains the value of the output Y for that row.

For example, the top left square corresponds to the first row in the
truth table and indicates that the output value Y = 1 when ABC =
000.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

You may have noticed that the A and B The top row of the K-map gives the four possible values for the A
combinations in the top row are in a peculiar
and B inputs.
order: 00, 01, 11, 10. This order is called a Gray
code.
The left column gives the two possible values for the C input.

Each square in the K-map corresponds to a row in the truth table

and contains the value of the output Y for that row.

For example, the top left square corresponds to the first row in the
truth table and indicates that the output value Y = 1 when ABC =
000.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

The top row of the K-map gives the four possible values for the A
and B inputs.

The left column gives the two possible values for the C input.

Each square in the K-map corresponds to a row in the truth table

and contains the value of the output Y for that row.

For example, the top left square corresponds to the first row in the
truth table and indicates that the output value Y = 1 when ABC =
000.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

The top row of the K-map gives the four possible values for the A
and B inputs.

The left column gives the two possible values for the C input.

Each square in the K-map corresponds to a row in the truth table

and contains the value of the output Y for that row.

For example, the top left square corresponds to the first row in the
truth table and indicates that the output value Y = 1 when ABC =
000.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS
▶ K-maps help us do this simplification graphically by circling 1’s in
K-map minimization adjacent squares.

▶ For each circle, we write the corresponding implicant. an implicant is

the product of one or more literals.

▶ Variables whose true and complementary forms are both in the circle
are excluded from the implicant.

▶ In this case, the variable C has both its true form (1) and its
complementary form (0) in the circle, so we do not include it in the
implicant.

▶ Y is TRUE when A = B = 0, independent of C. So the implicant is A B:

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

▶ Every 1 must be circled at least once

▶ Each circle must span a power of 2 (i.e. 1, 2, 4) squares in each direction

▶ Each circle must be as large as possible

▶ A circle may wrap around the edges

▶ A “don't care” (X) is circled only if it helps minimize the equation

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

Y
AB
C 00 01 11 10

0 ABC ABC ABC ABC

1 ABC ABC ABC ABC

Truth Table K-Map

Y
A B C Y AB
0 0 0 0 C 00 01 11 10
0 0 1 0
0 1 0 1 0
0 1 1 1
1 0 0 0
1 0 1 0 1
1 1 0 0
1 1 1 1 31
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

Y
AB
C 00 01 11 10

0 ABC ABC ABC ABC

1 ABC ABC ABC ABC

Truth Table K-Map

Y
A B C Y AB
0 0 0 0 C 00 01 11 10
0 0 1 0
0 1 0 1 0 1 Y = AB + BC
0 1 1 1
1 0 0 0
1 0 1 0 1
1 1 0 0
1 1
1 1 1 1 32
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0 Y = AC + ABD + ABC + BD

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS
K-Maps with don’t cares

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01 0 X X 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 X X
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01 0 X X 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 X X
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X Y = A + BD + C

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

Examples for Practicing

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS SEVEN-SEGMENT DISPLAY DECODER

A seven-segment display decoder takes a 4-bit data input D (3:0) and

produces seven outputs to control light-emitting diodes to display a digit
from 0 to 9.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS
A prime implicant is a product term obtained by combining the maximum possible
number of adjacent squares in the map.

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 4 : KARNAUGH MAPS

Alternative K-map for Sa Alternative K-map for Sa

K-map solution showing different set of prime showing incorrect nonprime
implicants implicant

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Combinational logic is often grouped into larger building blocks to build

more complex systems.

Multiplexers
Multiplexers are among the most commonly used combinational circuits.

They choose an output from among several possible inputs based on the value of a select signal.

50
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks
Multiplexers

2:1 Multiplexer

51
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

2:1 multiplexer implementation using two- Multiplexer using tristate

level logic buffers

52
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks 4:1 multiplexer implementations: (a) two-level logic,
(b) tristates, (c) hierarchical
4:1 multiplexer

53
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks Multiplexer Logic

Multiplexers can be used as lookup tables to perform logic

functions.

4:1 multiplexer implementation of two-input AND function

54
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks
Multiplexer logic using variable inputs

55
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

LOGIC WITH MULTIPLEXERS

56
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Alyssa’s circuit: (a) truth table, (b) 8:1 multiplexer implementation

57
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

58
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Alyssa’s new circuit

Multiplexer logic using variable inputs

59
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

60
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Implement a Full Adder using 4:1 Multiplexers

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks DECODER IMPLEMENTATION

A decoder has N inputs and 2^(N) outputs. It asserts exactly one of its outputs depending
on the input combination.

2:4 decoder

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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks
2:4 decoder implementation

63
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Logic function using decoder

64
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

Implement full adder circuit whose outputs are given as:

S (x,y,z)= Σ (1, 2, 4, 7) C (x,y,z)= Σ (3, 5, 6, 7)

65
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks

An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has maximum of
2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the input, which is active
High. Therefore, the encoder encodes 2n input lines with ‘n’ bits.

66
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks
Priority Encoder

We considered one more output, V in order to know, whether

the code available at outputs is valid or not.

•If at least one input of the encoder is ‘1’, then the code
available at outputs is a valid one. In this case, the output, V
will be equal to 1.

•If all the inputs of encoder are ‘0’, then the code available at
outputs is not a valid one. In this case, the output, V will be
equal to 0.

67
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 5 : Combinational Building Blocks
Priority Encoder

68
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : TIMING

One of the most challenging issues in circuit design is timing: making

a circuit run fast.

An output takes time to change in

response to an input change

69
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

Propagation and Contamination Delay

Combinational logic is characterized by its propagation delay and

contamination delay.
A=1

Y=1
The propagation delay tpd is the maximum time from when an input
changes until the output or outputs reach their final value.

70
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

Propagation and Contamination Delay

Combinational logic is characterized by its propagation delay and

contamination delay.
A=1

Y=1
The contamination delay tcd is the minimum time from when an input
changes until any output starts to change its value.

71
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

Causes for Delays in Circuits

The underlying causes of delay in circuits include –

The time required to charge the capacitance in a circuit and the speed of light.

tpd and tcd may be different for many reasons, including

▶ different rising and falling delays

▶ multiple inputs and outputs, some of which are faster than others

▶ circuits slowing down when hot and speeding up when cold

72
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing
Short path and critical path

Along with the factors already listed, propagation and contamination delays are also determined by the path a signal takes from
input to output.

The critical path, shown in blue, is the path from input A or B to output Y. It is the
longest, and therefore the slowest.

This path is critical because it limits the speed at which the circuit operates.

The short path through the circuit, shown in gray, is from input D to output Y. This is
the shortest, and therefore the fastest, path through the circuit.

73
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing
Critical and short path waveforms

74
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

The propagation delay of a combinational circuit is the sum of the propagation

delays through each element on the critical path.

The contamination delay is the sum of the contamination delays through each
element on the short path .

75
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

76
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

tpd is three times the propagation delay of a

single gate, or 300 ps.
Ben’s critical path
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COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

There are only two gates in the shortest path, so

Ben’s shortest path tcd is 120 ps

78
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

79
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

tpd_sy indicates the propagation delay from input S to output Y

tpd_dy indicates the propagation delay from input D to output Y

tpd is the worst of the two: max(tpd_sy, tpd_dy).

These circuits are control critical, because the critical path is from the
control signals to the output.

Any additional delay in the control signals will add directly to the worst-
case delay.
80
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

tpd_sy indicates the propagation delay from input S to output Y

tpd_dy indicates the propagation delay from input D to output Y

tpd is the worst of the two: max(tpd_sy, tpd_dy).

These circuits are control critical, because the critical path is from the
control signals to the output.

Any additional delay in the control signals will add directly to the worst-
case delay.
81
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing

This circuit is data critical, because the critical path is from the data
input to the output: tpd = tpd_dy.

If data inputs arrive well before the control inputs, we would prefer the
design with the shortest control-to-output delay

(the hierarchical design).

Similarly, if the control inputs arrive well before the data inputs, we
would prefer the design with the shortest data-to-output delay (the
Hierarchical Design tristate design).

82
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing
Glitches

So far we have discussed the case where a single input transition causes a single output transition.

However, it is possible that a single input transition can cause multiple output transitions. These are called
glitches or hazards.

Case Study

83
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing As long as we wait for the propagation delay to elapse before we depend on the output, glitches are
not a problem, because the output eventually settles to the right answer.
Glitches
Scenario The Boolean equation is correctly minimized, but let’s look at what happens when A = 0, C = 1,
and B transitions from 1 to 0.

Y starts at 1 and ends at 1 but

momentarily glitches to 0 84
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Combinational Logic Design
Topic 6 : Timing Although we have shown how to eliminate one kind of glitch, the point of discussing glitches is not to

Glitches eliminate them but to be aware that they exist.

If we choose to, we can avoid this glitch by adding another gate to the implementation.

Glitch-proof circuit
85
Computer Aided Digital Design
Unit 1 : Combinational Logic Design - HDL
Vinay Reddy
Department of Electronics & Communication Engineering

1
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language

Topic 1 : HDL Introduction

In the 1990s, designers discovered that they were far more productive if they worked at a higher

level of abstraction, specifying just the logical function and allowing a computer-aided

design (CAD) tool to produce the optimized gates.

The specifications are generally given in a hardware description language (HDL).

2
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
Modules

▶ A block of hardware with inputs and outputs is called a module.

▶ An AND gate, a multiplexer, and a priority circuit are all examples of hardware modules.

▶ The two general styles for describing module functionality are behavioral and structural.

▶ Behavioral models describe what a module does.

▶ Structural models describe how a module is built from simpler pieces; it is an application of hierarchy.

3
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
Language Origin

▶ Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984.
▶ Gateway was acquired by Cadence in 1989 and Verilog was made an open standard in 1990 under the control of
Open Verilog International.

▶ The language became an IEEE standard1 in 1995.

▶ The language was extended in 2005 to streamline idiosyncrasies and to better support modeling and verification of
systems.

▶ These extensions have been merged into a single language standard, which is now called SystemVerilog (IEEE
STD 1800-2009).
▶ SystemVerilog file names normally end in .sv.

4
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction

Simulation and Synthesis

▶ The two major purposes of HDLs are logic simulation and synthesis.

▶ During simulation, inputs are applied to a module, and the outputs are checked to verify
that the module operates correctly.

▶ During synthesis, the textual description of a module is transformed into logic gates.

5
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
module sillyfunction (a, b, c, y);
Example 1 input logic a, b, c;
output logic y ;
module sillyfunction (input logic a, b, c, output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
endmodule

▶ A SystemVerilog module begins with the module name and a listing of the inputs
and outputs.

▶ The assign statement describes combinational logic. ~ indicates NOT, & indicates
AND, and | indicates OR.

▶ logic signals such as the inputs and outputs are Boolean variables (0 or 1).They
may also have floating and undefined values 92
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
module sillyfunction (a, b, c, y);
Example 1 input logic a, b, c;

module sillyfunction (input logic a, b, c, output logic y); output logic y ;

assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;

endmodule endmodule

bc bc + ab

ab

Timing Waveform - Simulation

Synthesized circuit
7
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
module sillyfunction (a, b, c, y);
Example 1 input logic a, b, c;

module sillyfunction (input logic a, b, c, output logic y); output logic y ;

assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;

endmodule endmodule

bc bc + ab

ab

The synthesis tool labels each

of the synthesized gates . Timing Waveform - Simulation

Synthesized circuit
8
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
module sillyfunction (a, b, c, y);
Example 1 input logic a, b, c;
output logic y ;
module sillyfunction (input logic a, b, c, output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
endmodule

bc bc + ab
▶ The logic synthesizer might perform optimizations to reduce
the amount of hardware required.

▶ The netlist may be a text file, or it may be drawn as a

ab schematic to help visualize the circuit.

▶ Not all of these commands can be synthesized into hardware.

Synthesized circuit
9
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
Simulation and Synthesis on Quartus

10
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
Simulation and Synthesis on Quartus

Not all of these commands can be synthesized into hardware.

For example, a command to print results on the screen during simulation

does not translate into hardware.

module example (a,b);

input logic a;
output logic b;

assign b = a;

initial
begin
b = 0;
$display ("the Value of b = %0d",b);
end

endmodule 97
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 1 : HDL Introduction
Simulation and Synthesis on Quartus

▶ Our primary interest is to build hardware, we will emphasize a synthesizable subset of the
languages.

▶ Specifically, we will divide HDL code into synthesizable modules and a testbench.

▶ The synthesizable modules describe the hardware.

▶ The testbench contains code to apply inputs to a module, check whether the output
results are correct, and print discrepancies between expected and actual outputs.

▶ Testbench code is intended only for simulation and cannot be synthesized. 12

COMPUTER AIDED DIGITAL DESIGN https://www.edaplayground.com/x/B38E

Unit 1 : Hardware Description Language

Topic 1 : HDL Introduction
Simulation and Synthesis on Quartus

module HA (a,b,sum,cout);

input logic a,b;

output logic sum,cout;

assign sum = a ^ b;
assign cout = a & b;

endmodule

Let us write a simple testbench for the HA code.

13
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Bitwise Operator
Bitwise operators act on single-bit signals or on multi-bit busses.

module inv (input logic [3:0] a, output logic [3:0] y);

assign y = ~a;

endmodule

a = 1101, y = 0010

14
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Bitwise Operator

module gates(input logic [3:0] a, b, output logic [3:0] y1, y2, y3, y4, y5); /* five different two-input logic gates acting on 4-bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule

15
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Reduction Operators

Reduction operators imply a multiple-input gate acting on a single bus.

module and8 (input logic [7:0] a, output logic y);

assign y = &a;
// &a is much easier to write than assign y = a[7] & a[6] & a[5] & a[4] &
a[3] & a[2] & a[1] & a[0];
endmodule

16
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Conditional Assignment – 2:1 Mux

Conditional assignments select the output from among alternatives based on an input
called the condition.

module mux2(input logic [3:0] d0, d1, input logic s, output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule

17
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Conditional Assignment – 4:1 Mux

module mux4 (input logic [3:0] d0, d1, d2, d3, input logic [1:0]

s, output logic [3:0] y);

assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);

endmodule

18
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC

Internal Variables
Often it is convenient to break a complex function into intermediate steps.

In SystemVerilog, internal signals are usually declared as logic.

If we define intermediate signals, P and G,
module fulladder (input logic a, b, cin, output logic s, cout);
logic p, g;
assign p = a ^ b;
we can rewrite the full adder as follows: assign g = a & b;

assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule

19
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Precedence

Cout = G + (P · Cin)

Cout = (G + P) · Cin

If we had not used parentheses, the default operation order

is defined by the language.

20
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Numbers
Numbers can be specified in binary, octal, decimal, or hexadecimal (bases 2, 8, 10, and 16, respectively).

21
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Z’s and X’s

▶ HDLs use z to indicate a floating value, z is particularly useful for describing a tristate
buffer, whose output floats when the enable is 0.

▶ Similarly, HDLs use x to indicate an invalid logic level. If a bus is simultaneously driven to 0 and 1
by two enabled tristate buffers (or other gates), the result is x, indicating contention.

▶ At the start of simulation, state nodes such as flip-flop outputs are initialized to an unknown state.

22
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Z’s and X’s

module tristate(input logic [3:0] a, input logic en, output tri [3:0] y);
assign y = en ? a : 4’bz;
endmodule

23
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Z’s and X’s

If a gate receives a floating input, it may produce an x output when it can’t determine the correct
output value.

Similarly, if it receives an illegal or uninitialized input, it may produce an x output.

24
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Bit Swizzling

Often it is necessary to operate on a subset of a bus or to concatenate (join together)

signals to form busses.

These operations are collectively known as bit swizzling.

Y is given the 9-bit value c2c1d0d0d0c0101 using bit swizzling operations.

assign y = {c[2:1], {3{d[0]}}, c[0], 3'b101};

25
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Delays

▶ HDL statements may be associated with delays specified in arbitrary units.

▶ They are helpful during simulation to predict how fast a circuit will work (if you specify
meaningful delays) and also for debugging purposes to understand cause and effect (deducing the
source of a bad output is tricky if all signals change simultaneously in the simulation results).

▶ These delays are ignored during synthesis; the delay of a gate produced by the synthesizer
depends on its tpd and tcd specifications, not on numbers in HDL code.

26
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Delays

It assumes that inverters have a delay of 1 ns, three-input AND gates have a delay of 2
ns, and three-input OR gates have a delay of 4 ns.
‘timescale 1ns/1ps ▶ SystemVerilog files can include a timescale directive that
indicates the value of each time unit.
module example(input logic a, b, c, output logic y);
logic ab, bb, cb, n1, n2, n3; ▶ The statement is of the form 'timescale unit/precision.
assign #1 {ab, bb, cb} = ~{a, b, c};
assign #2 n1 = ab & bb & cb; ▶ In this file, each unit is 1 ns, and the simulation has 1 ps
assign #2 n2 = a & bb & cb; precision.
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3; ▶ If no timescale directive is given in the file, a default unit and
endmodule precision (usually 1 ns for both) are used. 113
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Delays

28
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC STRUCTURAL MODELING

Structural Modeling - describing a module in terms of how it is composed of simpler modules.

4 bit Ripple
Carry Adder

Half Adder Half Adder Half Adder Half Adder

HA HA HA HA HA HA HA
HA

29
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC STRUCTURAL MODELING – 4: 1 Mux
module mux4 (input logic [3:0] d0, d1, d2, d3, input logic [1:0] s, output logic [3:0] y);
logic [3:0] low, high;
mux2 lowmux (d0, d1, s[0], low);
mux2 highmux (d2, d3, s[0], high);
mux2 finalmux (low, high, s[1], y);
endmodule

▶ Multiple instances of the same module

are distinguished by distinct names, in this
case lowmux, highmux, and finalmux.

▶ This is an example of regularity, in

which the 2:1 multiplexer is reused many
times.
Each copy of the 2:1 multiplexer is called an instance. 116
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC STRUCTURAL MODEL OF 2:1 MULTIPLEXER

module mux2 (input logic [3:0] d0, d1, input logic s, output tri [3:0] y);
tristate t0(d0, ~s, y);
tristate t1(d1, s, y);
endmodule

31
COMPUTER AIDED DIGITAL DESIGN
Unit 1: Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC (a) UNSIGNED MULTIPLIER (b) SIGNED MULTIPLIER

(a): unsigned multiplier

module multiplier(input logic [3:0] a, b, output logic [7:0] y); In SystemVerilog, signals are considered unsigned by
assign y = a * b; default. Adding the signed modifier (e.g., logic signed
endmodule [3:0] a) causes the signal a to be treated as signed.

(b): signed multiplier

module multiplier(input logic signed [3:0] a, b, output logic signed [7:0] y);
assign y = a * b;
endmodule

32
COMPUTER AIDED DIGITAL DESIGN
Unit 1 : Hardware Description Language
Topic 2 : COMBINATIONAL LOGIC Data Types

▶ When a tri net is driven to a single value by one or

These other types are rarely used, but may be substituted anywhere a
more drivers, it takes on that value.
tri net would normally appear (e.g., for signals with multiple drivers).

▶ When it is undriven, it floats (z).

▶ When it is driven to a different value (0, 1, or x) by

multiple drivers, it is in contention (x).

▶ There are other net types that resolve differently

when undriven or driven by multiple sources.

33
 THANK YOU

Vinay Reddy
Department of Electronics & Communication Engineering
[email protected]
+91 9945730244

34