ARM EMBEDDED SYSTEMS

MODULE: 3
Microprocessors versus Microcontrollers
 A microprocessor is an electronic component that is used
by a computer to do its work. It is a central processing
unit on a single integrated circuit chip containing millions
of very small components including transistors, resistors,
and diodes that work together.

 A microcontroller is a compact integrated circuit designed

to govern a specific operation in an embedded system. A
typical microcontroller includes a processor, memory and
input/output (I/O) peripherals on a single chip
ARM EMBEDDED SYSTEMS

 The ARM processor core is a key component of many

successful 32-bit embedded systems. ARM cores are widely
used in mobile phones, handheld organizers, and a multitude
of other everyday portable consumer devices.

 The first ARM1 prototype was designed in 1985. The ARM

Company bases their success on a simple and powerful
original design, which continues to improve today through
constant technical innovation.
THE RISC DESIGN
PHYLOSOPHY:

 In contrast, the
traditional complex CISC RISC

instruction set computer 1. Complex instruction taking multiple

clock
1. Simple Instruction taking single clock

(CISC) relies more on 2. Emphasis on hardware, complexity is in 2. Emphasis on software, complexity is in

the micro- program/ processor the compiler
the hardware for 3. Complex instructions, Instructions 3. Reduced instructions, Instructions
instruction functionality. executed by micro- program/ processor executed by hardware

4. Variable format instructions, single 4. Fixed format instructions, multiple

register set and many instructions register sets and few instructions

5. Many instructions and many addressing 5.Fixed instructions and few addressing

 The CISC instructions modes modes

6. Conditional jump is usually based on 6. Conditional jump can be used based on a

are more complicated. status register bit bit anywhere in memory

Memory reference is embedded in many 7. Memory reference is embedded in LOAD/

instruction STORE instructions
The RISC philosophy is implemented with four major
design rules:
1. Instructions—
RISC processors have a reduced number of instruction classes. These classes
provide simple operations that can each execute in a single cycle.
In contrast, in CISC processors the instructions are often of variable size and
take many cycles to execute.
2. Pipelines—
The processing of instructions is broken down into smaller units that can be
executed in parallel by pipelines.
There is no need for an instruction to be executed by a mini-program called
microcode as on CISC processors.
3. Registers—
RISC machines have a large general-purpose register set. Any register can contain either data
or an address. Registers act as the fast local memory store for all data processing operations.
In contrast, CISC processors have dedicated registers for specific purposes.
4. Load-store architecture—
The processor operates on data held in registers. Separate load and store instructions transfer
data between the register bank and external memory. Memory accesses are costly, so
separating memory accesses from data processing provides an advantage because you can use
data items held in the register bank multiple times without needing multiple memory accesses.
In contrast, with a CISC design the data processing operations can act on memory
directly.
These design rules allow a RISC processor to be simpler, and thus the core can operate at
higher clock frequencies.
In contrast, traditional CISC processors are more complex and operate at lower clock
frequencies.
 THE ARM DESIGN PHYLOSOPHY:

 There are a number of physical features that have driven the ARM
processor design.

 Portable embedded systems require battery power. The ARM

processor has been specially designed to be small to reduce power
consumption and extend battery operation—essential for applications
such as mobile phones and personal digital assistants (PDAs).

 High code density is another major requirement since embedded

systems have limited memory due to cost and/or physical size
restrictions—useful for applications that have limited on-board
memory, such as mobile phones and mass storage devices.
 Embedded systems are price sensitive o Hence, use slow and
low-cost memory devices to get substantial savings—essential
for high-volume applications like digital cameras.

 ARM has incorporated hardware debug technology within the

processor so that software engineers can view what is happening
while the processor is executing code. With greater visibility,
software engineers can resolve issues faster.

 The ARM core is not a pure RISC architecture because of the

constraints of its primary application—the embedded system.
 Instruction Set for Embedded Systems:

 Variable cycle execution for certain instructions—Not every ARM

instruction executes in a single cycle.

 Inline barrel shifter leading to more complex instructions—The

inline barrel shifter is a hardware component that preprocesses one of
the input registers before it is used by an instruction.
 Thumb 16-bit instruction set—ARM enhanced the processor core
by adding a second 16-bit instruction set called Thumb that permits
the ARM core to execute either 16- or 32-bit instructions

 Conditional execution—An instruction is only executed when a

specific condition has been satisfied. This feature improves
performance and code density by reducing branch instructions.

 Enhanced instructions—The enhanced digital signal processor

(DSP) instructions were added to the standard ARM instruction set to
support fast 16×16-bit multiplier operations. These instructions allow
a faster-performing ARM processor
EMBEDDED SYSTEM HARDWARE:
EMBEDDED SYSTEM HARDWARE:

 The Figure shows a typical embedded device based on

an ARM core.

 Each box represents a feature or function.

 The lines connecting the boxes are the buses carrying

data.
 We can separate the device into four main hardware components:
1. The ARM processor controls the embedded device. Different
versions of the ARM processor are available to suit the desired operating
characteristics.
 An ARM processor comprises a core (the execution engine that
processes instructions and manipulates data) plus the surrounding
components (memory and cache) that interface it with a bus.
2. Controllers coordinate important functional blocks of the system.
Two commonly found controllers are interrupt and memory controllers.
3. The peripherals provide all the input-output capability external to the
chip and are responsible for the uniqueness of the embedded device.
4. A bus is used to communicate between different parts of the device.
 ARM Bus Technology:
Embedded devices use an on-chip bus that is internal to the chip and that
allows different peripheral devices to be interconnected with an ARM core.

There are two different classes of devices attached to the bus:

1. The ARM processor core is a bus master—a logical device capable of
initiating a data transfer with another device across the same bus.
2. Peripherals tend to be bus slaves—logical devices capable only of
responding to a transfer request from a bus master device.
 AMBA Bus Protocol:

 The Advanced Microcontroller Bus Architecture (AMBA) was

introduced in 1996 and has been widely adopted as the on-chip bus
architecture used for ARM processors.

 The first AMBA buses introduced were the ARM System Bus (ASB)
and the ARM Peripheral Bus (APB). Later ARM introduced another
bus design, called the ARM High Performance Bus (AHB).

 Using AMBA, peripheral designers can reuse the same design on

multiple projects. A peripheral can simply be bolted onto the on-chip
bus without having to redesign an interface for each different
processor architecture.
 ARM has introduced two variations on the AHB bus: Multi-layer
AHB and AHB-Lite.
 The Multi-layer AHB bus allows multiple active bus masters.
 AHB-Lite is a subset of the AHB bus and it is limited to a single bus
master.
 Memory:

An embedded system has to have some form of memory to store and

execute code.

You have to compare price, performance, and power consumption when

deciding upon specific memory characteristics, such as hierarchy,
width, and type.
Memory hierarchy:
Hierarchy:
All computer systems have memory arranged in some form of
hierarchy.

The Figure shows the memory trade-offs: the fastest memory cache is
physically located nearer the ARM processor core and the slowest
secondary memory is set further away.

Generally the closer memory is to the processor core, the more it costs
and the smaller its capacity
 The cache is placed between main memory and the core. It is used to
speed up data transfer between the processor and main memory.

 The main memory is large—around 256 KB to 256 MB (or even

greater), depending on the application—and is generally stored in
separate chips. Load and store instructions access the main memory
unless the values have been stored in the cache for fast access.

 Secondary storage is the largest and slowest form of memory. Hard

disk drives and CD-ROM drives are examples of secondary storage.
Width:

 The memory width is the number of bits the memory returns on each
access—typically 8, 16, 32, or 64 bits.

 The memory width has a direct effect on the overall performance and
cost ratio. Lower bit memories are less expensive, but reduce the
system performance.
 Types:
There are many different types of memory:

1. Read-only memory (ROM) is a memory device or storage

medium that stores information permanently. The memory from
which we can only read but cannot write on it.
ROMs are used in high-volume devices that require no
updates or corrections.

2. Flash ROM It can keep stored data and information even when the
power is off. It can be electrically erased and reprogrammed.
The erasing and writing of flash ROM are completely software controlled
with no additional hardware required, which reduces the manufacturing
costs.
3. Dynamic random access memory (DRAM) is the most commonly used RAM for
devices. It has the lowest cost per megabyte compared with other types of RAM.
DRAM is dynamic—it needs to have its storage cells refreshed and given a new
electronic charge every few milliseconds, so you need to set up a DRAM
controller before using the memory.

4. Static random access memory (SRAM) is faster than the more traditional DRAM,
but requires more silicon area.
SRAM is static—the RAM does not require refreshing. The access time for SRAM
is considerably shorter than the equivalent DRAM. But cost of SRAM is high.

5. Synchronous dynamic random access memory (SDRAM) is one of many

subcategories of DRAM. It can run at much higher clock speeds than conventional
memory.
SDRAM synchronizes itself with the processor bus, because it is clocked.
 Peripherals:

 Embedded systems that interact with the outside world need some form
of peripheral device. A peripheral device performs input and output
functions for the chip by connecting to other devices or sensors that are
off-chip.

 Each peripheral device usually performs a single function and may

reside on-chip.

 Peripheralsrange from a simple serial communication device to a more

complex 802.11 wireless device.
 Two important types of controllers are memory controllers and interrupt controllers.

 Memory Controllers: Memory controllers connect different types of

memory to the processor bus.
 On power-up a memory controller is configured in hardware to allow certain
memory devices to be active. These memory devices allow the initialization
code to be executed.

 Interrupt Controllers: When a peripheral or device requires attention, it

raises an interrupt to the processor.
 An interrupt controller provides a programmable governing policy that allows
software to determine which peripheral or device can interrupt the processor at
any specific time by setting the appropriate bits in the interrupt controller
registers.
There are two types of interrupt controller available for the ARM processor:

The standard interrupt controller and The vector interrupt controller

1. The standard interrupt controller sends an interrupt signal to the processor core when an
external device requests servicing.

The interrupt handler determines which device requires servicing by reading a device
bitmap register in the interrupt controller.

2. The vector interrupt controller (VIC) is more powerful than the standard interrupt
controller, because it prioritizes interrupts and simplifies the determination of which device
caused the interrupt.
 EMBEDDED SYSTEM SOFTWARE:

 4 Typicalcomponents required to control embedded system

are shown in the figure
 Theinitialization code is the first code executed on the board
and is specific to a particular target or group of targets.

 Theoperating system provides an infrastructure to control

applications and manage hardware system resources.

 Thedevice drivers provide a software interface to the

peripheral devices.

 Anapplication performs one of the tasks required for a

device.
Initialization (Boot) Code:

 Initialization code (or boot code) takes the processor from the reset state to a state where
the operating system can run.
 Booting is the process of starting a computer.
 It can be initiated by hardware such as a button press or by a software command.
 The initialization code handles a number of administrative
tasks before handing control over to an operating system .

 We can group these different tasks into three phases:

 Initial hardware configuration
 Diagnostics
 booting.
1. Initial hardware configuration involves setting up the target platform, so that it can
boot an image.
The target platform comes up in a standard configuration; but, this configuration requires
modifications based on the booted image.

Memory remapping is must for ARM-based embedded systems. Here initialization code is
starts from ROM at power-up.

 Then the initialization code remaps the memory map at address of RAM.
2. Diagnostics
 Diagnostic code are often embedded in the initialization
code itself.
 Diagnostic code tests the system whether the selected targets are
working fine or not.

 It also tracks standard system-related issues.

 The primary purpose of diagnostic code is fault identification and

prevention.
 3. Booting
 involves loading an image and handing control over to that image.
 It’s a complicated process where the system must boot different operating systems or
different versions of the same operating system.

 Booting an image is the final phase, but first you must load the image.

 Loading an image involves anything from copying an entire program including code
and data into RAM.

 Once booted, the system hands over control to that image.

 ARM processors support over 50 operating systems.
 We can divide operating systems into two main categories:
 real-time operating systems (RTOSs) and
 platform operating systems.
 real-time operating systems (RTOSs) : All real time
operating systems are designed to execute their task within a
particular time interval.
  Hard Real-Time operating system:
These operating systems guarantee that critical tasks be completed within a
range of time.
 Soft real-time operating system:
This operating system provides some relaxation in the time limit.
 Platform operating systems require a memory management unit to manage
large, non-real-time applications and tend to have secondary storage.
 The Linux operating system is a typical example of a platform operating system.
Applications:
 ARM processors are found in numerous market segments, including networking, auto-
motive, mobile and consumer devices, mass storage, and imaging.
 ARM processor is found in networking applications like home gateways, DSL modems for
highspeed Internet communication, and 802.11 wireless communications.
 The mobile device segment is the largest application area for ARM processors, because of
mobile phones.
 ARM processors are also found in mass storage devices such as hard drives and imaging
products such as inkjet printers.
ARM PROCESSOR FUNDAMENTALS
 Explain ARM core data flow model with neat diagram.

 The arrows represent the flow of data, the lines represent the buses, and the boxes
represent either an operation unit or a storage area.

 Data enters the processor core through the Data bus. The data may be an instruction to
execute or a data item.

 Figure shows a Von Neumann implementation of the ARM—data items and instructions
share the same bus. (In contrast, Harvard implementations of the ARM use two different
buses).
 Instruction Fetch: Fetches the instruction from the memory

 Instruction Decoder: Decodes the instruction and identifies the opcode of the instruction.

 Sign extend hardware: The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values
as they are read from memory and placed in a register.
 ALU (arithmetic logic unit) or MAC (multiply-accumulate unit): Takes the register
values Rn and Rm from the A and B buses and computes a result.

 Data processing instructions write the result in Rd directly to the register file.
 Load and store instructions use the ALU to generate an address to be held in the
address register and broadcast on the Address bus.

 Incrementer: For load and store instructions the incrementer updates the address
register before the core reads or writes the next register value from or to the next
sequential memory location.
Registers
 General-purpose registers hold either data or an address.
 They are identified with the letter r prefixed to the register number. For example, register
4 is given the label r4.
• All the registers shown are 32 bits in size.

• There are up to 18 active registers: 16 data registers and 2 processor status registers.

• The data registers are visible to the programmer as r0 to r15.

• The ARM processor has three registers assigned to a particular task or special function:
 Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack
in the current processor mode.

 Register r14 is called the link register (lr) and is where the core puts the return address
whenever it calls a subroutine.

 Register r15 is the program counter (pc) and contains the address of the next instruction to
be fetched by the processor.
• In addition to the 16 data registers, there are two program status registers:
– cpsr and spsr (the current and saved program status registers, respectively).

 Current Program Status Register- CPSR

• The cpsr is a dedicated 32-bit register and resides in the register file.

• The shaded parts are reserved for future expansion.

• The cpsr is divided into four fields, each 8 bits wide:

-flags,
- status,
- extension, and
- control.

• In current designs the extension and status fields are reserved for future use.
• The control field contains the
- processor mode,
-state, and
- interrupt mask bits.

• The flags field contains the condition flags.

• The processor mode determines which registers are active and the access rights to the
cpsr register itself.
• Each processor mode is either
– privileged or
– non privileged
• A privileged mode allows full read-write access to the cpsr.
• Conversely, a non-privileged mode only allows read access to the control field in
the cpsr but still allows read-write access to the condition flags.
• There are seven processor modes in total:

- six privileged modes

(abort, fast interrupt request, interrupt request, supervisor, system, and
undefined)
- one non privileged mode (User).

• Abort Mode: The processor enters abort mode when there is a failed attempt to
access memory.

• Fast interrupt and interrupt request modes: Correspond to the two interrupt
levels available on the ARM processor.
• Supervisor mode: is the mode that an operating system kernel operates in.

• System mode: is a special version of user mode that allows full read-write
access to the cpsr.

• Undefined mode: is used when the processor encounters an instruction that is

undefined or not supported by the implementation.

• User mode: is used for programs and applications.

Banked Registers
• There are 37 registers in the register file. Of those, 20 registers are
hidden registers and are called as banked registers indicated in
shade.
• They are available only when the processor is in a particular mode.
 State and Instruction Sets
• The state determines which instruction set is being executed.
• There are three instruction states:
– ARM state
– Thumb state, and
– Jazelle state.
 ARM State:
 The ARM instruction set (32 bit) is only active when the processor is in ARM state (T=0
and J=0).

 Thumb State:
 Similarly the Thumb instruction set (16 bits) is only active when the processor is in Thumb
state (T=1 and J=0).

 In Thumb state the processor executes only Thumb 16-bit instructions. You cannot
intermingle ARM , Thumb, and Jazelle instructions
 Jazelle State:
 The Jazelle instruction set (8 bits) is only active when the processor is in Jazelle state (T=0
and J=1).

 Jazelle executes 8-bit instructions and is a hybrid mix of software and hardware designed
to speed up the execution of Java byte-codes.

 To execute Java byte-codes, Jazelle technology plus a Java virtual machine is required.
Interrupt Masks
• Interrupt masks are used to stop interrupt requests from interrupting the
processor.

• There are two interrupt request levels available on the ARM processor core
- interrupt request (IRQ) and
- fast interrupt request (FIQ).

• The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which control the
masking of IRQ and FIQ, respectively.

• The I bit masks IRQ when set to binary 1, and similarly the F bit masks FIQ
when set to binary 1.
Condition Flags

 Condition flags are updated by comparisons and the result of

ALU operations that specify the S instruction suffix.

 For example, if a SUBS subtract instruction results in a register

value of zero, then the Z flag in the cpsr is set.
 Here we use a notation that presents the cpsr data in a more human readable
form.

 When a bit is a binary 1 we use a capital letter;

 when a bit is a binary 0, we use a lowercase letter.

 For the condition flags a capital letter shows that the flag has been set.

 For interrupts a capital letter shows that an interrupt is disabled.

Conditional Execution
 Conditional execution controls the execution of an instruction.

 Most instructions have a condition attribute that determines if the

Microcontroller core will execute it or not based on the setting of the condition
flags.

 Prior to execution, the processor compares the condition attribute with the
condition flags in the cpsr.

 If they match, then the instruction is executed; otherwise the instruction is

ignored.
Condition mnemonics
 Pipeline

✓ A pipeline is the mechanism in a RISC processor, which is used to execute

instructions.
✓ Pipeline speeds up execution by fetching the next instruction while other
instructions are being decoded and executed.
 Fetch loads an instruction from memory.

 Decode identifies the instruction to be executed.

 Execute processes the instruction and writes the result back to a register
Pipeline Executing Characteristics
 The three instructions are placed into the pipeline sequentially.
 In the first cycle, the core fetches the ADD instruction from memory.
 In the second cycle, the core fetches the SUB instruction and decodes the ADD
instruction.
 In the third cycle, both the SUB and ADD instructions are moved along the
pipeline. The ADD instruction is executed, the SUB instruction is decoded, and
the CMP instruction is fetched.
 This procedure is called filling the pipeline.
Exceptions, Interrupts, and the Vector
Table
 When an exception or interrupt occurs, the processor sets the pc to a specific
memory address.

 This special address range called the vector table.

 The entries in the vector table are instructions that branch to specific routines
designed to handle a particular exception or interrupt.

 On some processors the vector table is located at a higher address in memory

(starting at the offset 0xffff0000). On some processor from the lower address
0x00000000.
 When an exception or interrupt occurs, the processor suspends normal
execution and loads instructions from the vector table.

 Each vector table entry contains a form of branch instruction pointing to the
start of a specific routine.

 Reset vector:
 is the location of the first instruction executed by the processor when power
is applied. This instruction branches to the initialization code.

 Undefined instruction vector:

 is called when the processor cannot decode an instruction.
 Software interrupt vector:
 is called when you execute a SWI instruction. The SWI instruction is
frequently used as the mechanism to invoke an operating system routine.
 Prefetch abort vector:
 occurs when the processor attempts to fetch an instruction from an address
without the correct access permissions. The actual abort occurs in the decode
stage.
 Data abort vector:
 is similar to a prefetch abort but is raised when an instruction attempts to
access data memory without the correct access permissions.
 Interrupt request vector:
 is used by external hardware to interrupt the normal execution flow of the
processor. It can only be raised if IRQs are not masked in the cpsr.

 Fast interrupt request vector:

 is similar to the interrupt request but is reserved for hardware requiring faster
response times. It can only be raised if FIQs are not masked in the cpsr.
Core Extensions
• The extensions (Assistants) are standard components placed next to the
ARM core.

• They improve performance, manage resources, and provide extra

functionality and are designed to provide flexibility in handling particular
applications.

• There are three hardware extensions ARM wraps around the core:
- cache and Tightly Coupled Memory(TCM),
- memory management, and
- the coprocessor interface.
Cache and Tightly Coupled Memory(TCM),

 The cache is a block of fast memory placed between main memory and the core.
It allows for more efficient fetches from some memory types.

 With a cache the processor core can run for the majority of the time without
having to wait for data from slow external memory.

 Most ARM-based embedded systems use a single-level cache internal to the

processor.
 ARM has two forms of cache. The first is found attached to the Von Neumann–
style cores.

 It combines both data and instruction into a single unified cache, as shown in the
following Figure.
The second form, attached to the Harvard-style cores, has separate caches for
data and instruction, as shown in the following Figure.
 A cache provides an overall increase in performance, but at the expense of
predictable execution.

 But the real-time systems require the code execution to be deterministic— the
time taken for loading and storing instructions or data must be predictable.

 This is achieved using a form of memory called tightly coupled memory (TCM).
TCM is fast SRAM located close to the core and guarantees the clock cycles
required to fetch instructions or data.

 By combining both technologies, ARM processors can have both improved

performance and predictable real-time response. The following Figure shows an
example core with a combination of caches and TCMs.
 By combining both technologies, ARM processors can have both improved
performance and predictable real-time response. The following Figure shows an
example core with a combination of caches and TCMs.
Memory Management
 Embedded systems often use multiple memory devices.

 It is usually necessary to have a method to protect the system from applications trying to
make inappropriate accesses to hardware.

 This is achieved with the assistance of memory management hardware.

 ARM cores have three different types of memory management hardware.

- Non-protected memory – no protection
- MPUs – limited protection
- MMUs – full protection
 Non protected memory is fixed and provides very little flexibility. It is normally
used for small, simple embedded systems that require no protection from virus.

 MPUs employ a simple system that uses a limited number of memory regions.
These regions are controlled with a set of special coprocessor registers, and each
region is defined with specific access permissions. This type of memory
management is used for systems that require memory protection.

 A computer’s memory management unit (MMU) is the physical hardware that

handles its virtual memory and caching operations MMUs are designed for
operating systems that support multitasking.
 Coprocessors
 Coprocessors can be attached to the ARM processor. And that is designed to
perform specialized tasks.

 A coprocessor extends the processing features of a core and increases the

throughput.

 More than one coprocessor can be added to the ARM core via the coprocessor
interface.
 The coprocessor can be accessed through a group of dedicated ARM instructions
that provide a load-store type interface.

 The coprocessor can also extend the instruction set by providing a specialized
group of new instructions.

 These new instructions are processed in the decode stage of the ARM pipeline.