Scribd
Upload
3 views29 pages

Lecture 5 12082024

The document outlines the basic process steps for wafer preparation in IC fabrication, including wafer lapping, crystal growth, and various processing techniques. It compares silicon (Si) and germanium (Ge) as materials for electronic devices, highlighting Si's advantages in terms of stability, cost, and performance. Additionally, it details the production of electronic grade silicon (EGS) from metallurgical grade silicon (MGS) and the Czochralski growth method for creating single crystal silicon ingots.

Uploaded by

Tanvi naik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3 views29 pages

Lecture 5 12082024

The document outlines the basic process steps for wafer preparation in IC fabrication, including wafer lapping, crystal growth, and various processing techniques. It compares silicon (Si) and germanium (Ge) as materials for electronic devices, highlighting Si's advantages in terms of stability, cost, and performance. Additionally, it details the production of electronic grade silicon (EGS) from metallurgical grade silicon (MGS) and the Czochralski growth method for creating single crystal silicon ingots.

Uploaded by

Tanvi naik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 29

IC Fabrication Technology

Lecture -5
12-08-2024
Prof. Ramesha C K

BITS Pilani, K K Birla Goa Campus


Basic Process Steps for Wafer Preparation

Wafer Lapping and


Crystal Growth Edge Grind Cleaning

Shaping Etching Inspection

Wafer Slicing Polishing Packaging

BITS Pilani, K K Birla Goa Campus


Wafer preparation

BITS Pilani, K K Birla Goa Campus


Steps

BITS Pilani, K K Birla Goa Campus


Si vs Ge
◼ Ge was unstable in certain applications due to narrow gap of 0.66 eV

◼ Si becomes an obvious choice as the devices operate till 150 0C vs 100 0C for Ge.

◼ GeO2 is unsuitable, whereas, SiO2 is suitable for device applications.

◼  of Ge is 47  cm vs 23 x 104  cm for Si. Thus Si is more useful for the rectifying


devices. (reverse current in nA for Si, whereas, for Ge it is in microamps).
◼ Further the Si diode has large reverse breakdown voltage about 70-1000V compared
to Ge which has the reverse breakdown voltage around 50V.

Cost effectiveness: electronic grade Ge is more costly.


BITS Pilani, K K Birla Goa Campus
There are some advantages for Ge
as well

◼ It can be processed at low temperatures.

◼ Easily integrable over Si

◼ High electrical conductivity.

BITS Pilani, K K Birla Goa Campus


Electronic grade Si (EGS)

◼ A polycrystalline material of high impurity. It is a raw material for single


crystal Si.

◼ It is one of the purest materials routinely available.

◼ Good EGS: doping elements in ppb, C content less than ppm

◼ This is ensured by resistivity measurements.

BITS Pilani, K K Birla Goa Campus


Preparation of MGS

◼ Starting material is quartzite (SiO2)-a relatively pure form of sand.

◼ Firstly, metallurgical grade Si (MGS) is produced in an arc furnace.

◼ SiC+SiO2 = Si(L)+SiO(g)+CO (g)

◼ Finally, 98 % pure MGS is solidified.

BITS Pilani, K K Birla Goa Campus


BITS Pilani, K K Birla Goa Campus
Step2: Formation of SiHCl3
(Trichlorosilane)

◼ The Si is pulverized and subsequently treated with HCl

◼ Reaction at 300 0C

◼ Si (s)+3HCl(g) = SiHCl3 (g)+H2 (g)+ heat

◼ SiHCl3 is a liquid at room temperature (bp = 320C)

◼ Fractional distillation of SiHCl3

BITS Pilani, K K Birla Goa Campus


Step3: formation of EGS by CVD

• Hydrogen reduction of SiHCl3

• SiHCl3 + 2H2 = 2Si (s)+6HCl (g)

• Next step is Chemical vapour deposition (CVD) of EGS

BITS Pilani, K K Birla Goa Campus


What is chemical vapour deposition?

• A chemical process to produce high purity high performance


materials.
• Any wafer/substrate is exposed to volatile precursors, which
react/decompose on the substrate surface to form desirable
material.

BITS Pilani, K K Birla Goa Campus


• A resistance heated rod of Si serves as a nucleation point for Si
deposition. Finally, EGS rods are formed. Si is deposited on Si to
avoid foreign contamination.
• http://cnx.org/content/m31994/latest/
BITS Pilani, K K Birla Goa Campus
Si(solid) +3HCL (gas) → SiHCL3 (gas) +H2(gas)+heat
(trichlorosilane)
SiHCL3 (gas) +H2(gas → 2Si (solid) + 6HCL(gas)

BITS Pilani, K K Birla Goa Campus


Alternative process

• World wide consumption of EGS is 5 x 106kg/yr

BITS Pilani, K K Birla Goa Campus


Production of EGS from MGS

→Trichlorosilane
production

→Trichlorosilane
Purification

→Polycrystalline
Silicon Deposition

→Recovery

BITS Pilani, K K Birla Goa Campus


Growth of Single crystal Si

• Czochralski growth method (CZ method)

• Steps

• Step1: Preparation of high purity melt of Si. Supersaturated


molten Si will be a source of Si wafer deposition.

• Step2: Seed crystal is dipped into saturated molten Si

• Step3: Pulling the seed upwards and rotated at the same time.
BITS Pilani, K K Birla Goa Campus
CZ Growth Technique - steps

BITS Pilani, K K Birla Goa Campus


Wafer growth – Czochralski Method (Cz)

-From the high purity poly-Si, single crystal silicon is required,


-The Cz process is the most common for large wafer diameter production.

-The EGS is broken into small pieces and


placed in an SiO2 crucible,

-In an argon ambient, the crucible is


heated to just above 1417oC,

-A single crystal seed is then lowered into


the melt (crystal orientation and wafer
diameter determined by seed orientation
and pull rate),

-Dopant is added to the melt to


intentionally dope the resulting crystal,

-The oxygen and carbon (from graphite


furnace components), contribute about
1017-1018cm-3 contaminants.

BITS Pilani, K K Birla Goa Campus


Czochralski growth

• Polysilicon material is melted, held at


close to 1415 C and a single crystal
seed is used to start the crystal
growth.
• Pull rate, melt temperature and
rotation rate are all important control
parameters.
BITS Pilani, K K Birla Goa Campus
Polysilicon Ingots

⚫ The polycrystalline silicon


tubes refined by dissolving in
hydrofluoric acid producing
polysilicon ingots.
⚫ Polycrystalline silicon has
randomly oriented crystallites,
electrical characteristics not
ready for device fabrication.
⚫ Must be transformed into
single crystal silicon using
crystal pulling
BITS Pilani, K K Birla Goa Campus
All Si based ICs come from crystals
grown by cz technique.

BITS Pilani, K K Birla Goa Campus


Creating the Single Crystalline Ingot
⚫ Crushed high-purity polycrystalline
silicon is doped with elements like
arsenic, boron, phosphorous or
antimony and melted at 1400° in a
quartz crucible surrounded by an inert
gas atmosphere of high-purity argon.
⚫ The melt is cooled to a precise
temperature, then a "seed" of single
crystal silicon is placed into the melt and
slowly rotated as it is "pulled" out.

BITS Pilani, K K Birla Goa Campus


Step 3: Making the Ingot

⚫ A pure silicon seed


crystal is now
placed into the
molten sand bath.
⚫ This crystal will be
pulled out slowly as
it is rotated.
⚫ The result is a pure
silicon tube that is
called an ingot

BITS Pilani, K K Birla Goa Campus


Why the liquid rises?
Creating the Single Crystalline Ingot
(cont.)

⚫ The surface tension between the seed


and the molten silicon causes a small
amount of the liquid to rise with the seed
and cool into a single crystalline ingot
with the same orientation as the seed.
⚫ The ingot diameter is determined by a
combination of temperature and
extraction speed
BITS Pilani, K K Birla Goa Campus
Examples of completed ingots

BITS Pilani, K K Birla Goa Campus


BITS Pilani, K K Birla Goa Campus
Wafer Diameter Trends

300 mm

200 mm
150 mm
125 mm
100 mm
75 mm

3 4 5 6 8 12

BITS Pilani, K K Birla Goa Campus


Thank You

BITS Pilani, K K Birla Goa Campus

You might also like