STM32N6x5xx STM32N6x7xx

Arm® Cortex®-M55-based MCU, with ST Neural-ART Accelerator,

H264 encoder, Neo-Chrom 2.5D GPU, 4.2 Mbyte-contiguous SRAM
Datasheet - production data

Features VFBGA142 (8 x 8 mm) pitch 0.5 mm

VFBGA169 (6 x 6 mm) pitch 0.4 mm
• Includes ST state-of-the-art patented VFBGA178 (12 x 12 mm) pitch 0.8 mm
VFBGA198 (10 x 10 mm) pitch 0.65 mm
technology VFBGA223 (10 x 10 mm) pitch 0.5 mm
VFBGA264 (14 x 14 mm) pitch 0.8 mm
Core
Graphics
• Arm® 32-bit Cortex®-M55, 3360 CoreMark®,
frequency up to 800 MHz, 1280 DMIPS, • Neo-Chrom 2.5D GPU: scaling, rotation, alpha
32-Kbyte ICACHE, 32-Kbyte DCACHE blending, texture mapping, perspective
• Arm® MVE (M-Profile vector extension), transformation
Helium™ technology, TrustZone® MPU, NVIC • Chrom-ART Accelerator (DMA2D)
• Single and half-precision floating point unit • Hardware JPEG codec with MJPEG
(FPU) supports vector and scalar half-, single- • LCD-TFT controller up to XGA resolution
and double-precision floating-point datatypes
Video
Neural processing unit (STM32N6x7 only)
• Parallel and 2-lane CSI-2 camera interfaces
• ST Neural-ART Accelerator, frequency up to
1 GHz, 600 Gops, 288 MAC/cycle • ISP (image signal processor) with three parallel
pipes on the same input stream: bad pixel,
• Specialized hardware units for DNN decimation, black level, exposure, de-mosaic,
(deep-neural network) inference functions column conversion, contrast, crop, downsize,
• Flexible dedicated stream processing engine ROI, gamma, YUV convention, pixel packer
• Real-time encryption/decryption • H264 video encoding acceleration: baseline
• On-the-fly weight decompression profile, main profile, high profile level 1 to
level 5.2, 1080p30 and 720p60
Memories
Security and cryptography
• 4.2-Mbyte contiguous SRAM
• Arm® TrustZone® and securable I/Os
• 128-Kbyte TCM (tightly-coupled memory) RAM memories and peripherals
with ECC for critical real-time data + 64-Kbyte
instruction TCM RAM with ECC for critical • SESIP Level 3 (security evaluation standard
real-time routines for IoT platforms), Arm® PSA (platform security
architecture) certified
• 8-Kbyte backup SRAM active in VBAT mode
• Flexible life-cycle scheme with RDP and
• Flexible external memory controller with cypher password-protected debug
engine supporting up to 32-bit data bus:
SRAM, PSRAM, SDRAM/LPSDR SDRAM, • Secure provisioning of customer keys in OTP
NOR/NAND memories (one-time programmable) fuses

• XSPI with support for serial PSRAM, NAND, • Secure boot code in ROM, decrypting and
NOR, HyperRAM™/ HyperFlash™ frame authenticating customer uRoT (updatable
formats root-of-trust)

• 2 ports: XSPIM 8- and 16-bit configuration up • Secure data storage with hardware-unique key
to 200 MHz (HUK)

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This is information on a product in full production. www.st.com
 STM32N6x5xx STM32N6x7xx

• Secure firmware upgrade support with TF-M • RTC with subsecond accuracy and hardware
(trusted firmware-M) calendar
• Two AES coprocessors, including one with Debug
DPA (differential power analysis) resistance
• Development support: serial-wire debug, JTAG
• Public key accelerator (PKA), DPA resistant
• Embedded Trace Macrocell™ (ETM)
• On-the-fly encryption/decryption of external
memories General-purpose I/Os
• HASH hardware accelerator • Up to 165 pins
• True random number generator (RNG), Analog peripherals
NIST SP800-90B compliant
• 1x temperature sensor
• 96-bit unique ID
• 2x ADCs with 12-bit maximum resolution (up to
• 1.5-Kbyte OTP fuses 5 Msps), up to 20 channels
• Active tampers • 1x ADF filter with SAD and 1x MDF (six filters)
Communication peripherals Reset and power management
• 2x USB 2.0 high-speed/full-speed • POR, PDR, PBVD, and BOR
device/host OTG controllers (one with UCPD
USB Type-C® Power Delivery) • Embedded SMPS step-down converter
providing VDDCORE
• 10-Mbit, 100-Mbit, and 1-Gbit Ethernet with
TSN (time-sensitive networking) • 1.71 to 3.6 V application supply and I/Os

• 4x I2C Fm+ interfaces (SMBus/PMBus®) • Dedicated power for USB and XSPIM1,
+ 2x I3C XSPIM2, SDMMC1, and SDMMC2 I/Os

• 6x SPI, of which four I2S-capable • Backup regulator (~0.9 V)

• 2x SAI, with four DMIC support • Voltage reference for analog peripheral
(VREF+)
• 5x USART, 5x UART (ISO78916 interface, LIN,
IrDA, up to 12.5 Mbit/s) + 1x LPUART Clock management
• 2x SDMMC: MMC version 4.0, CE-ATA
• Internal oscillators: 64 MHz HSI, 4 MHz MSI,
version 1.0, and SD version 1.0.1
32 kHz LSI
• 3x FDCAN with TTCAN capability
• External oscillators: 16 to 48 MHz HSE,
Low power 32.768 kHz LSE
• Sleep, Stop and Standby modes • 4x PLL (one for the system clock, one for the
ST Neural-ART Accelerator, two for kernel
• VBAT supply for RTC, 32x 32-bit backup clocks) with fractional mode
registers + 8-Kbyte backup SRAM
Timers and watchdogs ECOPACK2 compliant packages
• 4x 32-bit timers with up to four IC/OC/PWM or
Table 1. Device summary
pulse counters and quadrature (incremental)
encoder input (up to 240 MHz) Reference Part numbers

• 2x 16-bit advanced motor control timers (up to STM32N645xx

STM32N645A0, STM32N645B0, STM32N645I0,
STM32N645L0, STM32N645X0, STM32N645Z0
240 MHz)
STM32N647A0, STM32N647B0, STM32N647I0,
• 13x 16-bit general-purpose and 5x 16-bit STM32N647xx
STM32N647L0, STM32N647X0, STM32N647Z0
low-power timers (up to 240 MHz) STM32N655A0, STM32N655B0, STM32N655I0,
STM32N655xx
STM32N655L0, STM32N655X0, STM32N655Z0
• 2x watchdogs (independent and window)
STM32N657A0, STM32N657B0, STM32N657I0,
• 1x SysTick timer STM32N657xx
STM32N657L0, STM32N657X0, STM32N657Z0

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Arm Cortex-M55 core with TrustZone, FPU, NVIC . . . . . . . . . . . . . . . . . . 23
3.2 SRAM configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 AXI cache configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.1 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.3 Core domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.4 SMPS usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.5 Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.6 Analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.7 System supply startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.8 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.9 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Convolution neural network accelerator (NPU) . . . . . . . . . . . . . . . . . . . . 32
3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.1 External flash boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.2 Serial boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.3 Development boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.8 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 34
3.9 General purpose direct memory access controller (GPDMA) . . . . . . . . . 34
3.10 High performance direct memory access controller (HPDMA) . . . . . . . . . 36
3.11 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . 38
3.12 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.13 Graphic timer (GFXTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40

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3.15 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 41

3.16 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.17 XSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.17.1 Extended-SPI interface (XSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.17.2 XSPI I/O manager (XSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18 Secure digital input/output MultiMediaCard interface (SDMMC) . . . . . . . 44
3.19 SDMMC delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.20 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.21 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.22 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.23 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.25 Camera subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.25.1 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.25.2 Digital camera interface pixel pipeline (DCMIPP) . . . . . . . . . . . . . . . . . 50
3.26 CSI-2 Host (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.27 Parallel synchronous target interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 51
3.28 Display subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.29 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.30 Neo-Chrom graphic processor (GPU2D) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.31 Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.32 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.33 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.34 Secure AES coprocessor (SAES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.35 Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.36 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.37 Memory cipher engine (MCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.38 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.39 Timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.39.1 Basic timers (TIM6/TIM7/TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.39.2 Advanced control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.39.3 General purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . . 61
3.39.4 General purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . . . 62
3.39.5 General purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . 63

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3.39.6 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.40 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.41 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.42 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.43 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.44 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.45 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.46 Universal synchronous/asynchronous receiver transmitter
(USART/UART/LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.46.1 USART/UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.46.2 LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.47 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.48 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.49 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.50 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.51 Controller area network with flexible data rate (FDCAN) . . . . . . . . . . . . . 78
3.52 USB on-the-go high speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.53 USB HS PHY controller (USBPHYC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.54 USB Type-C / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . 80
3.55 Ethernet (ETH): gigabit media access control (GMAC)
with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.56 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.56.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.56.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 83

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 141
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 141
5.3.4 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.7 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.3.8 External clock sources characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.3.9 External clock source security characteristics . . . . . . . . . . . . . . . . . . . 164
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 166
5.3.13 OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.3.20 XSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.3.21 SDMMC interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.3.22 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.3.24 Voltage reference buffer (VREFBUF) characteristics . . . . . . . . . . . . . 206
5.3.25 Digital temperature sensor (DTS) characteristics . . . . . . . . . . . . . . . . 207
5.3.26 VBAT, VDDx, VDDCORE, VDDA18AON, ADC
measurement characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.27 Temperature and VBAT monitoring characteristics
for tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
5.3.28 Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
5.3.29 Multifunction digital filter (MDF) characteristics . . . . . . . . . . . . . . . . . . 208

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5.3.30 Audio digital filter (ADF) characteristics . . . . . . . . . . . . . . . . . . . . . . . . 210

5.3.31 Camera interface (DCMI) characteristics . . . . . . . . . . . . . . . . . . . . . . . 211
5.3.32 Camera interface pixel pipeline (DCMIPP) characteristics . . . . . . . . . 212
5.3.33 Parallel interface (PSSI) characteristics . . . . . . . . . . . . . . . . . . . . . . . 213
5.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 216
5.3.35 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.36 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.37 Embedded PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
5.3.38 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 234
MDIOS target interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.2 VFBGA142 package information (B0GM) . . . . . . . . . . . . . . . . . . . . . . . 237
6.3 VFBGA169 package information (B0LA) . . . . . . . . . . . . . . . . . . . . . . . . 240
6.4 VFBGA178 package information (B0GL) . . . . . . . . . . . . . . . . . . . . . . . . 243
6.5 VFBGA198 package information (B0GJ) . . . . . . . . . . . . . . . . . . . . . . . . 245
6.6 VFBGA223 package information (B0GK) . . . . . . . . . . . . . . . . . . . . . . . . 249
6.7 VFBGA264 package information (B0GH) . . . . . . . . . . . . . . . . . . . . . . . . 252
6.8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

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List of tables STM32N6x5xx STM32N6x7xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32N645xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. STM32N647xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. STM32N655xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. STM32N657xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Operating mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8. GPDMA1 channel implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Implementation of HPDMA1 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10. HPDMA1 in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 12. Instance implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 14. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 15. SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 16. Supported OTG speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 17. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 18. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 19. Alternate functions: AF0 to AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 20. Alternate functions: AF8 to AF15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 25. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 27. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 142
Table 28. Characteristics of SMPS step-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 29. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 30. Embedded reference voltage calibration value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 31. Current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 32. Current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 33. Current consumption (core) in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 34. Current consumption (core) in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 35. Current consumption (1V8) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 36. Current consumption (1V8) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 37. Current consumption (Always ON) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 38. Current consumption (Always ON) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 39. Current consumption (SMPS) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 40. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 41. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 42. Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 43. Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 44. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 45. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 46. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 47. HSE clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 48. HSE clock characteristics (analog bypass). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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Table 49. HSE clock characteristics generated from crystal/ceramic resonator. . . . . . . . . . . . . . . . 161
Table 50. LSE clock characteristics (digital bypass). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 51. LSE clock characteristics (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 52. LSE clock characteristics generated from crystal/ceramic resonator . . . . . . . . . . . . . . . . 164
Table 53. High speed external user clock security system (HSE CSS) . . . . . . . . . . . . . . . . . . . . . . 164
Table 54. Low speed external user clock security system (LSE CSS) . . . . . . . . . . . . . . . . . . . . . . . 164
Table 55. 64 MHz high-speed internal (HSI) oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . 164
Table 56. Low power internal RC (MSI) oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 57. 32 kHz low-speed internal (LSI) oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 58. PLL1 to PLL4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 59. PLL2 to PLL4 SSCG constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 60. OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 61. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 62. EMI characteristics for fHSE = 32 MHz and fHCLK = 100 MHz . . . . . . . . . . . . . . . . . . . . 168
Table 63. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 64. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 65. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 66. Leakage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 67. RPU/RPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 68. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 69. Asynchronous non multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 174
Table 70. Asynchronous non multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 174
Table 71. Asynchronous non multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 176
Table 72. Asynchronous non multiplexed SRAM/PSRAM/NOR write - NWAIT timings . . . . . . . . . . 176
Table 73. Asynchronous multiplexed PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 74. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 178
Table 75. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 76. Asynchronous multiplexed PSRAM/NOR write - NWAIT timing . . . . . . . . . . . . . . . . . . . 180
Table 77. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 78. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 79. Synchronous non multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 80. Synchronous non multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 81. NAND flash memory read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 82. NAND flash memory write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 83. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 84. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 85. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 86. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 87. XSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 88. XSPI characteristics in DTR mode without DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 89. XSPI characteristics in DTR mode (with DQS or HyperBus) . . . . . . . . . . . . . . . . . . . . . . 196
Table 90. Output speed settings versus voltage and clock frequency . . . . . . . . . . . . . . . . . . . . . . . 198
Table 91. Dynamic characteristics: SD, VDD = 1.71 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 92. Dynamic characteristics: eMMC, VDD = 1.71 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 93. Delay block dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 94. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 95. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 96. Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 97. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 98. DTS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 99. VBAT, VDDx, VDDCORE, VDDA18AON, ADC measurement characteristics . . . . . . . . 207
Table 100. Temperature and VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

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Table 101. Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 102. MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 103. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 104. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 105. DCMIPP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 106. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 107. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 108. LCD-TFT characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 109. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 110. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 111. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 112. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 113. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 114. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 115. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 116. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 117. Dynamic characteristics: Ethernet MAC signals for MDIO/SMA. . . . . . . . . . . . . . . . . . . . 226
Table 118. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 119. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 120. Dynamic characteristics: Ethernet MAC signals for RGMII ID . . . . . . . . . . . . . . . . . . . . . 228
Table 121. USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 122. CSI PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 123. USB PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 124. UCPDPHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 125. Dynamic characteristics: JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 126. Dynamic characteristics: SWD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 127. MDIO target timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 128. VFBGA142 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 129. VFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 130. VFBGA178 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 131. VFBGA178 - Example of PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . . . 245
Table 132. VFBGA198 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 133. VFBGA223 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 134. VFBGA264 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 135. VFBGA264 - Recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . 254
Table 136. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

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List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 2. SMPS configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3. Device startup with VCORE supplied directly from an external SMPS. . . . . . . . . . . . . . . . 27
Figure 4. Device startup with VCORE supplied directly from the internal SMPS. . . . . . . . . . . . . . . . 28
Figure 5. XSPIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6. VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7. VFBGA142 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 8. VFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 9. VFBGA178 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 10. VFBGA198 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 11. VFBGA223 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 12. VFBGA264 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 13. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 15. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 17. SMPS power efficiency vs. ILOAD (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 18. HSE clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 19. HSE clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 20. Typical application with a 40 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 21. LSE clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 22. LSE clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 23. VIL/VIH for TT I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 25. Asynchronous non multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 175
Figure 26. Asynchronous non multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 177
Figure 27. Asynchronous multiplexed PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 28. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 29. Synchronous non multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 30. Synchronous non multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 31. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 32. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 33. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 34. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 35. XSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 36. XSPI timing diagram – DTR mode (no DQS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 37. XSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 38. XSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 39. XSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 40. XSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 41. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 42. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 43. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 44. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 45. Typical connection diagram using the ADC
with TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 46. MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 47. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

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List of figures STM32N6x5xx STM32N6x7xx

Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 49. DCMIPP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 50. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 51. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 52. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 53. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 54. SPI timing diagram - Controller mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 55. SPI timing diagram - Target mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 56. SPI timing diagram - Target mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 57. I2S target timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 58. I2S controller timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 59. SAI controller timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 60. SAI target timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 61. Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 62. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 63. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 64. USART timing diagram in SPI controller mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 65. USART timing diagram in SPI target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 66. VFBGA142 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 67. VFBGA169 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 68. VFBGA178 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 69. VFBGA178 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 70. VFBGA198 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 71. VFBGA223 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 72. VFBGA264 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 73. VFBGA264 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

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1 Introduction

This document provides the ordering information and mechanical device characteristics of
STM32N645xx and STM32N655xx (hereafter referred to as STM32N6x5xx) and
STM32N647xx and STM32N657xx (hereafter referred to as STM32N6x7xx) MCUs.
For information on the device errata with respect to the datasheet and reference manual
(RM0486) refer to the errata sheet ES0620.
For information on the Arm®(a) Cortex®-M55 core, refer to the Cortex®-M55
Technical Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description STM32N6x5xx STM32N6x7xx

2 Description
The STM32N6x5xx and STM32N6x7xx devices are based on the high-performance Arm®
Cortex®-M55, operating at a frequency up to 800 MHz.
The Cortex®-M55 core features the Arm® Helium™ vector processing technology. On top of
standard microcontroller tasks, this core enables energy-efficient digital signal processing.
The Cortex®-M55 is equipped with a floating-point unit (FPU) that supports single- and
half-precision (IEEE 754 compliant) data-processing. The Cortex®-M55 includes a 32-
Kbyte ICACHE, a 32-Kbyte DCACHE, as well as 128-Kbyte data TCM RAM and 64-Kbyte
instruction TCM RAM with ECC for critical real-time routines.
These microcontrollers have TrustZone®-aware support and a memory protection unit
(MPU) for enhanced application security. A secure boot ROM ensures secure booting from
external interfaces.
The devices embed a 4.2-Mbyte contiguous SRAM organized in several banks, an 8-Kbyte
backup SRAM active in VBAT mode, and a flexible external memory controller (FMC) for
static memories, XSPI 8-/16-bit configurations.
The STM32N6x7xx devices feature an ST Neural-ART accelerator, running at a maximum
frequency of 1 GHz, and providing 600 Gops using optimized hardware units for DNN
(deep-neural network) inference functions to optimize power efficiency. Dedicated streaming
engines are integrated into it to optimize data flow and minimize internal buffer usage and
power. The accelerator supports on-the-fly weight decompression and real-time data
encryption and decryption.
The Neo-Chrom graphic accelerator ensures efficient 2.5D graphic processing, by providing
hardware acceleration for functions like scaling, using high-quality interpolation, free
rotation, alpha blending, texture mapping, and perspective transformation.
For camera applications, a parallel and CSI interface together with an integrated hardware
ISP is foreseen. The ISP provides processing of three parallel pipes on the same input
stream. Supported algorithms are bad pixel, decimation, black-level tuning, exposure
control, de-mosaicking, column conversion, contrast, cropping, downsizing, ROI isolation,
gamma correction, YUV conversion, and pixel packer. The ISP output can be directly fed via
a DMA to the NPU.
Optionally, the devices embed a hardware H264 encoding block supporting baseline profile,
main profile and high profile level 1 to level 5.2, supporting frame rates of up to 30 frames
per second for 1080p resolution.
A dedicated hardware accelerator ensures fast and simple JPEG and motion JPEG
compression and decompression.
The devices offer an extensive range of enhanced I/Os and peripherals, and operate in the
-40 to +125 °C temperature range, from 1.71 to 3.6 V power supply. A comprehensive set of
low-power modes (Sleep, Stop, and Standby) allows the design of low-power applications.
The devices are offered in six VFBGA packages, ranging from 142 to 264 pins.

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Table 2. STM32N645xx features and peripheral counts

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N645X0 N645L0 N645B0 N645I0 N645A0 N645Z0

System (Mbytes) 4.2

SRAM
Backup (Kbytes) 8
(1)
16 bits 1 1 0
XSPI
8 bits 1
Advanced control 2 1 0
General purpose 10 7
Timers
Basic 3 2 1
Low-power 5 4 2 1
I2S 3 1 0
SPI 6 5
I2C 4 3
I3C 2
USART 5 4 3 2
UART 5 4 3
LPUART 1
Communication
SAI 2
interfaces
FDCAN 3
OTG HS 2
UCPD Yes
SDMMC 2 1 0
CSI Yes
PSSI Yes
LTDC Yes
FMC_NOR32
No
FMC_NOR16
FMC_NORMUX Yes No
FMC Yes
FMC SDRAM32 No
FMC SDRAM16
Yes No
FMC_NAND16
Multi-function digital filter (MDF) 6 filters 2 filters
Audio digital filter (ADF) Yes

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Description STM32N6x5xx STM32N6x7xx

Table 2. STM32N645xx features and peripheral counts (continued)

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N645X0 N645L0 N645B0 N645I0 N645A0 N645Z0

SAES No
CRYPT No
Crypto
PKA No
MCE1.4 No
Accelerator Neural-ART No
Real time clock (RTC) Yes
RNG Yes
ADC (12 bits) 2
Digital temperature sensor (DTS) Yes
Internal voltage reference buffer Yes
Maximum CPU frequency 600 MHz, 800 MHz with overdrive mode
Operating voltage 1.71 to 3.6 V
Operating
Ambient -40 to 125 °C
temperature
Name VFBGA264 VFBGA223 VFBGA198 VFBGA178 VFBGA169 VFBGA142
Package Size 14 x 14 mm 10 x 10 mm 10 x 10 mm 12 x 12 mm 6 x 6 mm 8 x 8 mm
Pitch 0.8 mm 0.5 mm 0.65 mm 0.8 mm 0.4 mm 0.5 mm
Number of IOs 165 144 126 106 90 75
1. Operates only in 8-bit mode.

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Table 3. STM32N647xx features and peripheral counts

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N647X0 N647L0 N647B0 N647I0 N647A0 N647Z0

System (Mbytes) 4.2

SRAM
Backup (Kbytes) 8
(1)
16 bits 1 1 0
XSPI
8 bits 1
Advanced control 2 1 0
General purpose 10 7
Timers
Basic 3 2 1
Low-power 5 4 2 1
I2S 3 1 0
SPI 6 5
I2C 4 3
I3C 2
USART 5 4 3 2
UART 5 4 3
LPUART 1
Communication
SAI 2
interfaces
FDCAN 3
OTG HS 2
UCPD Yes
SDMMC 2 1 0
CSI Yes
PSSI Yes
LTDC Yes
FMC_NOR32
No
FMC_NOR16
FMC_NORMUX Yes No
FMC Yes
FMC SDRAM32 No
FMC SDRAM16
Yes No
FMC_NAND16
Multi-function digital filter (MDF) 6 filters 2 filters
Audio digital filter (ADF) Yes

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Description STM32N6x5xx STM32N6x7xx

Table 3. STM32N647xx features and peripheral counts (continued)

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N647X0 N647L0 N647B0 N647I0 N647A0 N647Z0

SAES No
CRYPT No
Crypto
PKA No
MCE1.4 No
Accelerator Neural-ART Yes
Real time clock (RTC) Yes
RNG Yes
ADC (12 bits) 2
Digital temperature sensor (DTS) Yes
Internal voltage reference buffer Yes
Maximum CPU frequency 600 MHz, 800 MHz with overdrive mode
Operating voltage 1.71 to 3.6 V
Operating
Ambient -40 to 125 °C
temperature
Name VFBGA264 VFBGA223 VFBGA198 VFBGA178 VFBGA169 VFBGA142
Package Size 14 x 14 mm 10 x 10 mm 10 x 10 mm 12 x 12 mm 6 x 6 mm 8 x 8 mm
Pitch 0.8 mm 0.5 mm 0.65 mm 0.8 mm 0.4 mm 0.5 mm
Number of IOs 165 144 126 106 90 75
1. Operates only in 8-bit mode.

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Table 4. STM32N655xx features and peripheral counts

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N655X0 N655L0 N655B0 N655I0 N655A0 N655Z0

System (Mbytes) 4.2

SRAM
Backup (Kbytes) 8
(1)
16 bits 1 1 0
XSPI
8 bits 1
Advanced control 2 1 0
General purpose 10 7
Timers
Basic 3 2 1
Low-power 5 4 2 1
I2S 3 1 0
SPI 6 5
I2C 4 3
I3C 2
USART 5 4 3 2
UART 5 4 3
LPUART 1
Communication
SAI 2
interfaces
FDCAN 3
OTG HS 2
UCPD Yes
SDMMC 2 1 0
CSI Yes
PSSI Yes
LTDC Yes
FMC_NOR32
No
FMC_NOR16
FMC_NORMUX Yes No
FMC Yes
FMC SDRAM32 No
FMC SDRAM16
Yes No
FMC_NAND16
SAES Yes
CRYPT Yes
Crypto
PKA Yes
MCE1.4 Yes
Accelerator Neural-ART No

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Description STM32N6x5xx STM32N6x7xx

Table 4. STM32N655xx features and peripheral counts (continued)

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N655X0 N655L0 N655B0 N655I0 N655A0 N655Z0

Multi-function digital filter (MDF) 6 filters 2 filters

Audio digital filter (ADF) Yes
Real time clock (RTC) Yes
RNG Yes
ADC (12 bits) 2
Digital temperature sensor (DTS) Yes
Internal voltage reference buffer Yes
Maximum CPU frequency 600 MHz, 800 MHz with overdrive mode
Operating voltage 1.71 to 3.6 V
Operating
Ambient -40 to 125 °C
temperature
Name VFBGA264 VFBGA223 VFBGA198 VFBGA178 VFBGA169 VFBGA142
Package Size 14 x 14 mm 10 x 10 mm 10 x 10 mm 12 x 12 mm 6 x 6 mm 8 x 8 mm
Pitch 0.8 mm 0.5 mm 0.65 mm 0.8 mm 0.4 mm 0.5 mm
Number of IOs 165 144 126 106 90 75
1. Operates only in 8-bit mode.

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Table 5. STM32N657xx features and peripheral counts

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N657X0 N657L0 N657B0 N657I0 N657A0 N657Z0

System (Mbytes) 4.2

SRAM
Backup (Kbytes) 8
(1)
16 bits 1 1 0
XSPI
8 bits 1
Advanced control 2 1 0
General purpose 10 7
Timers
Basic 3 2 1
Low-power 5 4 2 1
I2S 3 1 0
SPI 6 5
I2C 4 3
I3C 2
USART 5 4 3 2
UART 5 4 3
LPUART 1
Communication
SAI 2
interfaces
FDCAN 3
OTG HS 2
UCPD Yes
SDMMC 2 1 0
CSI Yes
PSSI Yes
LTDC Yes
FMC_NOR32
No
FMC_NOR16
FMC_NORMUX Yes No
FMC Yes
FMC SDRAM32 No
FMC SDRAM16
Yes No
FMC_NAND16
SAES Yes
CRYPT Yes
Crypto
PKA Yes
MCE1.4 Yes
Accelerator Neural-ART Yes

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Description STM32N6x5xx STM32N6x7xx

Table 5. STM32N657xx features and peripheral counts (continued)

STM32 STM32 STM32 STM32 STM32 STM32
Feature / Peripheral
N657X0 N657L0 N657B0 N657I0 N657A0 N657Z0

Multi-function digital filter (MDF) 6 filters 2 filters

Audio digital filter (ADF) Yes
Real time clock (RTC) Yes
RNG Yes
ADC (12 bits) 2
Digital temperature sensor (DTS) Yes
Internal voltage reference buffer Yes
Maximum CPU frequency 600 MHz, 800 MHz with overdrive mode
Operating voltage 1.71 to 3.6 V
Operating
Ambient -40 to 125 °C
temperature
Name VFBGA264 VFBGA223 VFBGA198 VFBGA178 VFBGA169 VFBGA142
Package Size 14 x 14 mm 10 x 10 mm 10 x 10 mm 12 x 12 mm 6 x 6 mm 8 x 8 mm
Pitch 0.8 mm 0.5 mm 0.65 mm 0.8 mm 0.4 mm 0.5 mm
Number of IOs 165 144 126 106 90 75
1. Operates only in 8-bit mode.

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3 Functional overview

3.1 Arm Cortex-M55 core with TrustZone, FPU, NVIC

The device architecture relies on an Arm Cortex-M55 core optimized for execution:
• Main controllers:
– Cortex-M55 with Arm TrustZone mainline, with two controller ports
- M-AXI: provides access to the memory and to the peripherals
- P-AHB: provides access to the peripherals
– NPU (neural processor unit), including two controller AXI ports
• Memories:
– AHB and APB peripherals
– 4.2 Mbytes of SRAM
– 128-Kbyte data TCM RAM with ECC for critical real-time data, and 64-Kbytes of
instruction TCM RAM with ECC for critical real-time routines (TCMs case not
extended)
– 8 Kbytes of backup SRAM (BKPSRAM) active in VBAT mode
– 2 x 16-Kbyte AHB RAMs
– Flexible external memory controller (FLEXMEM) with cypher engine supporting up
to 32-bit data bus: SRAM, PSRAM, SDRAM, LPSDR SDRAM, NOR/NAND
memories
– XSPI 8-bit configuration with cypher engine
– XSPI 16-bit configuration with cypher engine (only on STM32N657X0H3Q,
STM32N657L0H3Q, and STM32N657B0H3Q)

3.2 SRAM configuration

AHBSRAM1/2, AXISRAM1 to 6, BKPSRAM, FLEXRAM, and VENCRAM, with the following
features:
• Error code correction (ECC):
– Single-error detection and correction with interrupt generation
– Double-error detection with interrupt generation
– Status with failing address
• Hardware erase: on reset or dedicated event, the RAM content is automatically erased
(written as 0)
• Software erase: the software can trigger an SRAM erase through RAMCFG registers

3.3 AXI cache configuration

The AXI cache (CACHEAXI) is introduced (only on STM32N6x7xx devices) on the AXI
interconnect driven by the NPU (neural network) peripheral, to improve the performance of
data traffic, by caching the NPU data accessed in the external memories.
When configured as an SRAM, the CACHEAXI can be accessed by the NPU, and also by
the Cortex-M55 processor or by any AXI controller peripheral.

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Main features:
• Bus interface
• Optionally, the CACHEAXI can be configured to behave as an SRAM
• Cache access
• Replacement and refill
• System compartments support:
• TrustZone security support
• Maintenance operations
• Performance counters
• Error management

3.4 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domain (VCORE = VDDCORE)
– VDD domain (VRET)
– Backup domain (VSW, VBAT)
– Analog domain (VDDA18ADC)
• System supply voltage regulation
– Switched-mode power supply power-efficient voltage down-converter (SMPS
step-down converter)
– 0.8 V backup regulator (external to the PWR)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– VDDA18PMU monitor
– PVD monitor
– PVM monitor (VDDIO2, VDDIO3, VDDIO4, VDDIO5, VDD33USB, VDDA18ADC)
– VBAT thresholds
– Temperature thresholds
– VDDCORE monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes

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Figure 1. Power supply overview

32-bit
AHB RCC
Register interface
bus

PDR_ON POR/PDR pwr_por_rstn

BOR pwr_bor_rstn
VDD

VBAT Backup domain Temperature

V08CAP thresholds
pwr_wkup
VBAT
VDDA18AON pwrds
System supply thresholds
VDDA18PMU VDDCORE
VDDSMPS monitor
SMPS
VLXSMPS step-down
converter
VFBSMPS Power
Voltage management
VSSSMPS scaling
VDDCORE

VSS EXTI
PWR_ON PWR control

exti_wkup
VDDA18ADC
VSSA Analog domain
VREF+
VREF-

WKUP[4:1] Wake-up Wake-up event

VDDIO2
VDDIO3
pwr_pvd_wkup Wake-up event
VDDIO4 PVD and PVM
VDDIO5 pwr_pvm_x_wkup[5:0] Wake-up event

VDD33USB

MSv70447V2

3.4.1 Voltage scaling

The VCORE domain is supplied from a single voltage regulator that supports voltage scaling
with the following features:
• Run mode voltage scaling
– VOS low
– VOS high
• Stop mode voltage scaling
– SVOS low
– SVOS high

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3.4.2 Power supply schemes

3.4.3 Core domain

The core domain supply can be provided by the SMPS step-down converter, or by an
external supply (VDDCORE). VCORE supplies all the digital circuitries, except for the backup
domain, and the retention domain in Standby mode. When a system reset occurs, the
SMPS step-down converter is enabled to deliver 0.81 V, hence the system can start up in
any supply configuration.
The system startup sequence from power-on in different supply configurations is controlled
through power management.

3.4.4 SMPS usage

The devices embed an SMPS to provide the VCORE supply. The SMPS generates this
voltage on VLXSMPS, with a total external capacitor of 60 (4x 15) μF (typical). The SMPS
requires an external coil of 0.9 μH (typical).
Two configurations exist (see Figure 2), namely SMPS step-down converter supply on and
off (bypass mode). In the latter the step-down converter supply is disabled.

Figure 2. SMPS configurations

VDDA18PMU VDDA18PMU

VDD18 VDDSMPS VDDSMPS

VLXSMPS SMPS VLXSMPS SMPS

(on) (off)
VFBSMPS VFBSMPS

VSSSMPS VSSSMPS

VDDCORE
VCORE External supply VDDCORE
VCORE

VSS VSS

SMPS supply External supply (bypass)

MSv70449V2

3.4.5 Backup domain

To retain the content of the backup domain (RTC, backup registers, and backup RAM) when
VDD is turned off, the VBAT pin can be connected to an optional voltage supplied from a
battery or another source. The switching to VBAT is controlled by the power-down reset
(PDR) embedded in the block that monitors the VDD supply.

3.4.6 Analog supply

The analog supply domain is powered by dedicated VDDA18ADC and VSSA pins, which
allow the supply to be filtered and shielded from noise on the PCB, thus improving ADC
conversion accuracy.
The analog supply voltage input is available on a separate VDDA18ADC pin, and an
isolated supply ground connection is provided on VSSA pin.

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3.4.7 System supply startup

The system startup sequence from power-on has different supply configurations (see
Figure 3 and Figure 4), according to the usage of the SMPS.

Figure 3. Device startup with VCORE supplied directly from an external SMPS
VDD

POR threshold

VDDA18AON

POR threshold

pwr_por_rstn

PWR_ON

Vddcore_ok threshold
VDDCORE

tempo

Vcore_ok

Power Wait Hardware system

Operating mode down
Reset
oscillator init
Run

ck_sys

Supply configuration Default configuration Bypass mode

SDEN X
(1) (2) (3) (4)
MSv70451V2

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Figure 4. Device startup with VCORE supplied directly from the internal SMPS

VDD
POR threshold

VDDA18AON
POR threshold

pwr_por_rstn

PWR_ON

VDDA18PMU / vdda18pmu_ok threshold

VDDSMPS

Vdda18pmu_ok
VOS low
VFBSMPS

VOS low vddcore_ok threshold

VCORE
tempo

Vcore_ok

Operating mode Power Wait

Reset Hardware system init Run
down oscillator

ck_sys

Direct
Supply configuration Default configuration SD
supply

SDEN X
(1) (2) (3) (4) (5)
MSv70450V3

3.4.8 Operation modes

Several system operating modes are available to tune the system according to the required
performance. The user can select the operating mode that gives the best compromise
between power consumption, start-up time, and available wake-up sources.

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Table 6. Operating mode summary

System oscillator

ON (SVOS low) ON (SVOS high) ON (VOS low/high) Voltage regulator

Peripheral clock
System clock

CPU clock

PWR_ON
System Entry Wake-up

ON
Run - -

ON(1)
ON

ON
WFI or return from ISR or
Sleep
WFE(2)

ON/OFF(3)
SVOS + SLEEPDEEP +

ON/OFF(5)
Stop 1
WFI or return from ISR,
SVOS See Table 7
WFE, or wake-up source
high
cleared(4)

OFF

OFF
Stop SLEEPDEEP + WFI or

OFF

OFF
SVOS return from ISR, WFE, or
low wake-up source cleared(3)

PDDS + SLEEPDEEP + WKUP pins rising or falling edge, RTC

WFI or return from ISR, alarm (A or B), RTC wake-up event, RTC
OFF

OFF

OFF

OFF

OFF
Standby 0(6)
WFE, or wake-up source tamper events, RTC timestamp event,
cleared(3) external reset in NRST pin, IWDG reset
1. The clock is gated in the core in Sleep mode.
2. WFI = wait for interrupt, ISR = interrupt service routine, WFE = wait for event.
3. The CPU subsystem peripherals with a PERxLPEN bit operate accordingly.
4. When the CPU is in Stop mode, the last EXTI wake-up source must be cleared by software.
5. When HSI or MSI is used, the state is controlled by HSISTOPEN and MSISTOPEN, otherwise the system oscillator is off.
6. A guaranteed minimum PWR_ON pulse low time can be defined by POPL bits in PWR_CR1.

Table 7. Functionalities depending on system operating mode

Stop mode Stop mode
Standby mode
SVOS high SVOS low
Run VBAT
Peripheral(1)
mode mode
Wake-up Wake-up Wake-up
- - -
capability capability capability

CPU Y R - R - - - -
NPU(2) O O - R - - - -
Debug O O O R - - - -
ROM Y R - R - - - -

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Table 7. Functionalities depending on system operating mode (continued)

Stop mode Stop mode
Standby mode
SVOS high SVOS low
(1) Run VBAT
Peripheral
mode mode
Wake-up Wake-up Wake-up
- - -
capability capability capability

RAMCFG O R - R - - - -
I-TCM O R - R - R - -
I-TCM FLEXMEM O R - R - R - -
D-TCM O R - R - R - -
(3)
AXISRAM1 O R - R - R - -
AXISRAMx (x = 2, 3, 4, 5, 6) O O - R - - - -
AXISRAM7(4) O O - R - - - -
I-TCM FLEXMEM extension O O - R - R(5) - -
D-TCM FLEXMEM extension O O - R - - - -
(2)
CACHEAXI1 O O - R - - - -
VENCRAM O O - R - - - -
GPU RAM O O - R - - - -
BKPSRAM O R - R - O - O
AHBSRAMx (x = 1, 2) O O - R - - - -
XSPIx (x = 1, 2, 3) O R - R - - - -
XSPIM O R - R - - - -
MCEx (x = 1, 2, 3, 4) O R - R - - - -
FMC O R - R - - - -
Backup registers Y R - R - R - R
Brownout reset (BOR) Y Y Y Y Y Y Y -
Programmable voltage detector (PVD) O O O O O - - -
Peripheral voltage monitor (PVM) O O O O O - - -
VBATH/VBATL monitoring O O O O O O O O
TEMPH/TEMPL monitoring O O O O O O O O
GPDMA1 O R - R - - - -
HPDMA1 O R - R - - - -
High speed internal (HSI) O O - - - - - -
High speed external (HSE) O - - - - - - -
Low speed internal (LSI) O O - O - O - -
Low speed external (LSE) O O - O - O - O
Multi speed internal (MSI) O O - - - - - -
HSE CSS (clock security system) O - - - - - - -

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Table 7. Functionalities depending on system operating mode (continued)

Stop mode Stop mode
Standby mode
SVOS high SVOS low
(1) Run VBAT
Peripheral
mode mode
Wake-up Wake-up Wake-up
- - -
capability capability capability

LSE CSS O O O O O O O O
RTC/auto wake-up O O O O O O O O
TAMP, number of tamper pins 7 7 O 4 O 4 O 4
OTG1 HS O R O R - - - -
OTG2 HS O R O R - - - -
UCPD1 O R O R - - - -
SDMMCx (x = 1, 2) O R - R - - - -
FDCAN O R - R - - - -
MDIOS O R O R - - - -
ETH1 O R O R - - - -
LPUART1 O O O R - - - -
U(S)ARTx (x = 1 to 10) O O O R - - - -
I2Cx (x = 1, 2, 3, 4) O O O R - - - -
I3Cx (x = 1, 2) O O O R - - - -
SPIx (x = 1 to 6) O O O R - - - -
SAIx (x = 1, 2) O R - R - - - -
ADF1 O O O R - - - -
MDF1 O O O R - - - -
DCMI O R - R - - - -
PSSI O R - R - - - -
DCMIPP O R - R - - - -
GPU O R - R - - - -
DMA2D O R - R - - - -
GFXTIM O R - R - - - -
GFXMMU O R - R - - - -
JPEG O R - R - - - -
VENC O R - R - - - -
LTDC O R - R - - - -
ADCx (x = 1, 2) O R - R - - - -
VREFBUF O R - R - - - -
DTS O R O R - - - -
TIMx (x = 1 to 18) O R - R - - - -

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Table 7. Functionalities depending on system operating mode (continued)

Stop mode Stop mode
Standby mode
SVOS high SVOS low
(1) Run VBAT
Peripheral
mode mode
Wake-up Wake-up Wake-up
- - -
capability capability capability

LPTIMx (x = 1 to 5) O O O R - - - -
IWDG O O O O O O O -
WWDG O R - R - - - -
RNG O R - R - - - -
SAES O R - R - - - -
CRYP O R - R - - - -
HASH O R - R - - - -
CRC O R - R - - - -
O O
GPIOs O O O O O -
4 pins 4 pins
1. Legend: Y = Yes (enable). O = Optional (disable by default. Can be enabled by software). R = data/state retained.
-= not available.
2. STM32N6x7 devices only.
3. Only the first 80 Kbytes can optionally be retained (see the dedicated section of RM0486 for details).
4. STM32N6x5 devices only.
5. Only the first 64 Kbytes can optionally be retained (see the dedicated section of RM0486 for details).

3.4.9 Low-power modes

Several low-power modes are available to save power when the CPU does not need to
execute code (when waiting for an external event). The user must select the mode that
gives the best compromise between low-power consumption, short start-up time, and
available wake-up sources:
• Low-power modes
– Sleep (CPU clock stopped and still in Run mode)
– Stop (system clock stopped)
– Standby (system powered down)
• Reset mode
– To improve the consumption under reset, the I/O state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset
pull-up is deactivated when the reset source is internal.

3.5 Convolution neural network accelerator (NPU)

The neural processing unit (NPU) core (available only on STM32N6x7xx devices) is the
design time parametric and runtime reconfigurable neural network inference engine. It can
accelerate a wide range of neural network architectures in hardware.
The NPU is considered as an accelerator subsystem with several specialized hardware
accelerators supporting various inference kernels connected via a reconfigurable data flow

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fabric. The specific instantiation can vary from a low-end version for low-cost
microcontrollers designed with two convolution accelerators (CA).
The NPU subsystem connects to the host system and the shared system memory.
The host configures the NPU subsystem through an AHB/AXI lite target port, connected to
one of the ports of the system bus matrix/interconnect. The two controller ports of NPU are
64-bit wide controller AXI-4 interfaces that connect to the system bus matrix/Interconnect.
The system memory is shared between the host subsystem and the NPU subsystem.
The used memory is configurable by software, it depends upon the complexity and target
performance of the selected neural network workload.

3.6 Boot modes

The BootROM is the first code executed after any system reset. The boot mode is
determined by BOOT0 and BOOT1 pins, one OTP word (flash source selection), and one
TAMP backup register.
• BOOT0 is a dedicated pin latched upon reset release
• BOOT1 is a non-dedicated boot pin. The BOOT1 value comes from BOOT1 pin
(default pin), or any other pin defined by system
Depending the configuration of these signals, there are two boot modes, namely serial boot,
and external flash boot.

3.6.1 External flash boot

The firmware is loaded from an external flash memory. The BootROM code supports
following types of boot memory devices:
• XSPI serial NOR (in SPI mode, single)
• XSPI HyperFlash™ (8-bit)
• e.MMC™ SDMMC1 or e.MMC™ SDMMC2 (up to JEDEC v5.1)
• SD-Card SDMMC1 (up to SD standard v6.0)

3.6.2 Serial boot

The image is loaded from a serial interface. The BootROM code supports following types of
serial boot interfaces:
• USB boot: USB 2.0 OTG HS
• UART boot

3.6.3 Development boot

If BOOT1 is selected, the BootROM code finishes in an endless loop after having reopened
debug in a secure way.
This boot mode is available only when the device is in development.

Secure installation
The ROM code is the root-of-trust of secure firmware installation.

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3.7 General-purpose inputs/outputs (GPIOs)

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR), a 16-bit reset register (GPIOx_BRR), and a 32-bit set/reset
register (GPIOx_BSRR).
In addition, all GPIOs have a 32-bit locking register (GPIOx_LCKR), two couples of 32-bit
advanced configuration registers (GPIOx_DELAYRL/H, GPIOx_ADVCFGRL/H), and two
32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Access to each general-purpose I/O configuration bit can be restricted to secure-only and/or
privileged-only.
The main features are:
• Multiple choice of configurations per I/O port:
– Input configuration in floating, pull-up/down, or analog state
– Analog configuration (output buffer and Schmitt trigger input disabled)
– Output configuration, or alternate function configuration, in push-pull or open drain
state, with pull-up or pull-down activated
• Data present on the I/O pin sampled to the input data register GPIOx_IDR (input
configuration) or to the peripheral (alternate function configuration)
• Output buffer on the I/O pin driven by the output data register GPIOx_ODR (output
configuration) or by the peripheral (alternate function configuration)
• I/O data output atomic read/modify through GPIOx_ BSRR and GPIOx_BRR
• Speed selection for each I/O (GPIOx_OSPEEDR)
• Lock mechanism (GPIOx_LCKR) to selectively freeze the I/O port configurations
• Highly-flexible pin multiplexing, enabling the use of I/O pins as GPIOs, or as one of
several possible peripheral functions
• Programmable delay to the input or the output path (GPIOx_DELAYR)
• Double edge selection, clock inversion, and optional retime (GPIOx_ADVCFGR)
• Possibility to restrict each I/O control to secure-only and/or privileged-only

3.8 System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The SYSCFG manages:
– Cortex-M55 internal settings (such as TCM, CACHE, or vectors)
– Iterconnect, security, and memory settings
– I/O compensation cells

3.9 General purpose direct memory access controller (GPDMA)

The GPDMA controller is a bus controller and system peripheral, used to perform
programmable data transfers between memory-mapped peripherals and/or memories via
linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB controller

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• Memory-mapped data transfers from a source to a destination:

– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Transfer arbitration based on a 4-grade programmed priority at channel level:
– One high priority traffic class, for time-sensitive channels (queue 3)
– Three low priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, half
transfer complete, data transfer error, user setting error, link transfer error, completed
suspension, and trigger overrun
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 16 concurrent GPDMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel GPDMA transfers chaining via programmable linked-list into
memory, supporting two execution modes: run-to-completion and link step mode.
– Intra-channel and inter-channel GPDMA transfers chaining via programmable
GPDMA input triggers connection to GPDMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive burst
transfers
– 2D source and destination addressing: programmable signed address offsets
between successive burst transfers (non-contiguous addressing within a block,
combined with programmable signed address offsets between successive blocks,
at a second 2D/repeated block level, for a reduced set of channels
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable GPDMA request and trigger selection
– Programmable GPDMA half transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the GPDMA linked-list control registers
– Channel abort and restart
• Debug:
– Channel suspend and resume support
– Channel status reporting, including FIFO level, and event flags
• TrustZone support:

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– Support for secure and non-secure GPDMA transfers, independently at a first

channel level, and independently at a source/destination and link sublevels.
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels.
– TrustZone-aware AHB target port, protecting any GPDMA secure resource
(register, register field) from a non-secure access.
• Privileged/unprivileged support:
– Support for privileged and unprivileged GPDMA transfers, independently at a
channel level
– Privileged-aware AHB target port

Table 8. GPDMA1 channel implementation

Hardware parameters
Channel
Features Comment
x dma_fifo_ dma_
size[x] addressing[x]

– 8 bytes, 2 words FIFO

Typically allocated for GPDMA transfers
0 to 11 2 0 – Fixed/contiguously between an APB/AHB peripheral and SRAM.
incremented addressing
Can be used for GPDMA transfers, between
– 32 bytes, 8 words FIFO
12 to 15 4 1 a demanding AHB peripheral and SRAM, or
– 2D addressing for transfers from/to external memories.

3.10 High performance direct memory access controller (HPDMA)

The HPDMA is used to perform programmable data transfers between memory-mapped
peripherals, and/or memories via linked-lists, upon the control of an off-loaded CPU.
Main features:
• Single bidirectional AXI controller and single bidirectional AHB controller
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Transfer arbitration based on a 4-grade programmed priority at channel level:
– One high priority traffic class, for time-sensitive channels (queue 3)
– Three low priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events:
– Transfer complete, half transfer complete
– Data transfer error, user setting error, link transfer error
– Completed suspension
– Trigger overrun
• Per channel interrupt generation, with separately programmed interrupt enable per
event

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• 16 concurrent HPDMA channels:

– Per channel FIFO for queuing source and destination transfers
– Intra-channel HPDMA transfers chaining via programmable linked-list into
memory, supporting two execution modes: run-to-completion and link step mode.
– Intra-channel and inter-channel HPDMA transfers chaining via programmable
HPDMA input triggers connection to HPDMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing, or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing either fixed or contiguously incremented
addressing, programmed at block level, between successive burst transfers
– 2D source and destination addressing programmable signed address offsets
between successive burst transfers (non-contiguous addressing within a block,
combined with programmable signed address offsets between successive blocks,
at a second 2D/repeated block level, for a reduced set of channels
– Support for scatter-gather (multi-buffer transfers), data interleaving and
de-interleaving via 2D addressing
– Selection of programmable HPDMA request and trigger
– Generation of programmable HPDMA half-transfer and transfer-complete event
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the HPDMA linked-list control registers
– Channel abort and restart
• Debug:
– Channel suspend and resume support
– Channel status reporting, including FIFO level, and event flags
• TrustZone support:
– Support for secure and non-secure HPDMA transfers, independently at a first
channel level, and independently at a source/destination and link sublevels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB target port, protecting any HPDMA secure resource
(register, bitfield) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged HPDMA transfers, independently at
channel level
– Privileged-aware AHB target port
• Channel isolation support:
– Support for compartmented DMA transfers, independently at channel level, via
compartment IDs (named CIDs)
– CID-aware interrupts reporting

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– CID-aware AHB target port, with integrated semaphores for a concurrent control
from any of the CPUs

Table 9. Implementation of HPDMA1 channels

Hardware parameters
Channel x Features
dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 11) is implemented with:

– a FIFO of 16 bytes, 4 words, 2 double-words
x = 0 to 11 3 0 – fixed/contiguously incremented addressing
These channels can be used for HPDMA transfers between an APB or
AHB peripheral, an AHB/AXI SRAM, or CPU TCM.
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 64 bytes, 8 double-words
x = 12 to 15 5 1 – 2D addressing
These channels can be also used for HPDMA transfers, including AXI
external memories.

Table 10. HPDMA1 in low-power modes

Feature Low-power modes

Wake-up HPDMA1 in Sleep mode

3.11 Chrom-ART Accelerator controller (DMA2D)

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
• Fill a part or the whole of a destination image with a specific color
• Copy a part or the whole of a source image into a part or the whole of a destination
image
• Copy a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blend a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format
All the classical color coding schemes are supported, from 4- up to 32-bit per pixel with
indexed or direct color mode, including block based YCbCr to handle JPEG decoder output.
The DMA2D has its own dedicated memories for CLUTs (color look-up tables).

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The main DMA2D features are:

• Single AXI controller bus architecture
• AHB target programming interface supporting 8-,16-,32-bit accesses (except for CLUT
accesses which are 32-bit)
• User-programmable working area size
• User-programmable offset for sources and destination areas expressed in pixels or
bytes
• User-programmable sources and destination addresses on the whole memory space
• Up to two sources with blending operation
• Alpha value that can be modified (source value, fixed value, or modulated value)
• User programmable source and destination color format
• Up to 12 color formats supported, from 4- up to 32-bit per pixel with indirect or direct
color coding
• Block based (8x8) YCbCr support with 4:4:4, 4:2:2 and 4:2:0 chroma sub-sampling
factors
• Two internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AXI bandwidth
• Operating modes:
– Register-to-memory
– Memory-to-memory
– Memory-to-memory with pixel format conversion
– Memory-to-memory with pixel format conversion and blending
– Memory-to memory with pixel format conversion, blending, and fixed color
foreground
– Memory-to memory with pixel format conversion, blending, and fixed color
background
• Area filling with a fixed color
• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion

3.12 Chrom-GRC (GFXMMU)

The Chrom-GRC (GFXMMU) is a graphical oriented memory management unit aimed to
optimize memory usage according to the display shape. Main features are:
• Fully programmable display shape to physically store only the visible pixel

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• Up to four virtual buffers

• Each virtual buffer has 3072 or 4096 bytes per line and 1024 lines
• Each virtual buffer can be physically mapped to any system memory
• Packing and unpacking operation to store 32-bit pixel data into 24-bit packed
• Interrupt in case of buffer overflow (one per buffer)
• Interrupt in case of memory transfer error

3.13 Graphic timer (GFXTIM)

The graphic timer (GFXTIM) is a graphic oriented timer for smart management of graphical
events for frame or line counting. Its main features are:
• Integrated frame and line clock generation
• One absolute frame counter with one compare channel
• Two auto-reload relative frame counters
• One line timer with two compare channels
• External tearing-effect line management and synchronization
• Four programmable event generators with external trigger generation
• One watchdog counter

3.14 Interrupts and events

3.14.1 Nested vectored interrupt controller (NVIC)

The NVIC includes the following features:
• Up to 196 maskable interrupt channels (not including the Cortex-M55 interrupt lines)
• 16 programmable priority levels (using four bits of interrupt priority)
• Low latency exception and interrupt handling
• Power management control
• Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. All interrupts,
including the core exceptions, are managed by the NVIC.

3.14.2 Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event
inputs. It provides wake-up requests to the power control, and generates interrupt requests
to the CPU NVIC and events to the CPU event input. For the CPU an additional event
generation block (EVG) is needed to generate the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes, and the
CPU to be woken up from CStop and CStandby modes.
The interrupt request and event request generation can also be used in Run modes.

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The EXTI main features are the following:

• 73 input events supported
• Most event inputs allow to wake up the system, some can be used only to generate a
CPU wake-up
• Events without an associated wake-up flag in the peripheral have a flag in the EXTI,
and generate a combined secure/non-secure interrupt to the CPUs from the EXTI
• Events can be used to generate a CPU wake-up event
• The asynchronous event inputs are classified in two groups:
– Configurable events (signals from I/Os or peripherals able to generate a pulse),
with the following features:
> Selectable active trigger edge
> Interrupt pending status register bits independent for the rising and falling
edge
> Individual interrupt and event generation mask, used to condition the CPU
wake-up, interrupt, and event generation
> Individual interrupt lines per CPU
> Software trigger possibility
– Direct events (interrupt and wake-up sources from peripherals with an associated
flag, which must be cleared in the peripheral), with the following features:
> Fixed rising edge active trigger
> No interrupt pending status register bit in the EXTI (the interrupt pending
status flag is provided by the peripheral generating the event)
> No interrupt pending status register bit in the EXTI (the interrupt pending
status flag is provided by the peripheral generating the event)
> No software trigger possibility
• Secure events
– The access to control and configuration bits of secure input events can be made
secure and or privileged
• EXTI I/O port selection

3.15 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

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Main features are:

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
(x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x +1)
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• • Input buffer to avoid bus stall during calculation
• CRC computation done in four AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility options on I/O data
• Accessed through AHB target peripheral by 32-bit words only, with the exception of
CRC_DR register, which can be accessed by words, right-aligned half-words, and
right-aligned bytes

3.16 Flexible memory controller (FMC)

The FMC includes three memory controllers, namely the NOR/PSRAM, the NAND, and the
synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller. Its main features are:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (four memory subregions)
– Ferroelectric RAM (FRAM, FeRAM)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• Burst mode support for faster access to synchronous devices such as NOR flash
memory, PSRAM and SDRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16- or 32-bit wide data bus
• Independent chip-select control for each memory region
• Independent configuration for each memory region
• Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM
devices
• External asynchronous wait control
At startup the FMC pins must be configured by the user application. The FMC input/output
pins not used by the application can be used for other purposes.

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3.17 XSPI interface

3.17.1 Extended-SPI interface (XSPI)

The XSPI supports most external serial memories such as serial PSRAMs, serial NAND and
serial NOR flash memories, HyperRAM™ and HyperFlash™ memories, with the following
functional modes:
• Indirect: all the operations are performed using the XSPI registers to preset
commands, addresses, data and transfer parameters.
• Automatic status-polling (available only in regular command protocol): the external
memory status register is periodically read and an interrupt can be generated in case of
flag setting.
• Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory, supporting both read and write operations.
The XSPI supports the following protocols with associated frame formats:
• regular-command frame format with the command, address, alternate byte, dummy
cycles and data phase
• HyperBus™ frame format
Main features:
• Functional modes: indirect, automatic status-polling, and memory-mapped
• Read and write support in memory-mapped mode
• Support for single, dual, quad, and octal communication
• Dual-memory configuration, where 8 bits can be sent/received simultaneously by
accessing two quad or octal memories in parallel
• XSPI mode accessing a single 16-bit memory
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• Support wrapped-type access to memory in read direction
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA protocol support
• DMA channel for indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
• AXI acceptance 2: acceptance is offered based on a read transaction followed by a
second write or read request (acknowledged on the bus), while the first one is being
processed
• Dual chip select support (NCS1 and NCS2)
• Extended external memory support: if two same size external memories (extmem1 and
extmem2) are connected to the same I/O port, contiguously in the memory map and
driven by a single XSPI. This XSPI automatically switches CS to extmem1 or extmem2,
according to the address on interconnect side.

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3.17.2 XSPI I/O manager (XSPIM)

The XSPI I/O manager is a low level interface, enabling efficient XSPI pin assignment with a
full I/O matrix (before alternate function map), and multiplex of single/dual/quad/octal/16-bit
SPI interfaces over the same bus.
Main features:
• Supports up to two single/dual/quad/octal/16-bit SPI interfaces
• Supports up to two ports for pin assignment
• Supports high-speed interfaces
• Manages up to three XSPIs

Figure 5. XSPIM block diagram

XSPI I/O manager

AHB AHB interface Control register High

speed
interface
Static
muxing XSPIM_P1_CLK
bus signals XSPIM_P1_NCLK

Port 1
PHY XSPIM_P1_DQS0,1
XSPI1 ACK1 XSPIM_P1_NCS1,2
XSPIM_P1_IO[15:0]
REQ1
I/O matrix
Arbiter
Dynamic
XSPIM_P2_CLK
muxing
REQ2 XSPIM_P2_NCLK
Port 2

PHY XSPIM_P2_DQS0
XSPI2
ACK2 XSPIM_P2_NCS1,2
XSPIM_P2_IO[7:0]

bus signals

REQ3
XSPI3
ACK3

bus signals
MS55949V2

3.18 Secure digital input/output MultiMediaCard interface

(SDMMC)
The SD/SDIO, embedded MultiMediaCard (eMMC™) host interface (SDMMC) provides an
interface between the AHB bus and SD memory cards, SDIO cards and eMMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
Association website at www.jedec.org, published by the MMCA technical committee. The
SD memory card and SD I/O card system specifications are available through the SD
Association website at www.sdcard.org.

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Main SDMMC features:

• Compliance with Embedded MultiMediaCard System Specification Version 5.1. Card
support for three different databus modes: 1-bit (default), 4-bit and 8-bit. HS200
SDMMC_CK speed limited to maximum allowed I/O speed, HS400 is not supported.
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specification version 6.0 (SDR104 SDMMC_CK
speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not
supported).
• Full compliance with SDIO card specification version 4.0. Card support for 1-bit
(default) and 4-bit databus modes. SDR104 SDMMC_CK speed limited to maximum
allowed I/O speed, SPI mode and UHS-II mode not supported.
• Data transfer up to 208 Mbyte/s for the 8-bit mode, depending upon maximum allowed
I/O speed.
• Data and command output enable signals to control external bidirectional drivers.
• IDMA linked list support.
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/eMMC card at any one
time, and a stack of eMMCs.

3.19 SDMMC delay block (DLYB)

This block is used to generate two output clocks dephased from two input clocks. The phase
of each output clock must be programmed by the user application. The output clocks are
then used to clock the data transmitted/received by another peripheral such as an SDMMC.
The delay block has the following features:
• Frequency for Lock mode in the 50 to 208 MHz range
• 32 phases (delay taps)
• Bypass mode for operation below 50 MHz

3.20 Analog-to-digital converters (ADC)

The devices embed two ADCs (ADC1, ADC2) tightly coupled, which can operate in Dual
mode (ADC1 is controller).
Each ADC consists of one 12-bit successive approximation analog-to-digital converter, and
has up to 20 multiplexed channels. The conversions can be performed in Single,
Continuous, Scan, or Discontinuous mode. The result is stored in a left- or right-aligned
(default configuration) 32-bit data register. The ADCs are mapped on the AHB bus for fast
data handling.
The analog watchdog features allow the application to detect if the input voltage goes
outside the user-defined high or low thresholds.
A built-in hardware oversampler improves analog performance, while off-loading the related
computational burden from the CPU.
An efficient low-power mode is implemented for very low consumption at low frequencies.

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The ADCs main features are:

– 12-, 10-, 8- or 6-bit configurable resolution
– Conversion time independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Management of single-ended or differential inputs (programmable per channels)
– AHB target bus interface to allow fast data handling
– Offset calibration support
– Channel-wise programmable sampling time
– Flexible sampling time control
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Data alignment with in-built data coherency
– Data can be managed by DMA for regular channel conversions
– Data can be routed to MDF for post processing
– Four dedicated data registers for the injected channels
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Allows slow bus frequency application while keeping optimum ADC performance
– Provides automatic control to avoid ADC overrun in low AHB bus clock frequency
application (Auto-delay mode)
• Oversampler
– 32-bit data register
– Ratio adjustable from 2 to 1024
– Programmable data right shift
• Data preconditioning
– Gain compensation
– Offset compensation
• Analog input channels
– External analog inputs (per ADC): up to 17 GPIO pads
– One channel for the internal reference voltage (VREFINT)
– One channel for monitoring the external VBAT power supply pin
– One channel connected to the analog positive reference voltage VREF+
– One channel for monitoring VDDCORE internal voltage
• Start-of-conversion can be initiated:
– By software for both regular and injected conversions
– By hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
• Conversion modes
– Each ADC can convert a single channel or can scan a sequence of channels
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode

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• Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular
or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or
three or overrun events
• Three analog watchdogs per ADC
• Input range: VSSA ≤ VIN ≤ VREF+

3.21 Digital temperature sensor (DTS)

The DTS is a high precision low-power junction temperature sensor (TS), composed of a
configurable controller plus two embedded temperature sensors (TS0 and TS1). The
controller features a generic interface that enables the DTS to be accessed in read and
write modes, through the APB bus.
The main features are:
• For each temperature sensor, two programmable (rise or fall) hardware alarms
incorporating hysteresis and status registers recording the minimum and maximum
data values received
• A power-up timer with IRQ to support manual operation

3.22 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer supporting 1.21 and 1.5 V, which can be
used as reference for ADCs and for external components through the VREF+ pin.

Figure 6. VREFBUF block diagram

VREFINT +
VREF+

VSSA
MSv64430V2

3.23 Multi-function digital filter (MDF)

The multi-function digital filter (MDF) is a high performance module dedicated to the
connection of external sigma-delta (Σ∆) modulators, mainly for audio capture signals, motor
control, and metering.
The MDF features six digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible
digital processing options to offer up to 24-bit final resolution.
The DFLTx of the MDF also include the filters of the audio digital filter (ADF).

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The MDF can receive, via its serial interfaces, streams coming from various digital sensors.
It supports SPI, Manchester coded 1-wire, and PDM interface standards.
Main features:
• AHB interface
• Six serial digital inputs
– configurable SPI interface to connect digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
• Two common clocks input/output for Σ∆ modulators
• Flexible matrix (BSMX) for connection between filters and digital inputs
• Two inputs to connect the internal ADCs
• Six flexible digital filter paths, including:
– A configurable CIC filter:
> Can be split into two CIC filters: high-resolution filter and out-off limit detector
> Can be configured in Sinc4 and Sinc5 filters
> Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– An offset error cancellation
– Gain control
– Saturation blocks
– An out-off limit detector
• Short-circuit detector
• Clock absence detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Break generation on out-of limit or short-circuit detector events
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services

3.24 Audio digital filter (ADF)

The audio digital filter (ADF) is a high performance module dedicated to the connection of
external sigma-delta (Σ∆) modulators, mainly for audio capture signals and metering.
The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with
flexible digital processing options in order to offer up to 24-bit final resolution.
The ADF serial interface supports SPI, Manchester coded 1-wire, and PDM interface
standards.

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Main features:
• AHB interface
• One serial digital input:
– Configurable SPI interface to connect various digital sensors
– Configurable Manchester coded interface support
– Compatible with PDM interface to support digital microphones
• Two common clocks input/output for Σ∆ modulators
• One flexible digital filter path including:
– An MCIC filter configurable in Sinc4 or Sinc5 filter with adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– Gain control
– Saturation blocks
• • Clock absence detector
• • Sound activity detector
• • 24-bit signed output data resolution
• • Continuous or single conversion
• • Possibility to delay the selected bitstream
• • One trigger input
• • Autonomous functionality in Stop modes
• • DMA can be used to read the conversion data
• • Interrupts services

3.25 Camera subsystem

The camera subsystem is built around a double path:
• a low resolution path, with the DCMI and a low-frequency parallel interface, supporting
sensors up to 24 Mpixel/s
• a high resolution path, with the DCMIPP and a high frequency parallel interface or
serial CSI-2 interface (RGB or rawBayer), targeting sensors up to 5 Mpixels at 30 fps
For the connection of a camera sensor, it is recommended to use the DCMIPP. The DCMI is
recommended only in two noticeable cases:
• to get backward compatibility with former platforms that embed also the DCMI
• to input the pixels from a second camera sensor
Note: The DCMIPP inputs pixels from one sensor via the CSI-2 interface, while the DCMI gets
pixels from the second sensor via the parallel interface.
The DCMI path offers the following summarized maximum features:
• Target sensor: 24 Mpixel/s 16 bpp (limited by the DMA)
• Parallel input: 80 MHz on 14-bit input capability
• Central DMA to extract and dump its pixels
• Software extraction of its pixel data

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The DCMIPP path offers the following summarized maximum features:

• Target sensors: 5 Mpixel at 30 fps max
• Parallel input: 120 MHz on 16-bit input capability
• Serial input: CSI-2 at 2.5 Gbps/lane on two data lanes
• ISP (image signal processor): demosaicing, exposure, white-balance, contrast,
bad-pixel
• Application pipes: two pipes with crop, downsize, gamma, YUV conversion, YUV420
Some over-target use cases are possible, but with specific constraints:
• sensors with resolution above 5 Mpixels
• sensors with pixel rate above 150 Mpixel/s
• double sensors in parallel

3.25.1 Digital camera interface (DCMI)

The digital camera is a synchronous parallel interface able to receive a high speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
DCMI main features are:
• 8-, 10-, 12- or 14-bit parallel interface at 80 MHz (no I/O ReTime)
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw Bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG (any default/byte data)

3.25.2 Digital camera interface pixel pipeline (DCMIPP)

The DCMIPP path groups the DCMIPP pixel pipeline block, its included parallel interface,
and the abutted CSI-2-Host and PHY.
The parallel interface has the following features:
• Input rate: 120 MHz up to 16-bit capability (with I/O ReTime)
• Pixel format: RGB565, 888, YUV422, RawBayer/Mono 8/10/12/14
• Synchronization: embedded versus external line and frame synchronization
The CSI-2 serial interface has the following features:
• Standard: MIPI CSI2 v1.3
• Input rate: two data lanes at 2.5 Gbps/lane
• Pixel rate: up to 200 Mpixel/s for RGB888, up to 333 Mpixel/s for rawBayer 10
• Pixel format: any MIPI CSI2 v1.3 (RGB565, 888, YUV422, rawBayer)
• Miscellaneous: interlaced video, interleaved packets, virtual channels

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3.26 CSI-2 Host (CSI)

The camera serial interface 2 (CSI-2) is a part of a group of communication protocols
defined by the MIPI® Alliance. The MIPI CSI-2 Host controller is a digital core that
implements all protocol functions defined in the MIPI CSI-2 specification. It provides an
interface between the system and the MIPI D-PHY, allowing communication with a CSI-2
compliant camera.
Standard and references:
• MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2) v1.3 - 29 May 2014
• MIPI Alliance Specification for D-PHY v1.2 - 01 August 2014
Main features:
• Compliant with MIPI Alliance standard
• Interface with MIPI D-PHY
• Up to two D-PHY data lanes supported
– Up to 2.5 Gbit/s per lane in high-speed (HS) mode
– 10 Mbit/s in low-power (LP) mode
• Data transmission in HS and LP modes supported by the D-PHY
• Escape mode (ESC) and ultra-low-power state mode (ULPS) supported
• CSI-2 lane management layer connected to the D-PHY_RX to merge 1 or 2 data lanes
in a single 32-bit ISB-Byte bus
• ECC and error correction capabilities
• CRC check capability
• CSI-2 virtual channel and data type filtering supporting interleaved data
– Up to four virtual channels
– Support the data formats specified into the MIPI Alliance standard for CSI-2 v1.3
(18 data formats, plus the user defined ones)
• Up to seven independent data types
• Programmable interrupts:
– Four timer interrupts mapped on a selected virtual channel with starting point from
SOF (start of frame) or EOF (end of frame)
– Four line/byte counter interrupts mapped on a selected virtual channel to trigger
an event
• ISB-Byte header generation for internal connection with the DCMIPP peripheral

3.27 Parallel synchronous target interface (PSSI)

The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the
same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output target interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.

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The PSSI peripheral main features are the following:

• Target mode operation
• 8- or 16-bit parallel data input or output
• 8-word (32-byte) FIFO
• Data enable (PSSI_DE) and Ready (PSSI_RDY) alternate function. When selected,
these signals can either enable the transmitter to indicate when the data is valid, allow
the receiver to indicate when it is ready to sample the data, or both.
• Clock out mode

3.28 Display subsystem

The display subsystem is targeted to drive up to 1080p60 display panels, through a parallel
interface. It supports some on-the-fly compositions to offload the GPU and optimize the use
of the system bandwidth: up to two layers, color conversion, blend, mirror, and a final YUV
conversion.
The display subsystem can display a secure layer with data that cannot be read by
nonsecure application, and with the display guaranteed stable.
The display subsystem is built around LTDC:
• LTDC: handles display composition and rotation
– Composition: 2 layers
– Input pixel format: flexible format, including YUV420 full-planar on layer L1
– Secure layer: protected access to buffer and configuration registers.
– Mirror: horizontal and vertical
– Miscellaneous: color lookup-table, color keying, Gamma
– 1080p60 max performance
• LTDC parallel interface (integrated inside the LTDC):
– Standard: 24 bpp + Hs, Vs, De (DataEnable) synchronization signals with ReTime
– Output rate: 150 Mpixel/s
– Resolution: 1920x1080 at 60 fps max, with HDMI blankings
– Pixel formats: RGB888, 666, 565, YUV422-16 bits/BT601/709

3.29 LCD-TFT display controller (LTDC)

The LTDC (liquid crystal display - thin film transistor) display controller provides a parallel
digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronization, pixel
clock and data enable as output to interface directly to a variety of LCD-TFT panels.
LTDC main features are:
• Two input layers blended together to compose the display
• Cropping of layers from any input size and location
• Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888,
BGRA8888, RGB565, BGR565, RGB888packed
– Flexible ARGB, allowing any width and location for A,R,G,B components

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– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV, Interleaved),

YUV420-2L (FourCC: NV12, semi planar), YUV420-3L (FourCC: Yxx I420, full
planar) with some flexibility on the sequence of the component
• Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
• Color transparency keying
• Composition with flexible window position and size versus output display
• Blending with flexible layer order and alpha value (per pixel or constant)
• Background underlying color
• Gamma with non-linear configurable table
• Dithering for output with less bits per component (pseudo-random on 2 bits)
• Polarity inversion for HSync, VSync, and DataEnable outputs
• Output as RGB888 24 bpp or YUV422 16 bpp
• Secure layer (using layer2) capability, with grouped regs and additional interrupt set
• Interrupts based on seven different events
• AXI controller interface with long efficient bursts (64 or 128 bytes)

3.30 Neo-Chrom graphic processor (GPU2D)

The GPU2D is a dedicated graphics processing unit accelerating numerous 2.5D graphics
applications such as graphical user interface (GUI), menu display or animations. The
GPU2D works together with an optimized software stack designed for state of the art
graphic rendering.
• GPU2D main features
– Multi-threaded fragment (pixel) processing core with a VLIW (very-long instruction
word) instruction set.
– Fixed point functional units
– Command list based DMAs to minimize CPU overhead
– Two 64-bit AXI controller interfaces for texture and framebuffer access
– Dedicated 64-bit AXI controller interface for command list
– 32-bit AHB target interface for register bank access
– Up to four general-purpose flags for system-level synchronization
– Texture decompression unit with TSC™4 and TSC™6/TSC™6a support
• 2D drawing features
– Pixel/line drawing
– Filled rectangles
– Triangles, quadrilateral drawing
– Anti-aliasing 8xMSAA (multi-sample anti-aliasing)
• Image transformations
– 3D perspective correct projections
– Texture mapping with bilinear filtering or point sampling
• Blit support
– Rotation, mirroring, stretching (independently on x and y axis)
– Source and/or destination color keying

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– Pixel format conversions

• Text rendering support
– A1, A2, A4, and A8 bitmap anti-aliased
– Subsampled anti-aliased
• Color formats
– ABGR8888, ARGB8888, BGRA8888, RGBA8888
– xBGR8888, xRGB8888, BGRx8888, RGBx8888, RGB888, BGR888
– BGR565, RGB565
– RGB322, BGR322
– TSC4, TSC6, TSC6A
– L1, L2, L4, L8 (gray scale)
– A1, A2, A4, A8
• Full alpha blending with hardware blender
– Programmable blending modes
– Source/destination color keying

3.31 Video encoder (VENC)

The video encoder (VENC) provides a hardware acceleration to encode a 1080p30 video
stream in H264 (= MPEG4_Part10/AVC). The VENC also provides hardware acceleration to
encode still images (JPEG) of up to 300 Mpixel/s. The VENC implementation embeds a
large 128-Kbyte video RAM (VENCRAM). When the VENC is disabled, the VENCRAM is
unused for video purposes, and is accessible by the system as a contiguous extension of
the system SRAM.
The VENC supports the following features:
• Video encode:
– codecs: H264 (MPEG4_Part10/AVC, baseline/Main/High up to 5.2)
– performance: 1080p30 for H264
• Still-image encode:
– codecs: JPEG (baseline interleaved)
– performance: 300 Mpixel/s for JPEG
• VENCRAM:
– size: 128 Kbytes
– access: can be statically assigned to the system by SYSCFG settings
• Security via RIF:
– the VENC is protected by a default target and controller control (RISUP and
RIMU)
– by default, the VENC works in non-protected mode
– the VENC can be set in protected mode, for instance to handle DRM tasks with a
secure datapath. In such cases, the drivers must run in a protected process.
• Synchronization from an upstream peripheral: pixels can be streamed from an
upstream peripheral (such as the camera) directly to the VENC, without writing to a full
frame buffer, nor requiring external bandwidth.

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• Encode with multiple codecs on a same system: the VENC hardware processes the
encode tasks sequentially, interleaved at frame level. Performance is shared across all
the tasks.

3.32 JPEG codec (JPEG)

The hardware 8-bit JPEG codec encodes uncompressed image data stream or decodes
JPEG-compressed image data stream. It also fully manages JPEG headers.
JPEG codec main features are:
• High-speed fully-synchronous operation
• Configurable as encoder or decoder
• Single-clock-per-pixel encode/decode
• RGB, YCbCr, YCMK and BW (grayscale) image color space support
• 8-bit depth per image component at encode/decode
• JPEG header generator/parser with enable/disable
• Four programmable quantization tables
• Single-clock Huffman coding and decoding
• Fully-programmable Huffman tables (two AC and two DC)
• Fully-programmable minimum coded unit (MCU)
• Concurrent input and output data stream interfaces

3.33 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
nondeterministic random bit generator (NDRBG).
The RNG true random number generator has been precertified NIST SP800-90B. It has
also been tested using the German BSI statistical tests of AIS-31 (T0 to T8).
RNG main features:
• Delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage.
• Entropy source to construct a nondeterministic random bit generator (NDRBG).
• Embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• Can be disabled to reduce power consumption, or enabled with an automatic
low-power mode (default configuration).
• AMBA® AHB target peripheral, accessible through 32-bit word single accesses only
(else an AHB bus error is generated, and the write accesses are ignored).

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3.34 Secure AES coprocessor (SAES)

The SAES (available only on STM32N655xx and STM32N657xx devices) encrypts or
decrypts data in compliance with the advanced encryption standard (AES) defined by NIST.
It incorporates a protection against side-channel attacks (SCA), including differential power
analysis (DPA), certified SESIP and PSA security assurance level 3.
SAES supports ECB, CBC, CTR, GCM, GMAC, and CCM chaining modes for key sizes of
128 or 256 bits, and special modes such as hardware secret key encryption/decryption
(Wrapped-key mode) and key sharing with faster CRYP peripheral (Shared-key mode).
SAES has the possibility to load STM32 hardware secret controller keys (boot hardware key
BHK and derived hardware unique key DHUK), usable but not readable by application.
The peripheral supports DMA single transfers for incoming and outgoing data (two DMA
channels are required). It is hardware-linked with the true random number generator
(TRNG) and with the CRYP peripheral.
SAES main features:
• Compliant with NIST FIPS publication 197 “Advanced encryption standard (AES)”
(November 2001)
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• Protection against side-channel attacks (SCA), incl. differential power analysis (DPA),
certified SESIP and PSA security assurance level 3
• 128-bit data block processing, supporting cipher key lengths of 128-bit and 256-bit
• 480 or 680 clock cycle latency in ECB mode for processing one 128-bit block with,
respectively, 128-bit or 256-bit key
• Hardware secret key encryption/ decryption (Wrapped-key mode)
• Using dedicated key bus, optional key sharing with faster CRYP peripheral (Sharedkey
mode), controlled by SAES
• Integrated key scheduler to compute the last round key for ECB/CBC decryption
• 256-bit of write-only registers for storing cryptographic keys (eight 32-bit registers)
• Optional 128-bit or 256-bit hardware loading of two hardware secret keys (BHK,
DHUK) that can be XOR-ed together
• Security context enforcement for keys
• 128-bit of registers for storing initialization vectors (four 32-bit registers)
• 32-bit buffer for data input and output
• Automatic data flow control supporting two direct memory access (DMA) channels, one
for incoming data, one for processed data. Only single transfers are supported.
• Data-swapping logic to support 1-, 8-, 16-, or 32-bit data
• AMBA AHB target peripheral, accessible through 32-bit word single accesses only.
Other access types generate an AHB error, and other than 32-bit writes may corrupt
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• Possibility for software to suspend a message if SAES needs to process another

message with a higher priority, then resume the original message

3.35 Cryptographic processor (CRYP)

The cryptographic processor (CRYP) encrypts or decrypts data in compliance with the
advanced encryption standard (AES) defined by NIST. This function is available only on
STM32N655xx and STM32N657xx devices.
CRYP supports ECB, CBC, CTR, GCM, GMAC, and CCM chaining modes for key sizes of
128, 192, or 256 bits. CRYP has the possibility to load by hardware the key stored in SAES
peripheral, under SAES control.
The peripheral supports both single and fixed DMA burst transfers for incoming and
outgoing data (two DMA channels are required). CRYP also includes input and output
FIFOs for better performance.
CRYP main features are:
• Compliant with NIST FIPS publication 197 “Advanced encryption standard (AES)”
(November 2001)
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 16-byte data block processing, supporting cipher key lengths of 128, 192 and 256 bits
• 14 or 18 clock cycle latency in ECB mode for processing one 16-byte block with 128-bit
or 256-bit key, respectively
• Using dedicated key bus, optional key sharing with side-channel resistant SAES
peripheral (shared-key mode), controlled by SAES
• Integrated key scheduler to compute the last round key for ECB/CBC decryption
• 256-bit of write-only registers for storing the cryptographic keys (eight 32-bit registers)
• 128-bit of registers for storing initialization vectors (four 32-bit registers)
• 32-bit input buffer associated with an internal input FIFO of eight 32-bit words,
corresponding to two AES blocks
• 32-bit output buffer associated with an internal output FIFO of eight 32-bit words,
corresponding to two AES blocks
• Automatic data flow control supporting two direct memory access (DMA) channels, one
for incoming data, one for processed data. The output FIFO supports both single and
burst transfers, while the input FIFO supports only burst transfers.
• Data swapping logic to support 1-, 8-, 16- or 32-bit data
• AMBA AHB target peripheral, accessible through 32-bit word single accesses only.
Other access types generates an AHB error, and write accesses are ignored.
• Possibility for software to suspend a message if CRYP needs to process another
message with a higher priority, then resume the original message

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3.36 Hash processor (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-2 family) and the HMAC (keyed-hash message authentication code)
algorithm. HMAC is suitable for applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) approved
digests of length of 160, 224, 256 bits, for messages of any length less than 264 bits (for
SHA-1, SHA-224 and SHA-256) or less than 2128 bits (for SHA-384, SHA-512).
HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA2-224, SHA2-256, SHA2-384, and SHA2-512
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 98 clock cycles for processing one 1024-bit block of data using either SHA2-384
or SHA2-512 algorithm
– Support for SHA-2 truncated outputs (SHA2-512/224, SHA2-512/256)
– Support for HMAC mode with all supported algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit-string
– Supported word swapping format: bits, bytes, half-words and 32-bit words
• Single 32-bit, write-only, input register associated to an internal input FIFO,
corresponding to a 64-byte block size (16 x 32 bits)
• Automatic padding to complete the input bit string to fit digest minimum block size
• AHB target peripheral, accessible by 32-bit words only (else an AHB error is
generated)
• 8 × 32-bit words (H0 to H15) for output message digest
• Automatic data flow control supporting direct memory access (DMA) using one
channel.
• Support for both single and fixed DMA burst transfers of four words.
• Interruptible message digest computation, on a per-block basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including DMA

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3.37 Memory cipher engine (MCE)

The memory cipher engine (MCE) defines, in a given address space, multiple regions with
specific security setup (encryption). All system bus traffic going through an encrypted region
is managed on-the-fly by the MCE, automatically decrypting reads and encrypting writes if
authorized. This function is available only on STM32N655xx and STM32N657xx devices.
Multiple ciphering option (stream, block, fast block) are available to offer the best security
versus performance trade-off.
MCE main features are:
• System bus in-line encryption (for writes) and decryption (for reads), based on
embedded firewall programming
– Four encryption modes per region (maximum 4 regions available): no encryption
(bypass mode), stream cipher, block cipher and fast block cipher modes
– Start and end of regions defined with 4-Kbytes granularity
– Default filtering (region 0): any access granted
– Regions 1 to 4 access filtering criteria: none
• Supported block ciphers: AES-128, AES-256 or Noekeon (12 round version), selected
at boot
• Supported chaining modes: block and stream
– Block mode with AES cipher is compatible with ECB mode specified in NIST FIPS
publication 197 Advanced encryption standard (AES) (normal or fast).
– Stream mode with AES cipher is compliant with CTR mode specified in NIST
SP800-38A Recommendation for Block Cipher Modes of Operation.
– Includes a leakage resilient mode of operation as defense against side channel
attacks (SCA).
• One set of write-only and lockable 256-bit controller key registers per block cipher
(normal, fast)
• Two sets of lockable cipher contexts (128-bit key, IV), usable for stream and block
ciphers
• Optimization for XSPI data pre-fetching mechanism (stream cipher only)
• Read-write arbitration scheme, for better read performances
• AHB configuration port
• AXI system bus controller/target interfaces (64-bit)
– Support for any AXI-64bit read transactions
– When encryption is enabled, support for AXI-64bit INCRx (x = 1 to 8) and WRAPx
(x = 4) write transactions

3.38 Public key accelerator (PKA)

PKA (public key accelerator) is intended for the computation of cryptographic public key
primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve
cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost,
these operations are executed in the Montgomery domain.
This function is available only on STM32N655xx and STM32N657xx devices.

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For a given operation, all needed computations are performed within the accelerator, so no
further hardware/software elaboration is needed to process the inputs or the outputs.
When manipulating secrets, the PKA incorporates a protection against side-channel attacks
(SCA), including differential power analysis (DPA), certified SESIP and PSA security
assurance level 3.
PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications:
– RSA modular exponentiation, RSA chinese remainder theorem (CRT)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• When manipulating secrets: protection against side-channel attacks (SCA), including
differential power analysis (DPA), certified SESIP and PSA security assurance level 3
• Applicable to modular exponentiation, ECC scalar multiplication and ECDSA signature
generation
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• AMBA AHB target peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)

3.39 Timers (TIMx)

The devices contain 15 timers and 5 low-power timers.

3.39.1 Basic timers (TIM6/TIM7/TIM18)

These timers consist in a 16-bit autoreload counter driven by a programmable prescaler.
They can be used as generic timers for time-base generation. The timers are completely
independent, and do not share any resources.
Main features:
• 16-bit autoreload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Interrupt/DMA generation on the update event: counter overflow
• ADC synchronization for jitter-free sampling points

3.39.2 Advanced control timers (TIM1/TIM8)

The devices embed two advanced control timers that consist in a 16-bit auto-reload counter
driven by a programmable prescaler. These timers can be used for a variety of purposes,
such as measuring the pulse length of input signals (input capture) or generating output
waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse

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lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced control timers are completely independent from the general purpose ones,
and do not share any resources. They can be synchronized together.
Advanced control timers main features are:
• 16-bit up, down, up/down auto-reload counter.
• 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65536.
• Up to six independent channels for:
– Input capture (except channels 5 and 6)
– Output compares
– PWM generation (edge- and center-aligned mode)
– One pulse mode output
• Complementary outputs with programmable dead-time
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
• Repetition counter to update the timer registers only after a given number of cycles of
the counter.
• Two break inputs to put the timer’s output signals in a safe user selectable
configuration.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Support of incremental (quadrature) encoder and Hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management
• ADC synchronization for jitter-free sampling points

3.39.3 General purpose timers (TIM2/TIM3/TIM4/TIM5)

These four timers consist of a 16- or 32-bit auto-reload counter driven by a programmable
prescaler. They can be used for a variety of purposes, such as measuring the pulse length
of input signals (input capture), or generating output waveforms (output compare and
PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to
several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together.
Main features:
• 16- or 32-bit up, down, up/down auto-reload counter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.
• Up to four independent channels for:

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– Input capture
– Output compare
– PWM generation (edge- and center-aligned modes)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Support of incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management
• ADC synchronization for jitter-free sampling points

3.39.4 General purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14)

These six timers consist in a 16-bit auto-reload counter driven by a programmable
prescaler. They may be used for a variety of purposes, including measuring the pulse
lengths of input signals (input capture) or generating output waveforms (output compare,
PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to
several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together.
Main features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65536 (can be changed “on the fly”)
• Independent channel (up to two independent channels with TIM9/TIM12) for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together (TIM9/TIM12 only)
• Interrupt generation on the following events:
– Update: counter overflow, counter initialization (by software or internal trigger)
– Trigger event: counter start, stop, initialization, or count by internal trigger
(TIM9/TIM12 only)
– Input capture
– Output compare
• ADC synchronization for jitter-free sampling points (TIM9/TIM12 only)

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3.39.5 General purpose timers (TIM15/TIM16/TIM17)

These timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They can be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources.
TIM15 can be synchronized. It includes the following features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• Up to two independent channels for:
– Input capture
– Output compare
– PWM generation (edge mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time (for channel 1 only)
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together
• Repetition counter to update the timer registers only after a given number of cycles of
the counter
• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow, counter initialization (by software or internal/external
trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compares
– Break input (interrupt request)
• ADC synchronization for jitter-free sampling points
TIM16/TIM17 main features:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535
• One channel for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Complementary outputs with programmable dead-time
• Repetition counter to update the timer registers only after a given number of cycles of
the counter

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• Break input to put the timer’s output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
– Update: counter overflow
– Input capture
– Output compare
– Break input

3.39.6 Low-power timer (LPTIM)

The LPTIM is a 16-bit timer that benefits from the ultimate developments in power
consumption reduction. Thanks to the diversity of its clock sources, the LPTIM is able to
keep running in all power modes except for Standby mode. Given its capability to run even
with no internal clock source, the LPTIM can be used as a pulse counter. The capability to
wake up the system from low-power modes makes it suitable for timeout functions with
extremely low consumption.
The LPTIM introduces a flexible clock scheme that provides the needed functionalities and
performance, while minimizing the power consumption. Its main features are:
• 16 bit upcounter
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, and 128)
• Selectable clock
– Internal clock sources: configurable internal clock source (see RCC section)
– External clock source over LPTIM input (working with no LP oscillator running,
used by pulse counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to two independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on ten events
• DMA request generation on the following events:
– Update event
– Input capture

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3.40 Independent watchdog (IWDG)

This peripheral offers a high safety level, thanks to its capability to detect malfunctions due
to software or hardware failures. The IWDG is clocked by an independent clock, and stays
active even if the main clock fails. In addition, the watchdog function is performed in the VDD
voltage domain, allowing the IWDG to remain functional even in low-power modes. Refer to
the dedicated section of the reference manual to check its capabilities in this product.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, making it very reliable to detect any
unexpected behavior. Its main features are:
• 12-bit down-counter
• Dual voltage domain, enabling operation in low-power modes
• Independent clock
• Early wake-up interrupt generation
• Reset generation in case of timeout and of refresh outside the expected window

3.41 System window watchdog (WWDG)

The WWDG is used to detect the occurrence of a software fault, usually generated by
external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence.
The watchdog circuit generates a reset on expiry of a programmed time period, unless the
program refreshes the contents of the down-counter before bit T6 is cleared. A reset is also
generated if the 7-bit down-counter value (in the control register) is refreshed before the
down-counter reaches the window register value. This implies that the counter must be
refreshed in a limited window.
The WWDG clock is prescaled from the APB clock, and has a configurable time-window that
can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications requiring the watchdog to react within an
accurate timing window. The WWDG main features are:
• Programmable free-running down-counter
• Conditional reset (if watchdog activated)
– When the down-counter value becomes lower than 0x40
– If the down-counter is reloaded outside the window
• Early wake-up interrupt (EWI): triggered (if enabled and the watchdog activated) when
the down-counter is equal to 0x40

3.42 Real-time clock (RTC)

The RTC is an independent BCD timer/counter that provides an automatic wake-up to
manage all low-power modes.
The RTC provides a time of- day clock/calendar with programmable alarm interrupts. As
long as the supply voltage remains in the operating range, it never stops, regardless of the
device status (Run mode, low-power mode or under reset). The RTC is functional in VBAT
mode.

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Its main features are:

• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Binary mode with 32-bit free-running counter.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. (can be used to synchronize it
with a controller clock).
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Timestamp, which can be used to save the calendar content: can be triggered by an
event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period.
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wake-up timer and timestamp individual secure or non-secure
configuration
• Alarm A, alarm B, wake-up timer and timestamp individual privilege protection
• The RTC is supplied through a switch that takes power either from the VDD supply
when present, or from the VBAT pin.
• The RTC is functional in VBAT mode and in all low-power modes when clocked by the
LSE.
• All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake
up the device from the low-power modes.

3.43 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks.
32 32-bit backup registers are retained in all low-power modes and in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and ten internal tampers. The external tamper pins
can be configured for edge or level detection with or without filtering, or active tamper, which
increases the security level by auto checking that the tamper pins are not externally opened
or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2,
cryptographic peripherals. The protected resources are named “device secrets”.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the backup domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to seven tamper pins for seven external tamper detection events:

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– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks.
– Flexible active tamper I/O management: from four meshes (each input associated
to its own exclusive output) to 7 meshes (single output shared for up to seven
tamper inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management.
– Configurable digital filter.
• Ten internal tamper events to protect against transient or environmental perturbation
attacks
• Each tamper can be configured in two modes:
– Confirmed mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Potential mode: most of the secrets erase following a tamper detection are
launched by software
• Any tamper detection can generate a RTC timestamp event.
• TrustZone support:
– Tamper secure or non-secure configuration
– Backup registers configuration in three configurable-size areas:
• One read/write secure area
• One write secure/read non-secure area
• Put configurable-size areas in a menu
• One read/write non-secure area
– Boot hardware key for secure AES, stored in backup registers, protected against
read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter

3.44 Inter-integrated circuit (I2C) interface

The devices contain four Inter integrated circuit (I2C1 to I2C4)
The I2C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I2C bus. It provides multicontroller capability, and controls all
I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode
(Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). It is also SMBus (system management
bus) and PMBus® (power management bus) compatible.
DMA can be used to reduce CPU overload.
I2C main features are:
• I2C bus specification rev03 compatibility:
– Target (formerly known as slave) and controller (formerly known as master) modes
– Multicontroller capability
– Standard-mode (up to 100 kHz)
– Fast-mode (up to 400 kHz)
– Fast-mode Plus (up to 1 MHz)

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– 7- and 10-bit addressing mode

– Multiple 7-bit target addresses (two addresses, one with configurable mask)
– All 7-bit addresses acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• 1-byte buffer with DMA capability
• Programmable analog and digital noise filters
The following additional features are also available, depending upon product
implementation
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the i2c_pclk reprogramming
• Wake-up from Stop mode on address match
]

Table 11. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4

7-bit addressing mode X X X X

10-bit addressing mode X X X X
Standard-mode (up to 100 kbit/s) X X X X
Fast-mode (up to 400 kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Independent clock X X X X
Wake-up from Stop mode X(2) X(2) X(2) X(2)
SMBus/PMBus X X X X
1. X = supported.
2. Supported only from Stop SVOS high.

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3.45 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between this device and others, such as sensors
and host processor, connected on an I3C bus. An I3C bus is a two-wire, serial single-ended,
multidrop bus, intended to improve a legacy I2C bus.
The I3C SDR-only peripheral implements all the features required by the MIPI® I3C
specification v1.1. It can control all I3C bus-specific sequencing, protocol, arbitration, and
timing, and can act as controller, or as target.
When acting as controller, the I3C peripheral improves the features of the I2C interface
preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in
legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does
not perform clock stretching.
The I3C peripheral can be used with DMA, to off-load the CPU. Its main features are:
• MIPI® I3C specification v1.1, as:
– I3C SDR-only primary controller
– I3C SDR-only secondary controller
– I3C SDR-only target
• I3C SCL bus clock frequency up to 12.5 MHz
• Registers configuration from the host application via the APB target port
• Queued data transfers:
– Transmit FIFO (TX-FIFO) for data bytes/words to be transmitted on the I3C bus
– Receive FIFO (RX-FIFO) for received data bytes/words on the I3C bus
– For each FIFO, optional DMA mode with a dedicated DMA channel
• Queued control/status transfers, when controller:
– Control FIFO (C-FIFO) for control words to be sent on the I3C bus
– Optional status FIFO (S-FIFO) for status words as received on the I3C bus
– For each FIFO, optional DMA mode with a dedicated DMA channel
• Messages:
– Legacy I2C read/write messages to legacy I2C targets in Fm/Fm+
– I3C SDR read/write private messages
– I3C SDR broadcast CCC messages
– I3C SDR read/write direct CCC messages
• Frame-level management, when controller:
– Optional C-FIFO and TX-FIFO preload
– Multiple messages encapsulation
– Optional arbitrable header generation on the I3C bus
– HDR exit pattern generation on the I3C bus for error recovery
• Programmable bus timing, when controller:
– SCL high and low period
– SDA hold time
– Bus free (minimum) time
– Bus available/idle condition time

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– Clock stall time

• Target-initiated requests management:
– Simultaneous support up to four targets, when controller
– In-band interrupts, with programmable IBI payload (up to four bytes), with pending
read notification support
– Bus control request, with recovery flow support and hand-off delay
– Hot-join mechanism
• HDR exit pattern detection when target
• Bus error management:
– CEx with x = 0, 1, 2, 3 when controller
– TEx with x = 0, 1, ..., 6 when target
– Bus control switch error and recovery
– Target reset
• Individual programmable event-based management:
– Per-event identification with flag reporting and clear control
– Host application notification via flag polling, and/or via interrupt with a per-event
programmable enable
– Error type identification
• Wake-up from low-power mode(s):
– Acknowledged target request completion, when controller
– Missed start detection, when target
– Reset pattern detection, when target
• Wake-up from Stop mode(s), as controller:
– On an in-band interrupt without payload
– On a hot-join request
– On a controller-role request
• • Wake-up from Stop mode(s), as target:
– On a reset pattern
– On a missed start
• Multiclock domain management:
– Separate APB clock and kernel clock, driven from independently programmed
clock sources via the RCC, in addition to SCL clock
– Minimum operating frequency for the kernel clock and the APB clock vs. the
application-driven SCL clock

3.46 Universal synchronous/asynchronous receiver transmitter

(USART/UART/LPUART)
USART offers a flexible way to perform Full-duplex data exchange with external equipments
requiring an industry standard NRZ asynchronous serial data format. A very wide range of
baud rates can be achieved through a fractional baud rate generator.

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3.46.1 USART/UART
The USART supports both synchronous one-way and Half-duplex Single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and Modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications are possible by using the DMA (direct memory access)
for multibuffer configuration.
USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data. Each FIFO can be enabled/disabled
by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous target/controller mode and clock output/input for synchronous
communications
• SPI target transmission underrun error flag
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Wake-up from Stop mode

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USART extended features are:

• LIN controller synchronous break send capability and LIN target break detection
capability
• 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode
• Smartcard mode
• Support of T = 0 and T = 1 asynchronous protocols for smartcards as defined in the
ISO/IEC 7816-3 standard
• 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition

3.46.2 LPUART
The LPUART is an UART that enables bidirectional UART communications with a limited
power consumption.
Only 32.768 kHz LSE clock is required to enable UART communications up to 9600 bauds.
Higher baud rates can be reached when the LPUART is clocked by other clock sources.
Even when the microcontroller is in low-power mode, the LPUART can wait for an incoming
UART frame while having an extremely low energy consumption.
The LPUART includes all necessary hardware support to make asynchronous serial
communications possible with minimum power consumption. It supports Half-duplex,
Single-wire communications, and modem operations (CTS/RTS). It also supports
multiprocessor communications. DMA can be used for data transmission/reception
LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 to 9600 bauds using a 32.768 kHz clock source.
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data. Each FIFO can be enabled/disabled
by software and come with status flags for FIFOs states.
• Dual clock domain with dedicated kernel clock for peripherals independent from PCLK.
• Programmable data word length (7, 8, or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (one or two stop bits)
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration

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• Hardware flow control for modem and RS-485 transceiver

• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wake up from Mute mode by idle line detection or
address mark detection
• Wake-up from Stop mode

Table 12. Instance implementation

Instance STM32N6xx
USART1 Full
USART2 Full
USART3 Full
USART6 Full
USART10 Full
UART4 Basic
UART5 Basic
UART7 Basic
UART8 Basic
UART9 Basic
LPUART1 Low-power

Table 13. USART/LPUART features

Mode or feature(1) Full feature Basic feature Low-power feature

Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (target/controller) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X

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Table 13. USART/LPUART features (continued)

Mode or feature(1) Full feature Basic feature Low-power feature

IrDA SIR ENDEC block X X -

LIN mode X X -
Dual-clock domain X X X
Receiver timeout interrupt X X -
Modbus communication X X -
Auto baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size (bytes) 16
(2)
Wake-up from low-power mode X X(2) X(2)
1. X = supported.
2. Wake-up supported from Stop mode.

3.47 Serial peripheral interface (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex and simplex synchronous, serial communication
with external devices.
The interface can be configured as controller or target and can operate in multitarget or
multicontroller configurations. The device configured as controller provides communication
clock (SCK) to the target device. The target select (SS) and ready (RDY) signals can be
applied optionally just to setup communication with concrete target and to assure it handles
the data flow properly. The Motorola® data format is used by default, but some other specific
modes are supported as well.

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The SPI main features are:

• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• From 4- to 32-bit data size selection
• Multicontroller or multitarget mode capability
• Dual-clock domain (the peripheral kernel clock is independent from the APB bus clock)
• Baud rate prescaler up to kernel frequency divided by two, or bypass from RCC in
controller mode
• Protection of configuration and setting
• Hardware or software management of SS for both controller and target
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• Support of SPI Motorola® and Texas Instruments® formats
• Hardware CRC feature can verify the integrity of the communication at the end of
transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun, the mode fault, and frame error, depending upon the operating mode
• Two 8-bit width embedded Rx and Tx FIFOs, whose size depends upon the instance
• Configurable FIFO thresholds (data packing)
• Configurable behavior at target underrun condition (support of cascaded circular
buffers)
• Configurable behavior at target underrun condition (support of cascaded circular
buffers)
• Optional status pin RDY signaling that the target device is ready to handle the data flow

Table 14. SPI features

Feature SPI1, SPI2, SPI3, SPI6 SPI4, SPI5

Data and CRC size Configurable from 4 to 32 bits Configurable from 4 to 16 bits
CRC polynomial length, CRC polynomial length,
CRC computation
configurable from 5 to 33 bits configurable from 5 to 17 bits
Size of FIFOs 16x8 bits 8x8 bits
Number of data control (TSIZE) Up to 65536
I2S feature Yes No

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Table 14. SPI features (continued)

Feature SPI1, SPI2, SPI3, SPI6 SPI4, SPI5

Autonomous in Stop modes with

No
wake-up capability
Autonomous in Standby mode No

3.48 Serial audio interface (SAI)

The SAI offers a wide set of audio protocols due to its flexibility and wide range of
configurations. Many stereo or mono audio applications can be targeted. I2S standards,
LSB or MSB-justified, PCM/DSP, TDM, and AC’97 protocols can be addressed. SPDIF
output is offered when the audio block is configured as a transmitter.
The SAI contains two independent audio sub-blocks, each has its own clock generator and
I/O line controller.
The SAI works in controller or target configuration. The audio sub-blocks act as receiver or
transmitter, and work synchronously or not (with respect to the other one).
The SAI can be connected with other SAIs, to work synchronously.
SAI main features are:
• Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or asynchronous mode between the audio sub-blocks
• Possible synchronization between multiple SAIs
• Target or controller configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in controller mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
• PDM interface, supporting up to four microphone pairs
• SPDIF output available if required
• Up to 16 slots available with configurable size
• Number of bits by frame can be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/Mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in target mode
– Late frame synchronization signal detection in target mode

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– Codec not ready for the AC’97 mode in reception

• Interrupt sources when enabled:
– Errors
– FIFO requests
• 2-channel DMA interface

Table 15. SAI features(1)

Feature SAI1 SAI2

I2S, LSB- or MSB-justified, PCM/DSP, TDM, AC’97 X X

FIFO size 8 words
SPDIF X X
(2)
PDM X -
1. ‘X’ = supported, ‘-’ = not supported.
2. Only signals D[3:1] and CK[2:1] are available.

3.49 SPDIF receiver interface (SPDIFRX)

The SPDIFRX interface handles S/PDIF audio protocol. Its main features are:
• Up to four inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 8 to 192 kHz supported
• Supports audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities

3.50 Management data input/output (MDIOS)

An MDIO bus can be useful in systems where a controller chip needs to manage (configure
and get status data from) one or multiple target chips.
The bus protocol uses only two signals, namely MDC (management data clock), and MDIO,
the data line carrying the opcode (write or read), the target (port) address, the MDIOS
register address, and the data.
In each transaction, the controller either reads the contents of an MDIOS register in one of
its targets, or it writes data to an MDIOS register in one of its targets.
The MDIOS peripheral serves as a target interface to an MDIO bus. An MDIO controller can
use the MDC/MDIO lines to write and read 32 16-bit registers held in the MDIOS. These
registers are managed by the firmware. This allows the MDIO controller to configure the
application running on the device and get status information from it.

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The MDIOS can operate in Stop mode, optionally waking up the device if the MDIO
controller performs a read or a write to one of its MDIOS registers.
The MDIOS includes the following features:
• 32 MDIOS register addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIOS read-only output data registers
– 32 x 16-bit firmware read-only, MDIOS write-only input data registers
• Configurable target (port) address
• Independently maskable interrupts/events:
– MDIOS register write
– MDIOS register read
– MDIOS protocol error
• Able to operate in and to wake up from Stop mode

3.51 Controller area network with flexible data rate (FDCAN)

The controller area network (CAN) subsystem consists of three CAN modules, a shared
message RAM and a clock calibration unit. Refer to the product memory organization for the
base address of each of them.
FDCAN modules are compliant with ISO 11898-1: 2015 (CAN protocol specification version
2.0 part A, B) and CAN FD protocol specification version 1.0.
In addition, the first CAN module FDCAN1 supports time triggered CAN (TTCAN), specified
in ISO 11898-4, including event synchronized time-triggered communication, global system
time, and clock drift compensation. The FDCAN1 contains additional registers, specific to
the time triggered feature. The CAN FD option can be used together with event-triggered
and time-triggered CAN communication.
A 10 Kbyte message RAM implements filters, receive FIFOs, receive buffers, transmit event
FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is shared between
the FDCAN modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for each FDCAN from the HSI internal RC oscillator and the PLL, by evaluating CAN
messages received by the FDCAN1.

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The main features are:

• Conform with CAN protocol version 2.0 part A, B, and ISO 11898-1: 2015, -4
• CAN FD with max. 64 data bytes supported
• TTCAN protocol level 1 and level 2 completely in hardware (FDCAN1 only)
• Event synchronized time-triggered communication supported (FDCAN1 only)
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• Two configurable receive FIFOs
• Separate signaling on reception of high priority messages
• Up to 64 dedicated receive buffers
• Up to 32 dedicated transmit buffers
• Configurable transmit FIFO / queue
• Configurable transmit event FIFO
• FDCAN modules share the same message RAM
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support

3.52 USB on-the-go high speed (OTG)

Reference is made to the following documents:
• USB On-The-Go Supplement, Revision 2.0
• Universal Serial Bus Revision 2.0 Specification
• USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB
2.0 specification, July 16, 2007
• Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007
• Battery Charging Specification, Revision 1.2
The USB OTG is a dual-role device (DRD) controller that supports both device and host
functions and is fully compliant with the On-The-Go Supplement to the USB 2.0
Specification. It can also be configured as a host-only or device-only controller, fully
compliant with the USB 2.0 Specification. OTG supports the speeds defined in Table 16.

Table 16. Supported OTG speeds

Mode HS (480 Mbit/s) FS (12 Mbit/s) LS (1.5 Mbit/s)

Host mode X X X
Device mode X X -

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3.53 USB HS PHY controller (USBPHYC)

There are two near-identical instances, namely USBPHYC1 (associated with OTG1), and
USBPHYC2 (associated with OTG2) including one additional control bit for hardware debug
(HDP).
For a more complete system view of the USB controllers and PHYs, refer to the block
diagram of the main OTG controller. This controller handles general and miscellaneous
control of the OTG PHYs.
The main features are:
• PLL configuration
• Trimming of the electrical parameters (if required)

3.54 USB Type-C / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• Compliance with USB Type-C specification release 2.3
• Compliance with USB Power Delivery specifications revision 2.0 and 3.2
– Enabling advanced applications such as PPS (programmable power supply)
• Stop mode low-power operation support
• Built-in analog PHY
– USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
– USB Power Delivery message transmission and reception
The digital controller handles:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts (DMA
compatible)
• USB power delivery timing dividers (including a clock prescaler)
• BMC (bi-phase mark coding) encode and decode
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Clock recovery from incoming Rx stream

3.55 Ethernet (ETH): gigabit media access control (GMAC)

with DMA controller
Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.
The Ethernet peripheral enables to transmit and receive data over Ethernet in compliance
with the IEEE 802.3-2015 standard.

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The peripheral is configurable to meet the needs of a large variety of consumer and
industrial applications, including AV nodes and TSN (time sensitive networking) nodes.
The Ethernet peripheral embeds a dedicated DMA for direct memory interface, a media
access controller (MAC) and a PHY interface block supporting several formats.
The Ethernet peripheral is compliant with the following standards:
• IEEE 802.3-2015 for Ethernet MAC and media independent interface (MII)
• IEEE 1588-2008 for precision networked clock synchronization (PTP)
• IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic
• IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE)
• AMBA 2.0 for AHB target port
• AMBA4 for AXI controller port
• RGMII specification version 2.6 from HP/Marvell
• RMII specification version 1.2 from RMII consortium
Caution: The gigabit media independent interface (GMII) is only available internally to supply the
RGMII adapter. No GMII signals are available off-chip

3.56 Development support

3.56.1 Serial-wire/JTAG debug port (SWJ-DP)

This is a CoreSight component that implements an external access port for connecting
debugging equipment. Two types of interface can be configured, namely a 5-pin standard
JTAG interface (JTAG-DP), and a 2-pin (clock + data) serial-wire debug port (SW-DP).
The two modes are mutually exclusive, as they share the same I/O pins.
By default, the JTAG-DP is selected after a system or POR. The five I/O pins are configured
by hardware in debug alternative function mode. The SWJ-DP incorporates pull-up resistors
on JTDI, JTMS/SWDIO, and NJTRST, as well as a pull-down resistor on JTCK/SWCLK.
A debugger can select the SW-DP by transmitting the following serial data sequence on
JTMS/SWDIO: ...(50 or more ones)...,0,1,1,1,1,0,0,1,1,1,1,0,0,1,1,1,...(50 or more ones)...
JTCK/SWCLK must be cycled for each data bit.
In SW-DP mode, the unused JTAG pins (JTDI, JTDO, and NJTRST) can be used for other
functions.
Note: All SWJ port I/Os can be reconfigured to other functions by software, but debugging is no
longer possible.

3.56.2 Embedded Trace Macrocell

The Cortex-M55 ETM is a CoreSight component closely coupled to the CPU. The ETM
generates trace packets that allow to trace the execution of the Cortex-M55 core.
Note: Data accesses are not included in the trace information.

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Functional overview STM32N6x5xx STM32N6x7xx

The ETM receives information from the CPU over the processor trace interface, including:
• the number of instructions executed in the same cycle
• changes in program flow
• the current processor instruction state
• addresses of memory locations accessed by load and store instructions
• type, direction and size of a transfer
• condition code information
• exception information
• wait for interrupt state information

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STM32N6x5xx STM32N6x7xx

4 Pinout, pin description and alternate functions

4.1 Pinout/ballout schematics

Figure 7. VFBGA142 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

OTG2_HS OTG1_HS OTG1_TX PH0-

A PDR_ON OTG2_ID
DM
NC
DM RTUNE OSC_IN
PC8 PC10 PC12 PE13 PE7 PE9 PE0 VSS

PC15- PH1-
OTG2_HS OTG1_HS VDD33US
B OSC32_O BOOT0
DP
OTG1_ID
DP B
OSC_OU PC9 PC11 PH2 PE12 PD1 PE10 PE1 PE2
UT T

PC14-
C OSC32_I NRST NC PD8 PB0 PE3
N

VDDA18U OTG2_TX UCPD1_C UCPD1_C

D VBAT PWR_ON
SB RTUNE C1 C2
VDDIO4 VSS PE14 PE15 PE8 PN1 PB6

VDDA18A
E V08CAP PC13
ON
PB7 PN4 PN8

VDDA18P VSSAPM VFBSMP

F MU U S
VSSAON VDD PN7 PN5

VSSSMP VSSSMP VSSSMP

G S S S
VDD PN9 PN6

H VLXSMPS VLXSMPS VLXSMPS VDD PN10 PN2

VDDSMP VDDSMP VDDSMP

J S S S
VSS PN11 PN0

VDDA18P
K PF4 PF10 PF5
LL
VDDIO3 PN12 PN3

L PF2 PF14 PF3 VDDIO3 PB4 PA15

VDDCOR VDDCOR VDDCOR VDDCOR VDDCOR

M PF15 PF7 VSS
E E E E E
VSS PA8 VSS PG2 PB5

N PF8 PF11 PF13 PB12 PB11 PB10

CSI_REX
P PF12 VREF+ VSSA CSI_D1N CSI_CKN CSI_D0N
T
VDDCSI PG14 PA12 PA9 PA2 PA6 PA1 PG10

VDDA18A VDDA18C
R VSS VREF-
DC
CSI_D1P CSI_CKP CSI_D0P
SI
PA14 PA13 PA11 PA10 PA5 PG13 PA0 VSS

MS56501V2

1. The above figure shows the package top view.

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Pinout, pin description and alternate functions STM32N6x5xx STM32N6x7xx

Figure 8. VFBGA169 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13
PH1-
OTG2_H OTG1_H OTG1_TX
A PDR_ON NC
SDM
NC
SDM RTUNE
OSC_OU PC11 PE11 PE13 PD7 PD1 VSS
T

PC14-
OTG2_H OTG1_H UCPD1_ PH0-
B OSC32_I OTG2_ID
SDP
OTG1_ID
SDP CC1 OSC_IN
PC12 PE14 PE12 PD10 PD0 PD15
N

PC15-
OTG2_TX VDDA18 VDD33U UCPD1_
C OSC32_ VBAT
RTUNE USB SB CC2
PC9 PH2 PE5 PD2 PE7 PD3 PD14
OUT

VDDA18A
D V08CAP PC13 BOOT0 PWR_ON
ON
PC10 PC8 VDDIO4 PE15 PD6 PD12 PE8 PD4

VDDA18P VSSAPM VFBSMP VDDCOR

E MU U S
NRST VSSAON VSS
E
VSS VDD PB3 PD8 PE10 PE9

VSSSMP VSSSMP VSSSMP VSSSMP VDDCOR VDDCOR

F S S S S
VSS
E
VSS
E
VSS PE2 PE1 PE0 PD11

VLXSMP VLXSMP VLXSMP VLXSMP VDDCOR VDDCOR

G S S S S E
VSS
E
VSS VDD PB7 PB6 PB0 PE3

VDDSMP VDDSMP VDDSMP VDDSMP VDDCOR VDDCOR

H S S S S
VSS
E
VSS
E
VSS VDDIO3 PN11 PN3 PN1

VDDA18P VDDCOR
J PF4 PF10 PF5 PF3
LL
VSS
E
VSS VDD VDDIO3 PN2 PN10 PN0

K PF2 PF14 PF15 PF7 VSSA PG14 PA12 PA2 PG13 PB12 PN7 PN6 PN9

VDDA18A
L PF8 PF11 PF12 PF13
DC
VDDCSI PA11 PA8 PA1 PB11 PB5 PN4 PN5

VDDA18
M VREF+ CSI_D1N CSI_CKN CSI_D0N
CSI
PA13 PA9 PA5 PA0 PB10 PB4 PN12 PN8

CSI_REX
N VSS CSI_D1P CSI_CKP CSI_D0P
T
PA14 PA10 PA6 PG10 PG2 PA15 PA3 VSS

MS56502V2

1. The above figure shows the package top view.

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STM32N6x5xx STM32N6x7xx

Figure 9. VFBGA178 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14

PH1-
OTG2_HS VDD33US OTG1_HS UCPD1_C
A PDR_ON
DM
NC
B DM C1
OSC_OU PC6 PC7 PE6 PD6 PD0 PD3 VSS
T

PC14-
OTG2_HS OTG2_TX OTG1_HS UCPD1_C PH0-
B OSC32_I
DP
OTG1_ID
RTUNE DP C2 OSC_IN
PC1 PE11 PE15 PD7 PD1 PD4 PE9
N

PC15-
C OSC32_O VBAT PC13 NC OTG2_ID PC8 PC11 PH9 PE14 PE13 PD10 PD15 PE8 PE10
UT

VFBSMP VDDA18U OTG1_TX

D V08CAP
S
BOOT0
SB RTUNE
PC9 PC12 PC10 PE5 PE12 PE7 PD14 PD8 PD5

VDDA18P VSSAPM VDDA18A

E MU U
PWR_ON NRST
ON
PH2 VSS VDDIO4 VDDIO4 PD2 PD12 PB3 PB2 PD13

VSSSMP VSSSMP VSSSMP VSSSMP

F S S S S
VSSAON VSS PD11 PE0 PE1 PE2

G VLXSMPS VLXSMPS VLXSMPS VLXSMPS VDD VDD VDD PE3 PB0

VDDSMP VDDSMP VDDSMP VDDSMP

H S S S S
VSS VSS PD9 PB7 PB6

J PF4 PF6 PF10 PF5 PF3 VDDIO3 VDDIO3 PN12 PN4 PN8

VDDCOR VDDCOR VDDCOR VDDCOR

K PF2 PF14 PF15 PF7 VSS
E E E E
VSS PA3 PN6 PN7 PN5

VDDA18P VDDCOR
L PF8 PF11 PF12
LL
PG14 PA12
E
PA6 PA1 PB11 PB4 PG8 PN2 PN9

VDDA18A
M VREF+ PF13
DC
VSSA PG15 PA11 PA9 PA5 PG1 PB12 PB5 PG0 PN0 PN10

CSI_REX
N VREF- CSI_D1N CSI_CKN CSI_D0N
T
VDDCSI PA10 PA2 PG12 PG10 PG2 PA15 PN3 PN11

VDDA18C
P VSS CSI_D1P CSI_CKP CSI_D0P
SI
PA14 PA13 PA8 PG13 PA0 PB10 PA7 PN1 VSS

MS56503V2

1. The above figure shows the package top view.

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Pinout, pin description and alternate functions STM32N6x5xx STM32N6x7xx

Figure 10. VFBGA198 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

OTG2_HS OTG1_HS PH0-

A PDR_ON
DP
NC
DP OSC_IN
PC10 PC7 PE11 PE15 PD6 PD12 PD3 PE10 PB3 VSS

PC15- PH1-
OTG2_HS VDD33US OTG1_HS
B OSC32_O
DM B DM
OSC_OU PC9 PC6 PE14 PE13 PD7 PD1 PD4 PD8 PD11 PE2
UT T

PC14-
VDDA18U OTG1_TX
C OSC32_I NC
SB
OTG1_ID
RTUNE
PC8 PC1 PE5 PE12 PD10 PD0 PE8 PD5 PE0 PE3
N

OTG2_TX UCPD1_C UCPD1_C

D VBAT OTG2_ID
RTUNE C1 C2
PC11 PH9 PE6 PD2 PE7 PD15 PE9 PE1 PB6 PB0

VFBSMP VDDA18A
E V08CAP
S
BOOT0 NRST
ON
PC12 PH2 VSS VDDIO4 VDDIO4 PD14 PB7 PD9 PP2 PP4

VDDA18P VSSAPM
F MU U
PWR_ON PC13 VSSAON PD13 PO1 PP3 PO5 PO4

VSSSMP VSSSMP VSSSMP VSSSMP

G S S S S
VSS PO0 PP6 PP0 PP5

H VLXSMPS VLXSMPS VLXSMPS VLXSMPS VDD VDD PP1 PP7 PO2

VDDSMP VDDSMP VDDSMP VDDSMP VDDA18P

J S S S S LL
VDDIO2 VDDIO2 VDD PN4 PN8

K PF4 PF6 PF10 PG6 PG5 VDDIO3 PN1 PN5 PN7 PN6

VDDCOR VDDCOR VDDCOR VDDCOR

L PF5 PF3 PF2 PF14 VSS
E E E E
VSS VDDIO3 PN12 PN9 PN2 PN10

VDDA18A
M PF15 PF7 PF8 PF9 VSSA
DC
PG15 PG14 PA9 PA6 PA1 PB11 PN0 PN11 PN3

CSI_REX
N PF11 PF1 PF12 PF0
T
VDDCSI PA12 PA11 PA8 PG13 PA0 PB10 PB4 PG8 PA3

VDDA18C
P PF13 PG4 VREF- CSI_D1N CSI_CKN CSI_D0N
SI
PA10 PA2 PG12 PG10 PG2 PA7 PG11 PG0

R VSS PG3 VREF+ CSI_D1P CSI_CKP CSI_D0P PA14 PA13 PA5 PG1 PB12 PB5 PA15 PG9 VSS

MS56504V2

1. The above figure shows the package top view.

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STM32N6x5xx STM32N6x7xx

Figure 11. VFBGA223 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
OTG1_T OTG1_H UCPD1_ PH0-
A PDR_ON
XRTUNE SDP CC1 OSC_IN
PC12 PC1 PC6 PE13 PD6 PD12 PD15 PE8 PB15 PD5 PB13 PD11 PE0 VSS

PH1-
OTG1_H UCPD1_
B NC OTG1_ID
SDM CC2
OSC_OU
T
PC11 PH9 PC7 PE6 PD2 PE7 PD0 PD4 PD8 PB9 PB2 PB3 PE1 PE2

OTG2_H OTG2_H VDD33U

C SDP SDM SB
PB14 PE3 PB0

PC15-
VDDA18
D OSC32_
OUT
NC
USB
PC9 PC10 PH2 PE11 PE5 PE12 PD10 PD1 PD3 PE10 PB8 PD13 PP10 PB6

PC14-
OTG2_T
E OSC32_I
N
XRTUNE
OTG2_ID PB7 PO3 PP9

F VBAT NRST BOOT0 PC8 VDDIO4 VDDIO4 PE14 PE15 PD7 VSS PD14 PE9 PO0 PP1 PP8

VFBSMP
G V08CAP
S
PWR_ON VSSAON PD9 PO5 PO2 PP7

VDDA18 VSSAPM VDDA18

H PMU U
PC13
AON
VSS VDDIO2 PP0 PP6

VSSSMP VSSSMP VSSSMP VSSSMP VSSSMP

J S S S S S
VDD VDDIO2 PO4 PP5

VLXSMP VLXSMP VLXSMP VLXSMP VLXSMP

K S S S S S
VDD VDDIO2 PP2 PP3

VDDSMP VDDSMP VDDSMP VDDSMP VDDSMP

L S S S S S
VDD VDDIO2 PP15 PP4

VDDA18
M PF4 PF10 PF6
PLL
VDDIO3 VDDIO3 PP14 PP13

N PG6 PG5 PF5 VSSA PO1 VSS PP12 PP11

VDDA18 VDDCOR VDDCOR VDDCOR VDDCOR VDDCOR

P PF3 PF14 PF2
ADC E
VSS
E E E
VSS
E
VSS PN1 PN11 PN3

R PF15 PF7 PF8 PN7 PN10 PN0

CSI_REX
T PF11 PF9 PG4 PG3
T
PG14 PA11 PA8 PA6 PG1 PG10 PB10 PB5 PA15 PG0 PN9 PN2

U PF1 PF12 PF0 PA3 PN5 PN6

VDDA18
V PF13 VREF- CSI_D1N CSI_CKN CSI_D0N
CSI
PA14 PA12 PA9 PA5 PG12 PA0 PB11 PB1 PA7 PG9 PG8 PN8 PN4

W VSS VREF+ CSI_D1P CSI_CKP CSI_D0P VDDCSI PA13 PG15 PA10 PA2 PG13 PA1 PB12 PG2 PB4 PG11 PA4 PN12 VSS

MS56505V2

1. The above figure shows the package top view.

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Pinout, pin description and alternate functions STM32N6x5xx STM32N6x7xx

Figure 12. VFBGA264 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

OTG2_HS VDD33US OTG1_HS UCPD1_C PH0-

A PDR_ON PQ6 PC10 PC1 PC4 PE13 PE15 PD10 PD1 PE8 PE9 VSS
DM B DM C1 OSC_IN

OTG2_HS OTG1_HS UCPD1_C PH1-

B PH3 PH6 NC PC11 PC6 PC5 PE14 PE12 PE7 PD15 PD4 PE10 PB14
DP DP C2 OSC_OUT

PC15-
VDDA18U OTG1_TX
C OSC32_O PH8 OTG1_ID NC PC9 PC12 PC7 PC0 PE5 PD2 PD12 PD14 PB13 PB2 PD13
SB RTUNE
UT

PC14- OTG2_TX
D PH7 PQ3 PQ4 PQ5 PC8 PH9 PC2 PE4 PE6 PD6 PD0 PD5 PB9 PB8 PB15
OSC32_IN RTUNE

E VBAT PWR_ON PQ2 PQ1 PQ0 OTG2_ID PH2 VDDIO4 VDDIO5 PC3 PE11 PD7 PD3 PD8 PB0 PB7 PB6

VDDA18A
F V08CAP VSSAPMU PC13 PH4 PH5 VSS VDDIO4 VDDIO5 VSS VSS VSS PB3 PE3 PE2 PE0 PE1
ON

VDDA18P
G VFBSMPS NRST BOOT0 PQ7 VSSAON VSS VDD PD11 PP7 PP6 PP0
MU

H VSSSMPS VSSSMPS VSSSMPS VSSSMPS VSSSMPS VSSSMPS VDD VDD PD9 PP4 PP1 PP15

J VLXSMPS VLXSMPS VLXSMPS VLXSMPS VLXSMPS VLXSMPS VDD VDD PP5 PP12 PP3 PP2

K VDDSMPS VDDSMPS VDDSMPS VDDSMPS VDDSMPS VDDSMPS VSS VDD PP13 PO5 PO1 PO2

L PG7 PF4 PG6 PF10 PF6 VDDCORE VDDCORE VDDIO2 VDDIO2 PP11 PP8 PP14

VDDA18P
M PF7 PF3 PF5 PG5 VSSA VDDCORE VSS VDDCORE VSS VDDCORE VSS VSS VDDIO2 VDDIO2 PO3 PO0
LL

VDDA18A
N PF15 PF14 PF8 PF2 VSS VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDIO3 PP9 PP10 PO4 PN4
DC

P PF9 PG4 PF11 PF1 CSI_REXT PG14 PA9 PA6 PA1 PB11 VDDCORE PA15 VDDIO3 PN12 PN6 PN8 PN0

VDDA18C
R PG3 PF13 PF0 VDDCSI PG15 PA10 PA5 PG1 PB12 PB1 PA7 PG0 PA3 PN3 PN5 PN1
SI

T PF12 VREF- CSI_CKP CSI_D1P CSI_D0P PA14 PA11 PA2 PG12 PG10 PG2 PB4 PG9 PG8 PN9 PN7 PN2

U VSS VREF+ CSI_CKN CSI_D1N CSI_D0N PA13 PA12 PA8 PG13 PA0 PB10 PB5 PG11 PA4 PN10 PN11 VSS

MS56500V2

1. The above figure shows the package top view.

88/258 DS14791 Rev 3

STM32N6x5xx STM32N6x7xx

4.2 Pin description

Table 17. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
I Input only pin
Pin type O Output only pin
I/O Input/output pin
A Analog or special level pin
TT 3.3 V-tolerant I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Options for TT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
I/O structure _c I/O with USB Type-C power delivery function
_f I/O, Fm+ capable
_h I/O with high speed low voltage mode
_t I/O with tamper function functional in VBAT mode
_v I/O very high-speed capable
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the following table are a concatenation of various options. Examples: TT_a, TT_hat, TT_f.

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90/258

Pinout, pin description and alternate functions

Table 18. Pin description
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

R2 - N1 P3 V2 T2 VREF- S - - - --
P2 M1 M1 R3 W2 U2 VREF+ S - - - -
D2 D4 E3 F3 G4 E2 PWR_ON O - - - -
A1 A1 A1 A1 A1 A1 PDR_ON I - - - -
B2 D3 D3 E3 F4 G4 BOOT0 I - - - -
C2 E4 E4 E4 F2 G3 NRST I - - - -
DS14791 Rev 3

P5 M3 N3 P5 V4 U3 CSI_CKN A - - - -
R5 N3 P3 R5 W4 T3 CSI_CKP A - - - -
P6 M4 N4 P6 V5 U5 CSI_D0N A - - - -
R6 N4 P4 R6 W5 T5 CSI_D0P A - - - -
P4 M2 N2 P4 V3 U4 CSI_D1N A - - - -
R4 N2 P2 R4 W3 T4 CSI_D1P A - - - -
P7 N5 N5 N5 T6 P5 CSI_REXT A - - - -
A3 A3 A2 B2 C2 A3 OTG2_HSDM A - - - -

STM32N6x5xx STM32N6x7xx
B3 B3 B2 A2 C1 B3 OTG2_HSDP A - - - -
A2 B2 C5 D2 E4 E6 OTG2_ID A - - - -
C3 A2 C4 C2 D2 C4 NC - - - - -
D5 C3 B4 D3 E2 D6 OTG2_TXRTUNE A - - - -
A5 A5 A5 B4 B3 A5 OTG1_HSDM A - - - -
B5 B5 B5 A4 A3 B5 OTG1_HSDP A - - - -
B4 B4 B3 C4 B2 C3 OTG1_ID A - - - -
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

A4 A4 A3 A3 B1 B4 NC - - - - -
A6 A6 D5 C5 A2 C6 OTG1_TXRTUNE A - - - -
D6 B6 A6 D4 A4 A6 UCPD1_CC1 A - - - -
D7 C6 B6 D5 B4 B6 UCPD1_CC2 A - - - -
F3 E3 D2 E2 G2 G2 VFBSMPS S - - - -
TIM2_CH1, TIM5_CH1, TIM9_CH1, TIM15_BKIN,
ADC1_INP0,
SPI6_NSS/I2S6_WS,
ADC2_INP0,
R14 M9 P10 N11 V12 U10 PA0 I/O - - USART2_CTS/USART2_NSS, UART4_TX,
DS14791 Rev 3

ADC1_INN1,
SAI2_SD_B, SDMMC2_CMD,
ADC2_INN1, WKUP1
FMC_AD7/FMC_D7, LCD_G3, HDP0
TIM2_CH2, TIM5_CH2, LPTIM3_IN1,
TIM15_CH1N, USART2_RTS, UART4_RX,
P14 L9 L9 M11 W12 P9 PA1 I/O - - ADC1_INP1, ADC2_INP1
DCMIPP_D0/DCMI_D0/PSSI_D0, SAI2_MCLK_B,
FMC_AD6/FMC_D6, LCD_G2, HDP1
TIM2_CH3, TIM5_CH3, LPTIM3_IN2,
TIM15_CH1, USART2_TX, SAI2_SCK_B, ADC1_INP14,
P12 K8 N8 P9 W10 T8 PA2 I/O - -
MDIOS_MDIO, FMC_AD5/FMC_D5, LCD_B7, ADC2_INP14, WKUP2
HDP2

- - TIM16_CH1, SPI5_NSS, SAI1_SD_B, -

- N12 K11 N15 U17 R14 PA3 I/O
UART7_RX, FMC_A17/FMC_ALE, EVENTOUT

SPI5_MOSI, USART6_RX,
- - - - W17 U14 PA4 I/O - - DCMIPP_D3/DCMI_D3/PSSI_D3, FMC_A13, -
EVENTOUT
91/258
 Table 18. Pin description (continued)
92/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

PWR_CSTOP, TIM2_CH1, TIM2_ETR,

TIM9_CH2, I3C1_SCL, SPI1_SCK/I2S1_CK,
R12 M8 M8 R9 V10 R8 PA5 I/O - - SPI6_SCK/I2S6_CK, ADC2_INP18
DCMIPP_D8/DCMI_D8/PSSI_D8, TIM10_CH1,
FMC_NOE, LCD_CLK, HDP5
BOOT1, TIM1_BKIN, TIM3_CH1, LPTIM3_ETR,
I3C1_SDA, SPI1_MISO/I2S1_SDI,
SPI6_MISO/I2S6_SDI,
P13 N8 L8 M10 T10 P8 PA6 I/O - - ADC1_INP3, ADC2_INP3
DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK,
TIM13_CH1, MDIOS_MDC, LCD_B7,
DS14791 Rev 3

LCD_HSYNC, HDP6
TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SDO,
ADC1_INP14,
- - P12 P13 V15 R12 PA7 I/O - - USART1_RX, SPI6_MOSI/I2S6_SDO, LCD_R4,
ADC2_INP14, WKUP2
TIM14_CH1, FMC_RNB, LCD_B1, HDP7
MCO1, TIM1_CH1, I3C2_SCL, I2C3_SCL,
M11 L8 P8 N9 T9 U8 PA8 I/O - - USART1_CK, TIM11_CH1, UART7_RX, ADC1_INP5, ADC2_INP5
FMC_AD4/FMC_D4, LCD_B6, HDP0
TIM1_CH2, I3C2_SDA, LPUART1_TX, I2C3_SDA,
SPI2_SCK/I2S2_CK, USART1_TX, ADC1_INP10,
P11 M7 M7 M9 V9 P7 PA9 I/O - -
DCMIPP_D0/DCMI_D0/PSSI_D0, ADC2_INP10

STM32N6x5xx STM32N6x7xx
FMC_AD3/FMC_D3, LCD_B5, HDP1

PWR_CSLEEP, TIM1_CH3, LPUART1_RX, ADC1_INP11,

- - USART1_RX, DCMIPP_D1/DCMI_D1/PSSI_D1, ADC2_INP11,
R11 N7 N7 P8 W9 R7 PA10 I/O
MDIOS_MDIO, FMC_AD2/FMC_D2, LCD_B4, ADC1_INN10,
HDP2 ADC2_INN10

ADC1_INP12,
TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS,
- - ADC2_INP12,
R10 L7 M6 N8 T8 T7 PA11 I/O FDCAN1_RX, USART1_CTS/USART1_NSS,
ADC1_INN11,
UART4_RX, FMC_AD1/FMC_D1, LCD_B3, HDP3
ADC2_INN11
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

ADC1_INP13,
TIM1_ETR, LPUART1_RTS, SPI2_SCK/I2S2_CK,
- - ADC2_INP13,
P10 K7 L6 N7 V8 U7 PA12 I/O FDCAN1_TX, USART1_RTS, UART4_TX,
ADC1_INN12,
SAI2_FS_B, FMC_AD0/FMC_D0, LCD_B2, HDP4
ADC2_INN12

R9 M6 P7 R8 W7 U6 PA13 (JTMS/SWDIO) I/O - - JTMS/SWDIO, HDP5 -

R8 N6 P6 R7 V7 T6 PA14 (JTCK/SWCLK) I/O - - JTCK/SWCLK, HDP6 -

JTDI, TIM2_CH1, TIM2_ETR,

- - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, -
DS14791 Rev 3

L15 N11 N12 R13 T15 P12 PA15(JTDI) I/O

SPI6_NSS/I2S6_WS, UART4_RTS, UART7_TX,
FMC_D15/FMC_AD15, LCD_R5, HDP7

TRACED1, TIM1_CH4, SAI1_D2, ADF1_SDI0,

- - MDF1_SDI2, SPI4_NSS, SAI1_FS_A, -
C14 G12 G14 D15 C19 E15 PB0 I/O
TIM15_CH1N, DCMIPP_D4/DCMI_D4/PSSI_D4,
FMC_D13/FMC_AD13, EVENTOUT

TIM1_CH3N, TIM3_CH4, TIM9_CH2,

- - - - V14 R11 PB1 I/O - - FDCAN2_TX, USART2_TX, FMC_NOE, -
[RNG_S2], LCD_R1, HDP1

RTC_OUT2, TIM1_CH1, SAI1_D1, ADF1_SDI0,

- - E13 - B16 C16 PB2 I/O - - MDF1_SDI1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, -
FMC_D2/FMC_AD2, LCD_B2, HDP2

TRACECLK, TIM1_CH4N, GFXTIM_FCKCAL,

- E10 E12 A14 B17 F13 PB3 I/O - - MDF1_CKI1, USART1_CK, SAI2_FS_B, -
FMC_NBL1, GFXTIM_LCKCAL, FMC_A23, HDP0
93/258
 Table 18. Pin description (continued)
94/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

NJTRST, TIM16_BKIN, TIM3_CH1, LPTIM4_ETR,

SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI,
PB4 - SPI2_NSS/I2S2_WS, SPI6_MISO/I2S6_SDI, -
L14 M11 L11 N13 W15 T12 I/O -
(NJTRST) DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY,
UART7_TX, SDMMC2_D3,
FMC_D13/FMC_AD13, LCD_R3, HDP4

JTDO/TRACESWO, TIM17_BKIN, TIM3_CH2,

LPTIM4_OUT, I2C1_SMBA,
PB5 SPI1_MOSI/I2S1_SDO, FDCAN2_RX, -
DS14791 Rev 3

M15 L11 M11 R12 T14 U12 I/O - -

(JTDO/TRACESWO) SPI3_MOSI/I2S3_SDO, SPI6_MOSI/I2S6_SDO,
DCMIPP_D10/DCMI_D10/PSSI_D10, UART5_RX,
FMC_D12/FMC_AD12, LCD_R2, HDP5

TRACED2, SAI1_CK2, ADF1_CCK1,

MDF1_CCK1, SPI4_MISO, SAI1_SCK_A, -
D15 G11 H14 D14 D19 E17 PB6 I/O - -
TIM15_CH1, DCMIPP_D6/DCMI_D6/PSSI_D6,
FMC_D14/FMC_AD14, EVENTOUT

TRACED3, TIM1_BKIN2, SAI1_D1, ADF1_SDI0,

MDF1_SDI1, SPI4_MOSI, SAI1_SD_A,

STM32N6x5xx STM32N6x7xx
E12 G10 H13 E12 E16 E16 PB7 I/O - - TIM15_CH2, DCMIPP_D7/DCMI_D7/PSSI_D7, -
SAI2_MCLK_B, FMC_D15/FMC_AD15,
EVENTOUT

SPI1_MISO/I2S1_SDI, USART6_RX,
SPDIFRX1_IN3,
- - - - D15 D16 PB8 I/O - - DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY, -
SAI2_FS_B, SDMMC2_D0, FMC_D1/FMC_AD1,
EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

LPTIM1_IN2, SPI1_SCK/I2S1_CK, USART10_TX,

SPDIFRX1_IN0, -
- - - - B15 D15 PB9 I/O - -
DCMIPP_D3/DCMI_D3/PSSI_D3, SDMMC2_D2,
FMC_D3/FMC_AD3, EVENTOUT
TIM2_CH3, I3C2_SCL, LPTIM2_IN1, I2C2_SCL, ADC1_INP8,
N15 M10 P11 N12 T13 U11 PB10 I/O - - SPI2_SCK/I2S2_CK, USART3_TX, ADC2_INP8,
FMC_D11/FMC_AD11, LCD_G7, HDP2 ADC1_INN4, ADC2_INN4
TIM2_CH4, I3C2_SDA, LPTIM2_ETR, I2C2_SDA,
N14 L10 L10 M12 V13 P10 PB11 I/O - - USART3_RX, FMC_D10/FMC_AD10, LCD_G6, ADC1_INP4, ADC2_INP4
DS14791 Rev 3

HDP3
TIM1_BKIN, LPTIM2_IN2, I2C2_SMBA,
N13 K10 M10 R11 W13 R10 PB12 I/O - - SPI2_NSS/I2S2_WS, FDCAN2_RX, USART3_CK, -
UART5_RX, FMC_D9/FMC_AD9, LCD_G5, HDP4
TRACED0, LPTIM1_CH1, TIM8_CH3N,
SPI6_SCK/I2S6_CK,
- - - - A16 C15 PB13 I/O - - USART10_CTS/USART10_NSS, -
USART6_CTS/USART6_NSS, SDMMC2_D6,
FMC_D5/FMC_AD5, LCD_CLK, EVENTOUT
LPTIM1_CH2, TIM8_CH4N, USART10_CK,
USART6_CTS/USART6_NSS,
- - - - C17 B17 PB14 I/O - - -
DCMIPP_D10/DCMI_D10/PSSI_D10,
FMC_D7/FMC_AD7, LCD_HSYNC, EVENTOUT
SPI6_NSS/I2S6_WS, USART6_RTS,
- - - - A14 D17 PB15 I/O - - SPDIFRX1_IN2, FMC_D0/FMC_AD0, LCD_G4, -
EVENTOUT
95/258
 Table 18. Pin description (continued)
96/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TIM2_CH2, LPTIM4_IN1, MDF1_CKI1,

SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK,
- - SPI6_SCK/I2S6_CK, -
- - - - - C10 PC0 I/O
DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE,
UART7_RX, SDMMC2_D2,
FMC_D14/FMC_AD14, LCD_R4, HDP3

TIM17_CH1, TIM4_CH4, I2C1_SDA,

SPI2_NSS/I2S2_WS, FDCAN1_TX, I3C1_SDA,
- - B8 C7 A7 A9 PC1 I/O - - UART4_TX, DCMIPP_D7/DCMI_D7/PSSI_D7, -
DS14791 Rev 3

SDMMC1_D5, SDMMC2_D5, SDMMC1_CDIR,

HDP1

SAI1_D1, ADF1_SDI0, MDF1_SDI1,

SPI3_MOSI/I2S3_SDO, SAI1_SCK_A,
- - USART2_RX, -
- - - - - D9 PC2 I/O
DCMIPP_D13/DCMI_D13/PSSI_D13,
SDMMC2_CK(boot), FMC_NE3, FMC_RNB,
EVENTOUT

SPI1_MOSI/I2S1_SDO, USART2_CK,

STM32N6x5xx STM32N6x7xx
SPDIFRX1_IN0,
- - - - - E10 PC3 I/O - - DCMIPP_D2/DCMI_D2/PSSI_D2, -
SDMMC2_CMD(boot), FMC_D8/FMC_AD8,
EVENTOUT

TIM1_CH2N, TIM12_CH1, LPTIM2_CH2,

- - USART1_TX, SPI2_MISO/I2S2_SDI, -
- - - - - A10 PC4 I/O
USART3_RTS, UART4_RTS, LCD_VSYNC,
SDMMC2_D0(boot), FMC_NE1, LCD_DE, HDP6
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

SPI1_NSS/I2S1_WS,
- - - - - B10 PC5 I/O - - DCMIPP_D2/DCMI_D2/PSSI_D2, SAI2_SD_B, -
SDMMC2_D1, FMC_NWE, EVENTOUT

TIM1_CH1, TIM3_CH1, TIM9_CH1, I2S2_MCK,

- - USART6_TX, DCMIPP_D1/DCMI_D1/PSSI_D1, -
- - A8 B7 A8 B9 PC6 I/O
SDMMC1_D6, SDMMC2_D6, SDMMC1_D0DIR,
HDP6

DBTRGIO, TIM16_CH1N, TIM3_CH2, TIM9_CH2,

DS14791 Rev 3

- - I2S3_MCK, USART6_RX, -
- - A9 A7 B8 C9 PC7 I/O
DCMIPP_D1/DCMI_D1/PSSI_D1, SDMMC1_D7,
SDMMC2_D7, SDMMC1_D123DIR, HDP7

TRACED1, TIM3_CH3, I2C3_SMBA,

UCPD1_FRSTX1, USART6_CK,
A8 D7 C6 C6 F6 D7 PC8 I/O - - DCMIPP_D2/DCMI_D2/PSSI_D2, -
SDMMC1_D0(boot), UART5_RTS, FMC_NE4,
LCD_B0, HDP0

MCO2, TIM3_CH4, I2C3_SDA, AUDIOCLK,

- - UCPD1_FRSTX2, USART6_RX, -
B8 C7 D6 B6 D5 C7 PC9 I/O
DCMIPP_D3/DCMI_D3/PSSI_D3, SDMMC1_D1,
UART5_CTS, LCD_B3, HDP1
TIM1_BKIN, I3C2_SCL, I2C4_SCL,
- - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, -
A9 D6 D8 A6 D6 A8 PC10 I/O
DCMIPP_D14/PSSI_D14, SDMMC1_D2,
FMC_CLK, HDP2
97/258
 Table 18. Pin description (continued)
98/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

I3C2_SDA, I2C4_SDA, SPI3_MISO/I2S3_SDI,

- - USART3_RX, UART4_RX, -
B9 A8 C7 D6 B6 B8 PC11 I/O
DCMIPP_D4/DCMI_D4/PSSI_D4, SDMMC1_D3,
HDP3

TRACED3, TIM1_CH4, TIM15_CH1,

- - SPI6_SCK/I2S6_CK, SPI3_MOSI/I2S3_SDO, -
A10 B8 D7 E6 A6 C8 PC12 I/O
USART3_CK, DCMIPP_D9/DCMI_D9/PSSI_D9,
SDMMC1_CK(boot), UART5_TX, FMC_NL, HDP4
DS14791 Rev 3

TAMP_IN1/TAMP_OUT2,
E2 D2 C3 F4 H4 F3 PC13 I/O - - HDP5 RTC_OUT1/RTC_TS,
WKUP3
PC14-OSC32_IN - - -
C1 B1 B1 C1 E1 D1 I/O OSC32_IN
(OSC32_IN)

PC15-OSC32_OUT - -
B1 C1 C1 B1 D1 C1 I/O OSC32_OUT
(OSC32_OUT)

TIM1_ETR, FDCAN1_RX, UART9_CTS,

- - UART4_RX, -
- B12 A12 C11 B12 D13 PD0 I/O

STM32N6x5xx STM32N6x7xx
DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE,
FMC_A6, FMC_A22, EVENTOUT

- - FDCAN1_TX, UART4_TX, ETH1_MDC, FMC_A7, -

B12 A12 B12 B11 D12 A14 PD1 I/O
FMC_A23, EVENTOUT

TRACED0, TIM1_CH3, SAI1_D1, ADF1_SDI0,

- - MDF1_SDI1, SPI2_MOSI/I2S2_SDO, SAI1_SD_A,
- C10 E10 D9 B10 C12 PD2 I/O WKUP4
TIM15_CH1N, MDIOS_MDC, SDMMC2_CK,
FMC_A0, FMC_A16/FMC_CLE, HDP1
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

I2C2_SMBA, USART10_RX, USART6_CTS,

- C12 A13 A12 D13 E13 PD3 I/O - - DCMIPP_D14/PSSI_D14, ETH1_PHY_INTN, -
FMC_A10, EVENTOUT

TIM1_BKIN2, I2C2_SDA, SPI5_MISO,

- D13 B13 B12 B13 B15 PD4 I/O - - USART6_RTS, DCMIPP_D9/DCMI_D9/PSSI_D9, TAMP_IN7/TAMP_OUT8
FMC_A11, EVENTOUT

TIM1_CH4N, USART2_TX,
- - D14 C13 A15 D14 PD5 I/O - - DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK, -
DS14791 Rev 3

SDMMC2_D7, FMC_D6/FMC_AD6, EVENTOUT

- TIM1_CH1, TIM15_CH2, SPI2_MISO/I2S2_SDI, -

- D10 A11 A10 A10 D12 PD6 I/O -
FMC_A1, FMC_A17/FMC_ALE, HDP2
TIM1_CH2, TIM15_CH1N,
- SPI2_MOSI/I2S2_SDO, SPI3_NSS/I2S3_WS, -
- A11 B11 B10 F11 E12 PD7 I/O -
DCMIPP_D0/DCMI_D0/PSSI_D0, FMC_A2,
FMC_A18, HDP3

USART3_TX, SPDIFRX1_IN1,
C13 E11 D13 B13 B14 E14 PD8 I/O - - DCMIPP_D11/DCMI_D11/PSSI_D11, FMC_NBL0, TAMP_IN3/TAMP_OUT4
LCD_R7, EVENTOUT

USART3_RX,
- - H12 E13 G14 H14 PD9 I/O - - DCMIPP_D11/DCMI_D11/PSSI_D11, TAMP_IN5/TAMP_OUT6
FMC_SDCLK, LCD_R1, EVENTOUT

TRACECLK, TIM1_ETR, MDF1_CKI3, I2S1_MCK,

- B11 C11 C10 D11 A13 PD10 I/O - - UCPD1_FRSTX1, SPDIFRX1_IN2, SAI2_FS_B, -
FMC_A3, GFXTIM_TE, FMC_A19, HDP4
99/258
 Table 18. Pin description (continued)
100/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

I2C4_SDA, SPI2_MISO/I2S2_SDI,
- F13 F11 B14 A17 G14 PD11 I/O - - UCPD1_FRSTX1, DCMIPP_D15/PSSI_D15, -
SDMMC1_D0, FMC_D8/FMC_AD8, EVENTOUT

SAI1_D3, MDF1_SDI3, UCPD1_FRSTX2,

- SPDIFRX1_IN3, -
- D11 E11 A11 A11 C13 PD12 I/O -
DCMIPP_D12/DCMI_D12/PSSI_D12,
ETH1_MDIO, FMC_A5, FMC_A21, HDP5

LPTIM1_CH1, TIM4_CH2, UCPD1_FRSTX2,

DS14791 Rev 3

UART9_RTS,
- - E14 F11 D16 C17 PD13 I/O - - DCMIPP_D13/DCMI_D13/PSSI_D13, -
SAI2_SCK_A, FMC_D4/FMC_AD4, LCD_R6,
EVENTOUT

- C13 D12 E11 F13 C14 PD14 I/O - - I2C2_SCL, USART10_RX, FMC_A9, EVENTOUT -

- - I2C2_SDA, USART10_TX, FMC_A8, LCD_R2, -

- B13 C12 D11 A12 B14 PD15 I/O
EVENTOUT

LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR,

- - USART3_RX, UART8_RX,
A14 F12 F12 C14 A18 F16 PE0 I/O TAMP_IN6/TAMP_OUT5

STM32N6x5xx STM32N6x7xx
DCMIPP_D2/DCMI_D2/PSSI_D2, SAI2_MCLK_A,
FMC_D9/FMC_AD9, EVENTOUT

LPTIM1_IN2, LPTIM2_CH2, USART3_TX,

B14 F11 F13 D13 B18 F17 PE1 I/O - - UART8_TX, DCMIPP_D8/DCMI_D8/PSSI_D8, -
FMC_D10/FMC_AD10, EVENTOUT

TRACECLK, LPTIM5_IN1, SAI1_CK1,

- - ADF1_CCK0, MDF1_CCK0, SPI4_SCK, -
B15 F10 F14 B15 B19 F15 PE2 I/O
SAI1_MCLK_A, UCPD1_FRSTX1,
FMC_D11/FMC_AD11, TIM1_CH2N, EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TRACED0, LPTIM5_ETR, MDF1_CKI2,

C15 G13 G13 C15 C18 F14 PE3 I/O - - SAI1_SD_B, TIM15_BKIN, FMC_D12/FMC_AD12, -
EVENTOUT

LPTIM1_IN1, SPI6_MISO/I2S6_SDI,
- USART10_RX, USART6_RTS, SPDIFRX1_IN1, -
- - - - - D10 PE4 I/O -
DCMIPP_D5/DCMI_D5/PSSI_D5, SDMMC2_D3,
FMC_RNB, LCD_G1, EVENTOUT

TIM16_CH1N, TIM4_CH1, LPUART1_TX,

DS14791 Rev 3

I2C1_SCL, I3C1_SCL, FDCAN2_TX,

- C9 D9 C8 D9 C11 PE5 I/O - - USART1_TX(boot), -
DCMIPP_D5/DCMI_D5/PSSI_D5, UART5_TX,
FMC_SDNE1, HDP6

TIM17_CH1N, TIM4_CH2, LPUART1_RX,

I2C1_SDA, I3C1_SDA, USART1_RX(boot),
- - A10 D8 B9 D11 PE6 I/O - - DCMIPP_VSYNC/DCMI_VSYNC/PSSI_RDY, -
DCMIPP_D1/DCMI_D1/PSSI_D1, UART5_TX,
FMC_SDCKE1, HDP7

- TIM1_ETR, MDF1_CKI0, UART7_RX, -

A12 C11 D11 D10 B11 B13 PE7 I/O -
SAI2_SD_B, FMC_A4, FMC_A20, EVENTOUT

TIM1_CH1N, MDF1_SDI0, USART3_TX,

D12 D12 C13 C12 A13 A15 PE8 I/O - - UART7_TX, DCMIPP_D4/DCMI_D4/PSSI_D4, -
FMC_A12, EVENTOUT

- TIM1_CH1, MDF1_CKI4, UART7_RTS, -

A13 E13 B14 D12 F14 A16 PE9 I/O -
FMC_A14/FMC_BA0, EVENTOUT
101/258
 Table 18. Pin description (continued)
102/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TRACECLK, TIM1_CH2N, MDF1_SDI4,

- USART3_RX, UART7_CTS, -
B13 E12 C14 A13 D14 B16 PE10 I/O -
DCMIPP_D3/DCMI_D3/PSSI_D3,
FMC_A15/FMC_BA1, EVENTOUT

TIM1_CH2, MDF1_CKI5, SPI4_NSS,

- A9 B9 A8 D8 E11 PE11 I/O - - FDCAN3_TX, SAI2_SD_B, FMC_SDNWE, -
LCD_VSYNC, EVENTOUT

TIM1_CH3N, MDF1_SDI5, SPI4_SCK,

- -
DS14791 Rev 3

B11 B10 D10 C9 D10 B12 PE12 I/O - FDCAN3_RX, SAI2_SCK_B, FMC_NRAS,
EVENTOUT

- TIM1_CH3, ADF1_CCK0, I2C4_SCL, SPI4_MISO, -

A11 A10 C10 B9 A9 A11 PE13 I/O -
SAI2_FS_B, FMC_NCAS, EVENTOUT

TIM1_CH4, GFXTIM_FCKCAL, ADF1_CCK1,

- I2C4_SDA, SPI4_MOSI, SAI2_MCLK_B, -
D10 B9 C9 B8 F9 B11 PE14 I/O -
FMC_SDNE0, GFXTIM_LCKCAL, FMC_NWE,
EVENTOUT

TIM1_BKIN, GFXTIM_LCKCAL, I2C4_SMBA,

STM32N6x5xx STM32N6x7xx
- SPI5_SCK, USART10_CK, USART2_CK, -
D11 D9 B10 A9 F10 A12 PE15 I/O -
SDMMC1_D0, FMC_SDCKE0, GFXTIM_FCKCAL,
EVENTOUT
LPTIM5_OUT, TIM4_CH4, UCPD1_FRSTX2,
UART9_TX, UART8_RTS,
- - - N4 U3 R3 PF0 I/O - - DCMIPP_D9/DCMI_D9/PSSI_D9, -
ETH1_MII_TX_CLK, ETH1_RGMII_GTX_CLK,
EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

LPTIM1_CH2, TIM4_CH3, LPTIM2_CH1,

UCPD1_FRSTX1, UART9_RX, UART8_CTS,
- - - N2 U1 P4 PF1 I/O - - -
DCMIPP_D7/DCMI_D7/PSSI_D7, ETH1_TX_ER,
EVENTOUT
TIM1_CH3N, SPI2_SCK/I2S2_CK, FDCAN3_TX,
USART2_CTS/USART2_NSS,
L1 K1 K1 L3 P4 N4 PF2 I/O - - -
ETH1_RGMII_CLK125, FMC_NWAIT, LCD_B1,
EVENTOUT
FDCAN3_RX, USART2_RTS,
DS14791 Rev 3

DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE,
L4 J4 J5 L2 P1 M2 PF3 I/O - - ADC1_INP16
ETH1_PPS_OUT, FMC_NL, LCD_R4,
EVENTOUT
TIM5_ETR, LPTIM3_CH2, SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS, USART2_CK,
K1 J1 J1 K1 M1 L2 PF4 I/O - - SPI6_NSS/I2S6_WS, ADC1_INP18
DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE,
ETH1_MDIO, LCD_R3, HDP4
TIM1_ETR, LPTIM2_IN2,
USART3_CTS/USART3_NSS,
K3 J3 J4 L1 N4 M3 PF5 I/O - - -
DCMIPP_D6/DCMI_D6/PSSI_D6, SAI2_SD_A,
ETH1_CLK, FMC_NE3, LCD_G0, EVENTOUT
TIM2_CH4, TIM5_CH4, LPTIM3_CH1,
TIM15_CH2, I2S6_MCK, SPI4_RDY,
ADC1_INP15,
- - J2 K2 M4 L5 PF6 I/O - - USART2_RX(boot), GFXTIM_LCKCAL,
ADC2_INP15
SPI5_RDY, SPI1_RDY, ETH1_MII_COL,
GFXTIM_FCKCAL, TIM1_CH3, LCD_DE, HDP3
103/258
 Table 18. Pin description (continued)
104/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TIM1_CH2N, TIM3_CH3, TIM9_CH1,

SPI1_SCK/I2S1_CK, UART4_CTS, ADC1_INP9,
M2 K4 K4 M2 R2 M1 PF7 I/O - - ETH1_MII_RX_CLK/ETH1_RMII_REF_CLK/ETH1 ADC2_INP9,
_RGMII_RX_CLK, GFXTIM_TE, [RNG_S1], ADC1_INN5, ADC2_INN5
LCD_VSYNC, HDP0
TRACECLK, UART9_TX,
N1 L1 L1 M3 R4 N3 PF8 I/O - - ETH1_MII_RXD2/ETH1_RGMII_RXD2, -
FMC_NWE, LCD_R6, EVENTOUT
TRACED0,
DS14791 Rev 3

- - - M4 T2 P1 PF9 I/O - - ETH1_MII_RXD3/ETH1_RGMII_RXD3, -

LCD_HSYNC, EVENTOUT
TIM16_BKIN, SAI1_D3, MDF1_SDI3,
UCPD1_FRSTX1, UART7_RX,
DCMIPP_D11/DCMI_D11/PSSI_D11,
K2 J2 J3 K3 M2 L4 PF10 I/O - - -
DCMIPP_D15/PSSI_D15,
ETH1_MII_RX_DV/ETH1_RMII_CRS_DV/ETH1_
RGMII_RX_CTL, LCD_R1, EVENTOUT
SPI5_MOSI, DCMIPP_D15/PSSI_D15,
SAI2_SD_B,
N2 L2 L2 N1 T1 P3 PF11 I/O - ADC1_INP2
ETH1_MII_TX_EN/ETH1_RMII_TX_EN/ETH1_RG

STM32N6x5xx STM32N6x7xx
MII_TX_CTL, LCD_B0, EVENTOUT
USART1_RX, SPI5_MISO,
DCMIPP_D13/DCMI_D13/PSSI_D13,
P1 L3 L3 N3 U2 T1 PF12 I/O - - ADC1_INP6, ADC1_INN2
ETH1_MII_TXD0/ETH1_RMII_TXD0/ETH1_RGMII
_TXD0, EVENTOUT
USART1_TX, SPI5_NSS,
DCMIPP_D10/DCMI_D10/PSSI_D10,
N3 L4 M2 P1 V1 R2 PF13 I/O - - ADC2_INP2
ETH1_MII_TXD1/ETH1_RMII_TXD1/ETH1_RGMII
_TXD1, EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TIM2_CH2, USART1_CTS, SPI5_MOSI,

L2 K2 K2 L4 P2 N2 PF14 I/O - - ETH1_MII_RXD0/ETH1_RMII_RXD0/ETH1_RGMI ADC2_INP6, ADC2_INN2
I_RXD0, LCD_G0, EVENTOUT
USART1_RTS, SPI5_SCK,
M1 K3 K3 M1 R1 N1 PF15 I/O - - ETH1_MII_RXD1/ETH1_RMII_RXD1/ETH1_RGMI -
I_RXD1, LCD_G1, EVENTOUT
TIM1_CH4N, TIM12_CH1, UART9_RX,
- - M12 P15 T16 R13 PG0 I/O - - LCD_VSYNC, ETH1_PHY_INTN, LCD_R0, -
EVENTOUT
DS14791 Rev 3

TIM16_CH1N, SPI5_MISO, SAI1_SCK_B,

UART7_RTS,
- - M9 R10 T11 R9 PG1 I/O - - -
DCMIPP_PIXCLK/DCMI_PIXCLK/PSSI_PDCK,
TIM13_CH1, FMC_A19, LCD_G1, EVENTOUT
TIM17_CH1N, SPI5_MOSI, SAI1_FS_B,
USART3_RTS, UART7_CTS,
M14 N10 N11 P12 W14 T11 PG2 I/O - - -
DCMIPP_D6/DCMI_D6/PSSI_D6, SAI2_MCLK_B,
TIM14_CH1, FMC_A21, LCD_R0, EVENTOUT
TRACED1, USART2_TX,
DCMIPP_HSYNC/DCMI_HSYNC/PSSI_DE,
- - - R2 T5 R1 PG3 I/O - - -
ETH1_MII_TXD2/ETH1_RGMII_TXD2,
EVENTOUT
TIM1_BKIN2,
- - - P2 T4 P2 PG4 I/O - - ETH1_MII_TXD3/ETH1_RGMII_TXD3, LCD_B0, -
EVENTOUT
TIM1_ETR, USART2_CTS/USART2_NSS,
- - - K5 N2 M4 PG5 I/O - - -
ETH1_MII_RX_ER, LCD_B1, EVENTOUT
TIM17_BKIN, USART6_CK,
105/258

- - - K4 N1 L3 PG6 I/O - - DCMIPP_D12/DCMI_D12/PSSI_D12, -

ETH1_MII_CRS, LCD_B3, EVENTOUT
 Table 18. Pin description (continued)
106/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TRACECLK, SAI1_MCLK_A, USART6_CK,

- - - - - L1 PG7 I/O - - DCMIPP_D13/DCMI_D13/PSSI_D13, -
ETH1_PHY_INTN, EVENTOUT

RTC_REFIN, TIM1_CH3N, TIM12_CH2,

- - USART1_RX, SPI2_MOSI/I2S2_SDO,
- - L12 N14 V17 T14 PG8 I/O PVD_IN
SAI1_SCK_B, UART4_CTS, SDMMC2_D1,
FMC_A20, LCD_G7, HDP7
- (1) -
- - - R14 V16 T13 PG9 I/O FMC_D8/FMC_AD8, LCD_R7, EVENTOUT
DS14791 Rev 3

TIM1_CH1N, LPTIM2_CH1, SPI2_SCK/I2S2_CK,

- - FDCAN2_TX, USART3_CTS/USART3_NSS, -
P15 N9 N10 P11 T12 T10 PG10 I/O
DCMIPP_D2/DCMI_D2/PSSI_D2, UART5_TX,
FMC_A16/FMC_CLE, LCD_G4, HDP5
(1)
- - - P14 W16 U13 PG11 I/O - UART7_RX, ETH1_MDC, LCD_R6, EVENTOUT -

- - TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, -

- - N9 P10 V11 T9 PG12 I/O
UART7_TX, FMC_A18, LCD_G0, EVENTOUT

LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,

USART3_RTS,

STM32N6x5xx STM32N6x7xx
R13 K9 P9 N10 W11 U9 PG13 I/O - - -
DCMIPP_D12/DCMI_D12/PSSI_D12, SAI2_FS_A,
FMC_NE1, LCD_DE, EVENTOUT

TRACED1, LPTIM1_ETR, TIM8_CH4,

SPI6_MOSI/I2S6_SDO, USART10_RTS,
P9 K6 L5 M8 T7 P6 PG14 I/O - - USART6_TX, USART2_RTS, -
DCMIPP_D11/DCMI_D11/PSSI_D11, FMC_NCE,
FMC_NE2, LCD_B1, EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

TIM1_CH4, SPI5_RDY, SPI4_RDY, USART3_CK,

ADC1_INP7,
- - DCMIPP_D4/DCMI_D4/PSSI_D4, SPI1_RDY,
- - M5 M7 W8 R6 PG15 I/O ADC2_INP7,
ETH1_MII_RX_CLK/ETH1_RMII_REF_CLK,
ADC1_INN3, ADC2_INN3
FMC_CLK, LCD_B0, EVENTOUT

A7 B7 B7 A5 A5 A7 PH0-OSC_IN(PH0) I/O - - EVENTOUT OSC_IN

B7 A7 A7 B5 B5 B7 PH1-OSC_OUT(PH1) I/O - - EVENTOUT OSC_OUT

TRACED2, TIM1_ETR, TIM3_ETR, TIM15_BKIN,

FDCAN1_TX,
DS14791 Rev 3

B10 C8 E6 E7 D7 E7 PH2 I/O - - DCMIPP_D11/DCMI_D11/PSSI_D11, -

SDMMC1_CMD(boot), UART5_RX, FMC_NE3,
EVENTOUT
- (1)
- - - - - B1 PH3 I/O TRACECLK, UART7_TX, LCD_B4, EVENTOUT -
(1)
- - - - - F4 PH4 I/O - UART7_TX, LCD_R4, EVENTOUT TAMP_IN4/TAMP_OUT3

- - - - - F5 PH5 I/O - - SPI5_SCK, ETH1_MDC, EVENTOUT -

- - - - - B2 PH6 I/O - - SPI5_NSS, LCD_B5, EVENTOUT -

(1)
- - - - - D2 PH7 I/O - I3C2_SCL, SPI5_MOSI, EVENTOUT -
(1)
- - - - - C2 PH8 I/O I3C2_SDA, SPI5_MISO, EVENTOUT -

TIM16_CH1, TIM4_CH3, USART3_CK,

I2C1_SCL, FDCAN1_RX, I3C1_SCL, UART4_RX,
- - C8 D7 B7 D8 PH9 I/O - - DCMIPP_D6/DCMI_D6/PSSI_D6, SDMMC1_D4, -
SDMMC2_D4, SDMMC1_CKIN,
FMC_D9/FMC_AD9, HDP0

J15 J13 M13 M13 R19 P17 PN0 I/O - - XSPIM_P2_DQS0(boot), FMC_A25, EVENTOUT -
107/258

D14 H13 P13 K12 P16 R17 PN1 I/O - - XSPIM_P2_NCS1(boot), FMC_A24, EVENTOUT -
 Table 18. Pin description (continued)
108/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

H15 J11 L13 L14 T19 T17 PN2 I/O - - XSPIM_P2_IO0(boot), FMC_A23, EVENTOUT -

K15 H12 N13 M15 P19 R15 PN3 I/O - - XSPIM_P2_IO1(boot), FMC_A22, EVENTOUT -

E14 L12 J13 J14 V19 N17 PN4 I/O - - XSPIM_P2_IO2(boot), EVENTOUT -

F15 L13 K14 K13 U18 R16 PN5 I/O - - XSPIM_P2_IO3(boot), EVENTOUT -

G15 K12 K12 K15 U19 P15 PN6 I/O - - XSPIM_P2_CLK(boot), EVENTOUT -

F14 K11 K13 K14 R16 T16 PN7 I/O - - XSPIM_P2_NCLK(boot), EVENTOUT -

- - -
DS14791 Rev 3

E15 M13 J14 J15 V18 P16 PN8 I/O XSPIM_P2_IO4(boot), EVENTOUT

- - XSPIM_P2_IO5(boot), -
G14 K13 L14 L13 T18 T15 PN9 I/O
DCMIPP_D5/DCMI_D5/PSSI_D5, EVENTOUT

H14 J12 M14 L15 R18 U15 PN10 I/O - - XSPIM_P2_IO6(boot), LCD_B4, EVENTOUT -

J14 H11 N14 M14 P18 U16 PN11 I/O - - XSPIM_P2_IO7(boot), LCD_B6, EVENTOUT -

K14 M12 J12 L12 W18 P14 PN12 I/O - - XSPIM_P2_NCS2, EVENTOUT -

- - - G12 F16 M17 PO0 I/O - - XSPIM_P1_NCS1, FMC_A22, EVENTOUT -

- - - F12 N14 K16 PO1 I/O - - XSPIM_P1_NCS2, FMC_A23, EVENTOUT -

STM32N6x5xx STM32N6x7xx
- - XSPIM_P1_DQS0, FMC_A24, LCD_B7, -
- - - H15 G18 K17 PO2 I/O
EVENTOUT

- - XSPIM_P1_DQS1, FMC_A25, LCD_G3, -

- - - - E18 M16 PO3 I/O
EVENTOUT

- - XSPIM_P1_CLK, LCD_B4, FMC_A24, -

- - - F15 J18 N16 PO4 I/O
FMC_NBL2, EVENTOUT

- - XSPIM_P1_NCLK, FMC_A25, FMC_NBL3, -

- - - F14 G16 K15 PO5 I/O
EVENTOUT
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

- - - G14 H18 G17 PP0 I/O - - XSPIM_P1_IO0, FMC_D16, EVENTOUT -

- - - H13 F18 H16 PP1 I/O - - XSPIM_P1_IO1, FMC_D17, EVENTOUT -

- - - E14 K18 J17 PP2 I/O - - XSPIM_P1_IO2, FMC_D18, EVENTOUT -

- - - F13 K19 J16 PP3 I/O - - XSPIM_P1_IO3, FMC_D19, EVENTOUT -

- - - E15 L19 H15 PP4 I/O - - XSPIM_P1_IO4, FMC_D20, EVENTOUT -

- - - G15 J19 J14 PP5 I/O - - XSPIM_P1_IO5, FMC_D21, EVENTOUT -

- - -
DS14791 Rev 3

- - - G13 H19 G16 PP6 I/O XSPIM_P1_IO6, FMC_D22, EVENTOUT

- - - H14 G19 G15 PP7 I/O - - XSPIM_P1_IO7, FMC_D23, EVENTOUT -

- - SPI2_MISO, XSPIM_P1_IO8, FMC_D24, -

- - - - F19 L16 PP8 I/O
EVENTOUT

- - SPI2_MOSI, XSPIM_P1_IO9, FMC_D25, -

- - - - E19 N14 PP9 I/O
EVENTOUT

- - XSPIM_P1_IO10, ETH1_MDC, FMC_D26, -

- - - - D18 N15 PP10 I/O
EVENTOUT

- - - - N19 L15 PP11 I/O - XSPIM_P1_IO11, FMC_D27, EVENTOUT -

- - - - N18 J15 PP12 I/O - - XSPIM_P1_IO12, FMC_D28, EVENTOUT -

- - - - M19 K14 PP13 I/O - - XSPIM_P1_IO13, FMC_D29, EVENTOUT -

- - - - M18 L17 PP14 I/O - - XSPIM_P1_IO14, FMC_D30, EVENTOUT -

- - XSPIM_P1_IO15, FMC_D31, LCD_B5, -

- - - - L18 H17 PP15 I/O
EVENTOUT
109/258

- - - - - E5 PQ0 I/O - - TRACECLK, TIM8_ETR, EVENTOUT -

 Table 18. Pin description (continued)
110/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

- - - - - E4 PQ1 I/O - - TIM8_BKIN, EVENTOUT -

- - - - - E3 PQ2 I/O - - TIM8_BKIN2, SAI2_SCK_B, EVENTOUT -

- - - - - D3 PQ3 I/O - - TIM8_CH1, EVENTOUT -

- - - - - D4 PQ4 I/O - - TIM8_CH1N, EVENTOUT -

- - - - - D5 PQ5 I/O - - TIM8_CH2, SAI2_FS_B, EVENTOUT -

- - - - - A2 PQ6 I/O - - TIM8_CH2N, SAI2_SD_B, EVENTOUT -

- -
DS14791 Rev 3

- - - - - G5 PQ7 I/O TIM8_CH3, SAI2_MCLK_B, EVENTOUT TAMP_IN2/TAMP_OUT1

D1 C2 C2 D1 F1 E1 VBAT S - - - -

K4 J5 L4 J5 M6 M5 VDDA18PLL S - - - -

- - - J11 H16 L13 VDDIO2 S - - - -

- - - J12 J16 L14 VDDIO2 S - - - -

- - - - K16 M14 VDDIO2 S - - - -

- - - - L16 M15 VDDIO2 S - - - -

STM32N6x5xx STM32N6x7xx
K12 H10 J10 K11 M14 N13 VDDIO3 S - - - -

L12 J10 J11 L11 M16 P13 VDDIO3 S - - - -

D8 D8 E8 E9 F7 E8 VDDIO4 S - - - -

- - E9 E10 F8 F8 VDDIO4 S - - - -

- - - - - E9 VDDIO5 S - - - -

- - - - - F9 VDDIO5 S - - - -

P8 L6 N6 N6 W6 R4 VDDCSI S - - - -
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

R7 M5 P5 P7 V6 R5 VDDA18CSI S - - - -

F1 E1 E1 F1 H1 G1 VDDA18PMU S - - - -

F2 E2 E2 F2 H2 F2 VSSAPMU S - - - -

J1 H1 H1 J1 L1 K1 VDDSMPS S - - - -

G1 F1 F1 G1 J1 H1 VSSSMPS S - - - -

J2 H2 H2 J2 L2 K2 VDDSMPS S - - - -

- - - -
DS14791 Rev 3

G2 F2 F2 G2 J2 H2 VSSSMPS S

J3 H3 H3 J3 L3 K3 VDDSMPS S - - - -

G3 F3 F3 G3 J3 H3 VSSSMPS S - - - -

- H4 H4 J4 L4 K4 VDDSMPS S - - - -

- F4 F4 G4 J4 H4 VSSSMPS S - - - -

- - - - L5 K5 VDDSMPS S - - - -

- - - - J5 H5 VSSSMPS S - - - -

- - - - - K6 VDDSMPS S - - - -

- - - - - H6 VSSSMPS S - - - -

E1 D1 D1 E1 G1 F1 V08CAP S - - - -

H1 G1 G1 H1 K1 J1 VLXSMPS S - - - -

H2 G2 G2 H2 K2 J2 VLXSMPS S - - - -

H3 G3 G3 H3 K3 J3 VLXSMPS S - - - -
111/258

- G4 G4 H4 K4 J4 VLXSMPS S - - - -
 Table 18. Pin description (continued)
112/258

Pinout, pin description and alternate functions

Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

- - - - K5 J5 VLXSMPS S - - - -

- - - - - J6 VLXSMPS S - - - -

D4 C4 D4 C3 D4 C5 VDDA18USB S - - - -

B6 C5 A4 B3 C3 A4 VDD33USB S - - - -

R3 L5 M3 M6 P6 N6 VDDA18ADC S - - - -

P3 K5 M4 M5 N6 M6 VSSA S - - - -

- - - -
DS14791 Rev 3

E4 D5 E5 E5 H6 F6 VDDA18AON S

F4 E5 F5 F5 G6 G6 VSSAON S - - - -

F12 E9 G10 H11 J14 G13 VDD S - - - -

G12 G9 G11 H12 K14 H12 VDD S - - - -

H12 J9 G12 J13 L14 H13 VDD S - - - -

- - - - - J12 VDD S - - - -

- - - - - J13 VDD S - - - -

STM32N6x5xx STM32N6x7xx
- - - - - K13 VDD S - - - -

M5 E7 K6 L6 P7 L6 VDDCORE S - - - -

M6 F6 K7 L7 P9 L12 VDDCORE S - - - -

M7 F8 K8 L8 P10 M7 VDDCORE S - - - -

M8 G5 K9 L9 P11 M9 VDDCORE S - - - -

M9 G7 L7 - P13 M11 VDDCORE S - - - -

- H6 - - - N8 VDDCORE S - - - -
 Table 18. Pin description (continued)

STM32N6x5xx STM32N6x7xx
Pin number

I/O structure
Pin type
VFBGA142

VFBGA169

VFBGA178

VFBGA198

VFBGA223

VFBGA264

Notes
Pin name (function
Alternate functions Additional functions
after reset)

- H8 - - - N10 VDDCORE S - - - -

- J7 - - - N12 VDDCORE S - - - -

- - - - - P11 VDDCORE S - - - -

A15 A13 A14 A15 A19 A17 VSS S - - - -

D9 E6 E7 E8 F12 F7 VSS S - - - -

J12 E8 F10 G11 H14 F10 VSS S - - - -

- - - -
DS14791 Rev 3

M4 F5 H10 L5 N16 F11 VSS S

M10 F7 H11 L10 P8 F12 VSS S - - - -

M12 F9 K5 R1 P12 G12 VSS S - - - -

R1 G6 K10 R15 P14 K12 VSS S - - - -

R15 G8 P1 - W1 M8 VSS S - - - -

- H5 P14 - W19 M10 VSS S - - - -

- H7 - - - M12 VSS S - - - -

- H9 - - - M13 VSS S - - - -

- J6 - - - N5 VSS S - - - -

- J8 - - - N7 VSS S - - - -

- N1 - - - N9 VSS S - - - -

- N13 - - - N11 VSS S - - - -

- - - - - U1 VSS S - - - -
113/258

- - - - - U17 VSS S - - - -
1. Power supply is VDD.
 4.3 Alternate functions
114/258

Pinout, pin description and alternate functions

Table 19. Alternate functions: AF0 to AF7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

USART2_CTS/U
PA0 - TIM2_CH1 TIM5_CH1 TIM9_CH1 TIM15_BKIN SPI6_NSS/I2S6_WS
SART2_NSS
PA1 - TIM2_CH2 TIM5_CH2 LPTIM3_IN1 TIM15_CH1N - - USART2_RTS
PA2 - TIM2_CH3 TIM5_CH3 LPTIM3_IN2 TIM15_CH1 - - USART2_TX
PA3 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B -
DS14791 Rev 3

PA4 - - - - - SPI5_MOSI - USART6_RX

PA5 PWR_CSTOP TIM2_CH1 TIM2_ETR TIM9_CH2 I3C1_SCL SPI1_SCK/I2S1_CK - -
SPI1_MISO/
PA6 BOOT1 TIM1_BKIN TIM3_CH1 LPTIM3_ETR I3C1_SDA - -
I2S1_SDI
SPI1_MOSI/
PA7 - TIM1_CH1N TIM3_CH2 - - - USART1_RX
Port A

I2S1_SDO
PA8 MCO1 TIM1_CH1 I3C2_SCL - I2C3_SCL - - USART1_CK
PA9 - TIM1_CH2 I3C2_SDA LPUART1_TX I2C3_SDA SPI2_SCK/I2S2_CK - USART1_TX

STM32N6x5xx STM32N6x7xx
PA10 PWR_CSLEEP TIM1_CH3 - LPUART1_RX - - - USART1_RX
USART1_CTS/U
PA11 - TIM1_CH4 - LPUART1_CTS - SPI2_NSS/I2S2_WS FDCAN1_RX
SART1_NSS
PA12 - TIM1_ETR - LPUART1_RTS - SPI2_SCK/I2S2_CK FDCAN1_TX USART1_RTS
PA13 JTMS/SWDIO - - - - - - -
PA14 JTCK/SWCLK - - - - - - -
SPI3_NSS/ SPI6_NSS/
PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS/I2S1_WS
I2S3_WS I2S6_WS
 Table 19. Alternate functions: AF0 to AF7 (continued)

STM32N6x5xx STM32N6x7xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PB0 TRACED1 TIM1_CH4 SAI1_D2 ADF1_SDI0 MDF1_SDI2 SPI4_NSS SAI1_FS_A TIM15_CH1N

PB1 - TIM1_CH3N TIM3_CH4 TIM9_CH2 - - FDCAN2_TX USART2_TX
SPI3_MOSI/
PB2 RTC_OUT2 TIM1_CH1 SAI1_D1 ADF1_SDI0 MDF1_SDI1 - SAI1_SD_A
I2S3_SDO
GFXTIM_FCK
PB3 TRACECLK TIM1_CH4N - MDF1_CKI1 - - USART1_CK
CAL
SPI1_MISO/ SPI3_MISO/ SPI2_NSS/
PB4 NJTRST TIM16_BKIN TIM3_CH1 LPTIM4_ETR -
DS14791 Rev 3

I2S1_SDI I2S3_SDI I2S2_WS

JTDO/ SPI1_MOSI/ SPI3_MOSI/
PB5 TIM17_BKIN TIM3_CH2 LPTIM4_OUT I2C1_SMBA FDCAN2_RX
TRACESWO I2S1_SDO I2S3_SDO
PB6 TRACED2 - SAI1_CK2 ADF1_CCK1 MDF1_CCK1 SPI4_MISO SAI1_SCK_A TIM15_CH1
Port B

PB7 TRACED3 TIM1_BKIN2 SAI1_D1 ADF1_SDI0 MDF1_SDI1 SPI4_MOSI SAI1_SD_A TIM15_CH2

SPI1_MISO/
PB8 - - - - - - USART6_RX
I2S1_SDI
PB9 - LPTIM1_IN2 - - - SPI1_SCK/I2S1_CK USART10_TX -
PB10 - TIM2_CH3 I3C2_SCL LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK - USART3_TX
PB11 - TIM2_CH4 I3C2_SDA LPTIM2_ETR I2C2_SDA - - USART3_RX
PB12 - TIM1_BKIN - LPTIM2_IN2 I2C2_SMBA SPI2_NSS/I2S2_WS FDCAN2_RX USART3_CK
USART10_CTS/ USART6_CTS/U
PB13 TRACED0 LPTIM1_CH1 TIM8_CH3N - - SPI6_SCK/I2S6_CK
USART10_NSS SART6_NSS
USART6_CTS/U
PB14 - LPTIM1_CH2 TIM8_CH4N - - - USART10_CK
SART6_NSS
115/258

PB15 - - - - - SPI6_NSS/I2S6_WS - USART6_RTS

 Table 19. Alternate functions: AF0 to AF7 (continued)
116/258

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

SPI3_SCK/
PC0 - TIM2_CH2 - LPTIM4_IN1 MDF1_CKI1 SPI1_SCK/I2S1_CK -
I2S3_CK
PC1 - TIM17_CH1 TIM4_CH4 - I2C1_SDA SPI2_NSS/I2S2_WS FDCAN1_TX I3C1_SDA
SPI3_MOSI/
PC2 - - SAI1_D1 ADF1_SDI0 MDF1_SDI1 SAI1_SCK_A USART2_RX
I2S3_SDO
SPI1_MOSI/
PC3 - - - - - - USART2_CK
I2S1_SDO
DS14791 Rev 3

SPI2_MISO/
PC4 - TIM1_CH2N TIM12_CH1 LPTIM2_CH2 USART1_TX - USART3_RTS
I2S2_SDI
PC5 - - - - - SPI1_NSS/I2S1_WS - -
PC6 - TIM1_CH1 TIM3_CH1 TIM9_CH1 - I2S2_MCK - USART6_TX
Port C

PC7 DBTRGIO TIM16_CH1N TIM3_CH2 TIM9_CH2 - - I2S3_MCK USART6_RX

PC8 TRACED1 - TIM3_CH3 - I2C3_SMBA - UCPD1_FRSTX1 USART6_CK
PC9 MCO2 - TIM3_CH4 - I2C3_SDA AUDIOCLK UCPD1_FRSTX2 USART6_RX
SPI3_SCK/
PC10 - TIM1_BKIN I3C2_SCL - I2C4_SCL - USART3_TX

STM32N6x5xx STM32N6x7xx
I2S3_CK
SPI3_MISO/
PC11 - - I3C2_SDA - I2C4_SDA - USART3_RX
I2S3_SDI
SPI3_MOSI/
PC12 TRACED3 TIM1_CH4 - - TIM15_CH1 SPI6_SCK/I2S6_CK USART3_CK
I2S3_SDO
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
 Table 19. Alternate functions: AF0 to AF7 (continued)

STM32N6x5xx STM32N6x7xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PD0 - TIM1_ETR - - - - FDCAN1_RX UART9_CTS

PD1 - - - - - - FDCAN1_TX -
SPI2_MOSI/
PD2 TRACED0 TIM1_CH3 SAI1_D1 ADF1_SDI0 MDF1_SDI1 SAI1_SD_A TIM15_CH1N
I2S2_SDO
PD3 - - - - I2C2_SMBA - USART10_RX USART6_CTS
PD4 - TIM1_BKIN2 - - I2C2_SDA SPI5_MISO - USART6_RTS
PD5 - TIM1_CH4N - - - - - USART2_TX
DS14791 Rev 3

SPI2_MISO/
PD6 - TIM1_CH1 - - TIM15_CH2 - -
I2S2_SDI
SPI2_MOSI/ SPI3_NSS/I2S3_
Port D

PD7 - TIM1_CH2 - - TIM15_CH1N -

I2S2_SDO WS
PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX
PD10 TRACECLK TIM1_ETR - - MDF1_CKI3 I2S1_MCK UCPD1_FRSTX1 -
SPI2_MISO/
PD11 - - - - I2C4_SDA UCPD1_FRSTX1 -
I2S2_SDI
PD12 - - SAI1_D3 - MDF1_SDI3 - UCPD1_FRSTX2 -
PD13 - LPTIM1_CH1 TIM4_CH2 - - - UCPD1_FRSTX2 UART9_RTS
PD14 - - - - I2C2_SCL - USART10_RX -
PD15 - - - - I2C2_SDA - USART10_TX -
117/258
 Table 19. Alternate functions: AF0 to AF7 (continued)
118/258

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PE0 - LPTIM1_ETR TIM4_ETR LPTIM2_ETR - - - USART3_RX

PE1 - LPTIM1_IN2 - LPTIM2_CH2 - - - USART3_TX
PE2 TRACECLK LPTIM5_IN1 SAI1_CK1 ADF1_CCK0 MDF1_CCK0 SPI4_SCK SAI1_MCLK_A UCPD1_FRSTX1
PE3 TRACED0 LPTIM5_ETR - - MDF1_CKI2 - SAI1_SD_B TIM15_BKIN
SPI6_MISO/
PE4 - LPTIM1_IN1 - - - USART10_RX USART6_RTS
I2S6_SDI
PE5 - TIM16_CH1N TIM4_CH1 LPUART1_TX I2C1_SCL I3C1_SCL FDCAN2_TX USART1_TX
DS14791 Rev 3

PE6 - TIM17_CH1N TIM4_CH2 LPUART1_RX I2C1_SDA I3C1_SDA - USART1_RX

PE7 - TIM1_ETR - - MDF1_CKI0 - - -
Port E

PE8 - TIM1_CH1N - - MDF1_SDI0 - - USART3_TX

PE9 - TIM1_CH1 - - MDF1_CKI4 - - -
PE10 TRACECLK TIM1_CH2N - - MDF1_SDI4 - - USART3_RX
PE11 - TIM1_CH2 - - MDF1_CKI5 SPI4_NSS FDCAN3_TX -
PE12 - TIM1_CH3N - - MDF1_SDI5 SPI4_SCK FDCAN3_RX -

STM32N6x5xx STM32N6x7xx
PE13 - TIM1_CH3 - ADF1_CCK0 I2C4_SCL SPI4_MISO - -
GFXTIM_FCK
PE14 - TIM1_CH4 ADF1_CCK1 I2C4_SDA SPI4_MOSI - -
CAL
GFXTIM_LCK
PE15 - TIM1_BKIN - I2C4_SMBA SPI5_SCK USART10_CK USART2_CK
CAL
 Table 19. Alternate functions: AF0 to AF7 (continued)

STM32N6x5xx STM32N6x7xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PF0 - LPTIM5_OUT TIM4_CH4 - - - UCPD1_FRSTX2 UART9_TX

PF1 - LPTIM1_CH2 TIM4_CH3 LPTIM2_CH1 - - UCPD1_FRSTX1 UART9_RX
USART2_CTS/
PF2 - TIM1_CH3N - - - SPI2_SCK/I2S2_CK FDCAN3_TX
USART2_NSS
PF3 - - - - - - FDCAN3_RX USART2_RTS
SPI3_NSS/I
PF4 - - TIM5_ETR LPTIM3_CH2 - SPI1_NSS/I2S1_WS USART2_CK
2S3_WS
DS14791 Rev 3

USART3_CTS/
PF5 - TIM1_ETR - LPTIM2_IN2 - - -
USART3_NSS
PF6 - TIM2_CH4 TIM5_CH4 LPTIM3_CH1 TIM15_CH2 I2S6_MCK SPI4_RDY USART2_RX
Port F

PF7 - TIM1_CH2N TIM3_CH3 TIM9_CH1 - SPI1_SCK/I2S1_CK - -

PF8 TRACECLK - - - - - - UART9_TX
PF9 TRACED0 - - - - - - -
PF10 - TIM16_BKIN SAI1_D3 - MDF1_SDI3 UCPD1_FRSTX1 -
PF11 - - - - - SPI5_MOSI - -
PF12 - - - - USART1_RX SPI5_MISO - -
PF13 - - - - USART1_TX SPI5_NSS - -
PF14 - TIM2_CH2 - - USART1_CTS SPI5_MOSI - -
PF15 - - - - USART1_RTS SPI5_SCK - -
119/258
 Table 19. Alternate functions: AF0 to AF7 (continued)
120/258

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PG0 - TIM1_CH4N TIM12_CH1 - - - - UART9_RX

PG1 - TIM16_CH1N - - - SPI5_MISO SAI1_SCK_B
PG2 - TIM17_CH1N - - - SPI5_MOSI SAI1_FS_B USART3_RTS
PG3 TRACED1 - - - - - - USART2_TX
PG4 - TIM1_BKIN2 - - - - -
USART2_CTS/
PG5 - TIM1_ETR - - - - -
USART2_NSS
DS14791 Rev 3

PG6 - TIM17_BKIN - - - - - USART6_CK

PG7 TRACECLK - - - - SAI1_MCLK_A USART6_CK
Port G

SPI2_MOSI/
PG8 RTC_REFIN TIM1_CH3N TIM12_CH2 - USART1_RX SAI1_SCK_B -
I2S2_SDO
PG9 - - - - - - - -
USART3_CTS/
PG10 - TIM1_CH1N LPTIM2_CH1 - SPI2_SCK/I2S2_CK FDCAN2_TX
USART3_NSS
PG11 - - - - - - - -

STM32N6x5xx STM32N6x7xx
PG12 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK_B
PG13 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 - - - USART3_RTS
SPI6_MOSI/
PG14 TRACED1 LPTIM1_ETR TIM8_CH4 - - USART10_RTS USART6_TX
I2S6_SDO
PG15 - TIM1_CH4 - - - SPI5_RDY SPI4_RDY USART3_CK
 Table 19. Alternate functions: AF0 to AF7 (continued)

STM32N6x5xx STM32N6x7xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PH0 - - - - - - - -
PH1 - - - - - - - -
PH2 TRACED2 TIM1_ETR TIM3_ETR - TIM15_BKIN - FDCAN1_TX -
PH3 TRACECLK - - - - - - -
PH4 - - - - - - - -
PH5 - - - - - SPI5_SCK - -
DS14791 Rev 3

PH6 - - - - - SPI5_NSS - -
PH7 - - I3C2_SCL - - SPI5_MOSI - -
Port H

PH8 - - I3C2_SDA - - SPI5_MISO - -

PH9 - TIM16_CH1 TIM4_CH3 USART3_CK I2C1_SCL - FDCAN1_RX I3C1_SCL
PH10 - - - - - - - -
PH11 - - - - - - - -
PH12 - - - - - - - -
PH13 - - - - - - - -
PH14 - - - - - - - -
PH15 - - - - - - - -
121/258
 Table 19. Alternate functions: AF0 to AF7 (continued)
122/258

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PN0 - - - - - - - -
PN1 - - - - - - - -
PN2 - - - - - - - -
PN3 - - - - - - - -
PN4 - - - - - - - -
PN5 - - - - - - - -
Port N
DS14791 Rev 3

PN6 - - - - - - - -
PN7 - - - - - - - -
PN8 - - - - - - - -
PN9 - - - - - - - -
PN10 - - - - - - - -
PN11 - - - - - - - -
PN12 - - - - - - - -
PO0 - - - - - - - -

STM32N6x5xx STM32N6x7xx
PO1 - - - - - - - -
PO2 - - - - - - - -
Port O

PO3 - - - - - - - -
PO4 - - - - - - - -
PO5 - - - - - - - -
 Table 19. Alternate functions: AF0 to AF7 (continued)

STM32N6x5xx STM32N6x7xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PP0 - - - - - - - -
PP1 - - - - - - - -
PP2 - - - - - - - -
PP3 - - - - - - - -
PP4 - - - - - - - -
PP5 - - - - - - - -
DS14791 Rev 3

PP6 - - - - - - - -
PP7 - - - - - - - -
Port P

PP8 - - - - - SPI2_MISO - -
PP9 - - - - - SPI2_MOSI - -
PP10 - - - - - - - -
PP11 - - - - - - - -
PP12 - - - - - - - -
PP13 - - - - - - - -
PP14 - - - - - - - -
PP15 - - - - - - - -
123/258
 Table 19. Alternate functions: AF0 to AF7 (continued)
124/258

Pinout, pin description and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

I2C1/2/3/4/ SPI3/I2S3/SAI1/ SPI2/I2S2/SPI3/

LPUART1/
Port USART1/ SPI1/I2S1/SPI2/I2S2 I2C4/UART4/ I2S3/SPI6/I2S6/
TIM1/2/16/17/ PDM_SAI1/ TIM8/LPTIM2/3/
SYS TIM15/LPTIM2/ /SPI3/I2S3/SPI4/5/6/ DFSDM1/2/ USART1/2/3/6/
LPTIM1 TIM3/4/5/12/15 DFSDM1/
DFSDM1/2/ I2S6/CEC OCSPI1/ UART7/
OCSPI1/2
DCMI/PSSI/CEC USB_PD OCSPI2/SDIO1

PQ0 TRACECLK - TIM8_ETR - - - - -

PQ1 - - TIM8_BKIN - - - - -
PQ2 - - TIM8_BKIN2 - - - - -
PQ3 - - TIM8_CH1 - - - - -
Port Q

PQ4 - - TIM8_CH1N - - - - -
PQ5 - - TIM8_CH2 - - - - -
DS14791 Rev 3

PQ6 - - TIM8_CH2N - - - - -
PQ7 - - TIM8_CH3 - - - - -

STM32N6x5xx STM32N6x7xx
 Table 20. Alternate functions: AF8 to AF15

STM32N6x5xx STM32N6x7xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

FMC_AD7/
PA0 UART4_TX - SAI2_SD_B SDMMC2_CMD - LCD_G3 HDP0
FMC_D7

DCMIPP_D0/ FMC_AD6/
PA1 UART4_RX SAI2_MCLK_B - - - LCD_G2
DCMI_D0/PSSI_D0 FMC_D6

FMC_AD5/
PA2 - - SAI2_SCK_B MDIOS_MDIO - - LCD_B7
FMC_D5

FMC_A17/
PA3 UART7_RX - - - - - -
FMC_ALE

DCMIPP_D3/
PA4 - - FMC_A13 - - -
DCMI_D3/PSSI_D3

SPI6_SCK/ DCMIPP_D8/
PA5 TIM10_CH1 - FMC_NOE - - LCD_CLK
DS14791 Rev 3

I2S6_CK DCMI_D8/PSSI_D8

DCMIPP_PIXCLK/
SPI6_MISO/
PA6 DCMI_PIXCLK/ TIM13_CH1 MDIOS_MDC LCD_B7 - - LCD_HSYNC
I2S6_SDI
PSSI_PDCK
Port A

SPI6_MOSI/
PA7 LCD_R4 TIM14_CH1 FMC_RNB - - LCD_B1
I2S6_SDO

FMC_AD4/
PA8 - TIM11_CH1 UART7_RX - - LCD_B6
FMC_D4

DCMIPP_D0/ FMC_AD3/
PA9 - - - - LCD_B5
DCMI_D0/PSSI_D0 FMC_D3

DCMIPP_D1/ FMC_AD2/
PA10 - - MDIOS_MDIO - - LCD_B4
DCMI_D1/PSSI_D1 FMC_D2

FMC_AD1/
PA11 UART4_RX - - - - - LCD_B3
FMC_D1

FMC_AD0/
PA12 UART4_TX - SAI2_FS_B - - LCD_B2
FMC_D0

PA13 - - - - - - - -

PA14 - - - - - - - -

FMC_D15/
PA15 UART4_RTS - UART7_TX - - - LCD_R5
FMC_AD15
125/258
 Table 20. Alternate functions: AF8 to AF15 (continued)
126/258

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

DCMIPP_D4/DCMI_D4/P FMC_D13/
PB0 - - - - - EVENTOUT
SSI_D4 FMC_AD13

PB1 - - - - FMC_NOE [RNG_S2] LCD_R1 HDP1

FMC_D2/
PB2 - - - - - LCD_B2 HDP2
FMC_AD2

PB3 - - SAI2_FS_B - FMC_NBL1 GFXTIM_LCKCAL FMC_A23 HDP0

DCMIPP_VSYNC/
SPI6_MISO/ FMC_D13/
PB4 DCMI_VSYNC/ UART7_TX SDMMC2_D3 - LCD_R3 HDP4
I2S6_SDI FMC_AD13
PSSI_RDY

SPI6_MOSI/ DCMIPP_D10/ FMC_D12/

PB5 - UART5_RX - LCD_R2 HDP5
I2S6_SDO DCMI_D10/PSSI_D10 FMC_AD12
DS14791 Rev 3

DCMIPP_D6/DCMI_D6/P FMC_D14/
PB6 - - - - - EVENTOUT
SSI_D6 FMC_AD14

DCMIPP_D7/DCMI_D7/P FMC_D15/
PB7 - SAI2_MCLK_B - - - EVENTOUT
SSI_D7 FMC_AD15
Port B

DCMIPP_VSYNC/
FMC_D1/
PB8 SPDIFRX1_IN3 DCMI_VSYNC/ SAI2_FS_B SDMMC2_D0 - - EVENTOUT
FMC_AD1
PSSI_RDY

DCMIPP_D3/DCMI_D3/P FMC_D3/
PB9 SPDIFRX1_IN0 - SDMMC2_D2 - - EVENTOUT
SSI_D3 FMC_AD3

FMC_D11/
PB10 - - - - - LCD_G7 HDP2
FMC_AD11

STM32N6x5xx STM32N6x7xx
FMC_D10/
PB11 - - - - - LCD_G6 HDP3
FMC_AD10

FMC_D9/
PB12 - - - UART5_RX - LCD_G5 HDP4
FMC_AD9

FMC_D5/
PB13 - - - SDMMC2_D6 - LCD_CLK EVENTOUT
FMC_AD5

DCMIPP_D10/ FMC_D7/
PB14 - - - - LCD_HSYNC EVENTOUT
DCMI_D10/PSSI_D10 FMC_AD7

FMC_D0/
PB15 SPDIFRX1_IN2 - - - - LCD_G4 EVENTOUT
FMC_AD0
 Table 20. Alternate functions: AF8 to AF15 (continued)

STM32N6x5xx STM32N6x7xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

SPI6_SCK/ DCMIPP_HSYNC/ FMC_D14/

PC0 UART7_RX SDMMC2_D2 - LCD_R4 HDP3
I2S6_CK DCMI_HSYNC/PSSI_DE FMC_AD14

DCMIPP_D7/DCMI_D7/
PC1 UART4_TX SDMMC1_D5 SDMMC2_D5 SDMMC1_CDIR - - HDP1
PSSI_D7

DCMIPP_D13/
PC2 - - SDMMC2_CK FMC_NE3 - FMC_RNB EVENTOUT
DCMI_D13/PSSI_D13

DCMIPP_D2/DCMI_D2/ FMC_D8/
PC3 SPDIFRX1_IN0 - SDMMC2_CMD - - EVENTOUT
PSSI_D2 FMC_AD8

PC4 UART4_RTS - LCD_VSYNC SDMMC2_D0 FMC_NE1 - LCD_DE HDP6

DCMIPP_D2/DCMI_D2/
PC5 - SAI2_SD_B SDMMC2_D1 FMC_NWE - - EVENTOUT
PSSI_D2
DS14791 Rev 3

DCMIPP_D1/DCMI_D1/
PC6 - SDMMC1_D6 SDMMC2_D6 SDMMC1_D0DIR - - HDP6
PSSI_D1
Port C

DCMIPP_D1/DCMI_D1/
PC7 - SDMMC1_D7 SDMMC2_D7 SDMMC1_D123DIR - - HDP7
PSSI_D1

DCMIPP_D2/DCMI_D2/
PC8 - SDMMC1_D0 UART5_RTS FMC_NE4 - LCD_B0 HDP0
PSSI_D2

DCMIPP_D3/DCMI_D3/
PC9 - SDMMC1_D1 UART5_CTS - LCD_B3 HDP1
PSSI_D3

PC10 UART4_TX DCMIPP_D14/PSSI_D14 SDMMC1_D2 - FMC_CLK - - HDP2

DCMIPP_D4/DCMI_D4/
PC11 UART4_RX SDMMC1_D3 - - - - HDP3
PSSI_D4

DCMIPP_D9/DCMI_D9/
PC12 - SDMMC1_CK UART5_TX FMC_NL - - HDP4
PSSI_D9

PC13 - - - - - - - HDP5

PC14 - - - - - - - -

PC15 - - - - - - - -
127/258
 Table 20. Alternate functions: AF8 to AF15 (continued)
128/258

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

DCMIPP_HSYNC/
PD0 UART4_RX - - FMC_A6 - FMC_A22 EVENTOUT
DCMI_HSYNC/PSSI_DE

PD1 UART4_TX - - ETH1_MDC FMC_A7 - FMC_A23 EVENTOUT

FMC_A16/
PD2 - - MDIOS_MDC SDMMC2_CK FMC_A0 - HDP1
FMC_CLE

PD3 - DCMIPP_D14/PSSI_D14 - ETH1_PHY_INTN FMC_A10 - - EVENTOUT

DCMIPP_D9/DCMI_D9/
PD4 - - - FMC_A11 - - EVENTOUT
PSSI_D9

DCMIPP_PIXCLK/
PD5 - DCMI_PIXCLK/ - SDMMC2_D7 FMC_D6/FMC_AD6 - - EVENTOUT
PSSI_PDCK
DS14791 Rev 3

FMC_A17/
PD6 - - - - FMC_A1 - HDP2
FMC_ALE
Port D

DCMIPP_D0/DCMI_D0/
PD7 - - - FMC_A2 - FMC_A18 HDP3
PSSI_D0

DCMIPP_D11/
PD8 SPDIFRX1_IN1 - - FMC_NBL0 - LCD_R7 EVENTOUT
DCMI_D11/PSSI_D11

DCMIPP_D11/
PD9 - - - FMC_SDCLK - LCD_R1 EVENTOUT
DCMI_D11/PSSI_D11

PD10 SPDIFRX1_IN2 - SAI2_FS_B - FMC_A3 GFXTIM_TE FMC_A19 HDP4

PD11 - DCMIPP_D15/PSSI_D15 SDMMC1_D0 - FMC_D8/FMC_AD8 - - EVENTOUT

STM32N6x5xx STM32N6x7xx
DCMIPP_D12/
PD12 SPDIFRX1_IN3 - ETH1_MDIO FMC_A5 - FMC_A21 HDP5
DCMI_D12/PSSI_D12

DCMIPP_D13/
PD13 - SAI2_SCK_A - FMC_D4/FMC_AD4 - LCD_R6 EVENTOUT
DCMI_D13/PSSI_D13

PD14 - - - - FMC_A9 - - EVENTOUT

PD15 - - - - FMC_A8 - LCD_R2 EVENTOUT

 Table 20. Alternate functions: AF8 to AF15 (continued)

STM32N6x5xx STM32N6x7xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

DCMIPP_D2/DCMI_D2/
PE0 UART8_RX SAI2_MCLK_A - FMC_D9/FMC_AD9 - - EVENTOUT
PSSI_D2

DCMIPP_D8/DCMI_D8/
PE1 UART8_TX - - FMC_D10/FMC_AD10 - - EVENTOUT
PSSI_D8

PE2 - - - - FMC_D11/FMC_AD11 TIM1_CH2N - EVENTOUT

PE3 - - - - FMC_D12/FMC_AD12 - - EVENTOUT

DCMIPP_D5/DCMI_D5/
PE4 SPDIFRX1_IN1 SDMMC2_D3 FMC_RNB - LCD_G1 EVENTOUT
PSSI_D5

DCMIPP_D5/DCMI_D5/
PE5 - UART5_TX FMC_SDNE1 - - HDP6
PSSI_D5

DCMIPP_VSYNC/ DCMIPP_D1/DCMI_D1/
DS14791 Rev 3

PE6 - UART5_TX FMC_SDCKE1 - - HDP7

DCMI_VSYNC/PSSI_RDY PSSI_D1
Port E

PE7 UART7_RX - SAI2_SD_B - FMC_A4 - FMC_A20 EVENTOUT

DCMIPP_D4/DCMI_D4/
PE8 UART7_TX - - FMC_A12 - - EVENTOUT
PSSI_D4

PE9 UART7_RTS - - - FMC_A14/FMC_BA0 - - EVENTOUT

DCMIPP_D3/DCMI_D3/
PE10 UART7_CTS - - FMC_A15/FMC_BA1 - - EVENTOUT
PSSI_D3

PE11 - - SAI2_SD_B - FMC_SDNWE - LCD_VSYNC EVENTOUT

PE12 - - SAI2_SCK_B - FMC_NRAS - - EVENTOUT

PE13 - - SAI2_FS_B - FMC_NCAS - - EVENTOUT

PE14 - - SAI2_MCLK_B - FMC_SDNE0 GFXTIM_LCKCAL FMC_NWE EVENTOUT

PE15 - - SDMMC1_D0 - FMC_SDCKE0 GFXTIM_FCKCAL - EVENTOUT

129/258
 Table 20. Alternate functions: AF8 to AF15 (continued)
130/258

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

DCMIPP_D9/DCMI_D9/
PF0 UART8_RTS - ETH1_MII_TX_CLK ETH1_RGMII_GTX_CLK - - EVENTOUT
PSSI_D9

DCMIPP_D7/DCMI_D7/
PF1 UART8_CTS - ETH1_TX_ER - - - EVENTOUT
PSSI_D7

PF2 - - - ETH1_RGMII_CLK125 FMC_NWAIT - LCD_B1 EVENTOUT

DCMIPP_HSYNC/
PF3 - - ETH1_PPS_OUT FMC_NL - LCD_R4 EVENTOUT
DCMI_HSYNC/PSSI_DE

SPI6_NSS/ DCMIPP_HSYNC/
PF4 - ETH1_MDIO - - LCD_R3 HDP4
I2S6_WS DCMI_HSYNC/PSSI_DE

DCMIPP_D6/DCMI_D6/
PF5 - SAI2_SD_A ETH1_CLK FMC_NE3 - LCD_G0 EVENTOUT
PSSI_D6
DS14791 Rev 3

PF6 - SPI5_RDY SPI1_RDY ETH1_MII_COL GFXTIM_FCKCAL TIM1_CH3 LCD_DE HDP3

ETH1_MII_RX_CLK/
PF7 UART4_CTS - - ETH1_RMII_REF_CLK/ GFXTIM_TE [RNG_S1] LCD_VSYNC HDP0
ETH1_RGMII_RX_CLK

ETH1_MII_RXD2/
PF8 - - - FMC_NWE - LCD_R6 EVENTOUT
ETH1_RGMII_RXD2
Port F

ETH1_MII_RXD3/
PF9 - - - - - LCD_HSYNC EVENTOUT
ETH1_RGMII_RXD3

ETH1_MII_RX_DV/
DCMIPP_D11/DCMI_D11/ DCMIPP_D15/
PF10 UART7_RX ETH1_RMII_CRS_DV/ - - LCD_R1 EVENTOUT
PSSI_D11 PSSI_D15
ETH1_RGMII_RX_CTL

STM32N6x5xx STM32N6x7xx
ETH1_MII_TX_EN/
PF11 - DCMIPP_D15/PSSI_D15 SAI2_SD_B ETH1_RMII_TX_EN/ - - LCD_B0 EVENTOUT
ETH1_RGMII_TX_CTL

ETH1_MII_TXD0/
DCMIPP_D13/DCMI_D13/
PF12 - - ETH1_RMII_TXD0/ - - EVENTOUT
PSSI_D13
ETH1_RGMII_TXD0

ETH1_MII_TXD1/
DCMIPP_D10/DCMI_D10/
PF13 - - ETH1_RMII_TXD1/ - - EVENTOUT
PSSI_D10
ETH1_RGMII_TXD1

ETH1_MII_RXD0/
PF14 - - - ETH1_RMII_RXD0/ - - LCD_G0 EVENTOUT
ETH1_RGMII_RXD0

ETH1_MII_RXD1/
PF15 - - - ETH1_RMII_RXD1/ - - LCD_G1 EVENTOUT
ETH1_RGMII_RXD1
 Table 20. Alternate functions: AF8 to AF15 (continued)

STM32N6x5xx STM32N6x7xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

PG0 - - LCD_VSYNC ETH1_PHY_INTN - - LCD_R0 EVENTOUT

DCMIPP_PIXCLK/
PG1 UART7_RTS DCMI_PIXCLK/ TIM13_CH1 - FMC_A19 - LCD_G1 EVENTOUT
PSSI_PDCK

DCMIPP_D6/DCMI_D6/
PG2 UART7_CTS SAI2_MCLK_B TIM14_CH1 FMC_A21 - LCD_R0 EVENTOUT
PSSI_D6

DCMIPP_HSYNC/ ETH1_MII_TXD2/
PG3 - - - - - EVENTOUT
DCMI_HSYNC/PSSI_DE ETH1_RGMII_TXD2

ETH1_MII_TXD3/
PG4 - - - - - LCD_B0 EVENTOUT
ETH1_RGMII_TXD3

PG5 - - - ETH1_MII_RX_ER - - LCD_B1 EVENTOUT

DS14791 Rev 3

DCMIPP_D12/DCMI_D12/
PG6 - - ETH1_MII_CRS - - LCD_B3 EVENTOUT
PSSI_D12
Port G

DCMIPP_D13/DCMI_D13/
PG7 - - ETH1_PHY_INTN - - - EVENTOUT
PSSI_D13

PG8 UART4_CTS - - SDMMC2_D1 FMC_A20 - LCD_G7 HDP7

PG9 - - - - FMC_D8/FMC_AD8 - LCD_R7 EVENTOUT

DCMIPP_D2/DCMI_D2/
PG10 - - UART5_TX FMC_A16/FMC_CLE - LCD_G4 HDP5
PSSI_D2

PG11 UART7_RX - - ETH1_MDC - - LCD_R6 EVENTOUT

PG12 UART7_TX - - - FMC_A18 - LCD_G0 EVENTOUT

DCMIPP_D12/DCMI_D12/
PG13 - SAI2_FS_A - FMC_NE1 - LCD_DE EVENTOUT
PSSI_D12

DCMIPP_D11/DCMI_D11/
PG14 USART2_RTS FMC_NCE - FMC_NE2 - LCD_B1 EVENTOUT
PSSI_D11

DCMIPP_D4/DCMI_D4/ ETH1_MII_RX_CLK/
PG15 - SPI1_RDY FMC_CLK - LCD_B0 EVENTOUT
PSSI_D4 ETH1_RMII_REF_CLK
131/258
 Table 20. Alternate functions: AF8 to AF15 (continued)
132/258

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

PH0 - - - - - - - EVENTOUT

PH1 - - - - - - - EVENTOUT

DCMIPP_D11/DCMI_D11/
PH2 - SDMMC1_CMD UART5_RX FMC_NE3 - - EVENTOUT
PSSI_D11

PH3 UART7_TX - - - - - LCD_B4 EVENTOUT

PH4 UART7_TX - - - - - LCD_R4 EVENTOUT

PH5 - - - ETH1_MDC - EVENTOUT

PH6 - - - - - - LCD_B5 EVENTOUT

PH7 - - - - - - EVENTOUT
Port H
DS14791 Rev 3

PH8 - - - - - - EVENTOUT

DCMIPP_D6/DCMI_D6/ FMC_D9/
PH9 UART4_RX SDMMC1_D4 SDMMC2_D4 SDMMC1_CKIN - HDP0
PSSI_D6 FMC_AD9

PH10 - - - - - - - -

PH11 - - - - - - - -

PH12 - - - - - - - -

PH13 - - - - - - - -

PH14 - - - - - - - -

PH15 - - - - - - - -

STM32N6x5xx STM32N6x7xx
 Table 20. Alternate functions: AF8 to AF15 (continued)

STM32N6x5xx STM32N6x7xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

PN0 - XSPIM_P2_DQS0 - - FMC_A25 - - EVENTOUT

PN1 - XSPIM_P2_NCS1 - - FMC_A24 - - EVENTOUT

PN2 - XSPIM_P2_IO0 - - FMC_A23 - - EVENTOUT

PN3 - XSPIM_P2_IO1 - - FMC_A22 - - EVENTOUT

PN4 - XSPIM_P2_IO2 - - - - - EVENTOUT

PN5 - XSPIM_P2_IO3 - - - - - EVENTOUT

Port N

PN6 - XSPIM_P2_CLK - - - - - EVENTOUT

PN7 - XSPIM_P2_NCLK - - - - - EVENTOUT

PN8 - XSPIM_P2_IO4 - - - - - EVENTOUT

DS14791 Rev 3

DCMIPP_D5/DCMI_D5/
PN9 - XSPIM_P2_IO5 - - - - EVENTOUT
PSSI_D5

PN10 - XSPIM_P2_IO6 - - - - LCD_B4 EVENTOUT

PN11 - XSPIM_P2_IO7 - - - - LCD_B6 EVENTOUT

PN12 - XSPIM_P2_NCS2 - - - - - EVENTOUT

PO0 - XSPIM_P1_NCS1 - - FMC_A22 - - EVENTOUT

PO1 - XSPIM_P1_NCS2 - - FMC_A23 - - EVENTOUT

PO2 - XSPIM_P1_DQS0 - - FMC_A24 - LCD_B7 EVENTOUT

Port O

PO3 - XSPIM_P1_DQS1 - - FMC_A25 - LCD_G3 EVENTOUT

PO4 - XSPIM_P1_CLK LCD_B4 - FMC_A24 - FMC_NBL2 EVENTOUT

PO5 - XSPIM_P1_NCLK - - FMC_A25 - FMC_NBL3 EVENTOUT

133/258
 Table 20. Alternate functions: AF8 to AF15 (continued)
134/258

Pinout, pin description and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port SPI6/I2S6/SAI2/ FDCAN1/2/ SAI2/TIM8/OCSPI1/ I2C4/USART10/UART7/9/

UART4/5/8/ TIM13/14/ FMC/SDIO2/ SWPMI1/TIM1/8/DFSDM1/2/ TIM1/8/FMC/SDIO1/ TIM1/DCMI/
UART5/LCD SYS
LPUART1/SDIO1/ OCSPI1/2/FMC/ OTG1_HS/OTG1_FS/ OCSPI1/SDIO2/MDIOS/ MDIOS/LCD/COMP PSSI/LCD/COMP
USB_PD/SPDIFRX SDIO2/LCD/SPDIFRX LCD/COMP/CRS USB_PD/LCD/COMP

PP0 - XSPIM_P1_IO0 - - FMC_D16 - - EVENTOUT

PP1 - XSPIM_P1_IO1 - - FMC_D17 - - EVENTOUT

PP2 - XSPIM_P1_IO2 - - FMC_D18 - - EVENTOUT

PP3 - XSPIM_P1_IO3 - - FMC_D19 - - EVENTOUT

PP4 - XSPIM_P1_IO4 - - FMC_D20 - - EVENTOUT

PP5 - XSPIM_P1_IO5 - - FMC_D21 - - EVENTOUT

PP6 - XSPIM_P1_IO6 - - FMC_D22 - - EVENTOUT

PP7 - XSPIM_P1_IO7 - - FMC_D23 - - EVENTOUT

Port P

PP8 - XSPIM_P1_IO8 - - FMC_D24 - - EVENTOUT

DS14791 Rev 3

PP9 - XSPIM_P1_IO9 - - FMC_D25 - - EVENTOUT

PP10 - XSPIM_P1_IO1O - ETH1_MDC FMC_D26 - - EVENTOUT

PP11 - XSPIM_P1_IO11 - - FMC_D27 - - EVENTOUT

PP12 - XSPIM_P1_IO12 - - FMC_D28 - - EVENTOUT

PP13 - XSPIM_P1_IO13 - - FMC_D29 - - EVENTOUT

PP14 - XSPIM_P1_IO14 - - FMC_D30 - - EVENTOUT

PP15 - XSPIM_P1_IO15 - - FMC_D31 - LCD_B5 EVENTOUT

PQ0 - - - - - - - EVENTOUT

STM32N6x5xx STM32N6x7xx
PQ1 - - - - - - - EVENTOUT

PQ2 - SAI2_SCK_B - - - - - EVENTOUT

PQ3 - - - - - - - EVENTOUT
Port Q

PQ4 - - - - - - - EVENTOUT

PQ5 - SAI2_FS_B - - - - - EVENTOUT

PQ6 - SAI2_SD_B - - - - - EVENTOUT

PQ7 - SAI2_MCLK_B - - - - - EVENTOUT

STM32N6x5xx STM32N6x7xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with junction temperature TJ = 25 °C and TJ = TJ max (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, supply voltage
VDD = 3.3 V or 1.8 V (operating condition), VDDA18ON = 1.8 V, and nominal
VDDCORE = 0.81 V. They are only given as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error lower than or equal to the value indicated (mean ± 2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines, and are
not tested.

5.1.4 Loading capacitor

Unless otherwise specified, the loading conditions used for pin parameter measurement are
shown in Figure 13.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 14.

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Figure 13. Pin loading conditions Figure 14. Pin input voltage

Device pin
Device pin

VIN
C = 50 pF

DT47493V1

DT47494V1

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5.1.6 Power supply scheme

Figure 15. Power supply scheme

VDDA18USB

VDDA18CSI
VDD33USB
VDDIO2
VDDIO4

VDDIO5

VDDIO3

VDDCSI
PC[1] PC[0] Port 1 Port 2
USB HS UCPD CSI
PC[12:6] PC[5:2] PO[5:0] PN[12:0]
PHYs I/Os PHY
PH[2,9] PE[4] PP[15:0]
I/Os I/Os
XSPIM I/Os VSS VSS VSS
VSS VSS VSS
Core domain (VCORE)
VDDCORE
VSS

I/O (CPU, system logic,

I/Os logic EXTI, peripherals, RAM)

VDD
VDDA18PMU
Retention domain
VDDSMPS
Step-down ITCM
VLXSMPS
converter
VFBSMPS DTCM

VSSSMPS
ITCM FLEX
VDD

LSI, WKUP, VRET

RET I/O
IWDG, BSEC,
I/Os logic
RIFSC
VSS
VDDA18AON OTP, HSE, HSI, MSI VSS

VDDA18PLL PLLs Backup domain

Power
V08CAP switch

VDD VSW Backup VBKP

VBAT regulator
Power switch

Backup
LSE, RTC, RAM
BKUP I/O
I/Os TAMP, backup
logic
registers, reset

VSS
VSS
VDDA18ADC Analog domain

VREFBUF ADCs
VREF+ VREF+
VREF- VREF-
VSSA
MSv70448V3

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Caution: Each power supply pair (VDD / VSS, VDDCORE / VSS, VDDA / VSSA) must be decoupled with
filtering ceramic capacitors. These capacitors must be placed as close as possible to (or
below) the appropriate pins to ensure correct device functionality. It is not recommended to
remove them to reduce PCB size or cost, as this can cause incorrect operation of the
device. The number of needed capacitors and their values are detailed in AN5967 “Getting
started with the hardware development for STM32N6 MCUs”, available on www.st.com.

5.1.7 Current consumption measurement

The IDD parameters in the tables in the next sections represent the total MCU consumption,
including the current supplying VDD, VDDA, and VDDCORE.

Figure 16. Current consumption measurement scheme

IDDCORE IDDA18
VDDCORE VDDA18PLL
VDDCORE VDDA18
VDDCSI VDDA18CSI

IDD VDDA18USB
VDD
IDDA18AON
VDD VDDA18AON
VDDA18AON

IDD33USB
IDDiox VDD33USB
VDDIO2
VDD33USB
VDDIOx
VDDIO3

VDDIO4
IDDA18ADC
VDDA18ADC
VDDIO5
VREF+ VDDA18ADC
IBAT
VBAT
VSS VSSA VBAT MS56792V1

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21, Table 22, and Table 23
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended
mission profiles are available on demand.

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Table 21. Voltage characteristics(1)(2)

Symbol Ratings Min Max Unit

External main supply voltage for 1.8 V range

VDDX - VSS 2.0
(including VDD, VDDIOx, VBAT)
External main supply voltage for 3.3 V range
VDDX - VSS 3.7
(including VDD, VDDIOx, VBAT, VDD33USB)
VDD18OAON - VSS 1.8 V supply voltage -0.3 1.98
External core supply voltage
VDDCORE - VSS 0.99 V
(including VDDCORE, VDDCSI)
1.8 V supply voltage
VDDA18 - VSS 1.98
(including VDDA18PLL, VDDA18CSI, VDDA18USB, VDDA18ADC)
Input voltage on TT_xx pins (VDDIOxVRSEL = 0) 3.6
VIN Input voltage on TT_xx pins (VDDIOxVRSEL = 1) VSS - 0.3 1.98
Input voltage on UCPD pins VDD33USB + 1.935
Variations between different VDDX power pins of the
|∆VDDx| -
same domain 50.0 mV
|VSSx-VSS| Variations between all the different ground pins -
1. All main power and ground pins must always be connected to the external power supply, in the permitted range.
2. Specified by design, not tested in production.

Table 22. Current characteristics

Symbol Ratings Conditions Max Unit

-40 °C < TJ ≤ 90 °C 20
IIO Output current sunk by any I/O and control pin 90 °C < TJ ≤ 110 °C 10
mA
TJ > 110 °C 4
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(1) ±25
1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).

Table 23. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150

°C
TJMAX Maximum junction temperature 125

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5.3 Operating conditions

5.3.1 General operating conditions

Table 24. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit

Clock frequency of Cortex-CM55

FCPU 0 - 600
(VOS low)
Clock frequency of Cortex-CM55 in
FCPU overdrive Base-TCM with 0 wait states 0 - 800
overdrive (VOS high)
Flex-TCM with 1 wait state
FNPU Clock frequency of NPU/CNN 0 - 800
Clock frequency of NPU/CNN
FNPU overdrive 0 - 1000 MHz
in overdrive
Fck_icn_hsl Clock frequency of USB, ETH buses - 0 - 400
FHCLK Clock frequency of AHB bus - 0 - 200
Fck_cpu_axi Clock frequency of AXI CPU bus - 0 - 400
Clock frequency of APB buses
FPCLKx - 0 - FHCLKx / 4
(x = 1, 2, 3, 4, 5)
1.8 V range 1.62 1.8 1.98
VDD(1) I/Os supply voltage
3.3 V range 3.0 3.3 3.6
VDDA18ON(1) Internal analog supply voltage - 1.71 1.8 1.935

Specific I/Os supply voltage 1.8 V range 1.71 1.8 1.935

VDDIOx
(x = 2, 3, 4, 5) 3.3 V range 2.7 3.3 3.6
SoC Run mode (VOS low) 0.782 0.81 0.842
SoC Run mode (VOS high) 0.858 0.89 0.921
Sleep mode (SoC Run
mode, peripheral clock 0.782 0.81 0.842
stopped, VOS low)
VDDCORE Main digital logic supply voltage
Sleep mode (SoC Run
mode, peripheral clock 0.858 0.89 0.921 V
stopped, VOS high)
Stop mode (SVOS low) 0.64 0.68 0.71
Stop mode (SVOS high) 0.782 0.81 0.842
VDDA18PLL 1.8 V analog supply for PLL FNPU range 1.62 1.8 1.98
VDDA18CSI 1.8 V analog supply for CSI FNPU overdrive range 1.746 1.8 1.98
VDDCSI CSI operating voltage - 0.784 0.81 0.842
VDD18USB 1.8 V analog supply for USBPHY - 1.746 1.8 1.935
VDD18ADCx ADC operating voltage (x = 1, 2) - 1.62 1.8 1.98
VREF+ ADC reference voltage - 1.1 - VDD18ADC
VBAT Backup operating voltage - TBD - 3.6

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Table 24. General operating conditions (continued)

Symbol Parameter Conditions Min Typ Max Unit

VDD18SMPS SMPS supply voltage - 1.62 1.8 1.89

VDDA18PMU SMPS analog supply voltage - 1.62 1.8 1.89
V
Backup regulator output voltage
V08CAP - 0.72 0.8 0.88
(SMPS)
Min VDDxx
I/O TT_xx in the 1.8 V range
+ 0.3(2)
Min(VDD,
VIN I/O input voltage I/O TT_xx in the 3.3 V range -0.3 - VDDIOx) + V
0.3
VDD18ADC
I/O TT_a
+ 0.3
PDR_ON Power-down reset enable - 1.62 1.8 1.98 V
1. Must be present before any other supply.
2. VDDxx depends upon power ring on I/Os (VDD, VDDIOx, VDDA18ADC, VDDA18USB, VDD33USB).

5.3.2 Operating conditions at power-up/power-down

The parameters in Table 25 are evaluated by characterization under ambient temperature
and supply voltage conditions summarized in Table 24.

Table 25. Operating conditions at power-up/power-down(1)

Symbol Parameter Conditions Min Max Unit

tVDD VDD, VDDIOx transitions

tVDDA18AON VDDA18AON transitions 20
tVDDcore VDDCORE transitions
Rise and fall
tVDDCSI VDDCSI transitions 1500 µs/V
time rates
tVDDA18 VDDAPLL, VDDA18CSI, VDDA18USB, VDDA18ADC transitions
10
tVDD33 VDD33USB transitions
tVBat VBAT transitions
1. Evaluated by characterization, not tested in production, unless otherwise specified.

5.3.3 Embedded reset and power control block characteristics

The parameters in Table 26 are derived under ambient temperature and supply voltage
conditions summarized in Table 24.

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tRSTTEMPO (1) Reset temporization after POR released - 200 - - μs

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Table 26. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

VPOR Power-on reset threshold Rising edge 1.62 1.67 1.71

V
VPDR Power-down reset threshold Falling edge 1.58 1.63 1.67
Vhyst POR Hysteresis voltage of POR/PDR - - 40 - mV
Rising edge - - -
VBOR0 Brown-out reset threshold 0 VDD
Falling edge - - - V
VBOR1 Brown-out reset threshold 1 Falling edge - - -
Vhyst BOR0 Hysteresis voltage of BOR0 - - 40 -
mV
Vhyst BOR1 Hysteresis voltage of BOR1 - - 80 -
VPOR ANA Power-on reset threshold Rising edge 1.62 1.67 1.71
V
VPDR ANA Power-down reset threshold VDDA18AON Falling edge 1.58 1.63 1.67
Vhyst POR ANA Hysteresis voltage of POR/PDR - - 40 - mV
Normal modes 0.61 0.66 0.71
VRDY VDDCORE Threshold on rising edge V
LPLV modes 0.50 0.55 0.61
Vhyst VDDCORE Hysteresis on falling edge VDDCORE - - 21 - mV
Rising edge 180 - -
Tdelay VDDCORE Delay after detection μs
Falling edge - 0 -
1. Specified by design, not tested in production.

5.3.4 SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter, which requires
external the components specified in Figure 2 and Table 27.

Table 27. Characteristics of SMPS step-down converter external components

Symbol Parameter Min Typ Max Unit

Lout External coil - 0.9 - µH

Cout External output capacitor - 4x15 - µF
Zout Output Impedance 16 25 33 mΩ

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The SMPS characteristics for external usage are given in Table 28. Figure 17 details the
average efficiency with VDD18 in the 1.62 to 1.89 V range.

Table 28. Characteristics of SMPS step-down(1)

Module Symbol Parameter Conditions Min Typ Max Unit

- VDDA18 Input voltage range - 1.62 1.80 1.89 V

SVOSLOW = 0.63 V,
VS_SD[1:0] = 00
VOSLOW = 0.81 V,
VS_SD[1:0]=01
0.63 - 0.9 V
VDDCORE Output regulated voltage SVOSHIGH=0.81 V,
VS_SD[1:0]=10
VOSHIGH = 0.89 V,
VS_SD[1:0]=11
Programming step - 10 - mV
VDDCORE_acc Output voltage accuracy Target only -2 - 2 %
SD converter

VDDCORE_rpp Output voltage ripple(2) - - - 30 mVPP

IOUT Maximum output current - - - 2200 mA
Iout = 0 mA, HP mode - 3.85 -
IQ Total quiescent current
Iout = 0 mA, LP mode - 3.2 - µA
IQ_LEAKAGE Input leakage current SD converter OFF - 2.6 -
Reference switching
FREFCLK - - 2.4 - MHz
frequency
∆Iout =1 A,
LOAD_TR_REG Load transient regulation - - 40
Trise/fall = 500 ns
mV
∆VDDA18 = TBD,
LINE_TR_REG Line transient regulation - - 5
Trise/fall = TBD
POWUP_OVERSHOOT Power-up overshoot - - - 20 mV
VSW supply
VSW Output voltage accuracy VSW = VSBAT in VBAT 2 3 3.62 V
regulator
Backup

mode, else = VDD

Derived from VDD
VSW_slew Slew rate to limit EOS 20 - - µs/V
slew rate
1. Evaluated by characterization, not tested in production, unless otherwise specified.
2. Noise at frequencies higher than 50-100 MHz should not be included.

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Electrical characteristics STM32N6x5xx STM32N6x7xx

Figure 17. SMPS power efficiency vs. ILOAD (A)

5.3.5 Embedded voltage reference

The parameters in Table 29 are derived under ambient temperature and supply voltage
conditions summarized in Table 24.

Table 29. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT(1) Internal reference voltage -40 °C ≤ TJ ≤ +130 °C 0.792 0.8 0.808 V

ADC sampling time when reading
tS_vrefint(2) - 34 - - ns
the internal reference voltage
Internal reference voltage spread
∆VREFINT - - 11 mV
over the temperature range -40 °C ≤ TJ ≤ +130 °C
TCoeff Temperature coefficient - - 43 ppm/°C
VDDCoeff Voltage coefficient 1.71 V ≤ VDDA18AON ≤ 3.6 V - - 1250 ppm/V
1. Guaranteed by test in production.
2. Specified by design, not tested in production.

Table 30. Embedded reference voltage calibration value

Symbol Parameter Memory address

VREFINT_CAL Raw data acquired on ADC1 at 30 °C, VDDA18ADC = VREF+ = 1.8 V 0x4400 01B8[11:0](1)
1. BSEC_FVR110 register, not automatically shadowed with OTP content, so a fuse read sequence must be issued to get the
register updated once (clear after reading). Refer to RM0486, BSEC section “Operations on fuses”.

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5.3.6 Supply current characteristics

The current consumption is measured as described in Figure 16. It depends upon several
parameters, such as operating voltage, ambient temperature, I/O pin loading, device
software configuration, operating frequency, I/O pin switching rate, program location in
memory, and executed binary code. All the Run mode current consumption measurements
are performed with a CoreMark code unless otherwise specified. Supply current
characteristics are evaluated by characterization, not tested in production unless otherwise
specified.

Typical and maximum current consumption

The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled, except when otherwise mentioned
• RTC/LSE are disabled, unless otherwise specified
• BKPSRAM, backup supplies in low-power modes (such as Stop, Standby and VBAT)
are disabled, unless otherwise specified
• Unless otherwise specified, the typical values are obtained for:
– VDD, VDDIOx = 1.8 V
– VBAT = 3.3 V
– VDDCORE = 0.81 V
– VDDA1V8, VDDA18AON = 1.8 V
The parameters given in tables 31 to 45 are evaluated by characterization under ambient
temperature and supply voltage conditions summarized in Table 24.

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Table 31. Current consumption in Run mode

SMPS external

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

All peripherals VOS high 800(3) 0.30 0.30 0.33 0.35 0.40
Code with data
disabled VOS low 600 (4)
0.30 0.30 0.33 0.35 0.40
processing running
(2)
from ITCM VOS high 800(3) 0.30 0.30 0.33 0.35 0.39
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600 (4)
0.30 0.30 0.33 0.35 0.40
(3)
All peripherals VOS high 800 0.33 0.32 0.35 0.38 0.42
Code with data
disabled VOS low 600(4) 0.33 0.32 0.35 0.38 0.42
processing running
(2)
from ITCM VOS high 800(3) 0.33 0.32 0.35 0.38 0.42
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
0.33 0.32 0.35 0.38 0.42
IDD mA
Code with data All peripherals VOS high 800(3) 0.30 0.30 0.33 0.35 0.40
processing running disabled VOS low 600(4) 0.30 0.30 0.33 0.35 0.40
from AXI-SRAM2,
Cache ON (2) All peripherals VOS high 800(3) 0.30 0.30 0.33 0.35 0.39
HSI, VDD = 1.8 V enabled VOS low 600 (4)
0.30 0.30 0.33 0.35 0.40

Code with data All peripherals VOS high 800(3) 0.33 0.32 0.35 0.38 0.42
processing running disabled VOS low 600(4) 0.33 0.32 0.35 0.38 0.42
from AXI-SRAM2,
Cache OFF (2) All peripherals VOS high 800(3) 0.33 0.32 0.35 0.38 0.42
HSI, VDD = 1.8 V enabled VOS low 600 (4)
0.33 0.32 0.35 0.38 0.42
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 32. Current consumption in Run mode

SMPS internal
frcc_c_ck
Symbol Conditions Max(1) Unit
(MHz)
Typ
TJ = 125 °C
(3)
All peripherals VOS high 800 0.27 0.40
Code with data
disabled VOS low 600(4) 0.27 0.40
processing running
(2)
from ITCM VOS high 800 (3)
0.27 0.39
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600(4) 0.27 0.40
(3)
All peripherals VOS high 800 0.30 0.42
Code with data
disabled VOS low 600(4) 0.30 0.42
processing running
(2)
from ITCM VOS high 800 (3)
0.30 0.42
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
0.30 0.42
IDD mA
(3)
Code with data All peripherals VOS high 800 0.27 0.40
processing running disabled VOS low 600(4) 0.27 0.40
from AXI-SRAM2,
(3)
Cache ON (2) All peripherals VOS high 800 0.27 0.39
HSI, VDD = 1.8 V enabled VOS low 600(4) 0.27 0.40

Code with data All peripherals VOS high 800(3) 0.30 0.42
processing running disabled VOS low 600(4) 0.30 0.42
from AXI-SRAM2,
(3)
Cache OFF (2) HSI, All peripherals VOS high 800 0.30 0.42
VDD = 1.8 V enabled VOS low 600 (4)
0.30 0.42
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 33. Current consumption (core) in Run mode

SMPS external

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

All peripherals VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
Code with data
disabled VOS low 600 (4)
89.7 115.5 327.3 484.1 756.2
processing running
(2)
from ITCM VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600 (4)
89.7 115.5 327.3 484.1 756.2
(3)
All peripherals VOS high 800 89.7 115.5 327.3 484.1 756.2
Code with data
disabled VOS low 600(4) 89.7 115.5 327.3 484.1 756.2
processing running
(2)
from ITCM VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
89.7 115.5 327.3 484.1 756.2
IDDCORE mA
Code with data All peripherals VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
processing running disabled VOS low 600(4) 89.7 115.5 327.3 484.1 756.2
from AXI-SRAM2,
Cache ON (2) All peripherals VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
HSI, VDD = 1.8 V enabled VOS low 600 (4)
89.7 115.5 327.3 484.1 756.2

Code with data All peripherals VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
processing running disabled VOS low 600(4) 89.7 115.5 327.3 484.1 756.2
from AXI-SRAM2,
Cache OFF (2) All peripherals VOS high 800(3) 89.7 115.5 327.3 484.1 756.2
HSI, VDD = 1.8 V enabled VOS low 600 (4)
89.7 115.5 327.3 484.1 756.2
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 34. Current consumption (core) in Run mode

Max(1) SMPS
frcc_c_ck internal
Symbol Conditions Typ Unit
(MHz)
TJ = 125 °C

All peripherals VOS high 800(3) 84.1 1017.1

Code with data
disabled VOS low 600 (4)
65.4 974.9
processing running
from ITCM(2) VOS high 800 (3)
169.5 1102.1
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600(4) 141.2 1051.3
(3)
All peripherals VOS high 800 82.8 813.1
Code with data
disabled VOS low 600(4) 61.9 824.4
processing running
from ITCM (2) VOS high 800 (3)
168.4 921.8
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600(4) 139.1 852.6
IDDA1V8 mA
Code with data All peripherals VOS high 800(3) 85.3 1016.6
processing running disabled VOS low 600(4) 66.4 974.9
from AXI-SRAM2,
(3)
Cache ON (2) All peripherals VOS high 800 169.9 1100.0
HSI, VDD = 1.8 V enabled VOS low 600(4) 141.5 1050.4

Code with data All peripherals VOS high 800(3) 70.4 795.7
processing running disabled VOS low 600(4) 55.4 744.7
from AXI-SRAM2,
(3)
Cache OFF (2) HSI, All peripherals VOS high 800 155.1 898.8
VDD = 1.8 V enabled VOS low 600(4) 130.8 663.7
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 35. Current consumption (1V8) in Run mode

SMPS external

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

All peripherals VOS high 800(3) 2.23 2.24 2.24 2.26 2.27
Code with data
disabled VOS low 600 (4)
4.73 4.73 4.83 4.86 4.91
processing running
(2)
from ITCM VOS high 800(3) 2.24 2.24 2.24 2.26 2.27
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600 (4)
4.73 4.74 4.84 4.87 4.92
(3)
All peripherals VOS high 800 2.23 2.21 2.22 2.23 2.26
Code with data
disabled VOS low 600(4) 1.55 1.54 1.53 1.53 1.55
processing running
(2)
from ITCM VOS high 800(3) 2.23 2.21 2.22 2.23 2.26
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
1.55 1.54 1.53 1.53 1.55
IDDA1V8 mA
Code with data All peripherals VOS high 800(3) 2.24 2.24 2.24 2.26 2.27
processing running disabled VOS low 600(4) 4.73 4.73 4.83 4.86 4.90
from AXI-SRAM2,
Cache ON (2) All peripherals VOS high 800(3) 2.24 2.24 2.24 2.26 2.27
HSI, VDD = 1.8 V enabled VOS low 600 (4)
4.74 4.75 4.83 4.87 4.92

Code with data All peripherals VOS high 800(3) 2.23 2.21 2.22 2.23 2.26
processing running disabled VOS low 600(4) 1.55 1.54 1.53 1.53 1.55
from AXI-SRAM2,
Cache OFF (2) All peripherals VOS high 800(3) 2.24 2.21 2.22 2.23 2.26
HSI, VDD = 1.8 V enabled VOS low 600 (4)
1.55 1.54 1.53 1.53 1.55
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 36. Current consumption (1V8) in Run mode

SMPS internal
frcc_c_ck
Symbol Conditions Max(1) Unit
(MHz)
Typ
TJ = 125 °C
(3)
All peripherals VOS high 800 2.60 3.12
Code with data
disabled VOS low 600(4) 4.83 5.79
processing running
(2)
from ITCM VOS high 800 (3)
2.67 3.12
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600(4) 4.93 5.79
(3)
All peripherals VOS high 800 2.67 3.09
Code with data
disabled VOS low 600(4) 1.97 2.39
processing running
(2)
from ITCM VOS high 800 (3)
2.67 4.52
All peripherals
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
2.05 2.39
IDDA1V8 mA
(3)
Code with data All peripherals VOS high 800 2.66 3.11
processing running disabled VOS low 600(4) 4.83 5.79
from AXI-SRAM2,
(3)
Cache ON (2) All peripherals VOS high 800 2.67 3.12
HSI, VDD = 1.8 V enabled VOS low 600(4) 4.92 5.79

Code with data All peripherals VOS high 800(3) 2.61 3.09
processing running disabled VOS low 600(4) 1.96 2.39
from AXI-SRAM2,
(3)
Cache OFF (2) HSI, All peripherals VOS high 800 2.67 5.40
VDD = 1.8 V enabled VOS low 600 (4)
2.05 2.38
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 37. Current consumption (Always ON) in Run mode

SMPS external

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

All peripherals VOS high 800(3) 0.50 0.50 0.53 0.54 0.55
Code with data
disabled VOS low 600 (4)
0.50 0.50 0.53 0.54 0.55
processing running
(2)
from ITCM VOS high 800(3) 0.50 0.50 0.53 0.54 0.55
All peripherals
HSI, VDD = 1.8 V
enabled VOS low 600 (4)
0.50 0.50 0.53 0.54 0.55
(3)
All peripherals VOS high 800 4.86 5.18 4.91 4.82 4.72
Code with data
disabled VOS low 600(4) 4.85 5.18 4.91 4.82 4.72
processing running
(2)
from ITCM VOS high 800(3) 5.08 5.40 5.13 5.05 4.95
All peripherals
HSE, VDD = 1.8 V
IDDA1V8AON

enabled VOS low 600 (4)

5.08 5.40 5.14 5.05 4.95
mA
Code with data All peripherals VOS high 800(3) 0.50 0.50 0.53 0.54 0.55
processing running disabled VOS low 600(4) 0.50 0.50 0.53 0.54 0.55
from AXI-SRAM2,
Cache ON (2) All peripherals VOS high 800(3) 0.50 0.50 0.53 0.54 0.55
HSI, VDD = 1.8 V enabled VOS low 600 (4)
0.50 0.50 0.53 0.54 0.55

Code with data All peripherals VOS high 800(3) 4.85 5.18 4.91 4.82 4.72
processing running disabled VOS low 600(4) 4.85 5.18 4.91 4.82 4.72
from AXI-SRAM2,
Cache OFF (2) All peripherals VOS high 800(3) 5.08 5.40 5.13 5.05 4.95
HSI, VDD = 1.8 V enabled VOS low 600 (4)
5.08 5.40 5.14 5.05 4.95
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 38. Current consumption (Always ON) in Run mode

SMPS internal
frcc_c_ck
Symbol Conditions Max(1) Unit
(MHz)
Typ
TJ = 125 °C
(3)
All peripherals VOS high 800 0.45 0.56
Code with data
disabled VOS low 600(4) 0.45 0.56
processing running
from ITCM(2) (3)
All peripherals VOS high 800 0.45 0.56
HSI, VDD = 1.8 V
enabled VOS low 600(4) 0.45 0.56
(3)
All peripherals VOS high 800 4.42 4.64
Code with data
disabled VOS low 600(4) 4.42 4.61
processing running
from ITCM (2) (3)
All peripherals VOS high 800 4.62 4.62
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
4.62 4.88
IDDA1V8AON mA
(3)
Code with data All peripherals VOS high 800 0.45 0.56
processing running disabled VOS low 600(4) 0.45 0.56
from AXI-SRAM2,
(3)
Cache ON (2) All peripherals VOS high 800 0.45 0.56
HSI, VDD = 1.8 V enabled VOS low 600(4) 0.45 0.56

Code with data All peripherals VOS high 800(3) 4.42 4.65
processing running disabled VOS low 600(4) 4.43 4.64
from AXI-SRAM2,
(3)
Cache OFF (2) HSI, All peripherals VOS high 800 4.65 4.51
VDD = 1.8 V enabled VOS low 600 (4)
4.62 4.86
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 39. Current consumption (SMPS) in Run mode

SMPS internal
frcc_c_ck
Symbol Conditions Max(1) Unit
(MHz)
Typ
TJ = 125 °C
(3)
All peripherals VOS high 800 54.10 687.5
Code with data
disabled VOS low 600(4) 54.10 687.5
processing running
from ITCM(2) (3)
All peripherals VOS high 800 36.18 584.5
HSI, VDD = 1.8 V
enabled VOS low 600(4) 99.93 757.3
(3)
All peripherals VOS high 800 78.54 643.8
Code with data
disabled VOS low 600(4) 53.35 489.9
processing running
from ITCM (2) (3)
All peripherals VOS high 800 34.29 460.7
HSE, VDD = 1.8 V
enabled VOS low 600 (4)
99.58 558.5
IDDA1V8AON mA
(3)
Code with data All peripherals VOS high 800 77.70 473.4
processing running disabled VOS low 600(4) 55.50 687.8
from AXI-SRAM2,
(3)
Cache ON (2) All peripherals VOS high 800 37.12 585.4
HSI, VDD = 1.8 V enabled VOS low 600(4) 100.6 757.5

Code with data All peripherals VOS high 800(3) 79.03 643.2
processing running disabled VOS low 600(4) 42.48 477.0
from AXI-SRAM2,
(3)
Cache OFF (2) HSI, All peripherals VOS high 800 30.53 405.0
VDD = 1.8 V enabled VOS low 600 (4)
92.21 530.0
1. Guaranteed by characterization results unless otherwise specified.
2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
3. cpu_overdrive range frequency.
4. cpu_nominal range frequency.

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Table 40. Current consumption in Sleep mode

SMPS external

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

All peripherals VOS high 800(2) 0.29 0.28 0.31 0.33 0.38
disabled VOS low 600 (3)
0.9 0.28 0.31 0.33 0.38
IDD
All peripherals VOS high 800(2) 0.9 0.28 0.31 0.33 0.38
enabled VOS low 600 (3)
0.9 0.28 0.31 0.33 0.38
(2)
All peripherals VOS high 800 51.3 75.1 284.5 437.8 713.9
disabled VOS low 600(3) 43.9 66.0 265.4 413.5 677.5
IDDCORE
All peripherals VOS high 800(2) 143.3 171.1 382.3 542.8 809.4
enabled VOS low 600 (3)
124.7 149.9 349.2 500.0 760.0
HSI,
mA
VDD = 1.8 V (2)
All peripherals VOS high 800 2.14 2.13 2.14 2.15 2.15
disabled VOS low 600(3) 4.50 4.52 4.61 4.64 4.67
IDDA1V8(4)
All peripherals VOS high 800(2) 2.14 2.14 2.15 2.15 2.16
enabled VOS low 600 (3)
4.53 4.52 4.61 4.65 4.69
(2)
All peripherals VOS high 800 0.26 0.26 0.28 0.29 0.30
disabled VOS low 600(3) 0.26 0.26 0.28 0.29 0.30
IDDA1V8AON
All peripherals VOS high 800(2) 0.47 0.48 0.50 0.51 0.53
enabled VOS low 600 (3)
0.48 0.48 0.50 0.51 0.53
1. Guaranteed by characterization results unless otherwise specified.
2. cpu_overdrive range frequency
3. cpu_nominal range frequency.
4. Sleep mode applies only to the CPU subsystem (CPU clock is stopped). PLL clock configuration changes.

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Table 41. Current consumption in Sleep mode

SMPS internal

frcc_c_ck Max(1)
Symbol Conditions Unit
(MHz)
Typ
TJ =
125 °C

All peripherals VOS high 800(2) 0.29 0.38

disabled VOS low 600 (3)
0.29 0.38
IDD
All peripherals VOS high 800(2) 0.29 0.38
enabled VOS low 600 (3)
0.29 0.38
(2)
All peripherals VOS high 800 47.9 973.0
disabled VOS low 600(3) 41.3 942.3
IDDCORE(4)
All peripherals VOS high 800(2) 134.0 1058.9
enabled VOS low 600 (3)
117.6 1014.4
(2)
All peripherals VOS high 800 28.5 653.6
disabled VOS low 600 (3)
22.7 563.7
IDDSMPS(4) HSI, VDD = 1.8 V mA
All peripherals VOS high 800(2) 80.9 724.4
enabled VOS low 600(3) 67.1 623.6
(2)
All peripherals VOS high 800 2.56 2.97
disabled VOS low 600(3) 4.80 5.51
IDDA1V8(4)
All peripherals VOS high 800(2) 2.67 2.98
enabled VOS low 600 (3)
4.92 5.52
(2)
All peripherals VOS high 800 0.25 0.31
disabled VOS low 600 (3)
0.25 0.32
IDDA1V8AON
All peripherals VOS high 800(2) 0.45 0.54
enabled VOS low 600(3) 0.45 0.54
1. Guaranteed by characterization results unless otherwise specified.
2. cpu_overdrive range frequency
3. cpu_nominal range frequency.
4. Sleep mode applies only to the CPU subsystem (CPU clock is stopped). PLL clock configuration changes.

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Table 42. Current consumption in Stop mode

SMPS external

Max(1)
Symbol Conditions Unit
Typ
TJ = TJ = TJ = TJ =
25 °C 85 °C 105 °C 125 °C

IDD 9.1 27.5 191.4 314.8 524.8 mA

IDDCORE 273.4 278.5 306.2 329.1 373.0
VDD = 1.8 V SVOS high
IDDA1V8 61.7 65.1 83.4 95.0 114.4 μA
IDDA1V8AON 41.7 41.7 56.7 64.4 76.2
1. Guaranteed by characterization results unless otherwise specified.

Table 43. Current consumption in Stop mode

SMPS internal

Symbol Conditions Max(1) Unit

Typ
TJ = 125 °C

SVOS high 273.4 362.1

IDD μA
SVOS low 273.4 362.1
SVOS high 8.62 744.2
IDDCORE mA
SVOS low 8.70 801.8
SVOS high 358.5 1022.1
IDDA1V8 VDD = 1.8 V μA
SVOS low 362.7 1050.6
SVOS high 4.16 434.2
IDDSMPS mA
SVOS low 3.60 396.0
SVOS high 56.05 87.97
IDDA1V8AON μA
SVOS low 41.97 86.39
1. Guaranteed by characterization results unless otherwise specified.

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Table 44. Current consumption in Standby mode

Max(1)
Symbol Conditions Typ Unit
TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C

Backup RAM OFF

47.0 65.9 306 504 801
RTC and LSE OFF
Backup RAM ON
48.4 68.7 339 571 927
IWDG off, RTC and LSE OFF
IDD μA
VDD = 1.8 V Backup RAM OFF
47.8 66.3 306 503 800
RTC and LSE OFF
Backup RAM ON
48.4 69.0 339 570 927
RTC and LSE OFF
Backup RAM OFF
42 80 122 133 143
RTC and LSE OFF
Backup RAM ON
42 80 122 133 143
RTC and LSE OFF
IDDA18ON IWDG off μA
Backup RAM OFF
42 80 122 133 143
RTC and LSE OFF
Backup RAM ON
42 80 122 133 143
RTC and LSE OFF
1. Guaranteed by characterization, unless otherwise specified.

Table 45. Current consumption in VBAT mode

Max(1)
Symbol Conditions Typ Unit
TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C

Backup RAM OFF

- 36.5 41.2 62.7 89.8
RTC and LSE(2)
Backup RAM ON
- 29.2 79.9 147.3 232.4
RTC and LSE OFF
IDDVBAT VDD = 3.3 V μA
Backup RAM OFF
20.3 20.7 45.7 66.5 92.1
RTC and LSE OFF
Backup RAM ON
21.6 23.7 85.60 145.9 233.5
RTC and LSE OFF
1. Guaranteed by characterization, unless otherwise specified.
2. LSE system modes Vsw domain only.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.17.

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For the output pins, any internal or external pull-up or pull-down and external load must also
be considered to estimate the current consumption.
An additional current consumption is due to I/Os configured as inputs when an intermediate
voltage level is applied externally. This is caused by the input Schmitt trigger circuits used to
discriminate the input value. Unless this specific configuration is required by the application,
this supply current consumption can be avoided by configuring these I/Os in analog mode.
This is the case of ADC input pins, which must be configured as analog inputs.
Caution: Any floating input pin can settle to an intermediate voltage level or switch inadvertently, as a
result of external electromagnetic noise. To avoid current consumption related to floating
pins, they must be configured in analog mode, or forced internally to a definite digital value.
This can be done by using pull-up/down resistors, or by configuring the pins in output mode.
I/O dynamic current consumption
The I/Os used in application contribute to the consumption. When an I/O pin switches, it
uses the current from the I/O supply voltage to supply the pin circuitry, and to
charge/discharge the capacitive load (internal and external) connected to it:

I SW = V DD × f SW × C
where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDD is the I/O supply voltage
• fSW is the I/O switching frequency
• C is the total capacitance seen by the I/O pin: C = CINT + CEXT
– CINT is the I/O pin capacitance
– CEXT is any connected external device pin capacitance

5.3.7 Wake-up time from low-power modes

The times given in Table 46 are measured starting from the wake-up event trigger up to the
first instruction executed by the CPU.
All timings are derived from tests performed under ambient temperature, VDD and
VDDA18AON = 1.8 V, VDDCORE at nominal voltage.
General conditions unless otherwise noted:
• CM55 CPU software in SRAMx
• CPU goes to low power mode after WFI instruction.

Table 46. Low-power mode wake-up timings(1)(2)

Symbol Parameter Conditions Typ Unit

tWU(Sleep) Wake-up time from Sleep - 38 CPU clock cycles

SVOS HIGH, HSI 64 MHz, clock disabled 10
SVOS HIGH, HSI 64 MHz, clock enabled 5
tWUDSTOP Wake-up time from Stop
SVOS HIGH, MSI 4 MHz, clock disabled 65 µs
SVOS HIGH, MSI 4 MHz, clock enabled 55
tWUSTBY Wake-up time from Standby mode - 400

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1. Evaluated by characterization, not tested in production, unless otherwise specified.

2. Measured from the wake-up event to the point in which the application code reads the first instruction.

5.3.8 External clock sources characteristics

HSE clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
Digital and analog bypass modes are available.
The external clock signal must respect the requirements specified in Section 5.3.17. The
recommended clock input waveform is shown in Figure 18 for digital bypass mode and in
Figure 19 for analog bypass mode. In the latter, the clock can be a sinusoidal waveform.

Figure 18. HSE clock source AC timing diagram (digital bypass)

VHSEH
90 %
10 %
VHSEL

tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE

External fHSE_ext
IL
clock source OSC_IN

MS56820V1
STM32

Figure 19. HSE clock source AC timing diagram (analog bypass)

VHSE

90%

VPP

10%

THSE tr(HSE) t

External
fHSE_ext OSC_IN
clock source IL
MS56821V1

STM32

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The characteristics of digital and analog bypass are defined in the following tables.

Table 47. HSE clock characteristics (digital bypass)(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext User external clock source 1.8 V range 16 40 48 MHz

VHSEH OSC_IN high level voltage 0.7 x VDDA18AON - VDDA18AON
1.8 V only V
VHSEL OSC_IN low level voltage - - 0.3 x VDDA18AON
tw(HSEH)
OSC_IN high or low time - 7 - - ns
tw(HSEL)
1. Specified by design, not tested in production.

Table 48. HSE clock characteristics (analog bypass)(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source 16 40 48 MHz

tHSE_ext Duty cycle 1.8 V range 45 50 55
%
Duty cycle deterioration - ±10 ±30
VHSEH OSC_IN high level voltage - 0.7 x VDDA18AON - VDDA18AON
V
VPP OSC_IN peak to peak amplitude - VSS - 0.67 x VDDA18AON(2)
tSU(HSE) Startup time VDD stabilized - 1 10(3) μs
Rise and fall time (10 to 90%
tr(HSE)
threshold levels of the input peak - 0.05 x tHSE - 0.3 x tHSE ns
tf(HSE)
to peak amplitude
1. Specified by design, not tested in production.
2. Minimum peak-to-peak amplitude, 25 °C, 0.1 < VDC < VDDA18AON - 0.1 V (VDC is the DC component of the input signal).
3. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.

HSE clock generated from a crystal/ceramic resonator

The clock can be supplied with a 16 to 48 MHz crystal/ceramic resonator oscillator. All the
information given in this paragraph are based on characterization results obtained with
typical external components specified in Table 49. In the application, the resonator and the
load capacitors must be placed as close as possible to the oscillator pins to minimize output
distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more
details on the resonator characteristics (frequency, package, accuracy).

Table 49. HSE clock characteristics generated from crystal/ceramic resonator(1)

Symbol Parameter Conditions Min Typ Max Unit

FHSE_ext User external clock source 1.8 V range 16 40 48 MHz

Gmcritmax Maximum critical crystal gm Startup - - 1.95 mA/V
Startup - - 10
IDD(HSE) Current consumption on VDDA18AON VDD =1.8 V, Rm= 400 Ω, mA
- 4.8 -
CL = 6 pF, 48 MHz

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Table 49. HSE clock characteristics generated from crystal/ceramic resonator(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

tSU(HSE) Startup time VDD stabilized - 2 - ms

RF Internal feedback equivalent resistor - - 250 - kΩ
1. Specified by design, not tested in production.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors,
designed for high-frequency applications, and selected to match the requirements of the
crystal or resonator (see Figure 20). CL1 and CL2 are usually the same size. The crystal
manufacturer typically specifies a load capacitance, which is the series combination of CL1
and CL2. The PCB and pin capacitance must be included (4 pF can be used as a rough
estimate of the combined pin and board capacitance).

Figure 20. Typical application with a 40 MHz crystal

CL1
OSC_IN fHSE

Bias
40 MHz
RF controlled
crystal
gain

MS56818V1
OSC_OUT
STM32
CL2

Note: For information on selecting the crystal, refer to AN2867 “Oscillator design guide for
STM8AF/AL/S, STM32 MCUs and MPUs”, available from www.st.com.

LSE user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal must respect the values indicated in Table 65. The recommended
clock input waveforms are shown in Figure 21 for digital bypass and Figure 22 for analog
bypass.

Figure 21. LSE clock source AC timing diagram (digital bypass)

VLSEH
90 %
10 %
VLSEL

t r(LSE) t W(LSE) t
t f(LSE) t W(LSE)

TLSE

External f LSE_ext
clock source OSC32 _IN IL
MS56819V1

STM32

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Figure 22. LSE clock source AC timing diagram (analog bypass)

VLSE

VPP

TLSE t

External
fLSE_ext OSC32_IN
clock source IL

STM32
MSv63037V1

The characteristics of digital and analog bypass are defined in the following tables.

Table 50. LSE clock characteristics (digital bypass)(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User external clock source - - 32.768 - kHz

VLSEH OSC_IN high level voltage - 0.75 x VSW - VSW(2)
V
VLSEL OSC_IN low level voltage - - - 0.25 x VSW
tw(LSE OSC_IN high or low time - 250 - - ns
1. Specified by design, not tested in production.
2. VSW is equal to VDD when present, to VBAT otherwise.

Table 51. LSE clock characteristics (analog bypass)(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User external clock source - - 32.768 - kHz

VLSE Absolute input range - 0 - VSW(2)
V
VPP OSC_IN peak to peak amplitude - 0.2(3) 1 -
1. Specified by design, not tested in production.
2. VSW is equal to VDD when present, to VBAT otherwise.
3. Minimum peak-to-peak amplitude, 25 °C, 0.1 < VDC < VDDA18AON - 0.1 V (VDC is the DC component of the input signal).

LSE clock generated from a crystal/ceramic resonator

The low-speed external clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this paragraph are based on characterization results
obtained with typical external components specified in Table 52. In the application, the
resonator and the load capacitors must be placed as close as possible to the oscillator pins

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to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on its characteristics (frequency, package, accuracy).

Table 52. LSE clock characteristics generated from crystal/ceramic resonator(1)

Symbol Parameter Conditions Min Typ Max Unit

FLSE Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00, low drive capability - - 0.5

Maximum critical LSEDRV[1:0] = 01, medium-low drive capability - - 0.75

Gmcritmax μA/V
crystal gm LSEDRV[1:0] = 10, medium-high drive capability - - 1.7
LSEDRV[1:0] = 11, high drive capability - - 2.7
tSU(2) Startup time VSW stabilized - 2 - s
1. Specified by design, not tested in production.
2. Startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This
value is measured for a standard crystal resonator, it can vary significantly with the crystal manufacturer.

5.3.9 External clock source security characteristics

Table 53. High speed external user clock security system (HSE CSS)(1)
Symbol Parameter Conditions Min Typ Max Unit

tDCM(HSE_CSS) Time to detect clock missing fHSE = 48 MHz - 1 2 μs

1. Specified by design, not tested in production.

Table 54. Low speed external user clock security system (LSE CSS)(1)
Symbol Parameter Conditions Min Typ Max Unit

tDCM(LSE_CSS) Time to detect clock missing - - - 300 μs

fMAX(LSE_CSS) Cutoff frequency - - - 2 MHz
1. Specified by design, not tested in production.

5.3.10 Internal clock source characteristics

The parameters given in the following tables are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24.

Table 55. 64 MHz high-speed internal (HSI) oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI(2) Frequency VDDA18AON = 1.8 V, TJ = 30 °C 63.68 64 64.32 MHz

TRIM User trimming step - - 0.25 0.5
DuCyHSI Duty cycle - 40 - 60
%
Oscillator frequency drift over
∆VDDA18AON(HSI)
voltage and temperature variation TJ = -40 to 125 °C -5 - 5
+ ∆TJ(HSI)
(after factory calibration)

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Table 55. 64 MHz high-speed internal (HSI) oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Startup time (from enable rise to

tsu(HSI) - - - 3
first output clock edge) μs
tstab(HSI) Stabilization time 1% of target frequency - - 5
IVDDCORE(HSI) Supply current on VDDCORE - - - 10
μA
IVDD18AON(HSI) Supply current on VDDA18AON - - 300 400
1. Evaluated by characterization, not tested in production unless otherwise specified.
2. Guaranteed by test in production.

Table 56. Low power internal RC (MSI) oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDCORE = 0.81 V, MSIFREQSEL = 0(2) 3.956 4 4.044

fMSI Frequency MHz
TJ = 30 °C MSIFREQSEL = 1 15.824 16 16.176
Trimming code is not a multiple of 32 - 0.8 1.1
TRIM Trimming step
Trimming code is a multiple of 32 - -2.5 -3.8
DuCyHSI Duty cycle At trimmed frequency 45 - 55 %

Frequency drift over

∆TJ(MSI) TJ = -40 to 125 °C -7 - +7
temperature
tsu(HSI) Start-up time - - - 3.5 μs

Supply current on 4 MHz MSIFREQSEL = 0 - 20 22

IVDDCORE(HSI) μA
VDDCORE 16 MHz MSIFREQSEL = 1 - 60 68
1. Evaluated by characterization, not tested in production unless otherwise specified.
2. Guaranteed by test in production.

Table 57. 32 kHz low-speed internal (LSI) oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

TJ = 30 °C 30.5 32 33.5
fLSI Frequency kHz
TJ = -40 to 125 °C 28.8 32 33.6
tsu(LSI) Start-up time (from enable rise to first output clock edge) - - - 180 μs
IVSW(LSI) Supply current on VSW - - 250 500 nA
1. Evaluated by characterization, not tested in production unless otherwise specified.

5.3.11 PLL characteristics

The parameters given in Table 58 are derived from tests performed under temperature and
supply voltage conditions summarized in Table 24.

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Table 58. PLL1 to PLL4 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode 5 - 64
fPLL_IN PLL input clock
Sigma delta mode 10 - 64
MHz
Normal mode 5 fPLL_IN / FREFDIV 50
fPFD PFD input clock
Sigma delta mode 10 - min(50, fVCO / 20)
Divided output clock 16.32 - 3200 MHz
Division by 1 48 50 52
fFOUTPOSTDIV Divided output clock
Even division 48 50 52 %
duty cycle
Odd division 47 50 53
fVCO PLL VCO output 800 - 3200 MHz
1 / fPFD
Frequency lock - - 400
cycles
tLOCK PLL lock time fPFD = 40 MHz
(fPLL_IN = 40 MHz, - - 10 μs
FREFDIV = 1)
RMS period jitter fVCO = 3200 MHz - - ±0.26
fVCO = 3200 MHz,
fPFD = 25 MHz, - ±2.7 ±6.6
Jitter RMS integrated jitter integer divider ps
(10 kHz - 20 MHz) fVCO = 3200 MHz,
fPFD = 25 MHz, - - ±11.9
fracN divider
fVCO = 3200 MHz,
- 5750 6850
FBDIV < 256
PLL supply current
fVCO = 3200 MHz,
IVDDA18PLL on VDDA18PLL - 7050 8450
FBDIV > 256
(analog)
μA
fVCO = 800 MHz,
- 715 860
FBDIV < 256

PLL supply current fVCO = 3200 MHz - 1200 3650

IVDDCORE(PLL)
on VDDCORE (0.81 V) f
VCO = 800 MHz - 295 910
1. Specified by design, not tested in production unless otherwise specified.

5.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows the reduction of
electromagnetic interferences (see Section 5.3.14). It is available only on PLL2 to PLL4.

Table 59. PLL2 to PLL4 SSCG constraints

Symbol Parameter Min Typ Max Unit

fMOD Modulation frequency 5.2 - 391 kHz

MD Peak modulation depth 0.1 - 3.1 %

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5.3.13 OTP characteristics

The characteristics are given at TJ = -40 to 125 °C, unless otherwise specified.

Table 60. OTP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Programming - 3.8 10
mA
IOTP(VDDA18AON) Supply current on VDDA18AON Reading - 0.66 1.13
Power down - 5 132 μA
Programming - 0.09 0.45
mA
IOTP(VDDCORE) Supply current on VDDCORE Reading - 1.8 3.6
Power down - 8 500 μA
1. Evaluated by characterization, not tested in production unless otherwise specified.

5.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs as follows:
• ESD (electrostatic discharge), positive and negative: applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB (fast transient voltage burst), positive and negative: applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 61. They are based on the EMS levels and classes
defined in AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”.

Table 61. EMS characteristics(1)

Symbol Parameter Conditions Level/Class

Voltage limits to apply on any I/O pin to

VFESD VDD = 3.3 V, TA = +25 °C, 2B
induce a functional disturbance
f PLL1 = 1200 MHz, fck_icn_hs_mcu = 600 MHz,
Fast transient voltage burst limits to apply VFBGA264 package,
VFTB through 100 pF on VDD and VSS pins to conforming to IEC 61000-4-2 5A
induce a functional disturbance
1. Evaluated by characterization, not tested in production, unless otherwise specified.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software.

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Good EMC performance is highly dependent on the user application, and the software in
particular. Therefore, it is recommended that the user applies EMC software optimization
and prequalification tests in relation with the requested EMC level.
Software recommendations
The software flow must include the management of runaway conditions, such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or on the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specified values. When an unexpected behavior is detected, the software can be hardened
to prevent the occurrence of unrecoverable errors. See AN1015 “Software techniques for
improving microcontrollers EMC performance” for more details.

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.

Table 62. EMI characteristics for fHSE = 32 MHz and fHCLK = 100 MHz(1)
Symbol Parameter Conditions Monitored frequency band Value Unit

0.1 MHz to 30 MHz 9

VDD = 3.6 V, TA = 25 °C,
Peak 30 MHz to 130 MHz 13
VFBGA264 package, dBµV
SEMI level(2) SMPS on, 130 MHz to 1 GHz 13
fck_icn_hs_mcu = 800 MHz,
1 GHz to 2 GHz 7
compliant with IEC 61967-2
Level(3) EMI level 3 -
1. Evaluated by characterization, not tested in production.
2. Refer to AN1709, “EMI radiated test” section.
3. Refer to AN1709, “EMI level classification” section.

5.3.15 Electrical sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

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Table 63. ESD absolute maximum ratings(1)

Symbol Ratings Conditions Package Class Max Unit

Electrostatic discharge voltage TA = 25 °C, conforming to

VESD(HBM) 2 2000(2)
(human body model) ANSI/ESDA/JEDEC JS-001
All V
Electrostatic discharge voltage TA = 25 °C, conforming to
VESD(CDM) C1 250
(charge device model) ANSI/ESDA/JEDEC JS-002
1. Evaluated by characterization, not tested in production, unless otherwise specified.
2. 400 V for USB_PD_CC1 and USB_PD_CC2 pins.

Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 64. Electrical sensitivity(1)

Symbol Parameter Conditions Class

LU Static latch-up class TJ = 130 °C conforming to JESD78 II.A

1. Evaluated by characterization, not tested in production, unless otherwise specified.

5.3.16 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during device characterization.

5.3.17 I/O port characteristics

General input/output characteristics
The parameters given in Table 65 are derived from tests performed at ambient temperature
and under the supply voltage conditions summarized in Table 24. All I/Os are designed as
CMOS- and TTL-compliant. For additional informations see AN4899 “STM32
microcontroller GPIO hardware settings and low-power consumption”.

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Table 65. I/O static characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Input low level 1.62 V ≤ VDDxx ≤ 1.98 V 0.36 x VDDxx - -

VIL
voltage 2.7 V ≤ VDDxx ≤ 3.6 V 0.4 x VDDxx - 0.27 - -

Input high level 1.62 V ≤ VDDxx ≤ 1.98 V 0.62 x VDDxx - -

VIH V
voltage 2.7 V ≤ VDDxx ≤ 3.6 V 0.52 x VDDxx - 0.11 - -
1.62 V ≤ VDDxx ≤ 1.98 V - 0.45 -
Vhys(2) Input hysteresis
2.7 V ≤ VDDxx ≤ 3.6 V - 0.45 -
CMOS port, IIO = 5.5 mA, Speed 00,
- - 0.45
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 8 mA, Speed 01,
- - 0.45
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 11 mA, Speed 10,
- - 0.45
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 16 mA, Speed 11,
- - 0.45
Output low level 1.62 V < VDDxx < 1.98 V
VOL V
voltage CMOS port, IIO = 6.5 mA, Speed 00,
- - 0.4
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 10 mA, Speed 01,
- - 0.4
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 13 mA, Speed 10,
- - 0.4
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 20 mA, Speed 11,
- - 0.4
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 5.5 mA, Speed 00,
VDDxx - 0.45 - -
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 8 mA, Speed 01,
VDDxx - 0.45 - -
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 11 mA, Speed 10,
VDDxx - 0.45 - -
1.62 V < VDDxx < 1.98 V
CMOS port, IIO = 16 mA, Speed 11,
VDDxx - 0.45 - -
Output high level 1.62 V < VDDxx < 1.98 V
VOH V
voltage CMOS port, IIO = 6.5 mA, Speed 00,
VDDxx - 0.4 - -
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 10 mA, Speed 01,
VDDxx - 0.4 - -
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 13 mA, Speed 10,
VDDxx - 0.4 - -
2.7 V < VDDxx < 3.6 V
CMOS port, IIO = 20 mA, Speed 11,
VDDxx - 0.4 - -
2.7 V < VDDxx < 3.6 V
1. VDDxx stands for VDD, VDDIO2, VDDIO3, VDDIO4, or VDDIO5.
2. Specified by design, not tested in production.

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Table 66. Leakage characteristics(1)

Symbol Parameter Min Typ Max Unit

Ileak TT-x input leakage - - 1500 nA

CIO I/O pin capacitance - 5 - pF
1. Evaluated by characterization, not tested in production.

Table 67. RPU/RPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

1.62 V < VDDIO < 1.98 V

RPU Weak pull-up equivalent resistor
2.7 V < VDDIO < 3.6 V
30 40 50 kΩ
1.62 V < VDDIO < 1.98 V
RPU Weak pull-down equivalent resistor
2.7 V < VDDIO < 3.6 V

Output driving current

The GPIOs can sink or source up to ±20 mA (depending on speed setup, supply voltage
range and temperature). In the application, I/O drive current must be limited to respect the
absolute maximum ratings specified in Section 5.2, in particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run mode
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 22).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run mode
consumption of the MCU sink on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 22).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23.

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Figure 23. VIL/VIH for TT I/Os

MSv69136V1

5.3.18 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 67).
Unless otherwise specified, the parameters in Table 68 are derived from tests performed
under the ambient temperature and supply voltage conditions summarized in Table 24.

Table 68. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

RPU(1) Weak pull-up equivalent resistor - 30 40 50 kΩ

tGEN NRST minimum generated output pulse - 17.5 - - μs
TFILT NRST input filtered pulse - - - 50
ns
TNFILT NRST input not filtered pulse - 150 - -
VIL(NRST) NRST input low-level voltage - - - 0.65 V
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10%).

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Figure 24. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 68. Otherwise, the reset is not taken into account by the device.

5.3.19 FMC characteristics

Unless otherwise specified, the parameters given in Table 69 to Table 86 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency,
and VDD supply voltage conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 × VDD
Refer to Section 5.3.17 for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figure 25 to Figure 28 represent asynchronous waveforms and Table 69 to Table 76
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• AddressSetupTime(ADDSET) = 0x1
• AddressHoldTime(ADDHLD) = 0x1
• DataSetupTime(DATAST) = 0x1 (except for asynchronous NWAIT mode for which
DataSetupTime = 0x5)
• DataHoldTime(DATAHLD) = 0x1 (1 × Tfmc_ker_ck for read operations and
2 × Tfmc_ker_ck for write operations)
• ByteLaneSetup(NBLSET) = 0x1
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period.

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Table 69. Asynchronous non multiplexed SRAM/PSRAM/NOR read timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × Tfmc_ker_ck - 0.5 3 × Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2 × Tfmc_ker_ck - 0.5 2 × Tfmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck - 0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
Address held until
th(A_NOE) Address hold time after FMC_NOE high -
next read operation ns
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 17 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 16 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1

Table 70. Asynchronous non multiplexed SRAM/PSRAM/NOR read-NWAIT timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × Tfmc_ker_ck - 0.5 8 × Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 7 × Tfmc_ker_ck - 0.5 7 × Tfmc_ker_ck + 1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × Tfmc_ker_ck + 15 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × Tfmc_ker_ck + 12 -

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Figure 25. Asynchronous non multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C, and D only. In mode 1, FMC_NADV is not used.

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Table 71. Asynchronous non multiplexed SRAM/PSRAM/NOR write timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 × Tfmc_ker_ck - 0.5 3 × Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 4 Tfmc_ker_ck - 3
tw(NWE) FMC_NWE low time Tfmc_ker_ck - 0.5 Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck + 3 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high 3 × Tfmc_ker_ck - 1 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0
th(BL_NWE) FMC_BL hold time after FMC_NWE high 3 × Tfmc_ker_ck - 1.5 -
tv(Data_NE) FMC_NEx low to Data valid - 2
th(Data_NWE) Data hold time after FMC_NEx high 3 × Tfmc_ker_ck - 1 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1

Table 72. Asynchronous non multiplexed SRAM/PSRAM/NOR write - NWAIT timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 × Tfmc_ker_ck - 0.5 8 × Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 6 × Tfmc_ker_ck - 0.5 6 × Tfmc_ker_ck + 1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × Tfmc_ker_ck + 15 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × Tfmc_ker_ck + 12 -

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Figure 26. Asynchronous non multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C, and D only. In mode 1, FMC_NADV is not used.

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Table 73. Asynchronous multiplexed PSRAM/NOR read timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 × Tfmc_ker_ck - 0.5 4 × Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2 × Tfmc_ker_ck - 1 2 × Tfmc_ker_ck + 0.5
tw(NOE) FMC_NOE low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 0.5
ns
FMC_AD(address) valid hold time after
th(AD_NADV) Tfmc_ker_ck - 1 -
FMC_NADV high
Address held until
th(A_NOE) Address hold time after FMC_NOE high -
next read operation
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 17 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 16 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -

Table 74. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 × Tfmc_ker_ck - 0.5 9 × Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 6 × Tfmc_ker_ck - 0.5 6 × Tfmc_ker_ck + 1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × Tfmc_ker_ck + 15 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × Tfmc_ker_ck + 12 -

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Figure 27. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 75. Asynchronous multiplexed PSRAM/NOR write timings

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 × Tfmc_ker_ck - 0.5 4 × Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 4 Tfmc_ker_ck - 3
tw(NWE) FMC_NWE low time 2 × Tfmc_ker_ck - 0.5 2 × Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck + 3 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 1
ns
FMC_AD(address) valid hold time after
th(AD_NADV) Tfmc_ker_ck - 1.5 -
FMC_NADV high)
th(A_NWE) Address hold time after FMC_NWE high 3 × Tfmc_ker_ck - 1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 1.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0
th(Data_NWE) Data hold time after FMC_NEx high - Tfmc_ker_ck + 2
th(Data_NWE) Data hold time after FMC_NEx high Tfmc_ker_ck - 1 -

Table 76. Asynchronous multiplexed PSRAM/NOR write - NWAIT timing

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 × Tfmc_ker_ck - 0.5 9 × Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 7 × Tfmc_ker_ck - 0.5 7 × Tfmc_ker_ck + 1
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × Tfmc_ker_ck + 15 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × Tfmc_ker_ck + 12 -

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Figure 28. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

Synchronous waveforms and timings

Figure 29 to Figure 32 represent synchronous waveforms and Table 77 to Table 80 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash memory; DataLatency = 0 for PSRAM
In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period with the following FMC_CLK
maximum values:
• For 1.65 V < VDD< 3.6 V, FMC_CLK = 65 MHz at 20 pF (55 MHz when using NWAIT)

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Table 77. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R × Tfmc_ker_ck - 0.5(2) -

FMC_CLK low to FMC_NEx low
td(CLKL-NExL) - 5
(x = 0…2)
FMC_CLK high to FMC_NEx high
td(CLKH_NExH) R × Tfmc_ker_ck / 2 + 5(2) -
(x = 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
FMC_CLK low to FMC_Ax valid
td(CLKL-AV) - 0
(x = 16…25)
FMC_CLK high to FMC_Ax invalid Address held until next
td(CLKH-AIV) -
(x = 16…25) read operation
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 0
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R × Tfmc_ker_ck / 2 + 4(2) -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0.5 -
FMC_A/D[15:0] valid data before
tsu(ADV-CLKH) 4.5 -
FMC_CLK high
FMC_A/D[15:0] valid data after
th(CLKH-ADV) 2 -
FMC_CLK high
FMC_NWAIT valid before FMC_CLK
tsu(NWAIT-CLKH) 5 -
high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
FMC_NWAIT valid after FMC_NEx low (DATLAT + 2.5) ×
Tcew(NExL-NWAIT) -
(x = 0…2) Tfmc_ker_ck × R - 10.5
1. Evaluated by characterization. Not tested in production.
2. Clock ratio R = FMC_CLK period / FMC_ker_CLK period.

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Figure 29. Synchronous non multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

tsu(ADV-CLKH) th(CLKH-ADV)

FMC_D[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx

td(NExL-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V3

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Table 78. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R × Tfmc_ker_ck - 0.5(2) -

FMC_CLK low to FMC_NEx low
td(CLKL-NExL) - 5
(x = 0…2)
FMC_CLK high to FMC_NEx high
td(CLKH_NExH) R × Tfmc_ker_ck / 2 + 5(2) -
(x = 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
FMC_CLK low to FMC_Ax valid
td(CLKL-AV) - 0
(x = 16…25)
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R × Tfmc_ker_ck(2) -
(x = 16…25)
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5 ns

td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R × Tfmc_ker_ck / 2(2) -

td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data after
td(CLKL-DATA) - 5
FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R × Tfmc_ker_ck / 2(2) -
FMC_NWAIT valid before FMC_CLK
tsu(NWAIT-CLKH) 5 -
high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
FMC_NWAIT valid after FMC_NEx low (DATLAT + 2.5) ×
Tcew(NExL -NWAIT) - -
(x = 0…2) Tfmc_ker_ck × R - 10.5
1. Evaluated by characterization. Not tested in production.
2. Clock ratio R = FMC_CLK period / FMC_ker_CLK period.

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Figure 30. Synchronous non multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

td(CLKL-ADIV) td(CLKL-Data)

FMC_D[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx

td(NExL-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
td(CLKH-NBLH)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NBL

Expected sampling edge at memory side

MS32760V3

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Table 79. Synchronous non multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R × Tfmc_ker_ck - 0.5(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0…2) - 5
(2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0…2) R × Tfmc_ker_ck/2 + 5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16…25) - 0
FMC_CLK high to FMC_Ax invalid Address held until next
td(CLKH-AIV) -
(x =16…25) read operation
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 0
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high R × Tfmc_ker_ck/2 + 4(2) -
FMC_A/D[15:0] valid data before FMC_CLK
tsu(DV-CLKH) 4.5 -
high
FMC_A/D[15:0] valid data after FMC_CLK
th(CLKH-DV) 2 -
high
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 5 -
CLKH)

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -

(DATLAT + 2.5) ×
Tcew(NExL - FMC_NWAIT valid after FMC_NEx low
- Tfmc_ker_ck × R - -
NWAIT) (x = 0…2)
10.5
1. Evaluated by characterization. Not tested in production.
2. Clock ratio R = FMC_CLK period / FMC_ker_CLK period.

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Figure 31. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE

td(CLKL-ADIV)
td(CLKL-ADV) tsu(ADV-CLKH)
th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx

td(NExL-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V3

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Table 80. Synchronous non multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period R × Tfmc_ker_ck - 0.5(2) -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0…2) - 5
(2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0…2) R × Tfmc_ker_ck/2 + 5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16…25) - 0
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) R × Tfmc_ker_ck(2) -
(x =16…25)
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high R × Tfmc_ker_ck / 2(2) -
FMC_A/D[15:0] valid data after FMC_CLK
td(CLKL-DATA) - 5
low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 0
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high R × Tfmc_ker_ck / 2(2) -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1 -
(DATLAT + 2.5) ×
Tcew(NExL - FMC_NWAIT valid after FMC_NEx low
- Tfmc_ker_ck × R - -
NWAIT) (x = 0…2)
10.5
1. Evaluated by characterization. Not tested in production.
2. Clock ratio R = FMC_CLK period / FMC_ker_CLK period.

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Figure 32. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK
Data latency = 0 (2 cycles)
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

td(CLKL-Data)
td(CLKL-ADIV)
td(CLKL-ADV)
FMC_AD[15:0] AD[15:0] D1 D2

td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx

td(NExL-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL = 0b)
td(CLKH-NBLH)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NBL

Expected sampling edge at memory side

MS32758V3

NAND flash memory controller waveforms and timings

Figure 33 and Figure 34 represent synchronous waveforms, and Table 81 and Table 82
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• FMC_SetupTime = 0x01
• FMC_WaitSetupTime = 0x03
• FMC_HoldSetupTime = 0x02
• FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• Capacitive load CL = 30 pF
In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period.

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Table 81. NAND flash memory read cycles

Symbol Parameter Min Max Unit

tw(NOE) FMC_NOE low width 4 × Tfmc_ker_ck - 1 4 × Tfmc_ker_ck + 1

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 15 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 2 × Tfmc_ker_ck + 1.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3 × Tfmc_ker_ck - 1 -

Figure 33. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

Table 82. NAND flash memory write cycles

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4 × Tfmc_ker_ck - 1 4 × Tfmc_ker_ck + 1

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 4 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 5 × Tfmc_ker_ck - 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 4 × Tfmc_ker_ck - 4.5 -
td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 2 × Tfmc_ker_ck + 1.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3 × Tfmc_ker_ck - 1 -

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Figure 34. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

SDRAM waveforms and timings

In all timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with primary interfaces and
RETIME = 1:
• Maximum FMC_CLK = 166 MHz at 20 pF for 1.71 V < VDD < 1.9 V
• Maximum FMC_CLK = 166 MHz at 20 pF for 2.7 V < VDD < 3.6 V
Otherwise:
• Maximum FMC_CLK = 70 MHz at 20 pF for 1.71 V < VDD< 1.9 V
• Maximum FMC_CLK = 75 MHz at 20 pF for 2.7 V < VDD< 3.6 V
• Maximum FMC_CLK = 80 MHz at 10 pF for 1.71 V < VDD < 1.9 V

Table 83. SDRAM read timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2 × Tfmc_ker_ck - 0.5 2 × Tfmc_ker_ck + 0.5

tsu(SDCLKH _Data) Data input setup time 1(2) /5 -
th(SDCLK H_Data) Data input hold time 2(2) / 0.5 -
td(SDCLKL_Add) Address valid time - 1,5
td(SDCLKL- SDNE) Chip select valid time - 1
ns
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
th(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. Primary interfaces used.

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Table 84. LPSDR SDRAM read timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2 Tfmc_ker_ck - 0.5 2 Tfmc_ker_ck + 0.5

(2)
tsu(SDCLKH _Data) Data input setup time 1 /5 -
(2)
th(SDCLK H_Data) Data input hold time 1.5 / 0.5 -
td(SDCLKL_Add) Address valid time - 1,5
td(SDCLKL- SDNE) Chip select valid time - 1
ns
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
th(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. Primary interfaces used.

Table 85. SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2 Tfmc_ker_ck - 0.5 2 Tfmc_ker_ck + 0.5

td(SDCLKL _Data) Data output valid time - 1.5(2) / 5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL-SDNWE) SDNWE valid time - 1
th(SDCLKL-SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL- SDNE) Chip select valid time - 1
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
th(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. Primary interfaces used.

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Table 86. LPSDR SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2 Tfmc_ker_ck - 0.5 2 Tfmc_ker_ck + 0.5

td(SDCLKL _Data) Data output valid time - 1.5(2) / 5.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL-SDNWE) SDNWE valid time - 1
th(SDCLKL-SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL- SDNE) Chip select valid time - 1
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
th(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. Primary interfaces used.

5.3.20 XSPI interface characteristics

Unless otherwise specified, the parameters given in Table 87 for XSPI are derived from
tests performed under the ambient temperature, fAHB frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.17 for more details on the input/output alternate function
characteristics.
The following table summarizes the parameters measured in SDR mode.

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Table 87. XSPI characteristics in SDR mode(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.65 V < VDD < 1.98 V

Voltage scaling VOS0 - - 185
CL = 15 pF
FCLK XSPI clock frequency MHz
2.7 V < VDD < 3.6 V
Voltage scaling VOS0 - - 140
CL = 15 pF
tw(CLKH) XSPI clock high and low PRESCALER[7:0] = t(CLK) / 2 - t(CLK) / 2 + 1
t time, even division n = 0,1,3,5 t(CLK) / 2 - 1 - t(CLK) / 2
w(CLKL)

(n / 2) × t(CLK) / (n / 2) × t(CLK) /
tw(CLKH) -
XSPI clock high and low PRESCALER[7:0] = (n + 1) (n + 1) + 1
time, odd division n = 2,4,6,8 (n / 2 + 1)*t(CLK)/ (n / 2 + 1)*t(CLK)/
tw(CLKL) - ns
(n + 1) - 1 (n + 1)
ts(DQ) Data input setup time - 1.5 - -
th(DQ) Data input hold time - 2 - -
tv(OUT) Data output valid time - - 0 0.5
th(OUT) Data output hold time - 0 - -
1. Evaluated by characterization. Not tested in production.
2. Voltage scaling = VOS low.

Figure 35. XSPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V1

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The following table summarizes the parameters measured in DTR mode (no DQS).

Table 88. XSPI characteristics in DTR mode without DQS(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.65 V < VDD < 1.98 V

Voltage scaling VOS0 - - 180
CL = 15 pF
F(CLK) XSPI clock frequency MHz
2.7 V < VDD < 3.6 V
Voltage scaling VOS0 - - 140
CL = 15 pF
tw(CLKH) XSPI clock high and t(CLK) / 2 - t(CLK) / 2 + 1
PRESCALER[7:0] =
low time, even
tw(CLKL) n = 0,1,3,5 t(CLK) / 2 - 1 - t(CLK) / 2
division
(n / 2) × t(CLK)
tw(CLKH) - - ns
/ (n + 1)
XSPI clock high and PRESCALER[:0] =
low time, odd division n = 2,4,6,8 (n / 2 + 1) ×
(n / 2 + 1) ×
tw(CLKL) t(CLK) / -
t(CLK) / (n + 1)
(n + 1) - 1
tsr(DQ),tsf(DQ) Data input setup time - 2 - -
thr(DQ),thf(DQ) Data input hold time - 1 - -
tvr(OUT), Data output valid t(CLK) / 4 + 0.5 t(CLK) / 4 + 1 ns
- -
tvf(OUT) time 6(3) 6.5(3)
thr(OUT) , t(CLK) / 4 - 0.5
Data output hold time - - -
thf(OUT) 4.5(3)
1. Evaluated by characterization. Not tested in production.
2. Voltage scaling = VOS low.
3. When Prescaler = 0 and F(CLK) < 40 MHz.

Figure 36. XSPI timing diagram – DTR mode (no DQS)

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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The following table summarizes the parameters measured in DTR mode (with DQS).

Table 89. XSPI characteristics in DTR mode (with DQS or HyperBus)(1)

Symbol Parameter Conditions Min Typ Max Unit

1.65 V < VDD < 3.6 V

F(CLK) XSPI clock frequency Voltage scaling VOS0 - - 200 MHz
CL = 15 pF
tw(CLKH) XSPI clock high and t(CLK) / 2 - t(CLK) / 2 + 1
PRESCALER[7:0] = n
low time, even
tw(CLKL) division = 0,1,3,5 t(CLK) / 2 - 1 - t(CLK) / 2

(n / 2) × t(CLK) / (n / 2) × t(CLK) /
tw(CLKH) -
XSPI clock high and PRESCALER[7:0] = n (n + 1) (n + 1) + 1
low time, odd division = 2,4,6,8 (n / 2 + 1) × (n / 2 + 1) × ns
tw(CLKL) -
t(CLK) / (n + 1) - 1 t(CLK) / (n + 1)
tw(CS) Chip select high time - 3 × t(CLK) - -
tv(CK) Clock valid time - - - t(CLK) + 1
th(CK) Clock hold time - t(CLK) / 2 - -
CLK, NCLK crossing
VODr(CK) level on CLK rising VDD = 1.8 V 1020 - 1138 / 1019(2)
edge
mV
CLK, NCLK crossing
VODf(CK) level on CLK falling VDD = 1.8 V 908 - 1080
edge
tsr(DQ), 0.5 - t(CLK) / 4
Data input setup time - - -
tsf(DQ) 3(3)
thr(DQ), 2 + t(CLK) / 4
Data input hold time - - -
thf(DQ) 7.5(3)
tv(DQ) Data input valid time - 0 - -
Data strobe input
tv(DS) - 0 - -
valid time
Data strobe input ns
th(DS) - 0 - -
hold time
Data strobe output
tv(RWDS) - - - 3 × t(CLK)
valid time
tvr(OUT), t(CLK) / 4 + 0.5 t(CLK) / 4 + 1
Data output valid time - -
tvf(OUT) 6(3) 6.5(3)
thr(OUT), t(CLK) / 4 - 0.5
Data output hold time - - -
thf(OUT) 4.5(3)
1. Evaluated by characterization. Not tested in production.
2. When using 33 Ω series termination on CLK and NCLK.
3. When Prescaler = 0 and F(CLK) < 40 MHz.

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Figure 37. XSPI HyperBus clock

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 38. XSPI HyperBus read

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

Figure 39. XSPI HyperBus read with double latency

NCS

tRWR=Read/write recovery Additional latency tACC = Access

CLK, NCLK

tCKDS
RWDS High = 2x latency count
Low = 1x latency count
RWDS and data
are edge aligned
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
A B A B

Command address Memory drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS. MSv49351V3

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Figure 40. XSPI HyperBus write

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

5.3.21 SDMMC interface characteristics

Unless otherwise specified, the parameters given in Table 91 to Table 92 are derived from
tests performed under the ambient temperature, fHCLK frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed set as shown in Table 90
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.5 V
Refer to Section 5.3.17 for more details on the input/output characteristics.

Table 90. Output speed settings versus voltage and clock frequency
OSPEEDRy[1:0]
Voltage range (V) Max clock frequency (MHz)
Clock Data

26/25 00 00
52/50 01 00
1.71 to 1.9 and 3.0 to 3.6
DDR 52/50 01 01
100 01 00
3.0 to 3.6 145 11 10
1.71 to 1.9 200 11 10

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Table 91. Dynamic characteristics: SD, VDD = 1.71 V to 3.6 V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

3.00 < VDD < 3.6 V - - 145

Clock frequency in data transfer mode
fPP 1.71 < VDD < 1.9 V - - 200 MHz
SDIO_CK / fPCLK2 frequency ratio 1.71 < VDD < 3.6 V - - 8/3
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in SD HS/SDR(3)/DDR(3) mode

tISU Input setup time HS - 3 - -

tIHD Input hold time HS - 1.5 - - ns
Tidw(4) Input valid window (variable window) - 2.5 - -

CMD, D outputs (referenced to CK) in SD HS/SDR(3)/DDR(3) mode

tOV Output valid time HS - - 6.5 6.5

ns
tOH Output hold time HS - 4.5 - -

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD - 2.5 - -

ns
tIHD Input hold time SD - 1.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - - 0.5 0.5

ns
tOHD Output hold default time SD - 0 - -
1. Evaluated by characterization. Not tested in production.
2. Above 100 MHz, CL applied is 20 pF.
3. For SD 1.8 V support, an external voltage converter is needed.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 92. Dynamic characteristics: eMMC, VDD = 1.71 V to 3.6 V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

3.00 < VDD < 3.6 V - - 145

Clock frequency in data transfer mode
fPP 1.71 < VDD < 1.9 V - - 200 MHz
SDIO_CK / fPCLK2 frequency ratio - - - 8/3
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 1.5 - - ns
Tidw(3) Input valid window (variable window) - 2.5 - -

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Table 92. Dynamic characteristics: eMMC, VDD = 1.71 V to 3.6 V(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS - - 6 6

ns
tOH Output hold time HS - 4.5 - -
1. Evaluated by characterization. Not tested in production.
2. Cload = 20 pF
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Figure 41. SDIO high-speed mode

tC(CK)
tW(CKH) tW(CKL)

CK
tOH
tOV

D, CMD output
tIH
tISU

D, CMD input
MSv69709V1

Figure 42. SD default mode

CK
tOV tOH

D, CMD output MSv69710V1

Figure 43. DDR mode

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

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5.3.22 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 93 are derived from tests
performed under the ambient temperature, fHCLKx frequency, and VDD supply voltage
summarized in Table 24.

Table 93. Delay block dynamic characteristics

Symbol Parameter Min Typ Max Unit

tinit Initial delay 150 250 350

Bypass mode 30 40 50 ps
t∆ Unit delay
(1) (1) (1)
Lock mode T / 32 - 10% T / 32 T / 32 + 1%
1. Period of the DLL clock.

5.3.23 12-bit ADC characteristics

Table 94. ADC characteristics(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

fADC Clock frequency - 0.7 - 70 MHz

Resolution = 12 bits 0.0467 - 4.666
Resolution = 10 bits 0.0538 - 5.384
fs Sampling rate Msps
Resolution = 8 bits 0.07 - 7
Resolution = 6 bits 0.0875 - 8.75
Resolution = 12 bits - 13.5 -
Resolution = 10 bits - 12 -
tC Conversion cycle 1 / fADC
Resolution = 8 bits - 10 -
Resolution = 6 bits - 8 -
fADC = 70 MHz - - TBD MHz
fTRIG External trigger frequency
Resolution = 12 bits - - TBD 1 / fADC
Single ended 0 - VREF+
VAIN Conversion voltage range V
Differential -VREF+ - VREF+
VCMIV Common mode input voltage Differential - VREF+ / 2 - V
Internal sample and hold
CADC - - 2.56 - pF
capacitor
tSTAB Start-up time - - 5 - μs
tOFF_CAL Offset calibration time - - TBD -
Trigger conversion latency CKMODE = 0 - TBD -
tLATR regular and injected channels
without conversion abort CKMODE = 1 - TBD - 1 / fADC
Trigger conversion latency CKMODE = 0 - TBD -
tLATRINJ regular injected channels
aborting a regular conversion CKMODE = 1 - TBD -

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Table 94. ADC characteristics(1)(2)(3) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tS Sampling time - 2.5 - 1502 1 / fADC

fs = 5 Msps,
- 315 -
resolution = 12 bits
fs = 5.8 Msps,
ADC supply current on - 330 -
IADC(VDDA18ADC) resolution = 10 bits μA
VDDA18ADC
Power down, ADEN = 0 - 1.71 -
Deep power down,
- 1.53 -
ADEN = 0, DEEPPWD = 1
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. All analog inputs must be between VSSA and VDDA18ADC.
3. TBD stands for “to be defined”.

Table 95. ADC accuracy(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Single ended - 3.52 -

ET Total unadjusted error
Differential - 2.98 -
Single ended - 0.60 0.97
ED Differential linearity error (DNL) LSB
Differential - 0.80 0.98
Single ended - 2.60 3.60
EL Integral linearity error (INL)
Differential - 2.10 3.80
Single ended - 9.9 -
ENOB Effective number of bits Bits
Differential - 10.5 -
Single ended - 62 -
SINAD Signal-to-noise and distortion ratio(3)
Differential - 65 -
Single ended - 62 -
SNR Signal-to-noise ratio dB
Differential - 65 -
Single ended - -76 -
THD Total harmonic distortion
Differential - -77 -
EG Gain error Vs. VREF+ value -1 - 1 % of
full
Without calibration -1 - 1 scale
EO Offset error
After calibration TBD - TBD LSB
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. TBD stands for “to be defined”.
3. Value measured with a -0.5 dBFS input signal and then extrapolated to full scale.

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Figure 44. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 45. Typical connection diagram using the ADC

with TT pins featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 94 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering RADC, and PCB layout quality)
plus the pad capacitance (refer to Table 65). A high Cparasitic value downgrades conversion accuracy. To
remedy this, fADC should be reduced.
3. Refer to Table 65 for the value of Ilkg.
4. Refer to Figure 15 .

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Table 96. Minimum sampling time versus RAIN(1)(2)

Conditions
Symbol Parameter Min Typ Max Unit
(Resolution / RAIN in ohms)

47 32 - -
68 33 - -
100 34 - -
150 36 - -
ts_min Minimum sampling time 12 bits 220 38 - - ns
330 42 - -
470 47 - -
680 55 - -
1000(3) 70 - -
47 23 - -
68 24 - -
100 25 - -
150 26 - -
220 28 - -
330 30 - -
ts_min Minimum sampling time 10 bits 470 33 - - ns
680 38 - -
1000 45 - -
1500 55 - -
2200 71 - -
3300 97 - -
(3)
4700 133 - -

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Table 96. Minimum sampling time versus RAIN(1)(2) (continued)

Conditions
Symbol Parameter Min Typ Max Unit
(Resolution / RAIN in ohms)

47 17 - -
68 17 - -
100 18 - -
150 19 - -
220 20 - -
330 22 - -
470 25 - -
680 28 - -
ts_min Minimum sampling time 8 bits 1000 34 - - ns
1500 42 - -
2200 53 - -
3300 70 - -
4700 94 - -
6800 128 - -
10000 183 - -
15000 277 - -
(3)
22000 435 - -
47 TBD - -
68 TBD - -
100 TBD - -
150 TBD - -
220 TBD - -
330 TBD - -
470 TBD - -
680 TBD - -
ts_min Minimum sampling time 6 bits 1000 TBD - - ns
1500 TBD - -
2200 TBD - -
3300 TBD - -
4700 TBD - -
6800 TBD - -
10000 TBD - -
15000 TBD - -
(3)
22000 TBD - -

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1. TBD stands for “to be defined”.

2. Specified by design. Not tested in production.
3. Maximum external input impedance value authorized for the given resolution.

5.3.24 Voltage reference buffer (VREFBUF) characteristics

Table 97. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply VRS = 000 1.62 1.8 1.98(2)

VDDA18ADC -
voltage VRS = 001 1.75 1.8 1.98(2)
V
ILOAD = 10 μA, VRS = 000 1.209 1.210 1.211
VREFBUF_ Voltage reference
VDDA18ADC = 1.8 V,
OUT buffer output VRS = 001 1.499 1.5 1.502
30 °C
TRIM Trim step resolution - - ±0.05 ±0.1 %
CL Load capacitor - 0.5 1.1 1.5 μF
Equivalent serial
esr - - - 1 W
resistor of CL

External DC load ADC ON - - 0.8

ILOAD mA
current ADC OFF - - 2
1.62 V ≤ VDDA18ADC ≤ 1.98 V,
ILINE_REG Line regulation - 6463 10559 ppm / V
TJ = +30 °C
ILOAD_REG Load regulation 100 μA ≤ ILOAD ≤ 800 μA, TJ = +30 °C - 6276 6974 ppm / mA

Temperature -40 °C < TJ < +25 °C 43 - 98

Tcoeff ppm / °C
coefficient 25 °C < TJ < +125 °C 64 - 139

Power supply DC 48 76 -
PSRR dB
rejection 100 KHz 51 60 -
tSTART Start-up time - - 300 800 μs
Control of max DC current drive on VREFBUF_OUT
IINRUSH - - 10 mA
during start-up phase
ILOAD = 0.8 mA DC - 9 17
VREFBUF supply
IVDDA18ADC( current VDDA18ADC ENVR = 1 Peak during 2× μA
- 48 60
VREFBUF) (excluding internal ADC conversions
and external load)
ENVR = 0 - 5 26 μA
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Static condition 1.98 V allowed during transients.

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5.3.25 Digital temperature sensor (DTS) characteristics

Table 98. DTS characteristics

Symbol Parameter Conditions Min Typ Max Unit

fDTS Operating frequency - 4 - 8 MHz

Res Resolution - 8 10 12 Bits
Step Step size - 0.86 0.22 0.06 °C
tconv Conversion time - 512 2048 8192
1 / fDTS
tpwrup Power up time - - - 256
TA = -20 °C to +130 °C - - 3
TA Accuracy °C
TA = -40 °C to -20 °C - - 6
G G constant 59.7 °C
H H constant Refer to reference manual for 204.4 °C
J J constant the formula -0.16 °C / MHz
Cal5 Cal5 constant 4094 -
fDTS = 8 MHz, continuous
- 120 160
measurements, single sensor
DTS supply current on
IDTS(VDDA18AON) μA
VDDA18AON 1 measurement/s - - 1
fDTS clock stopped - - 1
DTS supply current on
IDTS(VDDCORE) fDTS = 8 MHz - - 15 μA
VDDCORE

5.3.26 VBAT, VDDx, VDDCORE, VDDA18AON, ADC

measurement characteristics

Table 99. VBAT, VDDx, VDDCORE, VDDA18AON, ADC measurement characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

R Resistor bridge for VBAT - 130 - kΩ

Q Ratio on VBAT measurement - 4 - -
Er Error on Q - TBD - TBD %
ADC sampling time when
tS_VBAT - TBD - -
reading the VBAT
ADC sampling time when
tS_VDD - TBD - -
reading the VDD
μs
ADC sampling time when
tS_VDDA18AON - TBD - -
reading the VDDA18AON
ADC sampling time when
tS_VDDCORE - TBD - -
reading the VDDCORE
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. TBD stands for “to be defined”.

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5.3.27 Temperature and VBAT monitoring characteristics

for tamper detection

Table 100. Temperature and VBAT monitoring characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

TEMPH High TJ temperature monitoring - 110 - 125

°C
TEMPL Low Tj temperature monitoring - -40 - -30
V08CAPH High V08CAP(2) supply monitoring - 0.88 - 1
V
V08CAPL Low V08CAP(2) supply monitoring - 0.6 - 0.72
V08CAP_filter V08CAP(2) supply monitoring glitch filter - - - 1 μs
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. V08CAP is an internal regulator supplied by VSW. VSW is equal to VDD when present. It is equals to VBAT otherwise.

5.3.28 Compensation cell characteristics

Table 101. Compensation cell characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA18AON current consumption

ICOMPCELL - 250 - μA
during code calculation
Using a 8 MHz clock
Time needed to have the first code
Tready (HSI / 8) - 96 -
calculation after enabling μs
Tmeasure Time needed to update the code - 832 -
1. Evaluated by characterization and not tested in production, unless otherwise specified.

5.3.29 Multifunction digital filter (MDF) characteristics

Unless otherwise specified, the parameters given in Table 102 for MDF are derived from
tests performed under the ambient temperature, fAHB frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scale is set to VOS0

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Refer to Section 5.3.17 for more details on the input/output alternate function
characteristics.
Table 102. MDF characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit

Input clock frequency via

fCKI MDF_CKIx pin, in target SPI - - 25
mode
Input clock frequency via
fCCKI MDF_CCK[1:0] pin, in target - - 25
SPI mode
1.65 < VDD < 3.6 V MHz
Output clock frequency, in
fCCKO - - 25
controller SPI mode
Output clock frequency, in
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate,in
fSYMB - - 20
Manchester mode
MDF_CKIx input clock high
tHCKI, tLCKI Target SPI mode 2 × Tmdf_proc_ck(2) - -
and low time
MDF_CCK[1:0] input clock
tHCCKI, tLCCKI Target SPI mode 2 × Tmdf_proc_c - -
high and low time
tHCCKO, MDF_CCK[1:0] output clock
Controller SPI mode 2 × Tmdf_proc_ck - -
tLCCKO high and low time
tHCCKOLF, MDF_CCK[1:0] output clock
LF_MASTER SPI mode Tmdf_proc_ck - -
tLCCKOLF high and low time
ns
Data setup time w.r.t.
tSUCKI Target SPI mode, 2.5 - -
MDF_CKIx input
measured on rising and
Data hold time w.r.t. falling edge
tHDCKI 0 - -
MDF_CKIx input
Data setup time w.r.t. Target SPI mode,
tSUCCKI 3 - -
MDF_CCK[1:0] input MDF_CCK[1:0]
configured in input,
Data hold time w.r.t. measured on rising and
tHDCCKI 0 - -
MDF_CCK[1:0] input falling edge
Data setup time w.r.t. Controller SPI mode,
tSUCCKO 3 - -
MDF_CCK[1:0] output MDF_CCK[1:0]
configured in output,
Data hold time w.r.t. measured on rising and
tHDCCKO 0 - -
MDF_CCK[1:0] output falling edge
ns
Data setup time w.r.t. LF_MASTER SPI mode,
tSUCCKOLF 14 - -
MDF_CCK[1:0] output MDF_CCK[1:0]
configured in output,
Data hold time w.r.t. measured on rising and
tHDCCKOLF 0 - -
MDF_CCK[1:0] output falling edge
1. Evaluated by characterization. Not tested in production.
2. Tmdf_proc_ck is the period of the MDF processing clock.

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Figure 46. MDF timing diagram

tSUCKI tHDCKI tSUCKI tHDCKI

fCKI, fCCKI, FCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCKI, tLCCKI, tHCKI, tHCCKI,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKO tHCCKO

MDF_CKIx (I)
MDF_CCK (I/O)

MDF_SDIx (I)
MSv69125V1

5.3.30 Audio digital filter (ADF) characteristics

Unless otherwise specified, the parameters given in Table 103 are derived from tests
performed under the ambient temperature, fAHB frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scale is set to VOS0
Refer to Section 5.3.17 for more details on the input/output alternate function
characteristics.

Table 103. ADF characteristics(1)

Symbols Parameters Conditions Min Typ Max Units

Input clock frequency via

FCCKI ADF_CCK[1:0] pin, in target 1.65 < VDD < 3.6 V - - 25
SPI mode
Output clock frequency, in
FCCKO 1.65 < VDD < 3.6 V - - 25
controller SPI mode MHz
Output clock frequency, in
FCCKOLF 1.65 < VDD < 3.6 V - - 5
LF_MASTER SPI mode
Input symbol rate, in
FSYMB 1.65 < VDD < 3.6 V - - 20
Manchester mode
ADF_CCK[1:0] input clock
THCCKI, TLCCKI Target SPI mode 2 × Tadf_proc_ck - -
high and low time
ADF_CCK[1:0] output clock
THCCKO, TLCCKO Controller SPI mode 2 × Tadf_proc_ck - - ns
high and low time
THCCKOLF, ADF_CCK[1:0] output clock
LF_MASTER SPI mode Tadf_proc_ck - -
TLCCKOLF high and low time

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Table 103. ADF characteristics(1) (continued)

Symbols Parameters Conditions Min Typ Max Units

Data setup time w.r.t. Target SPI mode,

TSUCCKI 3 - -
ADF_CCK[1:0] input ADF_CCK[1:0] configured
Data hold time w.r.t. in input, measured on
THDCCKI rising and falling edge 0.5 - -
ADF_CCK[1:0] input
Data setup time w.r.t. Controller SPI mode,
TSUCCKO 3 - -
ADF_CCK[1:0] output ADF_CCK[1:0] configured
ns
Data hold time w.r.t. in output, measured on
THDCCKO rising and falling edge 0.5 - -
ADF_CCK[1:0] output
Data setup time w.r.t. LF_MASTER SPI mode,
TSUCCKOLF 14 - -
ADF_CCK[1:0] output ADF_CCK[1:0] configured
Data hold time w.r.t. in output, measured on
THDCCKOLF rising and falling edge 0.5 - -
ADF_CCK[1:0] output
1. Evaluated by characterization. Not tested in production.

Figure 47. ADF timing diagram

fCCKI, fCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCCKI, tLCCKO, tHCCKI, tHCCKO,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKOLF tHCCKOLF

ADF_CCK (I/O)

ADF_SDIx (I)
MSv69124V1

5.3.31 Camera interface (DCMI) characteristics

Unless otherwise specified, the parameters given in Table 104 are derived from tests
performed under the ambient temperature, fHCLK frequency, and VDD supply voltage
summarized in Table 24, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data format: 14 bits
• Capacitive load CL = 30 pF
• Measurement points done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 104. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 100 MHz

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Table 104. DCMI characteristics(1) (continued)

Symbol Parameter Min Max Unit

DPIXEL Pixel clock input duty cycle 30 70 %

tsu(DATA) Data input setup time 3.5 -
th(DATA) Data hold time 0.5 -
ns
tsu(HSYNC)tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times 3.5 -
th(HSYNC)th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times 1 -
1. Evaluated by characterization. Not tested in production.

Figure 48. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

5.3.32 Camera interface pixel pipeline (DCMIPP) characteristics

Unless otherwise specified, the parameters given in Table 105 are derived from tests
performed under the ambient temperature, fHCLK frequency, and VDD supply voltage
summarized in Table 24, with the following configuration:
• DCMIPP_PIXCLK polarity: falling
• DCMIPP_VSYNC and DCMIPP_HSYNC polarity: high
• Data format: 16 bits
• Capacitive load C = 30 pF
• HSLV deactivated
• Measurement points are done at CMOS levels: 0.5 VDD

Table 105. DCMIPP characteristics(1)

Symbol Parameter Min Max Unit

DCMIPP_PIXCLK Pixel clock input - 120 MHz

Dpixel Pixel clock input duty cycle 30 70 %

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Table 105. DCMIPP characteristics(1) (continued)

Symbol Parameter Min Max Unit

tsu(DATA) Data input setup time 2 -

th(DATA) Data hold time 3 -
ns
tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input setup time 2 -
th(HSYNC), th(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input hold time 3 -
1. Evaluated by characterization. Not tested in production.

Figure 49. DCMIPP timing diagram

1/DCMIPP_PIXCLK

DCMIPP_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMIPP_HSYNC

tsu(VSYNC) th(HSYNC)

DCMIPP_VSYNC
tsu(DATA) th(DATA)

DATA[15:0]

MSv73149V1

5.3.33 Parallel interface (PSSI) characteristics

Unless otherwise specified, the parameters given in Table 106 and Table 107 are derived
from tests performed under the ambient temperature, fHCLK frequency, and VDD supply
voltage summarized in Table 24, with the following configuration:
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
• Capacitive load CL = 30 pF
• Measurement points done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 106. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI clock input 1.65 V ≤ VDD ≤ 3.6 V - 100(2) MHz

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Table 106. PSSI transmit characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

DPIXEL PSSI clock input duty cycle - 30 70 %

tSU(DATA) Data output valid time 1.65 V ≤ VDD ≤ 3.6 V - 8
tH(DATA) Data output hold time 5 -
tSU(DE) DE output valid time - 8
ns
tH(DE) DE output hold time 1.65 V ≤ VDD ≤ 3.6 V 5 -
tOV(RDY) RDY input setup time 0 -
tOH(RDY) RDY input hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.

Figure 50. PSSI transmit timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)

tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)

DEPOL=1

ts(RDY) th(RDY)
PSSI_RDY

RDYPOL=0
(input)

RDYPOL=1

MSv63437V1

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Table 107. PSSI receive characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI clock input 1.65 V ≤ VDD ≤ 3.6 V - 100 MHz
DPIXEL PSSI clock input duty cycle - 30 70 %
tSU(DATA) Data input setup time 3.5 -
tH(DATA) Data input setup time 0.5 -
tSU(DE) DE input setup time 3 -
1.65 V ≤ VDD ≤ 3.6 V ns
tH(DE) DE input setup time 1 -
tOV(RDY) RDY output setup time - 7
tOH(RDY) RDY output hold time 6 -
1. Evaluated by characterization. Not tested in production.

Figure 51. PSSI receive timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)

DEPOL=1

tv(RDY) tho(RDY)
PSSI_RDY

RDYPOL=0
(output)

RDYPOL=1

MSv63436V1

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5.3.34 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 108 for TFT-LCD are derived
from tests performed under the ambient temperature, fHCLK frequency, and VDD supply
voltage summarized in Table 24, with the following configuration:
• LCD_CLK polarity: low
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel format: 24 bits
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.5 V
• Output speed is set to OSPEEDRy[1:0] = 11

Table 108. LCD-TFT characteristics(1)

Symbol Parameter Min Max Unit

LTDC clock output 1.65 V ≤ VDD ≤ 3.6 V,

fCLK - 88 MHz
frequency 30 pF
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH), tw(CLKL) Clock high time, low time tw(CLK) /2 - 0.5 tw(CLK) /2 + 0.5
tv(DATA) Data output valid time - 3.5 ns
th(DATA) Data output hold time 1.5 -

tv(HSYNC), -
HSYNC/VSYNC/DE output valid time -
tv(VSYNC), 1.5
th(HSYNC), ns
th(VSYNC), HSYNC/VSYNC/DE output hold time 0.5 -
th(DE)
1. Evaluated by characterization. Not tested in production.

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Figure 52. LCD-TFT horizontal timing diagram

tCLK

LCD_CLK

LCD_VSYNC

tv(HSYNC) tv(HSYNC)

LCD_HSYNC
tv(DE) th(DE)

LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)

HSYNC Horizontal Active width Horizontal

width back porch back porch

One line
MS32749V1

Figure 53. LCD-TFT vertical timing diagram

tCLK

LCD_CLK

tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]

VSYNC Vertical Active width Vertical

width back porch back porch

One frame
MS32750V1

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5.3.35 Timer characteristics

The parameters given in Table 109 and Table 110 are specified by design, not tested in
production.
Refer to Table 5.3.17 for details on the input/output alternate function characteristics (output
compare, input capture, external clock, PWM output).

Table 109. TIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tTIMxCLK

fTIMxCLK Timer kernel clock 0 200
MHz
fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK / 2
Timer resolution - 16
ResTIM bit
Timer resolution (TIM2 to TIM5) - 32
Maximum possible count with 16-bit counter - 65536
tMAX_COUNT tTIMxCLK
Maximum possible count with 32-bit counter (TIM2 to TIM5) - 65536 × 65536
1. Specified by design. Not tested in production.
2. TIMx is used as a general term to refer to the TIM1 to TIMx timers.

Table 110. LPTIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(LPTIM) Timer resolution time 1 - tLPTIMxCLK

Timer kernel clock 0 100 MHz
fLPTIMxCLK
Timer kernel clock (autonomous mode) 0 32768 Hz
fEXT Timer external clock frequency on IN1 and IN2 0 fLPTIMxCLK / 2 MHz
ResLPTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 fLPTIMxCLK
1. Specified by design. Not tested in production.
2. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.

5.3.36 Communications interfaces

SPI interface
Unless otherwise specified, the parameters given in Table 111 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load: C = 3 0pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.5 V

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Refer to Section 5.3.17 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, and MISO for SPI).

Table 111. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Controller mode, 1.65 < VDD < 1.98 V 115

Controller mode, 3.00 < VDD < 3.6 V 105
fSCK SPI clock frequency - - MHz
Target receiver mode 100
Target mode transmitter/full duplex 50(2)
tsu(NSS) NSS setup time Target mode 4 - -
th(NSS) NSS hold time Target mode 1 - -
tw(SCKH)
SCK high and low time Controller mode Tpclk - 1 Tpclk Tpclk + 1
tw(SCKL)
tsu(MI) Controller mode 4.5 - -
Data input setup time
tsu(SI) Target mode 4.5 - -
th(MI) Controller mode 1 - -
Data input hold time ns
th(SI) Target mode 1 - -
ta(SO) Data output access time Target mode 8 9 10.5
tdis(SO) Data output disable time Target mode 5.5 8 9
tv(SO) Target mode - 8.5 10
Data output valid time
tv(MO) Controller mode - 2.5 3
th(SO) Target mode 7.5 - -
Data output hold time
th(MO) Controller mode 2 - -
1. Evaluated by characterization. Not tested in production.
2. Maximum frequency in target transmitter mode is determined by the sum of tv(SO) and tsu(MI), which must fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a controller
having tsu(MI) = 0 while Duty(SCK) = 50%.

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Figure 54. SPI timing diagram - Controller mode

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

Figure 55. SPI timing diagram - Target mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

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Figure 56. SPI timing diagram - Target mode and CPHA = 1

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

I2C interface
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.
The timing requirements are specified by design, not tested in production, when the
peripheral is properly configured (refer to product reference manual).

Table 112. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes suppressed by analog filter 50(2) 230(3) ns
1. Evaluated by characterization. Not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.

I3C interface
The I3C interface meets the timing requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz

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The parameters given in Table 113 are obtained with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scale is set to VOS[0] = 1.

Table 113. I3C open-drain measured timing(1)

I3C open drain mode Timing measurements
Symbol Parameter Conditions Unit
Min Max Min Max

SDA data setup time during

tSU_OD Controller 3 - 20(2) - ns
open drain mode
1. Evaluated by characterization. Not tested in production.
2. This timing is not in line with minimal value in MIPI specification. This can be mitigated by adjusting the clock stall time on
the Tbit phase through the I3C_TIMINGR2 register, and/or by increasing the SCL low duration in the TIMINGR0 register.
For further details, refer to AN5879 “Introduction to I3C for STM32 MCUs”.

Table 114. I3C push-pull measured timing(1)

I3C push-pull mode Timing measurements Unit
Symbol Parameter Conditions
Min Max Min Max -

SDA signal data setup

tSU_PP Controller 3 - 18(2) - ns
in push-pull mode

1. Evaluated by characterization. Not tested in production.

2. This timing is not in line with minimal value in MIPI specification. This can be mitigated by adjusting the clock stall time on
the Tbit phase through the I3C_TIMINGR2 register, and/or by increasing the SCL low duration in the TIMINGR0 register.
For further details, refer to AN5879 “Introduction to I3C for STM32 MCUs”.

I2S interface
Unless otherwise specified, the parameters given in Table 115 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load: C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.17 for more details on the input/output alternate function characteristics
(CK,SDO,SDI,WS).

Table 115. I2S characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output - - 50 MHz

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Table 115. I2S characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Controller - 50
fCK I2S clock frequency Target TX - 27 MHz
Target RX - 50
tv(WS) WS valid time Controller mode - 3.5
th(WS) WS hold time Controller mode 1.5 -
tsu(WS) WS setup time Target mode 3 -
th(WS) WS hold time Target mode 1 -
tsu(SD_MR) Controller receiver 4 -
Data input setup time
tsu(SD_SR) Target receiver 4.5 -
ns
th(SD_MR) Controller receiver 1 -
Data input hold time
th(SD_SR) Target receiver 0 -
tv(SD_ST) Target transmitter (after enable edge) - 11
Data output valid time
tv(SD_MT) Controller transmitter (after enable edge) - 3.5
th(SD_ST) Target transmitter (after enable edge) 8 -
Data output hold time
th(SD_MT) Controller transmitter (after enable edge) 0.5 -
1. Evaluated by characterization. Not tested in production.

Figure 57. I2S target timing diagram (Philips protocol)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

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Figure 58. I2S controller timing diagram (Philips protocol)

tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

SAI interface
Unless otherwise specified, the parameters given in Table 116 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.17 for more details on the input/output alternate function characteristics
(CK,SD,WS).

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Table 116. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI main clock output - - 50

Controller transmitter - 38
Controller receiver - 34 MHz
fCK SAI clock frequency(2)
Target transmitter - 40
Target receiver - 50
tv(FS) FS valid time Controller mode - 13
th(FS) FS hold time Controller mode 9 -
tsu(FS) FS setup time Target mode 3.5 -
th(FS) FS hold time Target mode 1 -
tsu(SD_A_MR) Controller receiver 4 -
Data input setup time
tsu(SD_B_SR) Target receiver 4 -
ns
th(SD_A_MR) Controller receiver 1 -
Data input hold time
th(SD_B_SR) Target receiver 1 -
tv(SD_B_ST) Data output valid time Target transmitter (after enable edge) - 12.5
th(SD_B_ST) Data output hold time Target transmitter (after enable edge) 8 -
tv(SD_A_MT) Data output valid time Controller transmitter (after enable edge) - 12.5
th(SD_A_MT) Data output hold time Controller transmitter (after enable edge) 8.5 -
1. Evaluated by characterization. Not tested in production.
2. APB clock frequency must be at least twice SAI clock frequency.

Figure 59. SAI controller timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)

SAI_SCK_X
(CKSTR = 1)
th(FS)

SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
(transmit) Slot n Slot n+2

tsu(SD_MR) th(SD_MR)

SAI_SD_X
(receive) Slot n

MS32771V2

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Figure 60. SAI target timing waveforms

1/fSCK

SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)

tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X
Slot n
(receive)
MS32772V2

Ethernet (ETH) interface

Unless otherwise specified, the parameters given in Table 117 to Table 120 for MDIO/SMA,
RMII, MII, RGMII, and RGMII ID are derived from tests performed under the ambient
temperature, fHCLKx frequency, and VDD supply voltage conditions summarized in Table 24,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.17 for more details on the input/output characteristics.

Table 117. Dynamic characteristics: Ethernet MAC signals for MDIO/SMA(1)

Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time (2.5 MHz) 399 400 401

Td(MDIO) Write data valid time 3.5 4.5 5
ns
tsu(MDIO) Read data setup time 16 - -
th(MDIO) Read data hold time 0 - -
1. Evaluated by characterization. Not tested in production.

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Figure 61. Ethernet MDIO/SMA timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

Table 118. Dynamic characteristics: Ethernet MAC signals for RMII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(CRS) Carrier sense setup time 2 - -
ns
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 4 5 6
td(TXD) Transmit data valid delay time 4 5 6
1. Evaluated by characterization. Not tested in production.

Figure 62. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]

tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667b

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Table 119. Dynamic characteristics: Ethernet MAC signals for MII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 2.5 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(DV) Data valid setup time 1 - -
tih(DV) Data valid hold time 1.5 - -
ns
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 1 - -
td(TXEN) Transmit enable valid delay time 5 6 7.5
td(TXD) Transmit data valid delay time 5 6 7.5
1. Evaluated by characterization. Not tested in production.

Figure 63. Ethernet MII timing diagram

MII_RX_CLK

tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668b

Table 120. Dynamic characteristics: Ethernet MAC signals for RGMII ID(1)(2)(3)
Symbol Rating Min Typ Max Unit

Tcyc Clock cycle duration 7.5 8 8.5

Tskew_R (RXD) Receive data skew time -1(4) - 0.5(4)
Tskew R (DV) Receive valid skew time -1(4) - 0.5(4)
Tsetup T (TXEN) Transmit enable to clock output setup time 1.4(5) - - ns
TsetupT(TXD) Transmit data to clock output setup time 1.4(5) - -
Thold T (TXEN) Transmit clock to transmit enable output hold time 1.4(5) - -
Thold T (TXD) Transmit clock to data output hold time 1.4(5) - -
1. Evaluated by characterization. Not tested in production.

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2. RGMII TX/RX data bits are retimed.

3. Test done at 100 MHz.
4. With delay on RGMII_RX_CLK (GPIOx_DELAYR) = 0b1110.
5. With delay on RGMII_TX_CLK (GPIOx_DELAYR) = 0b1010.

USART (SPI mode) interface

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.17 for more details on the input/output alternate function characteristics
(NSS, CK, TX, RX for USART).

Table 121. USART (SPI mode) characteristics(1)

Symbol Parameter Conditions Min Typ Max(2) Unit

Controller mode, 1.65 V ≤ VDD ≤ 3.6 V - - 12.5

fSCK Clock frequency MHz
Target mode, 1.65 V ≤ VDD ≤ 3.6 V - - 33
tsu(NSS) NSS setup time Target mode tker+3 - -
th(NSS) NSS hold time Target mode 0.5 - -
tw(SCKH), SCK high and low
Controller mode 1 / fck / 2 - 1 1 / fck / 2 1 / fck / 2 + 1
tw(SCKL) time
tsu(RX) Data input setup Controller mode 13 - -
tsu(TX) time Target mode 6 - -
ns
th(RX) Data input hold Controller mode 0 - -
th(RX) time Target mode 0 - -
tv(TX) Data output valid Target mode - 11.5 14
tv(TX) time Controller mode - 4.5 5.5
th(TX) Data output hold Target mode 10 - -
th(TX) time Controller mode 3 - -
1. Evaluated by characterization. Not tested in production.

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Figure 64. USART timing diagram in SPI controller mode

1/fCK
tw(CKH)
CPHA=0
CK output
CPOL=0

CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output

CPOL=0

CPHA=1
CPOL=1
tsu(RX) th(RX)

RX input MSB IN BIT6 IN LSB IN

TX output MSB OUT BIT1 OUT LSB OUT

tv(TX) th(TX) MSv65386V6

Figure 65. USART timing diagram in SPI target mode

NSS input

1/fCK th(NSS)

tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input

CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

tsu(RX) th(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V6

FDCAN (controller area network) interface

Refer to Section 5.3.17 for more details on the input/output alternate function characteristics
(FDCANx_TX and FDCANx_RX).

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5.3.37 Embedded PHY characteristics

CSI PHY characteristics

Table 122. CSI PHY characteristics(1)

Symbol Parameter Conditions Min Max Typ Unit

REXT External resistor on REXT Connected to ground 198 200 202 Ω

2 lanes at 1 Gbps - 2.21 12.36

High-speed 2 lanes at 1.5 Gbps - 3.14 13.91

receive(2) 2 lanes at 2 Gbps - 4.07 14.94
Supply current on
IVDDCORE(CSIPHY) mA
VDDCORE 2 lanes at 2.5 Gbps - 5.00 16.48
LP receive Lane 0 at 10 Mbps - 0.42 8.29
ULPS receive ck_ker_csi2phy stopped - 0.06 8.70
2 lanes at 1 Gbps 2.19 2.23 2.84

High-speed 2 lanes at 1.5 Gbps 2.31 2.36 3.00

receive(2) 2 lanes at 2 Gbps 2.55 2.65 3.35
Supply current on
IVDDA18CSI mA
VDDA18CSI 2 lanes at 2.5 Gbps 2.54 2.64 3.35
LP receive Lane 0 at 10 Mbps 1.53 1.72 2.25
ULPS receive ck_ker_csi2phy stopped 0.01 0.01 0.02
2 lanes at 1 Gbps 3.51 4.06 5.80

High-speed 2 lanes at 1.5 Gbps 3.99 4.66 6.60

receive(2) 2 lanes at 2 Gbps 2.99 3.40 4.65
Supply current on
IVDDCSI mA
VDDCSI 2 lanes at 2.5 Gbps 3.41 3.86 5.25
LP receive Lane 0 at 10 Mbps 0.68 0.74 0.95
ULPS receive ck_ker_csi2phy stopped 0.00 0.00 0.01
1. Specified by design and not tested in production, unless otherwise specified.
2. The high-speed mode assumes PRBS9 pattern on data lanes and 100% occupation, that is continuous high speed.

USB PHY characteristics

Table 123. USB PHY characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

External resistor
RTXRTUNE Connected to ground 198 200 202 Ω
on TXRTUNE

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Table 123. USB PHY characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
(2)
HS transmit, maximum transition density - 7.52 23.72
HS transmit, minimum transition density(3) - 7.35 23.88
(4)
HS idle - 8.21 23.91
(5)
FS transmit, maximum transition density - 6.53 23.22
LS transmit, maximum transition density(6) - 6.45 24.70
Supply current on
IVDDCORE(USB2PHY) mA
VDDCORE Suspend(7) - 1.25 11.75
Sleep(8) - 1.24 11.52
VDATDETENB = 0,
- 3.17 17.26
Battery VDATSRCENB = 1
charging VDATDETENB = 1,
- 5.82 23.80
VDATSRCENB = 1(9)
HS transmit, maximum transition density(2) - 13.35 17.92
HS transmit, minimum transition density(3) - 9.69 9.71
HS idle(4) - 5.10 5.67
(5)
FS transmit, maximum transition density - 5.14 5.71
LS transmit, maximum transition density(6) - 5.12 5.69
Supply current on
IVDDA18USB mA
VDDA1V8USB Suspend(7) - 0.04 0.08
Sleep(8) - 0.04 0.08
VDATDETENB = 0,
- 3.48 3.88
Battery VDATSRCENB = 1
charging VDATDETENB = 1,
- 4.16 4.55
VDATSRCENB = 1(9)
HS transmit, maximum transition density(2) - 3.39 3.64
(3)
HS transmit, minimum transition density - 2.32 2.53
HS idle(4) - 2.15 2.34
FS transmit, maximum transition density(5) - 16.84 16.84
(6)
LS transmit, maximum transition density - 13.39 14.81
Supply current on
IVDD33USB mA
VDD33USB Suspend(7) - 0.07 0.17
Sleep(8) - 0.07 0.17
VDATDETENB = 0,
- 2.15 2.35
Battery VDATSRCENB = 1
charging VDATDETENB = 1,
- 2.15 2.34
VDATSRCENB = 1(9)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM).
Loading of 10 pF. Transfers do not include any interpacket delay.
3. Packet transmission by one transceiver operating in device mode while driving all 1s data (alternating 7-bit strings of J, then
K on DP/DM). Loading of 10 pF. Transfers do not include any interpacket delay.
4. HS receive mode with no traffic on the line.

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5. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM).
Loading of 50 pF. Transfers do not include any interpacket delay.
6. Packet transmission by one transceiver operating in host mode while driving all 0s data (constant JKJK on DP/DM).
Loading of 600 pF. Transfers do not include any interpacket delay.
7. Suspend when operating in device mode with no far-side host termination on DP/DM during measurements.
Measurements taken when COMMONONN (SYSCFG_USB2PHYxCR.USB2PHYxCMN) is deasserted.
8. Sleep mode when operating in device mode with no far-side host termination on DP/DM during measurements.
9. PHY is in suspend (with clocks turned OFF), nondriving mode and operating as a portable device in the “dead battery”
condition.

UCPD PHY characteristics

Table 124. UCPDPHY characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fBITRATE Bit rate (ensured by adequate RCC and UCPD settings) 270 300 330 Kbps
CRECEIVER Local capacitance added on PCB on each CC line 200 470 600 pF

Transmitter

Voltage swing applies on CC pin to both no load condition and under

VSWING 1.05 1.125 1.2 V
the load condition.
TX output impedance. Source output impedance at the Nyquist
ZDRIVER frequency of USB2.0 low speed (750 kHz) while the source is driving 33 - 75 Ω
the CC line.
Rise/fall time. 10% to 90% / 90% to 10% amplitude points, minimum
Tr / Tf 300 - 735 ns
is under an unloaded condition. Maximum set by TX mask.
TX duty cycle at 0.5625 V (see Y5Tx, BMC Tx 'ONE' Mask and BMC
DCYCLE 47 - 53 %
Tx 'ZERO' Mask in the PD Specification)

Receiver

VIL Sourcing - - 0.4825

Rx receive input thresholds. The position of the center V
VIH power 0.8925 - -
line of the inner mask is dependent on whether the
VIL receiver is sourcing or sinking power or is power - - 0.2325
Sinking
neutral.
VIH power 0.6425 - - V
Hysteresis Rx receive input hysteresis 0.15 - -
Number of transitions for signal detection (number to count to detect
NCOUNT 3 - - -
non-idle bus).
tTRANWIN Time window for detecting non-idle bus 12 - 20 µs
ZBMCRX Receiver input impedance 1 - - MΩ
1. Evaluated by characterization and not tested in production, unless otherwise specified.

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5.3.38 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 125 are derived from tests
performed under the ambient temperature, fHCLKx frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 0x01
• Capacitive load C = 30 pF
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.17 for more details on the input/output characteristics.

Table 125. Dynamic characteristics: JTAG

Symbol Parameter Conditions Min Typ Max Unit

Fpp
TCK clock frequency - - 40 MHz
1 / tc(TCK)
tisu(TMS) TMS input setup time 4 - -
tih(TMS) TMS input hold time 1 - -
1.65 < VDD < 3.6 V
tisu(TDI) TDI input setup time 4 - -
ns
tih(TDI) TDI input hold time 1 - -
tov (TDO) TDO output valid time - 10 12
toh(TDO) TDO output hold time 9.5 - -

Table 126. Dynamic characteristics: SWD

Symbol Parameter Conditions Min Typ Max Unit

Fpp
SWCLK clock frequency - - 80 MHz
1 / tc(SWCLK)
tisu(SWDIO) SWDIO input setup time 4 - -
1.65 < VDD < 3.6 V
tih(SWDIO) SWDIO input hold time 1 - -
ns
tov (SWDIO) SWDIO output valid time - 10 12
toh(SWDIO) SWDIO output hold time 8 - -

MDIOS target interface

Unless otherwise specified, the parameters given in Table 127 are derived from tests
performed under the ambient temperature, fHCLK frequency, and VDD supply voltage
conditions summarized in Table 24, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load: C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V

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Table 127. MDIO target timing parameters(1)

Symbol Parameter Min Typ Max Unit

FMDC Clock - - 30 MHz

td(MDIO) Input/output valid time 7 8 14
tsu(MDIO) Input/output setup time 2 - - ns
th(MDIO) Input/output hold time 0.5 - -
1. Evaluated by characterization. Not tested in production.

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 Device marking

Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

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6.2 VFBGA142 package information (B0GM)

This VFBGA is a 142-ball, 8 x 8 mm, 0.50 mm pitch, very thin fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 66. VFBGA142 - Outline(13)

b (N balls)
E1
eee M C A B
fff M C e
SE
e
R
P
N
M
SD L
K
J
H D1
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A1 ball pad corner

BOTTOM VIEW

C
ccc C ddd C

SEATING
(7) PLANE

A2 SIDE VIEW A1 A

E
B A

(8) A1 ball pad corner

(DATUM A)

(DATUM B)

aaa C
(4x)
TOP VIEW
B0GM_VFBGA142_ME_V1

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Table 128. VFBGA142 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.13 - - 0.0051 - -
A2 - 0.59 - - 0.0232 -
(5)
b 0.26 0.31 0.36 0.0102 0.0122 0.0142
(6)
D 8.00 BSC 0.3149 BSC
D1 7.00 BSC 0.2756 BSC
E 8.00 BSC 0.3149 BSC
E1 7.00 BSC 0.2756 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(10) 142
SD(11) 0.50 BSC 0.0197 BSC
SE(11) 0.50 BSC 0.0197 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. VFBGA stands for very thin profile fine pitch ball grid array: 0.8 mm < A ≤ 1.00 mm /
fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.

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8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or
integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to four decimal digits.
13. Drawing is not to scale.

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6.3 VFBGA169 package information (B0LA)

This VFBGA is a 169-ball, 6 x 6 mm, 0.4 mm pitch, very thin fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 67. VFBGA169 - Outline(13)

B0LA_VFBGA169_ME_V2

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Table 129. VFBGA169 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.11 - - 0.0043 - -
A2 - 0.62 - - 0.0344 -
(5)
b 0.22 0.26 0.30 0.0087 0.0102 0.0118
(6)
D 6.00 BSC 0.2362 BSC
D1 4.80 BSC 0.1890 BSC
E 6.00 BSC 0.2362 BSC
E1 4.80 BSC 0.1890 BSC
(9)
e 0.40 BSC 0.0157 BSC
N(10) 169
SD(11) 0.40 BSC 0.0157 BSC
SE(11) 0.40 BSC 0.0157 BSC
aaa 0,10 0.0039
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2018.
2. VFBGA stands for very thin fine pitch ball grid array: 0.80 mm < A ≤ 1.00 mm / Fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD & SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to four decimal digits.
13. Drawing is not to scale.

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6.4 VFBGA178 package information (B0GL)

This VFBGA is a 178-ball, 12 x 12 mm, 0.80 mm pitch, very thin fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 68. VFBGA178 - Outline(13)

b (N balls)
eee M C A B
fff M C E1
e SE e
P
N
M
L
K
SD J
H
G
D1
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14

A1 ball pad corner

BOTTOM VIEW

ccc C ddd C
C
SEATING
(7) PLANE

A2 A1 A
SIDE VIEW

E
B A

(8) A1 ball pad corner

(DATUM A)

(DATUM B)

aaa C
TOP VIEW
(4x)
B0GL_VFBGA178_ME_V2

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Table 130. VFBGA178 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.21 - - 0.0082 - -
A2 - 0.51 - - 0.0201 -
(5)
b 0.38 0.43 0.48 0.150 0.0170 0.189
(6)
D 12.00 BSC 0.4724 BSC
D1 10.40 BSC 0.4094 BSC
E 12.00 BSC 0.4724 BSC
E1 10.40 BSC 0.4094 BSC
(9)
e 0.80 BSC 0.0315 BSC
N(10) 178
SD(11) 0.40 BSC 0.0157 BSC
SE(11) 0.40 BSC 0.0157 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. VFBGA stands for very thin profile fine pitch ball grid array: 0.8 mm < A ≤ 1.00 mm /
fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.

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8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or
integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to four decimal digits.
13. Drawing is not to scale.

Figure 69. VFBGA178 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

1. Dimensions are expressed in millimeters.

Table 131. VFBGA178 - Example of PCB design rules (0.80 mm pitch BGA)
Dimension Values

Pitch 0.8 mm
Dpad 0.400 mm
Dsm 0.470 mm typ.
Stencil opening 0.400 mm
Stencil thickness 0.100 mm

6.5 VFBGA198 package information (B0GJ)

This VFBGA is a 198-ball, 10 x 10 mm, 0.65 mm pitch, very thin fine pitch ball grid array
package.

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Note: See list of notes in the notes section.

Figure 70. VFBGA198 - Outline(13)

b (N balls)
eee M C A B
fff M C
E1
e SE e
R
P
N
M
L
SD K
J
H D1
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A1 ball pad corner

BOTTOM VIEW

ccc C ddd C
C

SEATING
(7) PLANE

A2 SIDE VIEW
A1 A

E
B A

(8)
A1 ball pad corner
(DATUM A)

(DATUM B)

aaa C
TOP VIEW (4x)
B0GJ_VFBGA198_ME_V1

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Table 132. VFBGA198 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.21 - - 0.0082 - -
A2 - 0.51 - - 0.0201 -
(5)
b 0.35 0.40 0.45 0.0138 0.0157 0.0177
(6)
D 10.00 BSC 0.3937BSC
D1 9.10 BSC 0.3583 BSC
E 10.00 BSC 0.3937BSC
E1 9.10 BSC 0.3583 BSC
(9)
e 0.65 BSC 0.0256 BSC
N(10) 198
SD(11) 0.65 BSC 0.0256 BSC
SE(11) 0.65 BSC 0.0256 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.00315

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. VFBGA stands for very thin profile fine pitch ball grid array: 0.8 mm < A ≤ 1.00 mm /
fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.

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8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or
integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to four decimal digits.
13. Drawing is not to scale.

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6.6 VFBGA223 package information (B0GK)

This VFBGA is a 223-ball, 10 x 10 mm, 0.50 mm pitch, very thin fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 71. VFBGA223 - Outline(13)

E1
e SE

W
V
U
T e
R
P
N
M
L
K D1
J
SD H
G
F
E
D
C
B
A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A1 ball pad corner
b (N balls)
eee M C A B
fff M C
BOTTOM VIEW

ddd C A ccc C

SEATING
8 PLANE
A2
C A1
SIDE VIEW

A
B E

9 A1 ball pad corner

(DATUM A)

D
B0GK_VFBGA223_ME_V2

(DATUM B)

aaa C
TOP VIEW (4x)

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Table 133. VFBGA223 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.13 - - 0.0051 - -
A2 - 0.51 - - 0.0201 -
(5)
b 0.26 0.31 0.36 0.0102 0.0122 0.0142
(6)
D 10.00 BSC 0.3937BSC
D1 9.00 BSC 0.3543 BSC
E 10.00 BSC 0.3937BSC
E1 9.00 BSC 0.3543 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(10) 223
SD(11) 0.50 BSC 0.0197 BSC
SE(11) 0.50 BSC 0.0197 BSC
(12)
aaa 0.15 0.0059
(12)
ccc 0.20 0.0079
ddd(12) 0.08 0.0031
(12)
eee 0.15 0.0059
(12)
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. VFBGA stands for very thin profile fine pitch ball grid array: 0.8 mm < A ≤ 1.00 mm /
fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Tolerance of form and position drawing.
13. Values in inches are converted from mm and rounded to 4 decimal digits.
14. Drawing is not to scale.

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6.7 VFBGA264 package information (B0GH)

This VFBGA is a 264-ball, 14 x 14 mm, 0.8 mm pitch, very thin fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 72. VFBGA264 - Outline(13)

b (N balls)
eee M C A B
fff M C
E1
e SE e
U
T
R
P
N
M
L
SD K
J
H D1
G
F
E
D
C
B
A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A1 ball pad corner

BOTTOM VIEW

ccc C ddd C
C

SEATING
(8) PLANE

A2 SIDE VIEW A1 A

E
B A

(9) A1 ball pad corner

(DATUM A)

(DATUM B)

TOP VIEW B0GH_VFBGA264_ME_V1

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Table 134. VFBGA264 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.00 - - 0.0394

(4)
A1 0.21 - - 0.0082 - -
A2 - 0.59 - - 0.0232 -
(5)
b 0.38 0.43 0.48 0.150 0.0170 0.189
(6)
D 14.00 BSC 0.5512 BSC
D1 12.80 BSC 0.5039 BSC
E 14.00 BSC 0.5512 BSC
E1 12.80 BSC 0.5039 BSC
(9)
e 0.80 BSC 0.03149 BSC
N(10) 264
SD(11) 0.80 BSC 0.03149 BSC
SE(11) 0.80 BSC 0.03149 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.00315

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. VFBGA stands for very thin profile fine pitch ball grid array: 0.8 mm < A ≤ 1.00 mm /
fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.

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8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metallized markings, or other feature of package body or
integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to four decimal digits.
13. Drawing is not to scale.

Figure 73. VFBGA264 - Recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

1. Dimensions are expressed in millimeters.

Table 135. VFBGA264 - Recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values

Pitch 0.8 mm
Dpad 0.400 mm
Dsm 0.470 mm typ.
Stencil opening 0.400 mm
Stencil thickness 0.100 mm

6.8 Package thermal characteristics

For package thermal characteristics, refer to AN5036 “Guidelines for thermal management
on STM32 applications”, available on www.st.com.

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7 Ordering information

Example: STM32 N 6 57 X 0 H 3 Q U
Device family
STM32 = Arm® based 32-bit microcontroller

Product type
N = neural

Device subfamily
6 = Cortex M55 core

Die
4 = No crypto, 4 Mbytes
5 = Crypto, 4 Mbytes

Line
7 = Neural ART option (artificial intelligence)
5 = No neural ART option (artificial intelligence)

Pin/ball count
Z = 142
A = 169
I = 178
B = 198
L = 223
X = 264

Flash memory size

0 = 0-1 Kbytes

Package
H = VFBGA

Temperature range
3 = Industrial temperature range, -40 to 125 °C

Dedicated pinout
Q = Internal SMPS step-down converter

Packing
U = Universal part (not for production, sampling, and tools)
TR = Tape and ring

For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.

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Important security notice STM32N6x5xx STM32N6x7xx

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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9 Revision history

Table 136. Document revision history

Date Revision Changes

28-Nov-2024 1 Initial release

Updated Table 3: STM32N647xx features and peripheral counts,
Table 5: STM32N657xx features and peripheral counts, Table 18: Pin
description, Table 21: Voltage characteristics, Table 24: General
operating conditions, Table 40: Current consumption in Sleep mode,
Table 60: OTP characteristics, Table 63: ESD absolute maximum
ratings, Table 67: RPU/RPD characteristics, and Table 95: ADC
18-Dec-2024 2 accuracy.
Updated Figure 3: Device startup with VCORE supplied directly from an
external SMPS and Figure 4: Device startup with VCORE supplied
directly from the internal SMPS.
Added Section 6.8: Package thermal characteristics.
Minor text edits across the whole document.
Document scope extended to STM32N645xx and STM32N655xx
devices.
Updated document title, Features. Section 1: Introduction, Section 2:
Description, Section 3.3: AXI cache configuration, Section 3.4.4: SMPS
usage, Section 3.5: Convolution neural network accelerator (NPU),
Section 3.34: Secure AES coprocessor (SAES), Section 3.35:
Cryptographic processor (CRYP), Section 3.37: Memory cipher engine
(MCE), Section 3.38: Public key accelerator (PKA), and Section 7:
Ordering information.
25-Feb-2025 3 Added Section 5.3.4: SMPS step-down converter.
Updated Table 1: Device summary, Table 7: Functionalities depending
on system operating mode, Table 17: Legend/abbreviations used in the
pinout table, Table 18: Pin description, and tables in Section 5.3.6:
Supply current characteristics.
Added Table 2: STM32N645xx features and peripheral counts and
Table 4: STM32N655xx features and peripheral counts.
Updated Figure 67: VFBGA169 - Outline(13).
Minor text edits across the whole document.

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IMPORTANT NOTICE – READ CAREFULLY

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