Blocking & non-blocking

eInfochips Training and Research Academy [eiTRA]

Verilog Assignment
BLOCKING & NON-BLOCKING

Q1. Given the following Verilog code, what will be the value of "a" at output?

(a)
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end

(b)
always @(clk) begin
a <= 0;
a = 1;
$display(a);
end

Q2. Develop a Verilog code to swap contents of two registers without using a temporary register?

Q3. Analyze the value of ’A’ and ‘B’ in the following two Verilog codes:

(a)

module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A+1;
$display("Blocking: A= %b B= %b", A, B );
endmodule

(b)

module nonblocking;
reg [0:7] A, B;
initial begin: init1 A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A+1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule

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Q4. Registers x and y are declared as reg [2:0] x,y;. x and y have initial values of 1 and 2
respectively. Find the value of x and y after each of the following Verilog codes have been
executed.
(a) y = x && y;
x = y & x;
(b) x <= (y) ? y : x;
y <= (x) ? x : y;
(c) x = (y) ? y : x;
y = (x) ? x
: y;
(d) x <= x << 1;
x[0] <= x[2];
(e) x = x && (˜y);
y = x + y;

Q5. Registers a, b are declared as reg [2:0] a,b;. a and b have initial values of 3 and 1 respectively.
Find the values of a and b after each of the following Verilog codes are executed.
(a) a = b + 2;
b = a + 2;
(b) b = a + 2;
a = b + 2;
(c) a <= b + 2;
b <= a + 2;
(d) b <= a + 2;
a <= b + 2;
(e) b = a && b;
a = b & a;
(f) a <= |b;
b <= &a;

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Q6. How will these procedural assignments behave, draw the waveform for o1, o2, o3,o4, o5, o6?
Also Specify the type of assignment(blocking/nonblocking).

(a) always @(in)

o1 = in;
(b) always @(in)
o2 <= in;
(c) always @(in)
#5 o3 = in;
(d) always @(in)
#5 o4 <= in;

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(e) always @(in)

o5 = #5 in;
(f) always @(in)
o6 <= #5 in;

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Q7. How will the following procedural assignments behave? Draw the waveforms for Y1 and Y2,
for the given inputs. Also draw the hardware for all the codes.

(a) always @(posedge clk) begin

y1 = in;
y2 = y1;
end

(b) always @( posedge clk) begin

y1 <= in;
y2 <= y1;
end

(c) always @( posedge clk) begin

#5 y1 = in; #5 y2 = y1;
end

(d) always @( posedge clk) begin

#5 y1 <= in; #5 y2 <= y1;
end

(e) always @( posedge clk) begin

y1 = #5 in;
y2 = #5 y1;
end

(f) always @( posedge clk) begin

y1 <= #5 in;
y2 <= #5 y1;
end

(g) always @( posedge clk)

y1 = in;
always @( posedge clk)

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y2 = y1;

(h) always @( posedge clk)

y1 <= in;
always @( posedge clk)
y2 <= y1;

(i) always @( posedge clk) #5 y1 = in;

always @( posedge clk) #5 y2 = y1;

(j) always @( posedge clk) #5 y1 <= in;

always @( posedge clk) #5 y2 <= y1;

(k) always @( posedge clk)

y1 = #5 in;
always @( posedge clk)
y2 = #5 y1;

(l) always @( posedge clk)

y1 <= #5 in;
always @( posedge clk) y2 <= #5 y1;

Q8. Assume state and next_state are `STOP at the first clock, what is state in the following code:
- At the 2nd clock?
- At the 3rd clock?
- At the 4th clock?
- At the 5th clock?

always @(posedge clk)

begin
case (state)
`STOP: next_state <= `GO;
`GO: next_state <= `STOP;
endcase
state <= next_state;
end

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Q9. Write a procedure for an adder (combinational logic) that assigns C the sum of A plus B with
a 7ns propagation delay.

Q10. Write the procedure(s) for a 4-bit wide shift register (positive edge triggered) of clock and
has a 4ns propagation delay.

Q11. Draw the hardware implemented by the following verilog codes:

(a)

module example5_3 (D, Clock, Q1, Q2);

input D, Clock;
output reg Q1, Q2;
always @(posedge Clock) begin
Q1=D;
Q2 = Q1;
end
endmodule

(b)

module example5_4 (D, Clock, Q1, Q2);

input D, Clock;
output reg Q1, Q2;
always @(posedge Clock) begin
Q1<=D;
Q2<=Q1;
end
endmodule

(c)

module example5_5 (x1, x2, x3, Clock, f, g);

input x1, x2, x3, Clock;
output reg f, g;
always @(posedge Clock) begin
f = x1 & x2; g = f | x3;
end
endmodule

(d)

module example5_6 (x1, x2, x3, Clock, f, g);

input x1, x2, x3, Clock;
output reg f, g;
always @(posedge Clock) begin
f < = x1 & x2; g < = f | x3;
end
endmodule

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Q12. Draw the RTL design of the following Verilog codes. “Simulate the circuit’s behavior by loading
the pattern 001 into the LFSR and then enabling the register to count. What is the counting sequence
for all?

a)
module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;
always @(posedge Clock) begin
if (L)
Q<=R;
else
Q < = {Q[2], Q[0]^Q[2], Q[1]};
end
endmodule

b)
module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output reg [0:2] Q;
always @(posedge Clock) begin
if (L)
Q<=R;
else
Q < = {Q[2], Q[0], Q[1]^Q[2]};
end
endmodule

c)

module lfsr (R, L, Clock, Q);

input [0:2] R;
input L, Clock;
output reg [0:2] Q;
always @(posedge Clock) begin
if (L)
Q<=R;
else
begin
Q[0] = Q[2];
Q[1] = Q[0]^Q[2];
Q[2] = Q[1];
end
end
endmodule

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d)

module lfsr (R, L, Clock, Q);

input [0:2] R;
input L, Clock;
output reg [0:2] Q;
always @(posedge Clock) begin
if (L)
Q<=R;
else begin
Q[0] = Q[2];
Q[1] = Q[0];
Q[2] = Q[1]^Q[2];
end
end
endmodule