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Theses and Dissertations Theses and Dissertations

12-13-2008

Differential relay model development and validation using real

time digital simulator
Vamsi Krishna Vijapurapu

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DIFFERENTIAL RELAY MODEL DEVELOPMENT AND VALIDATION USING

REAL TIME DIGITAL SIMULATOR

By

Vamsi Krishna Vijapurapu

A Thesis
Submitted to the Faculty of
Mississippi State University
in Partial Fulfillment of the Requirements
for the Degree of Master of Science
in Electrical Engineering
in the Department of Electrical and Computer Engineering

Mississippi State, Mississippi

December 2008
 Copyright by

Vamsi Krishna Vijapurapu

2008
 DIFFERENTIAL RELAY MODEL DEVELOPMENT AND VALIDATION USING

REAL TIME DIGITAL SIMULATOR

By

Vamsi Krishna Vijapurapu

Approved:

_________________________________ _________________________________
Noel N. Schulz Herbert Ginn
Professor of Electrical and Assistant Professor of Electrical and
Computer Engineering Computer Engineering.
(Director of Thesis) (Committee Member)

_________________________________ _________________________________
Anurag K. Srivastava James E. Fowler
Assistant Research Professor of Electrical Professor of Electrical and Computer
and Computer Engineering Engineering
(Committee Member) (Graduate Coordinator)

_________________________________
Sarah A. Rajala
Dean of College of Engineering
Name: Vamsi Krishna Vijapurapu

Date of Degree: December 10, 2008

Institution: Mississippi State University

Major Field: Electrical Engineering

Major Professor: Dr. Noel N. Schulz

Title of Study: DIFFERENTIAL RELAY MODEL DEVELOPMENT AND

VALIDATION USING REAL TIME DIGITAL SIMULATOR.

Pages in Study: 92

Candidate for Degree of Master of Science

The protection system in a shipboard power system plays a vital role in detecting

the fault conditions, isolating the faulted zone and preventing the fault propagation into

other vital sections onboard the ship. The protection system should be able to remove

faults and restore the service to all the vital loads rapidly. In order to design the

protection system, preliminary hardware-in-the-loop testing is done using bus differential

relay hardware and a Real Time Digital Simulator (RTDS). In this thesis work, based

upon the functionalities of the relay hardware the software differential relay model is

designed and simulated using the RSCAD Version 2.00 software suite and RTDS. The

software differential relay model developed in RSCAD was tested on a terrestrial power

system and a shipboard power system test case for various fault conditions, and its

functionalities are validated based upon the hardware-in-the-loop test results.

 DEDICATION

This thesis work is dedicated to my grandfather,

Vijapurapu Venkata Ramadas

ii
 ACKNOWLEDGMENTS

I would like to thank my major professor, Dr. Noel N. Schulz. Her understanding,

guidance, and encouragement, made this thesis work possible. Her enthusiasm and

willingness to help made my research life smooth and rewarding. I greatly appreciate Dr.

Herbert Ginn and Dr. Anurag K. Srivastava for their willingness to serve as my graduate

committee, and for their valuable suggestions. I would also like to thank Dr. Jimena L.

Bastos for her valuable support during my research period. I am very grateful to Ms.

Heather Meiklejohn of RTDS Inc. for helping me out in my simulations in RSCAD. I

gratefully acknowledge and appreciate the Office of Naval Research (ONR) for funding

this research work.

Finally I would like to thank my parents and friends for their support during my

academic career at Mississippi State University.

iii
 TABLE OF CONTENTS

DEDICATION ........................................................................................................... ii

ACKNOWLEDGMENTS ......................................................................................... iii

LIST OF TABLES ..................................................................................................... vii

LIST OF FIGURES ................................................................................................... viii

CHAPTER

I. INTRODUCTION ......................................................................................... 1

1.1 Introduction ........................................................................................ 1

1.2 Shipboard Power System Overview .................................................. 2
1.3 Protection System Overview.............................................................. 3
1.4 Thesis Objective................................................................................. 4
1.5 Thesis Organization ........................................................................... 5

II. BACKGROUND ........................................................................................... 7

2.1 Introduction ........................................................................................ 7

2.2 Shipboard Power System Characteristics .......................................... 8
2.3 Terrestrial Power System ................................................................... 9
2.4 Shipboard Protection System ............................................................. 10
2.4.1 Protective Relays ................................................................... 11
2.4.2 Current Differential Protection Scheme................................. 12
2.4.3 Selection of Protection Scheme ............................................. 14
2.5 Hardware-in-the-Loop (HIL) Test ..................................................... 14
2.5.1 Hardware-in-the-Loop Test Characteristics ........................... 15
2.5.2 Protective Relay Testing ........................................................ 16
2.5.2.1 Open Loop Protective Relay Testing ........................ 17
2.5.2.2 Closed Loop Protective Relay Testing ..................... 19
2.5.2.3 Software-in-the-loop Protective Relay Testing ........ 20
2.6 Summary ............................................................................................ 22

III. PROBLEM DESCRIPTION.......................................................................... 24

iv
 3.1 Need for Power System Protection .................................................... 24
3.2 Problem Statement ............................................................................. 25
3.3 Problem Approach ............................................................................. 26
3.4 Tools .................................................................................................. 28
3.4.1 Protective Relays ................................................................... 28
3.4.2 RSCAD Software Suite.......................................................... 28
3.4.3 Real Time Digital Simulator .................................................. 29
3.5 Summary ............................................................................................ 29

IV. BUS DIFFERENTIAL PROTECTION USING RTDS ................................ 30

4.1 Introduction ........................................................................................ 30

4.2 Bus Differential Relay (SEL-487B)................................................... 31
4.2.1 SEL-487B Bus Differential Relay Settings ........................... 32
4.3 Real Time Simulation ........................................................................ 36
4.4 Software Design Module ................................................................... 38
4.5 Power System Test Case .................................................................... 39
4.5.1 Eight-Bus Terrestrial Power System Test Case ..................... 39
4.5.2 4-Bus Shipboard Power System Test Case ............................ 42
4.6 Hardware Setup for HIL Test ............................................................ 45
4.7 Fault Inception Logic design in RSCAD ........................................... 49
4.8 Software Differential Relay Modeling in RSCAD ............................ 50
4.8.1 Percentage Differential Scheme ............................................ 51
4.8.2 Analog Signal Sampling Block.............................................. 52
4.8.3 Extraction of Operating Current ............................................ 53
4.8.4 Extraction of Restraining Current .......................................... 54
4.8.5 Dual Slope Percentage Differential Scheme .......................... 55
4.8.6 Circuit Breaker Control.......................................................... 55
4.9 Summary ............................................................................................ 56

V. SIMULATION & RESULTS ........................................................................ 57

5.1 Introduction ........................................................................................ 57

5.2 Hardware-in-the-loop Test using SEL-487B and RTDS ................... 58
5.2.1 HIL test using eight-bus power system test case ................... 58
5.2.2 HIL test using four bus shipboard power system test case .... 67
5.3 Software-in-the-loop testing using RTDS ......................................... 75
5.3.1 SIL testing of the eight bus power system test case............... 75
5.3.2 SIL testing of the four bus shipboard power system test
case ......................................................................................... 79
5.4 Comparison of Results ....................................................................... 83
5.5 Summary ............................................................................................ 84

v
 VI. CONCLUSIONS AND FUTURE WORK .................................................... 86

6.1 Conclusions ........................................................................................ 86

6.2 Future Work ....................................................................................... 88

REFERENCES .......................................................................................................... 90

vi
 LIST OF TABLES

5.1 Comparison of HIL & SIL test for an eight-bus power system test case ...... 82

5.2 Comparison of HIL & SIL test for an eight-bus power system test case ...... 83

vii
 LIST OF FIGURES

2.1 Basic Differential Protection Circuit [29] ...................................................... 12

2.2 Percentage Differential Protection Circuit [29] ............................................. 13

2.3 Open Loop Test Arrangement ....................................................................... 18

2.4 Closed Loop test Arrangement ...................................................................... 19

2.5 Software Differential Relay Logic for Bus Protection [30] ........................... 20

2.6 Software in the loop test Arrangement .......................................................... 22

4.1 SEL-487B Bus Differential Relay Hardware [32] ......................................... 31

4.2 Aliases for BRK-1 as defined in the relay settings [32] ................................ 33

4.3 Breaker inputs as defined in the relay settings [32] ....................................... 34

4.4 Bus zone definition as in the relay settings [32] ............................................ 34

4.5 CT and PT ratios as defined in the relay settings [32] ................................... 35

4.6 Differential element as defined in the relay settings [32] .............................. 36

4.7 MSU Real Time Digital Simulator hardware [28] ......................................... 37

4.8 Eight Bus Power System Test Case ............................................................... 40

4.9 Eight Bus power system test case in RSCAD ................................................ 40

4.10 4-bus shipboard power system test case ........................................................ 43

4.11 4-bus shipboard power system in RSCAD .................................................... 44

4.12 Digital to analog converter in RSCAD library .............................................. 46

viii
4.13 Hardware in the loop test arrangement .......................................................... 47

4.14 Digital input port, Word to bit convert block and Output Signals in
RSCAD .......................................................................................................... 48

4.15 Timer block, Bit to word convert block in RSCAD ...................................... 49

4.16 Fault inception logic in RSCAD .................................................................... 50

4.17 Software differential relay model layout ....................................................... 51

4.18 Analog sampling block in RSCAD ................................................................ 53

4.19 Discrete Fourier transform in RSCAD .......................................................... 54

5.1 Eight Bus power system test case in RSCAD ................................................ 58

5.2 CT1 current at no fault condition ................................................................... 59

5.3 CT2 current at no fault condition ................................................................... 60

5.4 Voltage at Bus 8 at no fault condition ........................................................... 60

5.5 Breaker Status at no fault condition ............................................................... 60

5.6 CT1 current after a LG fault in phase A ........................................................ 61

5.7 CT2 current after a LG fault in phase A ........................................................ 61

5.8 Circuit Breakers status after a LG fault in phase A ....................................... 61

5.9 Voltage at Bus 8 after a LG fault in phase A ................................................. 62

5.10 Trip signal after LG fault in phase A ............................................................. 62

5.11 CT1 current after a LLG fault on phases A&B.............................................. 63

5.12 CT2 current after a LLG fault on phases A & B............................................ 63

5.13 Voltage at Bus 8 after a LLG fault on phases A&B ...................................... 64

5.14 Circuit Breakers status after a LLG fault on phase A&B .............................. 64

5.15 Trip signals after a LLG fault on phases A&B .............................................. 64

ix
5.16 Trip signals after a LLLG fault on phases A, B&C ....................................... 65

5.17 Trip signals after a LLLG fault on phases A, B&C ....................................... 65

5.18 Circuit breakers status after a LLG fault on phases A, B&C......................... 65

5.19 Voltage at Bus 8 after a LLLG fault on phases A, B&C ............................... 66

5.20 Trip signals after a LLLG fault on phases A, B & C ..................................... 66

5.21 Four Bus shipboard power system in RSCAD .............................................. 67

5.22 CT1 current at no fault condition ................................................................... 68

5.23 CT2 current at no fault condition ................................................................... 68

5.24 Voltage at Bus 1 at no fault condition ........................................................... 68

5.25 Circuit Breakers status at no fault condition .................................................. 69

5.26 CT1 current after a LG fault on phase A ....................................................... 69

5.27 CT2 current after a LG fault on phase A ....................................................... 69

5.28 Voltage at Bus 1 after LG fault on phase A ................................................... 70

5.29 Circuit Breakers status after LG fault on phase A ......................................... 70

5.30 Trip signals after LG fault on phase A........................................................... 70

5.31 CT1 current after a LLG fault on phases A & B............................................ 71

5.32 CT2 current after a LLG fault on phases A & B............................................ 71

5.33 Voltage at Bus 1 after a LLG fault on phases A & B .................................... 71

5.34 Circuit breakers status after LLG fault on phases A & B .............................. 72

5.35 Trip signal after LLG fault on phases A & B ................................................ 72

5.36 CT1 current after a LLLG fault on phases A, B & C .................................... 73

5.37 CT2 current after a LLLG fault on phases A, B & C .................................... 73

5.38 Voltage at Bus 1 after a LLLG fault on phases A, B & C ............................. 73

x
5.39 Circuit breakers status after LLLG fault on phases A, B & C ....................... 73

5.40 Trip signal after LLLG fault on phases A, B & C ......................................... 74

5.41 CT1 current after a LG fault on phase A ....................................................... 75

5.42 CT2 current after a LG fault on phase A ....................................................... 76

5.43 Trip Signal after a LG fault on phase A ......................................................... 76

5.44 CT1 current after a LLG fault on phases A & B............................................ 77

5.45 CT2 current after a LLG fault on phases A & B............................................ 77

5.46 Trip Signals after a LLG fault on phases A & B ........................................... 78

5.47 CT1 current after a LLLG fault on phases A, B & C .................................... 78

5.48 CT2 current after a LLLG fault on phases A, B & C .................................... 79

5.49 Trip Signals after a LLLG fault on phases A, B & C .................................... 79

5.50 CT1 current after a LG fault on phase A ....................................................... 80

5.51 CT2 current after a LG fault on phase A ....................................................... 80

5.52 Trip Signal after a LG fault on phase A ......................................................... 80

5.53 CT1 current after a LLG fault on phases A & B............................................ 81

5.54 CT2 current after a LLG fault on phases A & B............................................ 81

5.55 Trip Signal after a LLG fault on phases A & B ............................................. 81

5.56 CT1 current after a LLLG fault on phases A, B & C .................................... 82

5.57 CT2 current after a LLLG fault on phases A, B & C .................................... 82

5.58 Trip Signal after a LLLG fault on phases A, B & C ...................................... 82

xi
 CHAPTER I

INTRODUCTION

1.1 Introduction

A shipboard power system needs to supply energy to various other important

components of the ship including the navigation system, communication system, and the

propulsion system. The other main challenge that should be overcome by the SPS is

maintaining continuity of service to all the subsystems especially when they have been

damaged. In order to maintain the continuity of service there should be a reliable and

efficient protection system installed on the SPS.

The protection system should be able to detect the fault, operate a protective

device to open the circuit breakers or other devices and hence isolate the faulted zone

until the fault is removed from the SPS and finally restore the system to its normal state.

During the isolation of the fault, there will be other un-faulted, yet critical parts of the

power system, which are to be supplied with power to increase the survivability of the

ship. Thus the restoration process should be done simultaneously after the isolation of a

portion of the power system.

1
1.2 Shipboard Power System Overview

A shipboard power system (SPS) mainly consists of various components

including generators, cable transmission systems, circuit breakers, protective devices,

switchboards, loads and buses which are all interconnected to form a complex and

intricate system [1]. The complexity of the SPS increases as the geographical area is

smaller compared to the terrestrial power system. The main reason behind the physical

distribution of the sections of the SPS all over the ship is to avoid the damage to an

accumulated section of the SPS. The layout of the components of the SPS over a ship is

necessary to assess the damage and the steps to be taken to restore the system [24]. For

the protection system to detect a fault and isolate the faulted zone before the fault

propagates and causes a failure catastrophically, the information regarding the component

layout on the ship is necessary. The SPS mainly comprises the following characteristics

[23],

i. Sets of three-phase gas turbine generator connected in ring configuration.

ii. The gas turbine generator sets are interconnected through bus tie circuit

breakers, which allow the flow of energy from one switchboard to the other.

iii. Loads on the SPS are mainly classified into vital and non-vital loads. The

power is available based upon the priority of the load. The propulsion motors

are one of the major vital loads on the SPS. For the vital loads the power is

available through either automatic bus transfers (ABTs) or manual bus

transfers (MBTs) [25].

iv. In the latest SPS models high impedance grounding is preferred.

2
 v. The circuit breakers are placed at various locations on the SPS to improve the

flexibility in isolating a faulted zone from the unfaulted portion of the SPS.

vi. The transmission cables are much shorter in length and have low impedance

values when compared to those in a terrestrial land based system.

vii. The SPS have larger dynamic loads relative to the generator size unlike in the

case of the terrestrial land based systems.

The imbalance between the generator capacity and the load demand of the

shipboard power system makes it vulnerable to a catastrophic failure even without a fault.

In order to avoid such conditions the balance between the generation and the load should

be maintained at all times. Apart from isolating the faulted zone from the unfaulted zone

of the power system, the protection system should also be able to stabilize the SPS.

Hence the protection system is one of the most important components aboard a shipboard

power system, which not only saves the SPS from major damage, but also increases the

chances of survivability in the battle conditions.

1.3 Protection System Overview

This thesis will focus on designing an efficient and reliable protection system,

which is capable of detecting faults, isolating the faulted zone and restoring the system to

its normal working state after clearing the fault. In order to design the protection system

preliminary hardware-in-the-loop tests have been done. The protective device used in this

thesis work is a bus differential relay. The main aim was to design the software bus

differential relay model, which consists of most of the functionalities of actual bus

differential relay hardware.

3
 The hardware-in-the-loop testing involves the actual relay hardware and the real

time digital simulator (RTDS) in the loop, based upon which the software differential

relay model has been designed using the RSCAD software suite. The SEL-487B bus

differential relay hardware was used for the hardware-in-the-loop testing. The software-

in-the-loop testing has been done using the software bus differential relay hardware

developed in the RSCAD software suite. Finally the relay model has been validated upon

comparison to the functionalities of the actual relay hardware and proved to be consistent

in detecting a fault, isolating the faulted zone by opening the circuit breakers and finally

reclosing the circuit breakers once the fault has been cleared. The validation process

involves the comparison of the software-in-the-loop test output with the hardware-in-the-

loop test output and also comparison of the functionalities of the software bus differential

relay model and the actual SEL-487B bus differential relay hardware.

1.4 Thesis Objective

In the present day shipboard power systems the protection system plays a major

role in detecting the fault and isolating the faulted zone from the unfaulted portion of the

SPS. In order to detect a fault and isolate the faulted zone before the fault propagates

deeper into the power system and cause more damage than expected, the protection

system should be very consistent in its operation. The differential relay is often used as a

protective device on the shipboard power system. The main purpose of the thesis was to

design a software differential relay model based upon the functionalities of the SEL-487B

bus differential relay hardware. A consistent detection of a fault, isolation of the faulted

4
zone and reclosing of the circuit were expected from the software differential relay

model.

In order to design the software bus differential relay model, preliminary

hardware-in-the-loop testing has been done using the SEL-487B bus differential relay

hardware and the RTDS system. The results of the hardware-in-the-loop testing were the

basis upon which the software differential relay model was built in the RSCAD software

suite. The software differential relay model uses the dual slope percentage differential

protection scheme to issue the trip signals to the circuit breakers based upon the type of

fault conditions. The relay model has been tested for various fault conditions and the

functions of detecting a fault, isolating the faulted zone and reclosing the circuit were

consistently performed. The hardware-in-the-loop tests were implemented on two test

cases including one terrestrial land based power system test case, and one shipboard

power system test case. Eventually the software relay model was also tested with the two

power system test cases. Finally comparing its output to the results of the HIL test has

validated the relay model.

1.5 Thesis Organization

The thesis is organized as described in this section. Chapter II of this thesis gives

a brief description of the background related to shipboard power systems, terrestrial

power systems, differential protection scheme, selection of the protection scheme and the

shipboard protection system, which involves open-loop testing, closed loop testing, and

software in the loop testing techniques. Chapter II also gives the application of the HIL

and SIL tests to the development of protection system for the shipboard power system.

5
The literature review is also illustrated in Chapter II. Chapter III of this thesis explains

the problem description, problem statement and the work that has been proposed to solve

the problem. Chapter IV is the most critical chapter of this thesis, which explains the

percentage differential protection scheme in detail and the way in which the hardware-in-

the-loop test was implemented with the help of the SEL-487B bus differential relay and

the Real Time Digital Simulator (RTDS). The step-by-step procedure involved in

designing the software bus differential relay model has been explained in this chapter.

The chapter will explain how the power system test case was interfaced to the hardware

relay and the way in which the zones of the power system were defined in the settings of

the hardware relay. Chapter V of this thesis work includes the results for different test

cases and the validation of the software relay model. Chapter VI provides the conclusions

for this thesis work and also illustrates the scope of future work.

6
 CHAPTER II

BACKGROUND

2.1 Introduction

This chapter gives a brief overview of the key topics related to the thesis subject.

The topology and characteristics of the shipboard power system (SPS) and terrestrial

power system are introduced based on the reviewed literature. The Hardware in the Loop

(HIL) testing technique and the importance of it in advanced system modeling and

simulations are briefly discussed. The tools used to successfully implement the hardware

in the loop testing have been presented in detail. The differential protective relay is one

of the important components of the shipboard power system protection topology. The

ways of protecting the SPS based upon the multi-zonal differential protection scheme is

discussed in this chapter. The differential protection scheme based upon the zone

selection is a possible protection solution to detect and isolate the faulted zones based

upon the differential current monitored by the current transformers. Obtaining real time

simulation results with the help of the Real Time Digital Simulator (RTDS) is briefly

discussed based upon the literature review.

7
2.2 Shipboard Power System Characteristics

The shipboard power system has multiple AC generator systems to electrify the

ship. Electrification and automation of the ship demands a very complex and efficient

topology. One of the main components of this complex topology is the protection system,

which not only should be efficient but also should be able to improve the survivability of

the ship system [1]. The shipboard power system transmits and distributes the power

through an ungrounded and intricate power network. The power is transmitted through

the cable. The shipboard power system is ungrounded, to maximize the continuity of

power supply and avoid unwanted power outages on the ship. The other main advantage

of having an ungrounded system is that the post fault current of a single-phase fault is

very low, which helps in maintaining the continuity of power even during a fault

condition. On the other hand the ungrounded power system on a ship is highly

susceptible to transient over-voltages, hence in the future ship system high impedance

grounding is preferred.

The power is mainly delivered with the help of AC generators, which generate the

AC power and AC transmission cables and distribution networks, which distribute the

power to other components of the system. The immediate alternative of power

generation, transmission and distribution is using the AC/DC converter, DC/AC inverters

and DC links. The typical voltage levels in a naval shipboard power system are 120V,

440V, 4.16kV and 13.8kV [23].

The shipboard power systems are small in size when compared to a terrestrial

power system, due to which the length of the transmission cables is drastically reduced.

Due to the smaller size of the shipboard power system, a fault may lie right next to a

8
generator, and can lead to a failure of the whole power system catastrophically. Hence the

protection system should be very efficient and should implement rapid isolation of the

faulted zone and thus protect the critical components from being damaged.

The shipboard power system model known, as the DD (X) model is comprised of

four 13.8kV generators, each coupled with a gas turbine operating at 60Hz and an exciter

operating at 8 kV. Two of the four generators are considered to be the Main generators

and are rated at 36 MVA and the other two are considered to be the auxiliary generators

are rated at 4 MVA, thus providing an overall capacity of 80 MVA. All the generators are

connected by a cable transmission system. The majority of the load is comprised of two

induction machines each operating at 4.16kV, which are considered to be the propulsion

motors of the ship [24].

2.3 Terrestrial Power System

The terrestrial power system is a normal land based power system, which plays a

major role in the electrification. An 8-bus terrestrial power system case has been used to

implement the hardware in the loop tests and also the software in the loop tests in this

thesis work. The terrestrial power systems are similar to the shipboard power systems, in

the sense of generation of power, transmission and distribution of power, protective

devices and the loads considered. The main difference however lies in the transmission of

power, which is done through overhead lines and cables in a terrestrial system, where as

is done only with the help of cables in a shipboard power system. The other main

difference is that the terrestrial systems are grounded, where as the shipboard power

systems are ungrounded, with the neutral floating. Also with respect to the smaller space

9
and lower requirements of power on the ship, the transformers are selected carefully

based upon their weight and size. The all-electric ship shipboard power system is still in

the development stages [24].

2.4 Shipboard Protection System

The complex and intricate shipboard power system demands an efficient and

reliable protection system [3]. The protection system can be classified into AC protection

and DC protection. The thesis work deals with the AC protection system. The fault can

occur in a power system due to numerous reasons including failure of the equipment,

damage in the insulation, physical component damage, high voltage surges, and

lightning. In order to protect the power system from various fault conditions, the

protection system topology should be intelligent and should rapidly isolate the faulted

zone to prevent a major power system failure.

The protection system should be able to detect a fault, and reduce its damage to

the minimum extent, as a fault cannot be totally eliminated. In the modern world, the

power systems have sufficient flexibility so that one or more components may be out of

service with minimal interruption of service. The faults result due to electrical,

mechanical and thermal failure or any combination of these. Some of the common fault

conditions for which the protection system should react are:

i. Three-phase (a-b-c, a-b-c-g)

ii. Phase-to-phase (a-b, b-c, c-a)

iii. Two-phase-to-ground (a-b-g, b-c-g, c-a-g)

iv. Phase-to-ground (a-g, b-g, c-g)

10
The other problem is with the open circuits, which occur frequently on power systems.

The widely used device is a protective relay, which is the core of this thesis work.

2.4.1 Protective Relays

Protective relays are small systems themselves which are capable of providing

reliable and efficient protection to power systems. The main function of a protective relay

is to detect faults and other intolerable conditions on the power system and trip one or

more circuit breakers, thus isolating the faulted zone. The protection system is comprised

of relays, currents transformers (CTs), voltage transformer (VT) and circuit breakers. All

of these four components of a protection system must function together.

Generally the relay protection is based upon the zones defined on a power system.

The relays are coordinated according to the zones. The power system is divided into

protective zones for generators, transformers, buses, transmission and distribution circuits

and motors. The location of the CT (current transformer) plays a major role in the

functioning of the protective relay. The CTs send the current from the power system to

the relay continuously, and as soon as a fault current is detected, the relay issues the trip

signal to the circuit breakers in the protective zone. The main challenge of a relay is to

maintain the service of the un-faulted components of the power system even after a

section is removed due to faults [5]. The hardware in the loop testing and software in the

loop testing in this thesis work consist of CTs, circuit breakers and the relays. Based upon

the protection scheme, when the relay logic conditions are met the relay issues a trip

signal or a reclose signal to the appropriate circuit breakers present in the power system

test case.

11
2.4.2 Current Differential Protection Scheme

The differential protection scheme has been used in this thesis work. The basic

differential protection circuit is as shown in the Figure 2.1 below,

Figure 2.1 Basic Differential Protection Circuit [29]

In the above Figure 2.1 the differential circuit draws current i1 and i2 from both

sides of the protected equipment through current transformers and are compared using a

differential logic. Under normal conditions the current on both sides i.e. i1 and i2 are

equal and hence no current flows through the current relay coil. In case there is a fault in

the protected zone, then the current i1 and i2 would not be the same, and difference

current will cause the relay to trip the circuit breakers in the power system. This scheme

of protection is generally known as the current differential protection scheme. The main

disadvantage of this scheme is if the current transformers are not identical, then current

keeps on flowing through the relay even under normal conditions without a fault. In order

to reduce this error caused by the current transformer, the percentage differential

protection scheme has been introduced. In the case of a percentage differential protection

scheme, the current drawn by the current transformers flows through a restraint coil,

12
which reduces the errors caused by the current transformers [29]. The percentage

differential protection scheme is as shown in the Figure 2.2 below.

Figure 2.2 Percentage Differential Protection Circuit [29]

In the above shown Figure 2.2 the OC is the operating coil and the RC is the restraint

coil. The current at the primary end of the current transformer is i1 and on the secondary

side of the current transformer is i2. The operating current in the circuit is given by

i1 − i 2 , which is a percentage of the average current flowing through the restraint coils in

the circuit shown above. The operating current is needed by the relay to issue the trip

signal and hence isolate the faulted zone. The operating coil current is given by,

i1 + i 2
i1 − i 2 ≥ k , where k is the ratio of operating current and restraint current [29].
2

The percentage differential protection scheme is used as the basis for the development of

the software relay model in this thesis work. The relays may sometimes fail to operate

when they are expected to hence a backup relay is always included in the protection

system. The backup relays can be right next to the main relays or can operate from a

remote location.

13
2.4.3 Selection of Protection Scheme

The main challenge lies in selecting the appropriate protection scheme for the

power system situation. There are various protection schemes like the overcurrent,

distance and differential. Each protection scheme has its own advantages and drawbacks.

In general the power system characteristics, line impedances and grounding techniques

are the factor based upon which a protection scheme is selected. In the case of a

shipboard power system the length of the cables is short, and hence the usage of distance

protection scheme is ruled out. Since there are multiple sources and loops in the

shipboard power systems, the overcurrent directional protection scheme can only be used

after compromises of speed by introducing an intentional delay and avoid over tripping.

Hence the overcurrent directional protection scheme is ruled out in the case of a

shipboard power system [23].

Finally the current differential protection scheme proves to be the most

appropriate protection scheme for a shipboard power system. The current differential

scheme draws current from two points on the system, and uses the difference to detect the

fault in the protected zone. The current differential protection scheme is therefore suitable

for the shipboard power system as it can be used to protect various zones of the power

system keeping in mind the small geographical distribution of the shipboard power

system [23].

2.5 Hardware-in-the-Loop (HIL) Test

Real Time simulations are widely used by various branches of engineering. The

real time simulations play a major role in the power system sector also. The main

14
advantage of the real time simulation is to observe the power system behavior in response

to transient conditions and other rapid and sudden changes in the power system. The

modeling and simulation in real time helps in improving the quality of the protection

system and also maintain the stability and continuity of the power system operation. The

real time simulations have been done in the forms of hardware in the loop testing and

software in the loop testing in this project. In the past to gain confidence on the protective

relays, the tests have been done based upon signal generation. But as the relays became

more sophisticated, nowadays the real time simulation is the tool being used to test the

relay and observe it reliability and efficiency especially when there is a fault on the

power system. Real time open loop testing and closed loop testing prove to be the

ultimate testing techniques for any protective device. The real time closed loop testing is

capable of [7],

i. Interacting with one or more protective devices.

ii. Interfacing the power system and the protective devices to find the exact

interaction.

iii. Increasing the efficiency of simulation.

One of the most important techniques, which falls under closed loop and open loop

testing, is the hardware-in-the-loop (HIL) testing technique.

2.5.1 Hardware-in-the-Loop Test Characteristics

The hardware-in-the-loop technology is one of the techniques used to analyze the

nonlinear and dynamic behavior of the physical device, and helps in building and

validating a model to control the physical devices [31]. The HIL simulation is being used

15
in the development and testing of complex real time systems. The main idea behind the

HIL simulation is to provide an effective platform to develop and test the real time

systems like a protective relay. The HIL simulation of the protective relay has been done

in this project work. The protective relay used to carry out the HIL simulation is a SEL-

487B bus differential relay manufactured by Schweitzer Engineering Laboratories Inc.

The HIL simulation must include electrical emulation of sensors and actuators for

the communication over an interface between the simulator and the physical device,

which is a protective relay in our case. There is also a control algorithm, which enables

the flow of signals through the sensors and the actuators in the protective system. In this

thesis work the simulator used is one of the most powerful and accurate simulators

available today. The simulator is known to be the Real Time Digital Simulator (RTDS)

developed by RTDS Inc. The Real Time Digital Simulator (RTDS) is an effective tool for

modeling and simulation of power and control systems [28]. A detailed description of the

RTDS working has been given in Chapter 4 of this thesis.

In a HIL simulation, the virtual power system is connected to the actual physical

devices. Authors in [27] presented experimental design for hardware in the loop test and

HIL tests have been used for testing electric machines in [21]. The basic functionality and

applications of the SEL-487B bus differential relay given in [26] were analyzed.

2.5.2 Protective Relay Testing

The hardware in the loop testing of the differential relay has been done

considering a power system test case and a particular bus, which is to be protected. In

addition to the hardware in the loop testing, a software differential model has been

16
designed which has the similar functionality of the hardware relay and can be used to

protect the bus in the protection zone. The main functions of software differential relay

model developed are:

• Obtain the measurement of the currents using current transformers. The current

transformers help in detecting the faulted current when a fault is injected at the

bus.

• Filter out the harmonics and noise from the current and also sample the current

into a fundamental component.

• Implement the dual slope percentage differential protection principle based upon

the fundamental components of the current sampled.

• Issue a trip signal to open the breakers in order to isolate the bus as soon as a fault

is injected and issue the reclose signals to the breakers as and when the fault is

cleared.

The overall research objective involves having a fault on the bus, detecting the

fault by filtering out the harmonics, applying the differential principle to clear the fault

and restoring the system to its normal condition. The open loop testing and the closed

loop testing techniques are explained in future sections. The modeling and simulation

was done using the RSCAD software suite and the RTDS hardware.

2.5.2.1 Open Loop Protective Relay Testing

The open loop testing is the preliminary stage of the closed loop testing in this

thesis work. In the case of an open loop test the main idea is to measure the response and

17
reduce the errors before forming a feedback loop and implementing the closed loop test.

In the case of a protective relay open loop testing, the power system is modeled and is

simulated in the RTDS. The currents drawn by the current transformers are sent to the

protective relay, which behaves as a controller. The responses of the relay are monitored

on its front panel. This is an open loop test because the signals from the hardware relay

are not fed back to the RTDS. The open loop test arrangement is as shown in Figure 2.3

below.

Figure 2.3 Open Loop Test Arrangement

As shown in the above figure, the terrestrial power system is simulated in the

RTDS and the currents, which are drawn by the CTs, are sent to the hardware controller,

which is a SEL-487B bus differential relay with the help of sensors. The response of the

relay is observed on its front panel. The faults are incepted on the power system and the

trip signals are observed on the front panel of the relay. The importance of the open loop

18
testing lies in reducing the errors of the responses and also helps to modify the controller

before conducting the closed loop test.

2.5.2.2 Closed Loop Protective Relay Testing

Once the open loop test has been done and the responses from the relay are

reliable, the closed loop test is implemented. In the closed loop testing the response

signals from the hardware controller, which is a SEL-487B bus differential relay are fed

back to the RTDS, and this enables the user to see the trip signals, and circuit breaker

status through the Real Time window present in the RSCAD software suite. The closed

loop hardware-in-the-loop test arrangement is as shown in the Figure 2.4 below.

Figure 2.4 Closed Loop test Arrangement

As shown in the above figure, the power system test case is simulated in the RTDS. The

current signals drawn by the current transformers are sent to the hardware controller

through the sensors and also the response signals from the hardware controller are fed

19
back to the RTDS through the actuators. The basic idea behind closed loop hardware-in-

the-loop testing is to observe the behavior of the protective relay when interfaced to the

RTDS and hence implement the real time simulation. Based upon the HIL simulation

results of the SEL-487B bus differential relay, its usage in the actual shipboard protection

system can be determined.

2.5.2.3 Software-in-the-loop Protective Relay Testing

The software in the loop testing is similar to the closed loop hardware in the loop

testing except for the SEL-487B bus differential relay hardware which is replaced by a

software differential relay model developed in the RSCAD software suite. The software

differential relay model is designed based upon the dual slop percentage differential

protection scheme. Figure 2.5 shows the dual slope differential protection logic based on

which the software differential relay model was developed in RSCAD.

Figure 2.5 Software Differential Relay Logic for Bus Protection [30]
20
In the above figure the I01 and I02 are the current inputs to the differential relay from the

current transformers present in the power system. The Digital Band Pass Filter (DBPF)

gives out the filtered differential and directional signals and the other path is towards the

fault detection logic. The filtered differential element block calculates the operating

current and the restraint current basing upon the filtered current I01CF and I02CF,

respectively. The directional element block determines the direction of the fault by

comparing the direction of current at the reference bus with all the currents at the buses in

the protected zone. The parameters FAULT1 and CON1 distinguish between an internal

fault and an external fault. The signal from the directional element (DE1F) and the

internal fault detector (FAULT1) are combined by an OR gate. The AND gate present in

the circuit combines the OR combination and the 87ST1, which is the sensitive

differential element. The parameter P87R1 coming out of the AND gate controls the

security timer, which in turn controls the final output 87R1 of the bus protection logic

circuit. The software-in-the-loop test arrangement is as shown in Figure 2.6 below.

21
Figure 2.6 Software in the loop test Arrangement

The software differential relay model does not have all the functionalities of the SEL-

487B bus differential relay. There is a good scope to improve the functionalities and

include the breaker failure protection function into the relay model in the future work.

The software differential relay model has been tested with the terrestrial power system

test case and gave out reliable results for different fault conditions. The shipboard power

system has also been tested with the software differential relay model using RTDS.

2.6 Summary

The characteristics of shipboard power systems were discussed in this chapter.

The differential protection scheme was illustrated briefly in this chapter. The background

of hardware-in-the-loop testing, its importance and the reason behind its increasing usage

has been discussed. The hardware-in-the-loop test technique has been discussed when

applied to a terrestrial power system. The open loop, closed loop and software-in-the-

loop techniques were briefly outlined with respect to the RTDS and the SEL-487B bus
22
differential relay hardware. The reason behind selecting the percentage differential

protection scheme and the logic circuit of the bus protection element was discussed with

the help of figures. The flexibility of the percentage differential protection scheme makes

it an obvious choice for protection the shipboard power system.

23
 CHAPTER III

PROBLEM DESCRIPTION

3.1 Need for Power System Protection

The shipboard power system is highly vulnerable to various kinds of fault conditions,

which need to be rectified before a catastrophe happens. In addition to the fault

conditions, there are other reasons due to which the power system components can be

severely affected. In order to avoid such damaging effects to the power system, the

protection system has to be designed such that it is very reliable and consistent. If the

intensity of the fault is very high, it may cause an unbalance in the load of the system or

might cause the collapse of the entire system. The unbalance in the load might affect the

efficiency of the generator and this might lead to the complete malfunction of the

generator. There are various ways of protecting the power system ranging from a fuse for

a small system to the circuit breakers and relays in the case of a large power system. The

method of protection should be selected appropriately based upon the power system

topology [25].

The protection system should be capable of removing the fault on the system and also

restore the system to its normal condition without much of a delay in time. The time

factor is very important because, the longer the fault stays on the system, the higher will

be the intensity of damage. Thus the selection and usage of the appropriate protection

24
system is required depending upon the type, location and intensity of fault. In order to

protect all the desired zones of the power system, the protection system should be able to

judge and co-ordinate among the zones based upon the priority of the components

affected. The protection system should try to restore the service to all the vital loads,

based upon the priority [25].

3.2 Problem Statement

The importance of protecting the shipboard power system is illustrated in the

previous section. As the size of the power system grows, it is favorable to use of a device,

which is compact, sensitive to faults and can detect a fault without any delay. The device,

which has the requisite capabilities, is a relay. The relay is a compact and powerful

device, which can be placed at various points of the power system in order to detect any

faulty conditions and take necessary action, which might be opening a circuit breaker and

in turn isolating the fault, or by sounding an alarm. Based upon the functionality there are

various kinds of relays like the protective relays, monitoring relays, reclosing relays,

regulating relays, auxiliary relays, and synchronizing relays.

This work mainly focuses on the protective relays, specifically the bus differential

relay. The differential relay uses the difference in current between two points on the

power system to trip and open the circuit breakers. Since a shipboard power system is

small in geographic distribution, the currents can be measured at various points on the

power system, and this justifies the usage of differential relays in the shipboard power

system protection. The differential protection scheme operates faster when compared to

the overcurrent and distance protection schemes.

25
 The bus is a very critical element of the power system [19], as it behaves as the

electrical node between transmission lines, generators, loads and other circuitry of the

power system. The fault on a bus is equivalent to many simultaneous faults and involved

a high current magnitude because of the concentration of supply circuits at the bus.

Therefore the faults at the bus should be cleared as soon as possible in order to limit the

damage to the equipment and stability of the system. The differential protection scheme

is the most sensitive and suitable for the protection of buses in the power system. The

main criterion of the differential protection is to see that the sum of the currents entering

and leaving a particular bus is zero unless there is a fault on the system. In a particular

zone of protection any fault on the system leads to a summation, which is not equal to

zero, and leads to a current out of the criterion called the differential current [30].

Based upon the differential current the relaying has to be designed, so that the bus

is protected before the differential current goes over the threshold value and damages the

system. In this work the bus differential protection scheme has been analyzed and

reinforced with hardware in the loop testing and software relay model testing.

3.3 Problem Approach

The main theme of the thesis is to design a protection system for the shipboard

power system. In order to attain this goal a combination of power and control systems is

necessary. Therefore the approach used was to develop the power system test cases and

the control systems in the RSCAD software suite [28]. The main power system test cases

used in this thesis were classified as a terrestrial power system test case and a shipboard

power system test case. The main idea behind considering a terrestrial power system and

26
a shipboard power system case was to conduct the hardware-in-the-loop and software-in-

the-loop tests, and observe the behavior of the differential relay based protection system

for a grounded system and an ungrounded system respectively. Also the terrestrial power

system test case and the shipboard power system test cases carry different topologies,

which helps in observing the consistency of the differential relay based protection system

in a better way. The power system test cases were designed using the library of

components present in the RSCAD software suite. The next step was to integrate the

power and the control systems and implement advanced simulation. The advanced

simulations mainly include the hardware-in-the-loop (HIL) testing and the software-in-

the-loop testing. In the case of the HIL testing the use of a physical device, which is a

protective relay in the case of this thesis is mandatory. The HIL testing is a widely used

simulation technique, where the behavior of the protective relay can be observed. On the

other hand the software-in-the-loop testing (SIL) does not involve any physical protective

relay hardware. Instead in the SIL test, the protective relay and its functionalities are

designed in RSCAD software suite, and the software model behaves as the software

controller.

The software protective relay model development was completely based upon the

functionalities of the actual SEL-487B bus differential relay hardware. The advantage of

developing a software protective relay model is that the simulations can be carried out

without the presence of the actual relay hardware. Additionally the main advantage lies in

the flexibility of the software relay model, i.e. new functionalities can be added to the

protective relay circuitry. In order to test for the consistency and efficiency of the

27
software relay model, the preliminary HIL tests were done using the RTDS and the SEL-

487B bus differential relay hardware.

3.4 Tools

This section summarizes the tools including the software modules and the

hardware modules that were used for the development of the software bus differential

relay model.

3.4.1 Protective Relays

In order to implement the HIL tests, the protective relay hardware was used. The

working of the digital protective relays is based upon the microprocessor technology. The

digital relays have the capability to communicate with the computer and also with one

another and thus co-ordinate themselves. The other main advantage of the digital relay is

that the relays can be set using particular software. For example the Schweitzer

Engineering Laboratories (SEL) relays can be set using the ACSELERATOR software

[32].

3.4.2 RSCAD Software Suite

The power system test cases and the software relay model were designed in the

RSCAD software suite. The RSCAD Version 2.00 software suite has an impressive

library of power and control system components, using which the power system test cases

have been designed.

28
3.4.3 Real Time Digital Simulator

The real time digital simulator is the hardware simulator used in this thesis work.

All the simulations were done using the RTDS. The RTDS can simulate a system at a

time step of 50 microseconds. The detailed description of the RTDS has been given in the

Chapter IV of this thesis.

3.5 Summary

The need for protecting the power system from faults, the importance of differential

protection, and the way in which the bus differential protection scheme is implemented

were presented in this chapter. The problem statement was also presented in detail.

29
 CHAPTER IV

BUS DIFFERENTIAL PROTECTION USING RTDS

4.1 Introduction

This chapter describes the bus differential protection scheme applied to two

different power system test cases including the eight-bus terrestrial power system test

case and the 4-bus shipboard power system test case. The main tool used to conduct the

hardware in the loop and the software in the loop tests is the Real Time Digital Simulator

[11]. The power system test cases are developed in RSCAD software suite and simulated

using the real time digital simulator (RTDS) hardware [10]. The hardware in the loop test

procedure has been described in detail in this chapter. Some of the main aspects of the

hardware in the loop testing like the interfacing between the relay hardware and the

RTDS have been highlighted. The software differential relay model was developed in the

RSCAD software suite based upon the percentage differential protection scheme. The

hardware in the loop testing and software in the loop testing have been done on the same

power system test cases so that the validation of the software differential relay model will

be easier.

30
4.2 Bus Differential Relay (SEL-487B)

The SEL-487B bus differential relay [32] can protect bus systems with up to 18

terminals (54 CTs) and six protection zones. In order to improve the efficiency of

protection the six zones of the power system can be defined and the relay can be

coordinated accordingly. The use of a differential relay increases the security and

improves the speed of fault detection. The SEL-487B relay can be set based upon the

power system characteristics through the ACSELERATOR software. The

ACSELERATOR software helps in defining the zones of the power system and

coordinating the protection scheme for the power system in consideration. The hardware

SEL-487B bus differential relay is as shown in the Figure 4.1 below.

Figure 4.1 SEL-487B Bus Differential Relay Hardware [32]

Some of the key features of the relay include [32],

a. The effects of CT saturation are reduced by the SEL-487B bus differential relay

circuitry, hence preventing improper tripping issues during external fault

conditions. The importance of this feature lies in the prevention of operation delay

of the relay during faulted conditions.

31
 b. The SEL-487B bus differential can be easily set using the SEL-ACSELERATOR

software based upon the topology of the power system test case. The protection

logic can be defined based upon the SELOGIC® control equations described in

detail in the instruction manual. The relay setting involves creating the database

file, defining the zones of the power system and framing the protection logic

equations.

c. The relay provides a detailed event report of its response to a fault condition, and

the front panel LED’s display the trip signals and the breaker status. The relay

continuously monitors the currents measured by the current transformers present

in the power system test case.

d. The other good feature of the SEL-487B bus differential relay is the scope to

define the zones of the power system test case. By defining the zones of the power

system the improper relay operation can be eliminated. In this way the relay reacts

only to faults in its zone of operation.

4.2.1 SEL-487B Bus Differential Relay Settings

The SEL-487B bus differential relay is set using the ACSELERATOR software

developed by the Schweitzer Engineering Laboratories Inc. Using this software any SEL

relay can be set provided the relay database is available. The settings of the relay were

decided based upon the power system test cases topologies discussed in the section 4.5 in

this chapter.

The parameters, which were defined in the settings of the SEL-487B bus

differential relay, were the zones of protection, the pickup values of the relay and the

32
current transformer ratio. The zones of protection are defined based upon the number of

circuit breakers and their position in the power system test case. Based upon the number

of breakers present in the power system test case the aliases are defined in the relay

settings. The CT ratios were decided based upon the current flowing through the

transmission lines, and the capacity of the SEL-487B bus differential relay hardware. The

aliases simply assign a particular name for the circuit breakers in each phase of the power

system test case. The renaming is based upon the names of the input ports of the relay

hardware. For example the aliases assigning the three phases of circuit breaker BRK1 are

as shown in the Figure 4.2.

Figure 4.2 Aliases for BRK-1 as defined in the relay settings [32]

The six current signals drawn by the current transformers in the power system test case

IBUR1A, IBUR1B, IBUR1C, IBUR2A, IBUR2B, IBUR2C are read by the relay

hardware through the breaker inputs setting as shown in Figure 4.3 below.

33
Figure 4.3 Breaker inputs as defined in the relay settings [32]

The bus zones are defined based upon the number of circuit breakers and their position in

the power system test case. As shown in Figure 4.4 below each zone is defined with

respect to the circuit breaker phase. This is a good feature of the SEL-487B bus

differential relay. It enables the multi-zonal bus protection scheme where we can define

specific zones and co-ordinate the relay accordingly.

Figure 4.4 Bus zone definition as in the relay settings [32]

34
The current transformer and potential transformer ratios are defined in the relay settings

file as shown in the Figure 4.5 below.

Figure 4.5 CT and PT ratios as defined in the relay settings [32]

The differential element parameters are defined in the relay settings file as shown in the

Figure 4.6 below. The pick up value of the relay hardware is defined through the O87P

restrained differential pickup parameter in the settings.

35
Figure 4.6 Differential element as defined in the relay settings [32]

4.3 Real Time Simulation

The importance of using real time simulation increases when it comes to

observing the dynamic behavior of a system. The real time simulation is of paramount

importance when the behavior of a power system is to be studied under transient

conditions and under dynamically changing conditions. There is a need to simulate

different fault conditions on a power system in order to observe the reliability of the

protection system being used. By simulating the fault conditions in real time improves the

accuracy of observations, as the simulations would be closer to the real world. This helps

in improving the protection strategy and also the protective system models [9]. The

RTDS simulator is one such tool to model and simulate the real time simulations of

power and control systems [8].

The RTDS uses a custom parallel processing hardware architecture, which takes

place in units called racks. The RTDS consists of various cards including Triple

Processor Cards (3PC), Giga Processor Cards (GPC), and Twelve Channel Analog

36
Output Card (DDAC) etc. The 3PC card can be used to model the power system test case.

There are three analog devices called the ADSP21062 (SHARC) digital signal processors

(DSP) in each 3PC card present in the RTDS hardware [28]. The 3PC cards provide the

output analog channels, which can be used to connect external equipment and conduct the

hardware in the loop testing.

Each of the Triple Processor Card (3PC) cards contains three SHARC digital

signal processors ADSP21062, 24 analog output channels that can output ±10 Volts peak,

two 16 bit digital input channels of 5 Volts, and two 16-bit digital output channels of 5

Volts [28].

The Giga Processor Card (GPC) is another component of the RTDS with

powerful computational capacity. The GPC can be used to find the overall network

solution and to do this it uses two IBM Power PC 750GX RISC processors each

operating at 1GHz [28]. The RTDS hardware is as shown in Figure 4.7 below,

Figure 4.7 MSU Real Time Digital Simulator hardware [28]

37
As seen in the above figure, the racks are placed on the front panel of the RTDS

hardware. The digital input/output port on the front panel allows the feedback signals

from the relay hardware to be connected to the RTDS hardware.

4.4 Software Design Module

The RSCAD software suite employs an advanced and easy to use graphical user

interface. The software is comprised of several modules, which enable the user to design,

simulate and analyze the simulation output. The users can model the system using the

components present in the power and control system library and simulate it using the

Real Time Digital Simulator after compilation. The file manager window in the RSCAD

has ‘Draft’, ‘Runtime’, ‘Multiplot’, ‘Cable’, ‘T-Line, ‘Help’, ‘Convert’ and ‘Manuals’

menus. The power system modeling is done through the ‘Draft’ option in RSCAD, where

the requisite components can be modeled using a drag and drop interface provided. The

transmission lines present in the power system test case have been modeled using the ‘T-

Line’ option. Once the model is compiled without any errors, the simulation results can

be observed through the ‘Runtime’ option. The RSCAD software is an excellent

graphical user interface through which the parameters of the power system components

can be defined to the extreme inner detail. The RSCAD software suite also enables the

user to prioritize the components, so that the processor usage is distributed properly

without overloading a particular processor [28].

38
4.5 Power System Test Case

The power system test cases used in the hardware in the loop testing were been

developed in RSCAD. The components present in the power system test cases were

acquired from the RSCAD library.

4.5.1 Eight-Bus Terrestrial Power System Test Case

The power system test case’s specifications are as listed below,

• 230 kV AC Source

• 230 kV (Δ-Y) Transformer

• Transmission Lines of 100 km distance

• 1200 MVA 15 kV Synchronous Machine with a base frequency of 60 Hz

• Governor Mechanism with base frequency of 60 Hz.

• Current Transformers CT-1 and CT-2 of turns ratio 300 respectively.

The eight bus power system test case one-line diagram is as shown in the Figure 4.8

below. The one line diagram displays the basic outline basing upon which the eight bus

power system was designed in the RSCAD software suite.

39
Figure 4.8 Eight Bus Power System Test Case

The power system test case developed in RSCAD is shown in Figure 4.9 below.

The above listed components are prioritized to various processors present in the RTDS.

This prioritizing prevents the processors from getting overloaded.

Figure 4.9 Eight Bus power system test case in RSCAD

40
 There are eight buses in the power system test, and the Bus 8 is protected by the

SEL-487B bus differential relay in the hardware in the loop testing. In the case of the

software in the loop testing, the software differential relay model developed in RSCAD

protects Bus 8.

The faults are incepted by the fault control logic at Bus 8 of the power system test

case. The current transformers namely, CT1 and CT2, draw the currents continuously and

send them to the hardware interface block present in the model. In this power system test

case the breakers, BRK1 and BRK2, receive the signals from the circuit breaker control

logic present in the SEL-487B bus differential relay hardware. With respect to the

practical applications of the differential relay, the relay is set to open both the breakers at

the same time without any delay between them.

The primary current signals are denoted as IBRK1A, IBRK1B, and IBRK1C for

BRK1, and IBRK2A, IBRK2B and IBRK2C for BRK2, respectively. The burden current

signal names are denoted as IBUR1A, IBUR1B, IBUR1C for CT1, and IBUR2A,

IBUR2B and IBUR2C for CT2, respectively. These burden current signals are used to

design the fault control logic, which is described later in this chapter. The main challenge

in interfacing different components in the RSCAD software suite is while settings the

priorities of each component based upon the number of 3PC processors available on a

particular rack.

41
4.5.2 4-Bus Shipboard Power System Test Case

The shipboard power system test case’s specifications are as listed below,

• Two generators of 13.8kV, 36MVA and 60Hz frequency.

• Two generators of 13.8kV, 4MVA and 60Hz frequency.

• Transmission is done through cable system.

• Two 4.16kV, 60Hz induction motor loads.

• Gas Governor Turbine Mechanism with base frequency of 60 Hz.

• Two Resistive Loads of 50 Ohms each.

The one-line diagram of the 4-bus shipboard power system test case is given in

Figure 4.10 below. The 4-bus shipboard power system was designed in RSCAD software

suite. Bus 1 as shown in the Figure 4.10 is an artificial bus, which was inserted into the

power system test case to conduct the hardware-in-the-loop and software-in-the-loop tests

using the RTDS. The cable transmission system present in the RSCAD software suite

needs more than 2 racks to compile. Hence a pi-section transmission line has been used

instead of the cable system while designing the 4-bus shipboard power system test case.

The 4-bus shipboard power system test case has been developed in the RSCAD

software suite. The parameters were defined based upon the DD (X) notional shipboard

power system test case [24]. The pi-section transmission line system is preferred for

smaller sized power system test cases.

42
Figure 4.10 4-bus shipboard power system test case

The shipboard power system shown in Figure 4.11 below is much smaller than the

previous Eight-Bus power system terrestrial test case described. In this power system test

case the Bus 1 is protected by the SEL-487B bus differential relay hardware. The faults

are incepted by the fault control logic at Bus 1 of the power system test case.

43
Figure 4.11 4-bus shipboard power system in RSCAD

The current transformers, namely CT1 and CT2, measure the currents

continuously and send them to the hardware interface block present in the model. As

described in section 4.5.1, the breakers BRK1 and BRK2 receive the signals from the

circuit breaker control logic present in the SEL-487B bus differential relay hardware and

both the breakers are opened at the same time without any delay with respect to the

practical applications of the differential relay. The primary current signals are denoted as

IBRK1A, IBRK1B, and IBRK1C for BRK1, and IBRK2A, IBRK2B and IBRK2C for

BRK2, respectively. The burden current signal names are denoted as IBUR1A, IBUR1B,

and IBUR1C for CT1, and IBUR2A, IBUR2B and IBUR2C for CT2, respectively. The

44
fault control logic remains the same for either of the power system test cases described in

the previous section 4.5.1 and this section.

4.6 Hardware Setup for HIL Test

Hardware in the loop testing technology is one of the techniques used to

understand the nonlinear and dynamic behavior of the physical device, and helps in

building and validating a model to control the physical devices. In a HIL simulation, the

virtual power system is connected to the actual physical devices [12].

The hardware interface block is designed in RSCAD, which allows the connection

between the SEL-487B bus differential relay and the RTDS interface. The currents

measured by the current transformers present in the power system model being simulated

in RTDS are sent to the hardware relay. The feedback connection from the hardware

relay to the front panel of the RTDS is made to send the trip and reclose signals, which

can be seen in the RSCAD runtime window. The currents sent to the hardware relay are

continuously monitored and updated. The digital current signals from the RTDS are

amplified and fed to the hardware relay. The amplification of currents helps in simulating

a real time environment [15].

The SEL-487B bus differential relay is set to issue trip signals to the circuit

breakers present in the power system model being simulated in RTDS. The relay is set

using the ACSELERATOR software. Some of the settings include the CT ratio and the

power system zone definition. The zone definition is done based upon the position of the

circuit breakers in the power system test case [16].

45
 The digital to analog converter component present in the RSCAD is used to send

the currents measured by the CTs to the protective relay equipment. The currents

measured by the CT1 are named as IBUR1A, IBUR1B and IBUR1C, where as the

currents measured by the CT2 are named as IBUR2A, IBUR2B and IBUR2C,

respectively. The digital to analog converter (DAC) can be seen in the Figure 4.12 below.

Figure 4.12 Digital to analog converter in RSCAD library

The DDAC component, as it is called in the RSCAD library, sends the input

signals to DDAC high precision analog output board. The DDAC board is a 12-channel

component of the RTDS hardware. The DDAC takes in REAL input signals. The

component converts the input signals and scales them to 16-bit and writes them to the

DDAC card via the optical port of the RTDS hardware. The DDAC gives an output in the

range of ±10 V.

46
 The current signals are constantly sent to the protective relay through the DDAC.

The signals from the RTDS are connected through the back panel to the SEL-487B relay

hardware. The relay monitors the current signals and based upon its protective logic

issues a trip signal when there is a fault condition at the system bus. This trip signal from

the relay is sent to the digital input port present on the front panel of the RTDS hardware.

The trip and reclose signals are sent from the relay hardware through the cables

connected to the front panel (input port) of the RTDS, thus completing the hardware in

the loop physically. The hardware in the loop test arrangement of the SEL-487B bus

differential relay and the RTDS is as shown in the Figure 4.13 below.

Figure 4.13 Hardware in the loop test arrangement

47
 Eventually the 16 bit data is read through the digital input port. Only the 3PC

processors A and B access the digital input port. The digital input port reads the 16 bit

data and returns an INTEGER. In order to further process this INTEGER word, there is a

word to bit conversion block, which converts the INTEGER word to multiple logical

signals. In the present HIL test case, the word to bit convert block outputs six signals

namely, TRIP1A, TRIP1B, TRIP1C, REC1A, REC1B, and REC1C, which are the trip

and reclose signals of phases A, B and C, respectively. The digital input port, word to bit

convert block and the output trip and reclose signals are shown in the Figure 4.14 below.

Figure 4.14 Digital input port, Word to bit convert block and Output Signals in RSCAD

The pickup and drop off times are defined using the Timer block present in the

RSCAD library. The pickup and drop off times are 0.05 seconds (3 Samples),

respectively. The timer block outputs three signals namely BRK10A, BRK10B and

48
BRK10C, which are signals to open or reclose the circuit breakers present in the system.

But the circuit breakers take a single signal to open or relcose so the three signals from

the timer block shown in Figure 4.15 should be combined into a single word i.e.

BRK10C. The BRK10C issues the open and reclose signals to the circuit breakers in the

power system test case.

Figure 4.15 Timer block, Bit to word convert block in RSCAD

4.7 Fault Inception Logic design in RSCAD

The fault inception logic shown in Figure 4.16 was designed to incept single line

to ground, double line to ground and triple line to ground faults at the bus, which is

protected by the relay hardware. The inception of the faults at the protected bus is based

upon the node voltages at the bus. The fault inception logic is a critical part of the

hardware in the loop testing, because it enables the inception of the fault, which is

eventually detected by the relay hardware. The fault inception logic considers the node

voltage at the protected bus namely N22 as the reference signal. As soon as the FLT

button is pressed, the raising edge detector sends out a signal carrying the value ‘1’ which

initiates the fault sequence. The point on the wave and the duration of the fault can be
49
varied using the POW and FDUR sliders, respectively. The three switches FA, FB and

FC are used to select the phase on which the fault is to be incepted. The final signal out of

the logic i.e. FAULT is sent to the fault inception block present at the protected bus in the

power system test case.

Figure 4.16 Fault inception logic in RSCAD

4.8 Software Differential Relay Modeling in RSCAD

The software bus differential relay model designed in RSCAD replaces the actual

SEL-487B bus differential relay hardware in the setup. The software bus differential

relay model enables software in the loop testing using RTDS. The software differential

model was designed based upon the percentage differential protection scheme. The

Figure 4.17 below shows the blocks involved in the design of the software differential

relay model. Each of the blocks are explained in detail in the sections below.

50
Figure 4.17 Software differential relay model layout

4.8.1. Percentage Differential Scheme

The main idea behind the differential protection is that the sum of all the current

flowing into a differential relay should be equal to the sum of all the current flowing out

of the differential relay. The basic two winding differential relay circuit comprises two

current transformers, and an operate coil. The current transformers draw the currents

from the line, step them down and send them to the operate coil. When there is no fault

on the system under normal conditions the current flowing through the operate coil will

be approximately zero, where as in case the system is faulted, the current flowing through

the operate coil will be enough to operate the relay. Eventually a signal will be sent from

the relay to isolate the faulted zone of the power system.

In the case of percentage differential protection scheme there is a restraint coil, for

each current transformer present in the power system. In this type of differential relay

scheme for the relay to operate the operate coil should overcome the restraining force of

the restraint coil present in the circuit under no fault conditions as well as faulted

conditions on the power system. The percentage of the current in the restraint coil is

directly related to the operating current of the relay. For instance if the restraint current is

51
10A, then the operating current required to operate a 25% percentage differential relay

would be 2.5A.

4.8.2. Analog Signal Sampling Block

The analog signal sampling plays a major role when it comes to operating the

digital relays. The analog signal is sampled at a rate of 5.76 kHz or 96 samples per cycle

for a 60 Hz frequency base. The sampling is based upon the protection cycle considered

for the power system test case. The software differential relay model developed in

RSCAD has a protection cycle of eight times per cycle. Therefore the data is down

sampled at a rate of 0.480 kHz i.e. eight times per cycle. Each current drawn by the

current transformer should be sampled. In the present power system test case each of the

CTs draw three currents each, therefore all the six signals should be down sampled at a

rate of 0.480 kHz. The currents drawn by CT1, IBUR1A, IBUR1B and IBUR1C, are

sampled at 96 samples per cycle and then down sampled to 8 times per cycle. The analog

sampling block designed in RSCAD is shown in the Figure 4.18 below.

52
Figure 4.18 Analog sampling block in RSCAD

The resulting sampled quantities are named as IAD1, IBD1 and ICD1 respectively

as shown in the above figure. The currents drawn by CT2 are also sampled in the similar

manner resulting in IAD2, IBD2 and ICD2, respectively.

4.8.3. Extraction of Operating Current

The sampled data from the current transformers described in the previous section

is used to create the operating current for each phase. For instance in the case of phase A

the sampled data components IAD1 and IAD2 are added using a summing junction. The

operate current in this case if the vector sum of IAD1 and IAD2. In the normal operation

the magnitudes of IAD1 and IAD2 are equal, but they are 180 degrees apart in phase. The

operate current is given by, I o

= I A
− I B , where I A
is IAD1 and I B
is IAD2 in the

case of phase A. Eventually a full cycle DFT (Discrete Fourier Transform) was used to

53
extract the fundamental quantities of the operating current. In order to do this for each

phase the RAMP block supplies the phase angle continuously to the DFT. The DFT takes

in the magnitude and phase of the current component in each phase to give out the

fundamental components. The DFT used to extract the fundamental component as shown

in Figure 4.19 below takes the magnitude of the signal as IN and angle as PHASE and

gives out the fundamental component.

Figure 4.19 Discrete Fourier transform in RSCAD

4.8.4. Extraction of Restraining Current

The restraining currents flowing through the restraint coils present in the test case

are extracted with the help of the DFT. The DFT is used to extract the fundamental real

and imaginary components for each phase signal sampled down earlier. Using a complex

operator the magnitude of each signal is found based upon the real and imaginary

components for each phase. Summing the magnitudes and dividing them by the number

of current transformers present in the system obtain the restraint current. Therefore the

I + IB
operating current in this case would be, IR = A

2
, where I A
is IAD1 and I B
is

54
IAD2 when the phase A is taken into consideration. The resulting restraint currents are

IAR, IBR and ICR for A, B and C phases, respectively.

4.8.5. Dual Slope Percentage Differential Scheme

The dual slope percentage differential scheme is one of the widely used schemes

for differential relay protection. The dual slope percentage differential characteristic

includes the operating current magnitude, the restraining current magnitude and the relay

setting values. The logic designed in RSCAD for the dual slope percentage differential

protection scheme compares the fundamental current to the minimum operating current

setting defined in the relay settings. For the relay to operate the fault current should be

above the operating current. The dual slope percentage logic compares the fundamental

current to the restraint current value characterized by the necessary relay slope setting.

When the two comparisons fall in the trip zone there is an AND gate which gives out a

binary value, which is in turn finally compared to the high set current setting and issues

the trip signal to the hardware relay. The same logic is designed for each phase of the

power system test case. All the comparisons are done using the If-Else logic block

present in the RSCAD library.

4.8.6. Circuit Breaker Control

The basic setting for the relay is to open both the breakers BRK1 and BRK2 in the

power system test case as soon as a fault is applied in any phase. The relay will open the

breakers no matter which phase is faulted. The circuit breaker control uses a simple OR

gate to issue the binary signal ‘1’ which operates the relay eventually.

55
4.9 Summary

The concepts of bus differential protection are explained in detail with respect to

the power system test cases developed in RSCAD. The importance of hardware in the

loop testing grows when there is a need to test a physical device before putting it into use

in the real world. The hardware in the loop testing not only improves the efficiency of the

physical device, but also helps in improving the control system to control the device.

56
 CHAPTER V

SIMULATION & RESULTS

5.1 Introduction

The hardware-in-the-loop tests were implemented on two-power system test cases

designed in RSCAD software suite. The test case 1 is an eight-bus terrestrial power

system test case and the test case 2 is a four-bus shipboard power system test case, both

developed using the RSCAD software suite. The HIL test was implemented successfully

for both power system test cases. Eventually the software in the loop test was

implemented based upon the software bus differential relay model designed in RSCAD,

which uses the dual slope percentage differential protection scheme. The HIL test

technique was explained in detail in the Chapter IV. The basic design and the working of

the software bus differential were also described in Chapter IV. The relay settings for the

two power system test cases were described in Chapter IV of this thesis work. The

settings were based upon the current flowing through the transmission lines of the power

system test cases. Some important results with respect to the HIL test and the SIL test

will be presented in this chapter.

57
5.2 Hardware-in-the-loop Test using SEL-487B and RTDS

5.2.1 HIL test using eight-bus power system test case

The eight-bus terrestrial power system model was designed using the RSCAD

software suite and the specifications were illustrated in the section 4.5.1 in the Chapter IV

of this thesis work. The faults were placed on bus 8, which lies at the 50% point of the

transmission line. The eight-bus power system test case is as shown in the Figure 5.1

below.

Figure 5.1 Eight Bus power system test case in RSCAD

Bus 8 as shown in the above Figure 5.1 is protected by the SEL-487B bus

differential relay hardware. Various fault conditions are incepted at the Bus 8 through the

fault inception block included in the design. As soon as the relay detects the fault, the

relay settings make both the breakers BRK1 and BRK2 to open and isolate the bus until

the fault is cleared. The hardware-in-the-loop test implemented on the SEL-487B bus

differential hardware does not include reclosing of the breakers. The breakers are to be

closed manually after the fault is cleared. Therefore in the HIL test results with respect to
58
the eight-bus power system model, we can only observe the trip signals for various fault

conditions. The relay will open both the breakers as soon as a fault is detected. The

hardware interface between the power system and the relay hardware has been described

in section 4.6 in Chapter IV.

The hardware-in-the-loop testing of the eight-bus power system test case involves

simulating the power system test case in the RTDS and interfacing the RTDS to the

actual SEL-487B bus differential relay hardware. The currents drawn by the current

transformers, CT1 and CT2 as shown in the Figure 5.1, are sent to the relay hardware

through this interface. The faults are incepted at the protected Bus 8 through the fault

inception block. The relay issues a trip signal as soon as it detects a fault at Bus 8. The

CT ratio used for CT1 and CT2 is 300 turns. The HIL test technique has been explained

in detail in Chapter IV. The HIL test results of the eight-bus power system test case are as

presented for the conditions when there is no fault and when there is a fault incepted at

the protected bus. The figures below show the current, voltage and circuit breakers status

when there is no fault applied on the eight-bus power system test case at the protected

bus.

Figure 5.2 CT1 current at no fault condition

59
Figure 5.3 CT2 current at no fault condition

Figure 5.4 Voltage at Bus 8 at no fault condition

Figure 5.5 Breaker Status at no fault condition

In the above figures 5.2, 5.3 and 5.4 it can be seen that the peak-to-peak current

drawn by the CT1 and CT2 is 5A and the magnitude of voltage at Bus 8 is 186 kV,

respectively. Figure 5.5 shows the circuit breakers, status at no fault condition. If the

lights are yellow in color, it indicates that the circuit breakers are closed. In case the

circuit breakers are opened the lights turn to dark grey color.

Eventually single line to ground, double line to ground and triple line to ground

faults are incepted at the Bus 8 of the power system test case. The figures below show the
60
current, voltage, circuit breakers status, and trip signals when a single line to ground fault

is incepted on the phase A at the Bus 8 of the power system test case.

Figure 5.6 CT1 current after a LG fault in phase A

Figure 5.7 CT2 current after a LG fault in phase A

Figure 5.8 Circuit Breakers status after a LG fault in phase A

61
Figure 5.9 Voltage at Bus 8 after a LG fault in phase A

Figure 5.10 Trip signal after LG fault in phase A

From the above Figures 5.6 and 5.7 it can be noticed that the CT1 and CT2 show

the fault current when a fault is incepted in the phase A at Bus 8. The fault current

magnitude is approximately 13A. In Figure 5.10 the trip signal shifts from binary ‘0’ to

‘1’ in the phase A as soon as a fault is incepted. The main point to be noted here is that

the SEL-487B bus differential relay does not reclose the circuit breakers. Therefore the

62
circuit breakers need to be closed manually. The same behavior was observed in the case

of single line to ground faults on phases B and C, respectively.

The figures below show the current, voltage, circuit breakers status, and trip

signals when a double line to ground fault is incepted on the phases A and B at the Bus 8

of the power system test case.

Figure 5.11 CT1 current after a LLG fault on phases A&B

Figure 5.12 CT2 current after a LLG fault on phases A & B

63
Figure 5.13 Voltage at Bus 8 after a LLG fault on phases A&B

Figure 5.14 Circuit Breakers status after a LLG fault on phase A&B

Figure 5.15 Trip signals after a LLG fault on phases A&B

64
 As shown in Figures 5.11 and 5.12 the CT1 and CT2 fault current magnitudes

approximately 21A as soon as a LLG fault is incepted on phases A and B. The trip signal

in Figure 5.15 shows the shifting from binary ‘0’ to ‘1’ in the phases A and B.

The figures below show the current, voltage, circuit breakers status, and trip

signals when a triple line to ground fault is incepted on the phases A, B and C at the Bus

8 of the power system test case.

Figure 5.16 Trip signals after a LLLG fault on phases A, B&C

Figure 5.17 Trip signals after a LLLG fault on phases A, B&C

Figure 5.18 Circuit breakers status after a LLG fault on phases A, B&C

65
Figure 5.19 Voltage at Bus 8 after a LLLG fault on phases A, B&C

Figure 5.20 Trip signals after a LLLG fault on phases A, B & C

As shown in Figures 5.16 and 5.17 the CT1 and CT2 show fault currents of

approximately 38A in the case of LLLG fault on phases A, B and C. In Figure 5.20 the

trip signals shift from binary ‘0’ to binary ‘1’ in all three phases. In this way the HIL

testing of the eight-bus power system test case was successfully implemented using the

RTDS and the SEL-487B bus differential relay hardware.

66
5.2.2 HIL test using four bus shipboard power system test case

The four-bus shipboard power system model designed in RSCAD software suite

is based upon the notional shipboard power system model. The specifications of this

model were illustrated in the section 4.5.2 in the Chapter IV of this thesis work. The

faults were placed on the Bus 1, which is an artificial bus in the power system test case.

The four-bus power system test case is as shown in Figure 5.21 below,

Figure 5.21 Four Bus shipboard power system in RSCAD

The hardware interface between the power system and the relay hardware has

been described in section 4.6 in Chapter IV. The HIL test results for the four-bus

shipboard power system test case are presented in the following section.

67
 The figures below show the current, voltage, circuit breakers status, and trip

signals when there is no fault applied at the Bus 1 of the power system test case.

Figure 5.22 CT1 current at no fault condition

Figure 5.23 CT2 current at no fault condition

Figure 5.24 Voltage at Bus 1 at no fault condition

68
Figure 5.25 Circuit Breakers status at no fault condition

As shown in Figures 5.22 and 5.23 the CT1 and CT2 read a current of 0.75A

when there is no fault on the Bus 1 of the power system test case. The voltage as shown

in the Figure 5.24 has a magnitude of 11.5 kV.

The figures below show the current, voltage, circuit breakers status, and trip

signals when a single line to ground fault is incepted on the phase A at the Bus 1 of the

power system test case.

Figure 5.26 CT1 current after a LG fault on phase A

Figure 5.27 CT2 current after a LG fault on phase A

69
Figure 5.28 Voltage at Bus 1 after LG fault on phase A

Figure 5.29 Circuit Breakers status after LG fault on phase A

Figure 5.30 Trip signals after LG fault on phase A

70
 The figures below show the current, voltage, circuit breakers status, and trip

signals when double line to ground fault is incepted on the phases A and B at the Bus 1 of

the power system test case.

Figure 5.31 CT1 current after a LLG fault on phases A & B

Figure 5.32 CT2 current after a LLG fault on phases A & B

Figure 5.33 Voltage at Bus 1 after a LLG fault on phases A & B

71
Figure 5.34 Circuit breakers status after LLG fault on phases A & B

Figure 5.35 Trip signal after LLG fault on phases A & B

The figures below show the current, voltage, circuit breakers status, and trip

signals when triple line to ground fault is incepted on the phases A, B and C at the Bus 1

of the power system test case.

72
Figure 5.36 CT1 current after a LLLG fault on phases A, B & C

Figure 5.37 CT2 current after a LLLG fault on phases A, B & C

Figure 5.38 Voltage at Bus 1 after a LLLG fault on phases A, B & C

Figure 5.39 Circuit breakers status after LLLG fault on phases A, B & C

73
Figure 5.40 Trip signal after LLLG fault on phases A, B & C

The similar trip signal plots can be seen for the HIL testing of the four-bus

shipboard power system, as the SEL-487B bus differential relay setting was similar to

that of the HIL testing with the eight-bus power system test case. The above figures give

the HIL test results for the LG fault in phase A, LLG fault in phases A and B, and LLLG

fault in phases A, B and C respectively.

Eventually the software differential relay model, which was designed in the

RSCAD software suite as described in Chapter IV was looped with the eight-bus

terrestrial power system and the four-bus shipboard power system and tested for various

fault conditions. The plots of the software-in-the-loop test are presented in the following

section and the results are compared, therefore validating the software differential model.

74
5.3 Software-in-the-loop testing using RTDS

The main object of implementing the software in the loop test is to test and

validate the software bus differential relay model designed in RSCAD software suite. The

software relay model is connected to the eight-bus terrestrial power system and the four-

bus shipboard power system test cases discussed in Chapter IV of this thesis work. This

section gives the results of the software-in-the-loop testing for the eight-bus power

system test case and the four-bus shipboard power system test case using the real time

digital simulator.

5.3.1 SIL testing of the eight bus power system test case

The eight-bus power system test case has been discussed in detail in the Chapter

IV of this thesis. The following results include the CT currents and the trip signals when

a single line to ground fault is applied at the Bus 8 of the power system test case.

Figure 5.41 CT1 current after a LG fault on phase A

75
Figure 5.42 CT2 current after a LG fault on phase A

Figure 5.43 Trip Signal after a LG fault on phase A

In the above Figure 5.43 we can see that the trip signal shift from binary ‘0’ to ‘1’

and again shifts back to ‘0’ after the fault has been cleared. This is because of the reclose

function included in the software bus differential relay model designed in RSCAD

software suite. When compared to the HIL test results of the eight-bus power system test

case, the point at which the trip signal has been issued is quite similar. This shows that

the software bus differential relay model is able to detect the fault, issue the trip signal,

open the circuit breakers and reclose them reliably. But in order to look at the consistency

76
of the software bus differential relay model, the SIL test has been conducted using the

four-bus shipboard power system also, which is discussed in the next section.

The figures below show the CT currents and trip signals for the SIL test when a

double line to ground fault is applied at the Bus 8 of the power system test case. The CT1

and CT2 current plots shown in the figures below have a magnitude of 3.25A and 2.77 A,

respectively. A ratio of 300 is defined for each other two CTs.

Figure 5.44 CT1 current after a LLG fault on phases A & B

Figure 5.45 CT2 current after a LLG fault on phases A & B

77
Figure 5.46 Trip Signals after a LLG fault on phases A & B

The figures below show the CT currents and trip signals for the SIL test when a

triple line to ground fault is applied at the Bus 8 of the power system test case.

Figure 5.47 CT1 current after a LLLG fault on phases A, B & C

78
Figure 5.48 CT2 current after a LLLG fault on phases A, B & C

Figure 5.49 Trip Signals after a LLLG fault on phases A, B & C

5.3.2 SIL testing of the four bus shipboard power system test case

The four-bus shipboard power system test case has been discussed in detail in the

Chapter IV of this thesis. The following results include the CT currents and the trip

signals when the SIL test is implemented using the four-bus shipboard system when a

single line to ground fault is incepted at the Bus 1 of the power system test case.

79
Figure 5.50 CT1 current after a LG fault on phase A

Figure 5.51 CT2 current after a LG fault on phase A

Figure 5.52 Trip Signal after a LG fault on phase A

80
Figure 5.53 CT1 current after a LLG fault on phases A & B

Figure 5.54 CT2 current after a LLG fault on phases A & B

Figure 5.55 Trip Signal after a LLG fault on phases A & B

81
Figure 5.56 CT1 current after a LLLG fault on phases A, B & C

Figure 5.57 CT2 current after a LLLG fault on phases A, B & C

Figure 5.58 Trip Signal after a LLLG fault on phases A, B & C

82
 As shown in the above figures the software bus differential relay model issues the

trip signal and opens the circuit breaker, and also recloses it after the fault has been

cleared. From the above two sections 5.3.1 and 5.3.2 it can be seen that the trip signal is

quite similar in both the cases. When compared to the HIL test results described in the

section 5.2 the software bus differential relay model proved to be very reliable and

efficient. The software bus differential relay model has the reclose option, which is

additional functionality. The SEL-487B bus differential relay cannot reclose the circuit

breakers. Therefore based upon the results presented in this chapter, the reliability of the

software bus differential relay model can be determined.

5.4 Comparison of Results

The results of the software-in-the-loop tests are compared to those of the

hardware-in-the-loop tests in this section. In Table 5.1 below, the software-in-the-loop

tests and the hardware-in-the-loop tests are compared for an eight-bus power system test

case.

Table.5.1 Comparison of HIL & SIL test for an eight-bus power system test case

Fault type at Bus 8 Type of test conducted Trip signal (seconds)

L-G fault on phase A HIL 0.234

L-G fault on phase A SIL 0.221
L-L-G fault on phases A & B HIL 0.218
L-L-G fault on phases A & B SIL 0.216
L-L-L-G fault on phases A, B & C HIL 0.216
L-L-L-G fault on phases A, B & C SIL 0.212

83
From the above table it can be understood that the software differential relay model is

functioning quite similar to the actual SEL-487B bus differential relay hardware. Table

5.2 below shows the comparison of the software-in-the-loop tests and the hardware-in-

the-loop tests for a four-bus power system test case.

Table.5.2 Comparison of HIL & SIL test for an eight-bus power system test case

Fault type at Bus 1 Type of test conducted Trip signal (seconds)

L-G fault on phase A HIL 0.233

L-G fault on phase A SIL 0.206
L-L-G fault on phases A & B HIL 0.232
L-L-G fault on phases A & B SIL 0.208
L-L-L-G fault on phases A, B & C HIL 0.218
L-L-L-G fault on phases A, B & C SIL 0.216

From the above Table.5.2 it can be understood that the software differential relay

works quite similar to the actual SEL-487B bus differential relay hardware. There is a

very small difference in the tripping times of the SEL-487B relay and the software relay

model. Thus the software differential relay model has been validated based upon the

tabulated results.

5.5 Summary

The two different power system test cases used have been discussed briefly in this

chapter. The most important sections of this chapter include the hardware-in-the-loop test

results and the software-in-the-loop test results, which have been presented with respect

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to the two power system test cases considered. The software in the loop test also showed

the working of the software bus differential relay model designed in RSCAD software

suite and its advantages over the SEL-487B bus differential relay hardware. Since the

SIL test results for both the test cases were similar, the software bus differential relay

model can be used for protecting even larger power system test cases.

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 CHAPTER VI

CONCLUSIONS AND FUTURE WORK

6.1 Conclusions

The protection system of the shipboard power systems plays a vital role in

protecting and maintaining the continuity of service of critical equipment. The protection

system should be able to detect the faulted zone on the shipboard power system, and

isolate the zone rapidly to reduce the damage to other unfaulted zones of the system. The

selection of the protective device and the protection scheme play a major role in the

design of the protection system. The protective relay is used as the protective device and

the dual slope percentage differential protection scheme has been used to design the

protection system in this thesis work [24].

In order to test the power system in real time condition the Real Time Digital

Simulator (RTDS) has been used as the hardware simulator and the RSCAD software

suite has been used to design the power and control systems involved in the thesis work.

The hardware-in-the-loop (HIL) tests have been carried out using the SEL-487B bus

differential relay and the RTDS. The software bus differential relay model was designed

and tested with a terrestrial power system and a shipboard power system test case.

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 The dual slope percentage differential protection scheme was selected because it

is the most suitable scheme with respect to the size and capacity of the shipboard power

system. The main contributions of this thesis work are summarized as follows:

• The eight-bus power system test case was developed in the RSCAD

software suite and care was taken to make it as realistic as possible. The

test case was a good platform to conduct the preliminary HIL tests.

• The hardware interface between the power system test case being

simulated in RTDS and the SEL-487B bus differential relay hardware was

designed using the RSCAD software suite. The hardware interface block

can be used to send a maximum of 12 signals to the relay hardware.

• The HIL testing built the platform upon which the outline was drawn to

design the software differential relay model. Based upon the behavior of

the relay in the HIL tests, the functionalities were studied and the software

differential relay model’s outline was defined.

• The software differential relay model was designed in such a way that it is

very flexible enough to be applied for various power system test cases.

Though the software differential relay model is simple, the response to

faulted conditions is pretty consistent.

• Some of the key functions of the software differential relay model were:

o Sampling the analog signals, which are six current signals drawn

by the current transformers in this thesis work.

o Extraction of the operating and restraint current using Discrete

Fourier Transform blocks (DFT).

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 o Issue the trip signals to the circuit breaker control block, based

upon the dual slop percentage differential protection scheme. The

software differential relay model will issue the reclose signals as

soon as the fault is cleared, unlike the actual SEL-487B relay

hardware, which comprises of manual reclosing of circuit breakers.

• The relay model is flexible, and the parameters of the model can be

changed based upon the power system topology. The relay model proved

to be consistent when tested on two different power system test cases.

• The entire software relay modeling was done in the RSCAD software

suite. The test results of the software relay model when compared to the

HIL test results proved to be pretty similar, thus validating the software

relay model.

6.2 Future Work

In this thesis work the HIL testing and the SIL testing of a bus differential relay

was done in the RSCAD Version 2.00 software suite. The thesis also includes the design

and validation of the software bus differential relay model. But the software relay model

does not include all the functionalities of the SEL-487B bus differential relay. In future

more sophisticated functionalities like Dynamic Zone Selection, which is the best option

in the cases of more complex bus arrangements, and Breaker Failure Protection.

The present thesis can be used in future to develop the multi-zonal differential

protection scheme, and thus improve the reliability of the protection system [13] [14]. At

present the HIL testing using the relays and the RTDS is pretty prominent, but there is a

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scope of developing the software differential relay models, which will increase the

flexibility of protection, and also help in understanding the concept of differential

protection in a better fashion.

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