7.

28 ANSWERS is
ring?
v e c t o r i n
7.29
AND Whal

of
of

0
SHORT
QUESTIONS
1,11 vectoring
1s the prOcess
generating the address of
an
interrupt service routine to be loaded in
the program countcr.
s o as t o .
7.1 What is an interrupt extermal
device to the
processor

quuest te rcess iet and hardware

is a
An ntemupta particular task or
signal sent by
an

ork 7.12
the so interrupts
LSoftware inte ots: RST), RSTI, RST of 8085?
o pertorm 2, RST 3, RST
? Hardware inaterrupts: TRAP,RST7.5, RST 6.5, RST 4, RST 5
7.2 How are interrupts classified and RST 7.
5.5 and
here are three methods
of classifying
interrupts:

classificd into
hardware and sofiware intes
re and sofiware
interrupts. What
is TRAP
INTR.
Method I The interupts
are
nto
vectored and non-vectoredinte 1.13
TRAP is
a n-maskable interrupt of 8085. It is not disabled
non-maskable

Method II The intermupts are classified maskable and non-maskable in P s

of the interrupt. by processor reset or after
recogniuon
classified into
Method I l : The intemupts
are
? upts. State whether
HOLD has a higher priority than TRAP?
services a n
interrupt request
7.3 Fplain how a microprocessor
ne processor status in the
the
1.14 terrupts including TRAP are
recognized only if the HOLD is not
When the processor
it savesAt the end of the ISR, it res
recognizes an intemupt. (ISR). stack. Then lower priority than HOLD. valid, hence TRAP has
Service Routine restore the processori
calls and executes an Intemupt 8085 processor accept a hardware
When does
an
to the main program.
status and the program control
is transferred 7.15 interrupt?
The paracessor keeps checking the interrupt pins at the
routine? on
interrupt services
of the
7.4 What is the role
job. An interrupt service out Fevery instruction. u n e processor nnas a valid interruptsecond T-state of the last machine
cycle
the processor has to pertom specitie signal and if the interrupt is unmasked
a
For eachinterrupt, O nabled, then the processor accepts
required for a device that is interruptingthas been and the
interrupt. The acceptance of the interrupt
developed in order to perform the operations acknowledged by sending 1s

7.5 How are interrupts aected by system

reset in an 8085 ? processor. an iNTA Signal to the interrupting device.
Whenever the 8085 processor is reset, all the intemupts EXCept TRAP are disabled, In 1.16 List the type of signaus that has to be applied to initiate
a hardware
interrupt in an 8085.
be executed after a reset. order to The TRAP is level and edge-sensitive and
the interrupt
so
enable theintermupts. El instruction has to signal has to take a low to high
transition and then remain high, untul
it s recognized. The RST 7.5 is edge-sensitive and so the
7.6 What are sofrware interrupts? interrupt signal has to take a l10w to
high transition and need not remain
high, until it is recognized.
Software interrupts are program instructions. These instructions are inserted at desired loca. The RST 6.5, RST 5.5 INTR are level-senstive and so the
and interrupt signal should be high unul
in a program. While running a if a
software interrupt instruction is encounteredthen
program.
processor executes an interrupt service rouline.
then the the interrupt is recognized.
1.17 What are maskable and non-maskable interrupts of an 8085?
7.7 What is hardware interrupr? The TRAP is an non-maskable interrupt. The RST 7.5, RST 6.5 andRST 55 are maskable interrupts.
If an interupt is initiated in a processor by applying an appropriate signal to the The INTR of 8085 can also be disabled by DI instruction.
the interrupt is called a hardware interrupt. interrupt pin, then
7.18 When does an 8085 processor disable the interrupt system ?
7.8 What is the difference between a hardware and software interrupt?
The software
The interrupts of an 8085 except TRAP are disabled after any one of the following operations:
interrupt is initiated by the main program, but the hardware interrupt is initiated El instruction.
external device. by an Executing the
System or processor reset.
In an 8085, the software
interupts cannot be disabled or masked but the hardware
interrupts After recognition (acceptance) of
except TRAP can be disabled or masked. an interrupt.
In an 8086, the software 1.19 What is the function performed by DI instruction?
interrupts cannot be disabled
except NMI can be disabled or masked.
or masked but the hardware interupls The function of DI instruction is to disable the entire interrupt system.
7.9 What are vectored and non-vectored 7.20
interrupts?
What is the function performed by El instruction?
When an intemupt is The El instruction can be used to enable all the interrupts after disabling.
accepted. if the processor control branches to a
the manufacturer, then the
intemupt is calleda vectored interrupt. specific address defined oy 7.21 How can the interrupt INTR of 8085 be expanded?
In a non-vectoredintermupt there is no
specific address for storing the interrupt service The interrupt INTR of an 8085 can be expanded of eight interrupts using an 8-to-3 priority encoder.
Hence the intemupting device should
give the address of the rou lt can also be expanded to eight interrupts using one number of 8259 (Programmable interrupt
7.10 What is masking and
why is t interrupt service routine controller) or upto 64 interrupts using 8259's in cascaded mode.
required?
Masking is
preventing
the
interrupt from 7.22 7Ow can the hardware interrupt of an 8085 can be masked or unmasked?
processor pertorming an important job disturbing the current program
is When he
then all the
interrupts should be masked or(process) and, if the process shouldexecuuoerrupted
notD ne masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts performed by moving
the SIM instruction. The format of the 8-bit
can be

In a
processor with multiple intermupts, the disabled. data to the accumulator and then executing
it from lower priority data is shown in Fig. Q7.22.
interrupting the execution of can be
be masked so as to prevent
the interrupt service interrupt
routine of a maskeuinterrupt.
interrt
higher prion
 D 0= Interrupt Pending
=

I is Not
Intermupt Pending 9.

(D

I=Masked 0=Available
0=Unmasked 1 = Masked

.
9

5
 MICROPROCESSOHS AND MiCRO CHAPTER INTIE
En

7.32 MicROCONTROLLERA difference in programming

thediffere
is.he
7.3

will be different tor master 8259master 8259 and slave 8259?

What
in 8086?
fress
generated
to 20-bit to get a
147 1
7.38 How is the interrupt exiend and
slaves. For slave, the ICW3slavewill8259. For master, the ICW3 will info
sign ory
the type
number by four and
interrupt will
be available in input.that areh
The 8086 will multiply
table. The vector
address for an
word in the table is thaCOnSco
ess ICW4 send to 8259 inform its slave ID num
umber.
of the vector address. Ihe tirst ade When is
this 20-bit base addrens llset
memory location
starting from
and the next
wOrd is the segment
of the ddress 7.48
ICW4 is send to 8259
9 to
perform any one of the
of ISR (Interrupt
Service Routine) ISR, The
.8085 or 8086 mode following features:
controller?
interrupt Auto Normal end of
7.39 What is the need for an
It can handle
or
interupt
controller is employed toexpand the
imenruplnput. .Special fully nested mode Buffered or
The interupt
request from various
devices and allow
them by one to the processor.
one rupt ite a
Write program segment tolo
a p r o g r a m segment ntulize
Non-burffered mode.
8259 (Programmable Interrupt Controller) 1.49
a
single 8259 connected to an 8085
7.40 List some of the features of 1NTEL Let us assume that 8259 1s
I0-mapped in the processor
l t manage eipht interrupt requests
The priorities of interrupts are programmable and OCW1. Let the 8-bit addresssystem. The 8259 can be initialized by sending
can be masked or when A, 0 be 00, and
Ihe interrupt vector addresses are programmable
The interrupt unmasked individue
MVI A,ICWL; Move ICWl to A-register.
when A,=1 be 04
=

INTEL 8259?
7.41 Wrie the various functional blocks of OUT 00H :Send ICW1 to 8259.
The various functional blocks of 8259 are Control logic, Kead Write logic, Data us MVI A,ICWZ MOVe iCwz to A-register.

Intemupt Request Register (IRR), Intempt Mask Register (IMR)

and In-Service Reois buffer, OUT O1H Send ICW2 to 8259.

Priority Resolver (PR) and Cascade buffer.

(ISR). MVI A,OCWL
OUT 01H
Move OCwl to A-register.
;send oCW1 to 8259.
7.42 What is master and slave 8259? HLT :Halt program executíon.
When 8259s are connected in cascade. one 8259 will be directly interrupting the processor :
50Frame the Command words ICWI, ICW2 and OCW1 for initialiinga single 8259 interfaced
is called master 8259. To each interupt request input of master 8259, one slave 8259 Can be t o 8085 with the call address interval of 8 and for level triggered interrupt. Also unmask all
connected. The 8259's interrupting the master 8259 are called slave 8259. interrupt inputs. The desired vector address is 5000,.
7.43 How is 8259 programmed?
The 8259 is programmed by sending Initialization Command Words (ICWs) and Operatianat B, B, B, B, B, B. B B,
Command Words (OCWNs).
ICW1
7.44 What are the features of 8259 that are
programmed using 1CWs?
The ICWs are used to program the following features of an 8259: As, A, andA ICW+ is Not Needed
Call address interval (in case of B0B5 8085 or 8086 modes of CALL Address
Single 8259
Cascade mode or single Auto or Normal end of
Level or Edge trippered interrupt Call Address Interval of8
Special fully nested mode
Vector address (in case of 8085 >Level Triggered Interrupt
or Type nurmber (in case of
8086)
7.45 Whad are
features of 8259 that can be programmed using OCWs?
The OCWs are used to
program the following features of an 8259: B, B B, B, B, B. B B,
Masking of individual imterrupts.
Specific or Non-specific end of interrupt. Priority modes.
7.46 Write the format of ICW1?
A BB,
ICW2
o-
B. B B, B. B B, A, to A,, of CALL Address

A.ALTIMADI |SNGL|IKc = ICW4 Needed

=ICW4 is Not Needed B,

Single
B, B, B B, B, B, B,
0-Cascade Mode OCWI
Call Address Interval
Interval of 4
Reset
All the Interrupt Mask are
=interval of 8
Level Triggered Mode
dye'Tiypered Mode j
A, A. of Interrupt
Vector Address
(MCS-8O80/8085 Mode Only)
7.34 MICROPROCESSORSS Ar MICROCONTRO

7.51 ICW2, ICW3 and OCW1 for initiali-:.

Frame the command words 1CWI,8086-based system. The
desired featurecsing
initiate 1NT 40H to INT 47H in an
are level trig
nterrupt and automatic end of interrup.
B B, B, B, B B, B
B,

ICWI

ICW4 is Nceded
Single 8259
Level Triggered Interrupr
B. B B. B, B, B, B
B
ICW2

Upper 5 Bits of Type Number40,

B, B B B, B, B, B, B%
- 03u
ICW3

8086 Mode
Auto EOI
Non-Buffered Mode
Not Special Fully Nested Mode

B, B. B, B. B, B, B B
00
OCW1
ooo|oooo-
All the Interrupt Mask are Reset

7.52
7.52 Write a program segment to initialize a single 8259 connected to an 8086 processor
Let us assume that 8259 is 1O-mapped in the system with an even address. The 825
initialized by sending ICW1, ICW2, ICW4 and 0CW1. Let the 8-bit address withA, =0he,
when A, 1 be 024
MOVAL, ICw1 ;Move ICWl to AL-register

oUT [OOH] Send ICW1 to 8259

MOV AL, ICW2 ; Move ICW2 to AL-register
oUT [02H] Send IcW2 to 8259
MOV AL ICW4 ;MOve ICw4 to AL-register
OUT [O2H] Send ICw4 to 8259
MOV AL,OCW1 ; Move OcWl to AL-register
oUT [02H] Send ocw1 to 8259

HLT Stop