DMA Controller

DMA
• DMA Definitions:
• DMA occurs between an I/O device and memory
without the use of the microprocessor

• DMA read transfer data from the memory to I/O device

• DMA write transfer data from the I/O to memory

• MRDC & IOWC signals to simultaneously activate for

read DMA
 Basic DMA operation
• The direct memory access (DMA) I/O technique provides direct
access to the memory while the microprocessor is temporarily
disabled.

• A DMA controller temporarily borrows the address bus, data bus,

and control bus from the microprocessor and transfers the data
bytes directly between an I/O port and a series of memory
locations.

• The DMA transfer is also used to do high-speed memory-to

memory transfers.

• Two control signals are used to request and acknowledge a DMA

transfer in the microprocessor-based system.
• The HOLD signal is a bus request signal which asks the
microprocessor to release control of the buses after the current
bus cycle.

• The HLDA signal is a bus grant signal which indicates that the
microprocessor has indeed released control of its buses by placing
the buses at their high-impedance states.

• The HOLD input has a higher priority than the INTR or NMI
interrupt inputs.
 The 8237 DMA controller

• The 8237 DMA controller supplies the memory and I/O

with control signals and memory address information
during the DMA transfer.

• The 8237 is capable of DMA transfers at rates of up to

1.6M bytes per second.

• Each channel is capable of addressing a full 64K-byte

section of memory and can transfer up to 64K bytes
with a single programming.
 8237 pins
• CLK: System clock
• CS΄: Chip select (decoder output)
• RESET: Clears registers, sets mask register
• READY: 0 for inserting wait states
• HLDA: Signals that the μp has relinquished buses
• DREQ3 – DREQ0: DMA request input for each channel
• DB7-DB0: Data bus pins
• IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
• IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process
or as output to signal the end of the DMA transfer
• A3-A0: Address pins for selecting internal registers
• A7-A4: Outputs that provide part of the DMA transfer address
• HRQ: DMA request output
• DACK3-DACK0: DMA acknowledge for each channel.
• AEN: Address enable signal
• ADSTB: Address strobe
• MEMR΄: Memory read output used in DMA read cycle
• MEMW΄: Memory write output used in DMA write cycle

ACOE255 Microprocessors I - Frederick University 6

▪A DMA controller is capable of becoming the bus master
and supervising a transfer between an I/O or mass storage
interface and memory.

▪ While making a transfer, it must be able to place memory

addresses on the bus and send and receive handshaking
signals in a manner similar to that of the bus control logic.

▪ The purpose of a DMA controller is to perform a sequence

of transfers (i.e., a block transfer) by stealing bus cycles.

▪A DMA controller is designed to service one or more I/O or

mass storage interfaces, and each interface is connected
to the controller by a set of conductors.

▪ A portion of a DMA controller for servicing a single

interface is called a channel.
▪ The general organization of a one-channel DMA controller
and its principal connections is shown in Fig. 9-36.

▪ In addition to the usual control and status registers, each

channel must contain an address register and a byte (or
word) count register.

▪ Initializing the controller consists of filling these registers

with the beginning (or ending) address of the memory
array that is to be used as a buffer and the number of
bytes (words) to be transferred.

▪ For an input to memory, each time the interface has data

to transfer it makes a DMA request. The controller then
makes a bus request and, when it receives a bus grant, it
puts the contents of the address register on the address
bus, sends an acknowledgment back to the interface,
 and issues I/O read and memory write signals.

▪ The interface then puts the data on the data bus and
drops its request. When the memory accepts the data it
returns a ready signal to the controller, which then
increments (or decrements) the address register,
decrements the byte (word) count, and drops its bus
request.

▪ Upon the count reaching zero, the process stops and a

signal is sent to the processor as an interrupt request
or to the interface to notify it that the transfers have
terminated. An output is similarly executed, except that
the controller issues I/O write and memory read signals
and the data are transferred in the other direction.
▪As an example, let us consider the Intel 8237 DMA
Controller, whose overall organization alone with that of
the associated logic needed an 8088 system is given in
Fig. 9-37.
▪ When data are being put in or taken out of the 8237’s
registers, the 8237 is a slave it receivers 16-bit addresses
with the 12 MSBs of those addresses determining whether
or not the chip is selected and the 4 LBSs being used fro
internal addressing.

▪ When both HRQ and CS are low, the 8237 becomes a

slave with the IOR and IOW being the input control pins.
The CPU can read from or write to the internal registers of
the controller by activating IOR or IOW.

▪ The AEN, which is active when the controller is-a master

and is outputting an address, is 0 while the system is
communicating with the controller’s registers.
▪ If the controller is the master, then it must supply the
bus address. When it is master it puts the low-order
byte of the address on the pins A7-A0 and the high
order byte on DB7-DB0, and sets AEN to l.

▪ With AEN = 1, the outputs of the external address latch

are enabled, thereby allowing the upper address byte to
be put on the A15-A8 lines.
▪ The upper-4 bits of the address, A19-A16, cannot be
obtained from the 8237, but must be programmed
separately before the block transfer begins.
▪ While it is master the controller must also output the
necessary read/write commands.

▪ These commands are IOR, MEMR, IOW and MEMW

and indicate an I/O read, a memory read, an I/O write,
respectively. Because these signals do not match the
RD, WR, and IO/M signals output by a minimum
mode-8086, a read/write encoding circuit such as the
one shown in Fig. 9-39 is needed to perform the
translation between the two sets of signals.

▪ During a DMA transfer, the controller disables the

outputs of the read/write encoder from the command
lines by activating the AEN signal.
▪ As with the processor timing, the READY signal is
used to extend the bus cycles by inserting wait states
when servicing slow devices. A RESET signal clears
the control, status, and temporary registers and the
request flags, and sets the mask flags.
An 8237 includes control, status, and temporary registers, and
four channels, each containing a mode register, current address
register, base address register, current byte count register, base
byte count register, request flag, and mask flag. Each channel
may be put in one of four modes, with its current mode being
determined by bits 7 and 6 of the charnel’s mode register. The
four possible modes are:

Single Transfer Mode (O1)- After each transfer the controller

will release the bus to the processor for at least one bus cycle,
but will immediately begin testing for DREQ inputs and proceed
to steal another cycle as soon as a DREQ line becomes active.

Block Transfer Mode (10)-DREQ need only be active until

DACK becomes active, after which the bus is not released until
the entire block of data has been transferred.
further.
Demand Transfer Mode (00)---This mode is similar to
the block mode except that DREQ is tested after each
transfer. If DREQ is inactive, transfers are suspended
until DREQ once again becomes active, at which time
the block transfer continues from the point at which it
was suspended. This allows the interface to stop the
transfer in the event that its device cannot keep up.

Cascade Mode (11)-In this mode 8237s may be

cascaded so that more than four channels can be
included in the DMA subsystem. In cascading the con
trollers, those in the second level are connected, to
those in the first level by joining HRQ to DREQ and
HLDA to DACK. To conserve space, this mode will not
be considered