Flags Affected Instructions Assembly Language Tested Condition Operation

MOV (2-6B), MOVSX (3-6B), MOVZX (3-6B), PUSH (1-2B), POP (1- JA Z = 0 and C = 0 Jump if above
None 2B), LEA (2-6B), LDS (3-6B), LES (3-6B), LODS (1B), STOS (1B), JAE C=0 Jump if above or equal
MOVS (1B), INS (1B), OUTS (1B), JMP (2-6B), RET (1-3B)
JB C=1 Jump if below
ADD (2-6B), ADC (2-6B), SUB (2-6B), CMP (2-6B), SBB (2-6B), JBE Z = 1 or C = 1 Jump if below or equal
CF, OF, SF, ZF, AF, PF
MUL (2-6B), IMUL (2-6B), INC (1-2B), DEC (1-2B), CMPS (1B)
JC C=1 Jump if carry
CF, OF ROL (2-6B), ROR (2-6B), RCL (2-6B), RCR (2-6B)
Jump if equal or jump if
CF, SF, ZF, PF SHR (2-6B), SHL (2-6B), SAL (2-6B), SAR (2-6B) JE or JZ Z=1
zero
CF NEG (2-6B) JG Z = 0 and S = 0 Jump if greater than
OF, SF, ZF, AF, PF AAA (1B), AAS (1B) Jump if greater than or
JGE S=0
AAD (2B), AAM (2B), TEST (2-6B), AND (2-6B), OR (2-6B), XOR (2- equal
SF, ZF, PF
6B) JL S≠0 Jump if less than
AF, CF DAA (1B), DAS (1B) JLE Z = 1 or S ≠ 0 Jump if less than or equal
DF (Direction Flag) CLD (1B), STD (1B) JNC C=0 Jump if no carry
Instruction Pointer: combined with the Code Segment(CS) register. Jump if not equal or jump
8086 (5V) 8088(5V) JNE or JNZ Z=0
Points to the next instruction to be executed. if not zero
Base Pointer: Combined with Stack Segment(SS) register. Typically packaged in Dual In-Line Packages packaged in Dual In-Line
JNO O=0 Jump if no overflow
Packages
used to reference parameters or variables within the stack. JNS S=0 Jump if no sign (positive)
Stack Pointer: Combined with the stack Segment register. Points to 16 bit MuP with 16bit data bus 16bit MuP with 8bit data bus
Jump if no parity or jump if
the top of the stack Draws maxm supply current of Draws maxm supply current JNP or JPO P=0
parity odd
Source Index and Destination Index: combined with the data 360mA of 340mA
JO O=1 Jump if overflow
segment register, used in string operations and indexed addressing
Jump if parity or jump if
JP or JPE P=1
parity even
JS S=1 Jump if sign (negative)
JCXZ CX = 0 Jump if CX is zero
JECXZ ECX = 0 Jump if ECX equals zero
Jump if RCX equals zero
JRCXZ RCX = 0
(64-bit mode)
Short jump : disp btw +127 to -128
IP = IP + sign extend(disp)
EB(opcode) Disp(offset from current posn after call)
Intrasegment jump
size - 2 bytes
Near jump : +- 32K bytes
signed 16-bit disp
E9 disp low(low byte) disp high(high byte)
Intrasegment jump
size - 3 bytes
Far jump : new segment and offset address
32 - bit address
EA IP low IP high CS low CS high
Intersegment jump
size - 5 bytes
The CALL instruction pushes address of instruction following the call
on the stack while RET instruction removes the address from the stack

First 6 bits are binary opcode

Then 1 bit is Direction(1 is data going
to the REG field, 0 is data coming from
Reg field)
Then 1 bit is Word( 1 if data size is
word/doubleword, 0 is always a byte)
R/M MOD 00 MOD 01 MOD 10 MOD 11 (W=0) MOD 11 (W=1)
000 [BX] + [SI] [BX] + [SI] + d8 [BX] + [SI] + d16 AL AX
001 [BX] + [DI] [BX] + [DI] + d8 [BX] + [DI] + d16 CL CX
010 [BP] + [SI] [BP] + [SI] + d8 [BP] + [SI] + d16 DL DX
011 [BP] + [DI] [BP] + [DI] + d8 [BP] + [DI] + d16 BL BX
100 [SI] [SI] + d8 [SI] + d16 AH SP
101 [DI] [DI] + d8 [DI] + d16 CH BP
110 d16 (direct address) [BP] + d8 [BP] + d16 DH SI
111 [BX] [BX] + d8 [BX] + d16 BH DI

Memory Mode Register Mode

d8 = 8-bit displacement d16 = 16-bit displacement
SHIFT: basically moves the bits left or right n times, the endmost
bit going through carry.
SHL/SAL: both do same thing, shifting n bits left, one bit at a
time(in a sense multiplying by 2^n) and filling those n bits of space
with 0
SHR/SAR: both shift n bits right, one bit at a time, BUT SAR fills the
new MSB space with a copy of the old MSB that got shifted right.
ROTATE: rotates the bits either from one end to another or
through the carry flag, either left or right(clockwise and anti).
Rotate count can be immediate or be stored in reg CL( the value
stored in reg cl doesn't change after the rotate operation finishes
tho)
RCL/RCR rotate with carry flag while in ROR/ROL rotates normally
and the bit rotated out is copied onto carry flag
Pin Name Function
Crystal oscillator input pins for generating the clock
X1, X2
signal. A crystal is connected between these pins.
Provides the system clock signal for the 8086/8088
CLK (Clock Output)
microprocessor.
PCLK (Peripheral Clock Outputs a clock signal for peripheral devices, typically
Output) half the CPU clock frequency.
Generates an active-high reset signal for the
RESET
microprocessor.
RES Active-low reset input, used to initiate a reset cycle.
Ready inputs to insert wait states into the processor bus
RDY1, RDY2
cycle.
Address Enable inputs, used for bus arbitration in DMA
AEN1, AEN2
(Direct Memory Access) operations.
CSYNC (Clock
Synchronizes the clock signal with external events.
Synchronization) Pin Name Function
F/C (Frequency/Crystal Selects between external clock input or crystal oscillator Multiplexed Address/Data bus (used for address
Select) mode. AD0 – AD15 during the first clock cycle and for data during later
OSC (Oscillator Provides an unbuffered clock signal from the crystal cycles)
Output) oscillator. A16 – A19/S3 – S6 Higher address lines (A16-A19) / Status signals
Combined ready signal output to indicate whether the Bus High Enable (BHE) indicates access to higher
READY BHE/S7
system is ready to proceed with the next operation. byte in 16-bit data bus / Status signal (S7)
Selects between asynchronous and synchronous READY Read signal (active low) to indicate memory or I/O
ASYNC RD
mode operation. read operation
EFI (External Frequency Allows an external clock source to be used instead of the Write signal (active low) to indicate memory or I/O
Input) internal oscillator. WR
write operation
VCC Power supply (+5V) for the chip. Wait-state control; when low, CPU waits until high to
Pin Name Function READY
GND Ground (0V reference). continue execution
Status inputs used to generate
S0, S1, S2 Resets the processor, forcing execution from address
system timing signals. RESET
FFFF0H
Clock input from the 8284A clock
CLK CLK System clock input
generator for internal timing.
INTR Maskable interrupt request
Address Latch Enable, used to
ALE demultiplex the address and data NMI Non-maskable interrupt request
bus. INTA Interrupt acknowledge signal
Data Enable, controls bidirectional HOLD Request for bus control (for DMA)
DEN
data bus buffer (active high). Hold acknowledge (indicates CPU has released
HLDA
Data Transmit/Receive signal, control of bus)
DT/R
indicates data direction. Memory/IO operation select (high for memory, low
M/IO
Address Enable, enables memory for I/O)
AEN
control in the 8288. Data Transmit/Receive (used for interfacing with
DT/R
Control Enable, activates command transceivers)
CEN
output pins on the 8288. DEN Data Enable (used to control data bus transceivers)
I/O Bus Mode Select, selects between Address Latch Enable (used to latch address during
IOB ALE
I/O bus mode and system bus mode. first clock cycle)
AIOWC/ Advanced I/O Write, provides early Used for wait-state generation (executes WAIT
TEST
AMWC I/O write control signal. instruction when low)
Bus Buffering and Latches IORC/IOWC I/O Read and Write control signals. Prevents other processors from accessing bus (used
LOCK
MWTC/ Memory Write and Read control in multiprocessing)
MRDC signals. Queue Status signals (indicate instruction queue
QS0, QS1
status)
INTA Interrupt Acknowledge signal.
S0, S1, S2 Status signals (used to indicate operation type)
Master Cascade/Peripheral Data
Enable, selects cascade mode for the MN/MX Minimum/Maximum mode selection (Min = Single
MCE/PDEN processor mode, Max = Multiprocessor mode)
interrupt controller or enables I/O
bus transceivers GND Ground (0V reference for power supply)
VCC Power supply (+5V)
Request/Grant signals used for bus arbitration in
RQ/GT0, RQ/GT1
TI TMS4464 DRAM (64K X 4) Timing Diagram: multiprocessor configurations
MAX Mode 8086 System

Clock Cycle Operation AH Function Other Registers Used

The address is placed on the address/data bus 01H Read character from keyboard AL = Character read
(AD0–AD15). The ALE (Address Latch Enable)
02H Write character to console DL = Character to print
T1 (Address Latch Cycle) signal is activated to store the address. The M/IO,
RD, and WR signals are set for memory or I/O 06H Direct console output DL = Character to print, AL = Status (if input)
operation. 07H Direct console input AL = Character read
The bus is released, and the data bus switches to 08H Read character from keyboard(w/o echo) AL = Character read
read/write mode. If it’s a write operation, data is 09H Write string (terminated by $) DS:DX = Offset of string
placed on the bus. If it’s a read operation, the
T2 (Bus Idle / Wait for Ready) 0AH Read string with buffer length DS:DX = Offset of buffer
system waits for data from memory/I/O. The
READY signal is checked to determine if the 0CH Check keyboard status without waiting AL = Keyboard status
external device is ready. 0EH Write character with advanced control AL = Character to print
Data transfer occurs in this cycle. If it’s a read 25H Set interrupt vector AL = Interrupt number, DS:DX = Address of ISR
cycle, data is placed on the bus by memory/I/O. If 3DH Open/Create file AL = Mode, DX = Filename address, AX = File handle (returned)
T3 (Data Transfer)
it’s a write cycle, data is written to the 3EH Close file BX = File handle
memory/I/O.
3FH Read from file/device BX = File handle, CX = Bytes to read, DX = Buffer address
The bus is freed for the next cycle. Control and
40H Write to file/device BX = File handle, CX = Bytes to write, DX = Buffer address
T4 (Bus Idle / Deactivation) address signals return to idle. The processor
prepares for the next operation. 42H Move file pointer BX = File handle, CX:DX = Offset, AL = Mode
4CH Terminate program AL = Return code