VLSI Projects

Q.1 a) Design an 8-bit ripple carry adder using 1-bit full adder using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption

Q.2 a) Design an 8-bit shifter which can shift left or right by N-bits, based on the given
inputs using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption

Q.3 a) Design an 8-bit magnitude comparator using the Verilog HDL.

b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption

Q.4 a) Design 3-8 Decoder using the Verilog HDL.

b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption

Q.5 a) Design a logic circuit which will detect the sequence ‘110’ from the input stream of
single but using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption

Q.6 a) Design 8x1 MUX for 8-bit inputs using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
VLSI Projects

Q.7 a) Design 1-to 8 De-MUX for 8-bit inputs using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.8 a) Design 4-bit Up/down counter using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.9 a) Design 4-bit Adder-cum-subtractor circuit using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.10 a) Design 8-bit subtractor circuit using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.11 a) Design 4-bit binary to gray code converter using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.12 a) Design 8-bit ALU supporting addition, subtraction, AND, OR, XOR,
SHIFT_LEFT_1-bit, and SHIFT_RIGHT_1-bit using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.13 a) Design 4-bit priority encoder using the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
VLSI Projects

Q.14 a) Design 32-bit Floating Point addition based on IEEE 754 representation using the
Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.15 a) Design 32-bit Floating Point subtraction based on IEEE 754 representation using
the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption
Q.16 a) Design 32-bit Floating Point multiplication based on IEEE 754 representation using
the Verilog HDL.
b) Do Functional Verification of the design using UVM.
c) Generate GDS-II layout of the design using OpenROAD-flowscripts tool.
i. Report Design Area
ii. Clock frequency, where slack value is positive but less than 1.
iii. Report power consumption