STEP TOWARDS SUCCESS AKASH’S Guru Gobind Singh Indra Prastha University Series SOLVED PAPERS, | (PREVIOUS VEAR SSTION PAPERS) [B.Tech] THIRD SEMESTER Digital Logic and Computer Design (ECC-207)SYLLABUS DIGITAL LOGIC AND COMPUTER DESIGN PAPER CODE : ECC-207 Instructions for paper setter: 1. There should be 9 questions in the tert 2. The first (1st) question should be com) question should be objective, single line answers o) total 15 marks. 3. Apart from question 1 which is compulsory, rest of the paper shall consist of 4 units { as per the syllabus. Every unit shall have two questions covering the corresponding weit of the syllabus. However, the student shall be asked to attempt only one of the two questions in the unit. Individual questions may contain upto sub-parts / Sub-questions. Each Unit shall have a marks weightage of 15 UNIT-1I Boolean Algebra and Combinational Logic: Review of number systems » signed, unsigned, fixed point, floating point numbers, Binary Codes, Boolean algebra — basic postulates, theorems, Simplification of Boolean function using ‘Karnaugh map and Quine-MeCluskey method ~ Implementations of combinational logic functions using gates, Adders, Subtractors, Magnitude comparator, encoder and decoders, multiplexers, ease converters, parity generator/checker, implementation of combinational circuits using multiplexers. 1m end examinations question paper. pulsory and cover the entire syllabus. This 1r short answer type question of UNIT-II Sequential Circuits: General model of sequential circuits, Flip-flops, latches, level triggering, edge triggering, master slave configuration, concept of state diagram, state taife, state reduction procedures, Design of synchronous sequential circuits, up/down wea modulus counters, shift registers, Ring counter, Johnson counter, timing diagram, aeval adder, sequence detector, Programmable Logic Array (PLA), Programmable ‘Array Logic (PAL), Memory Unit, Random Access Memory UNIT - II Basic Computer organization: Stored Program, Organization, Computer | registers, bus system, instruction set completeness, instruction cycle, Register Transfer Language, Arithmetic, Logic and Shift Micro-operations, Instruction Codes, Design of a simple computer, Design of Arithmetic Logic unit, shifter, Design of a simple hardwired control unit, Programming the basic computer, Machine language instructions, assembly language, Microprogrammed control, Horizontal and Vertical Microprogramming, Central Processing Unit, instruction sets and formats, addressing ‘modes, data paths, RISC and CISC characteristics. UNIT -IV Computer Arithmetic, addition, subtraction, multiplication and division algorithms, put Organization, Modes of data transfer, Interrupt cycle, direct memory Input-Output processor, Memory Organization, Memory Hierarchy, Associative | Cache Memory, Internal and external Memory, Virtual Memory.FROM ACADEMIC SESSION [2022-23] THIRD SEMESTER [B.TECH] a s 3 ‘This method is suitable for ps DIGITAL LOGIC AND COMPUTER DESIGN (ECC-207) ntepe are followed for simplification of Bool UNIT-I of variables. = AB+CD+ EFG+.. nt of a sum is equal to the product of the complements. ‘Demorgan’s second theorem42021 ‘Third Semester, Digital Logic and Computer Design. ‘Table: Truth table for Demorgan’s second theorem 3B 0 1 o oli} o lolol o Lo ‘This law can be extended to any number of variables or combinations of variables, For example. ‘ BpBsCsD>.. = ABCD. ABSCD+EFG+.. = AB CD EFG-.. Q.3. Draw the logic diagram of 3-bit parity generator and respective truth table (2014) pit of a ‘0’ or a ‘I's attached to the data bits such that total no. of 1's 8 bit can be attached to the : Q7. Find essential 8 prime implicant in the given equation: F (WXY,Z) = Em (0,2y4,5,6,7,8,10,13.15) cw, X, ¥, Z) = Em (0, 2 4,5, 6,7,8, 10, 13, 15) ‘encoder is a combinational logic cireuits. It is ‘and‘n’ output lines. An encoder accepts (2015) ‘representing a digit such as a decimal/octal digit and converts‘Third Semester, Digital Logic and Computer Design ioe i are expeal in. if both ae I's or et 4 Where x, = 1 only if the pair of bits i pom are 0's. For the equality condition to exist. all « ‘an AND operation of all variables (A=B) = 334 ‘The binary variable (A = B) is equal to 1 only f al pairs of digit of thee cae mamewou 82021 Third Semester, Digital Logic and Computer Design pene" sa Q.13. Implement the followis i er \¢ following multiple output combinational logic circus a= “sing a 3-0-8 line Decoder? Sate tatiacin, afer ee () Fy = 2m (0,1,2,6) Gi) F, = 5m (2,4,6) Gil) F, = 220(0,1,5,6) ee AL Ans. Given that : @ F, = 5m(0,1,2,6) i) F, = Lmi2, 4,6) , : cane / ® a8 ribal Sera re (i) Excess 3 = aipes | (O Gi) Octal = 13 ing 4:1 multiplexer and 6! 6:1 multiplexer using #1 Q.18. Design an ‘Ans. 8:1 MUX using 4:1 MUX10-2021 i ‘Third Semester, Digital Logic and Computer Design 20. Simplify th Boolean function us IA mCi eis Gh a i ion using K-map: 2016) LP. University-[B.Tech}-Akash Books 021-11 +8, 7, 11, 15) + 2d (0, 2, 5) Ans. . 5 K-map forthe given fancin i "18 ‘ye ep [EB c5] ob 2 G5 [g0°¢5) aieo at 0048 lf a fotaan et Tala fo c8 THs 01 Aa| 1 {fs 1 1 4 |e is] 1 1 1148 «gia Bae n|__10 1028 | 1 E T a] ol In . oo “ Y = AB0+ACD+ Aco + ABC ¢ } Q24. Desoribe the circuit and operation of single Dit magnitude comparator. (2016) ‘Ans. One bit magnitude comparator is & combination logic circuit which compares ‘the two inputs in the binary code and gives three outputs ‘Truth Table of 1-bit comparator Baek) be eee ___ Input Comparator Outputs A B AB A=B AB ‘. a 0 o 1 oO o a o o 1 ot o 1 o o 1 2 1 ° (A> B) = AB (A=B) = AB+AB-AOB AB) = AB A s2021-13 's complement method? Outputs 1 (2017) sia (11101100), -+ 2's complement of addition of ~ 10 and —10 in 2's complement form, @.26. FIA, B,C, D) =2(0, 1,2,5,7, 8,9, 10, 14, 16). Find all the prime: )=3(0, 1, 2,557 im ‘essential prime implicants and minimal SOP expression. ort 10 Ans. ‘pit number X and Y. X consists of XXX, and Y consists of with three outputs Z,, Z, and Z, suc! (2017) (ii) Z, = Lwhen X=¥ iii) Z,= 1 when X>¥14-202} i 1 ‘Third Semester, Digital Logic and Computer Design Ans. Truth table for 2 - Bit Magnitude comparator. Outputs | xresvivsen | xm vive) [xr ve LP. University-1B.Tech}-Akash Books 2021-15 Q.30. Why is the ASCII code « 7 bit code? (62 symbols) and some 1 ym It is used extensively for printers and terminals that interface with small computer systems. Q.31. What are the two basic form of the Boolean expression name them? (2017) expression are: rroduet Of Sum (POS) ‘Ans. Two basic form of the B (@) Sum Of Product (SOP) Q82, Realize EX-OR gate using minimum number of NAND gate only, 2017) 4 2, = XRVFo + EXT Vo + MXN Mo KK i a oer) a : 3 {> Output =AeB Q.38. Simplify the given Boolean expression and implement it with NOR eon gate circuit only F = AB + ABD + ABD + ACD + ABC Ans. ACD s0000+c000+c000+ ©44400+-000400c0 @000-c004s00+~~ B +e-0-0-0-0-0-0-0 F = AB+ ABD+ ABD~ ACD ~ ABC P= a+BC+ACD the essential prime implicants? jor rectangle made up of the bunch of adjacent mit b of these subcubes is called a prime implicants “which cannot be covered by any other PI is called an essent the following function using K-map 2017) »2, 6,8, 9, 10) 5, 7,9, 12) + 400, 1.6)Third Semester, Digital Logic and ( F,= AcD« BCD + ABD F,= AB + BCD + AD + BCD Q.35. Obtain the decimal equivalent of the given hexadecimal number (2017) Ams (ARF), = 3x 16's 10= 16" + 2x 16 + 15 = 16% = 48+10+ ¢- g (2.58 + 0.125 + 0.058 = (58.183), 36, Ree (2017) abe ebede he18-2021 ‘Third Semester, Digital Logic and Computer Design ‘Table truth table common cathode 7-segment display. Dit BCD input 7 Segment Beem ow! ° of. Oe o 1 Oo Fo 2 ot 8 3 Oo Py 4 ot 0 5 - OF 3 6 1s 6 1 ee 1 8 0-7 04-0 9 OM Come ‘The unused BCD codes are 1010, condition for these corresponding cells, Kemap Simplification Fors oo orn b=B+t5+co e=B++0 LP. University-{B Tech}-Akash Books 2021-19 Fort eo wo So on oo Logic diagram: Fig. shows the logic diagram of BCD to 7-segment display decoder/ driver. Lta ‘Third Semester, Digital Logic and Computer Design Realize the ms half adder circuit using minimum umber of NAND, Ans, > ‘orn, cla ies BT, LP. University-{B.Tech|~Akash Books 2021-21 = X¥+ zs vz = X¥+R2+¥2 = (X+¥)(x+2Z).(F+z)2021-23 (2018) 1 D)\A+B+O+ Dy output logic 1 of 2-bit enever 2-bit input A is greater than 2-bit24-2021 ‘Third Semester, Digital Logic and Computer Design ‘Bray code converter: rerter a tional ‘Crcuit is deni Tet cea oa = ee yert binary to Gray code. The inpat ame ‘output code of code converter is. Gray code. eee ee ‘Truth Table le of-H-H LEE FP le 3 -[-[-[- LP. University-{B-Tech}-Akash Books K-Map Simplification Expression For Gy ny 6 fe 1ol8 Fe fe 6,06 +De=co We get the simplified boolean expression for the code converter of Binary of Binary to Gray code G,= BA+BA=BOA G, = CB+CB-coB G, = Dé+Be-c@D a, =D B 1 ag the above expression we can construct the binary to gray code converter as fol \ se Fig.) Logic Diagram 8 ‘Ae Binary code, 2 & 6, G, Bewy code Pig. Logic circuit for binary to gray code converter : QA8, Implement the logic expression using 4:1 MUX, F = Im (1, 3, 5 7) P = tm(1,3,5,7) ante26-2021 ‘Third Semester, Digital Logic and Computer Design Raw a Data s— A) even Paty Sonera | & T cf (lobe > SJ tances lee) p> Even panty Fig. Even Parity generator Error in the data can be detected using XOR gates. Bin: pee eee een Binary data may be corrupted ZS ee At the receiving side, the parity bit will be used to check. ‘errors and then the additional bit will be truncated before processing the data. (2018) LP. University-1B:Tech}-Akash Books 2021-27 UNIT-II Q.1. Explain various types of isters? Ans. Shift Register: A registe FFs used to store binary data. In shift into and shifted out register, FFs are connected together ‘data may be shifted into an‘ a chift register. Thus shifting may be in serial form or parallel form. types of shift register. (2018) ot a at ar Tat Teta BESO ee. Q2. Explain the process of state reduction and stage assignment ero owens corel crest oe acces sTwo states are said to be redundant every possible set of inputs ‘the same outputs and the same next states. When two states are equivalent one of them can be removed ‘without altering input output relationship, Let us consider the state diagram as shown in Fig. The states are denoted by letter symbols ‘Step 1: Finding the state tabl First the given state diag: of state diagram. Present state the given state diagram. ” ‘averted intoa state table. Fig. shows the examplethe most significant bits in ax LLP. University-{B TechI-Akash Books 021-29 cy eepain varios operations performed Raa and ROM. Menta data and control signals in RAM and ROM? «aoid) "hms. The basic memory operation follows the given functisee vic Held the data coming from Uhe memory during « read operation 5. Explain the features ofedge-trignered flip-flop. Draw the logic diagram of D-type positive edge-triguered fip-op? (2018) age Triggered D Flip Flop: Thi from low to high to I ‘during the positive transition or megat ‘equivalent circuit (called as edge det ‘The shorter pulse (spike) width at the clock input of « chance of the output being synchronized to the flip flop fives less chance for the SET and RESET inputs to cha30-2021 ‘Third Semester, Digital Logic and Computer Design P= Poni Es wig Neqaive Ege Tageing Fig. (4) Logic symbol of positive and negative edge triggered of D flip flop. When D = 0, and the edge detector senses a positive edge at the CLK input, the output of the lower AND gate steers a low going pulse to the RESET input of fip flop, thus storing a 0 at Q. When D = 1, the upper AND gate is enabled. The edge detector sends a high going pulse to the upper steering gate, which transmits a low going SET pulse to the output of flip flop. The action stores a 1 at Q. ‘Table 1: Truth table of edge positive triggered D flip flop CLK D & t 0 0 1 1 1 Q6. Compare the design features of synchronous and Asynchronous Counters. Give an illustration for each. 2014) ‘Ans. Asynchronous Counter: To design an asynchronous counter, the number of flip-flops required depends on the number of states. The maximum number of state of a counter is 2%, where m is the number of flip-flops in the counter. If we have two flip- flops, the maximum possible number of output states of the counter is 2" ie., 4. In this case, all the flip-flops are not clocked simultaneously. Example of 3-bit asynchronous up counter is shown below. 2 +» Ol een rms of flip-flop outputs as the input LP. University-1BTech|-Akash Books 2021-81 ify the k-maps and obtain the minimized expressions Connect he cireuit wsing Sip-fleps and other gates corresponding.lo the zed expressions synchronous counter is shown below. cu: Q.7.A sequential circuit with two D flip-flops A to and B, two inputs and yvone output zis specified by the following next-state and output equations: Atte) = xy ed Bit+1) = xB+xA 2=B ( Draw the logic diagram of the circuit. @ i) Derive the state table, @ Derive the state diagram. es ‘The next state and output equation are as follows: Atte) = xyexA Bite) = xB+xA 2-8 oid) 1 logie diagram is as follows:32-2021 ‘Third Semester, Digital Logic and Computer Design Gi) The state table is as follows: LP. University-{B.Techt-Alcash Books peal [tapes Neat State Output x ® x y a B = ° ° ° ° ° ° ° ° ° ° 1 1 ° ° ° ° 1 o ° ° ° ° ° 1 1 ° © ° ° 1 ° ° ° 1 1 ° 1 ° 1 1 1 1 ° 1 1 ° ° ° 1 ° 1 1 1 ° ° 1 1 ° ° ° ° ° ° ‘ - ° 1 1 ° ° : ° 1 ° 1 1 ° z - a 1 1 1 ° 1 1 ° ° ° 1 1 2 1 ° 1 1 1 1 : 1 1 ° 1 1 1 : 5 1 1 1 1 fe | ‘The state diagram is as follows: 20 own U ws on 8. Design a 4-bit nynchronous counter. (2015) ‘Ans. 4-bit asynchronous counter, counts 0000 i woe titan to 1111, Le. 16 states; itis also calledswat 4 lay ot lei‘ Tove. Tin ia tha pan sue able sitet qi2.Forthe state diagram ‘Ans. For the given state diagram, the state table is given below aa , 3 LP. University AB. sTech|-Akash Books 2021-35 ar pli wh mi 14. What do you mean bby the te! next state, input tor 011 is shown description about present #is00: revthe state table of sequence detec and output of a sequential below. Output the output. Now the effect of SR flip-flop canbe z x 0 Qa o Q ° Q o ° 1 1 0 not used @.15. Show the characteristic equation Jor the complement output of 2 JE obtain the state table? tens) sip>top is Oe +1) = 70+ ko. (2015) Ao "ania The characteristic table of Jk Aip- Hop 1 QD Que) Input NS. 0 00 ° 10 n ere Qu +) =70~ KO) at Q.16. Explain four bit Bi-directional Register with the help of Multiplesses (2015) ‘Ans. Fig shows a 4b a o data right oF left, we need « ster can serially shift Q13. What is. p-flop? the drawback of JK i Ans. In JK Gip-op, when J = K = 1 output toggle. If t, < when J = K= 1 re ee time of| lp is less than and forth between 0 and 1 cen width of the clock, the output will oscil ion delay ave bak oP input on BF ‘When the Right/eft contr Mtraion of Ue clock puloe width. TM ; il flip flop output of each bits is moved towards left side96-2021 Third Semester, Digital Logic and Computer Design LP. Universi ity-[B.Tech]-Akash Books 2021-37 Tx 200. Ty AQ Tate -0, 0:05 aa) ae 2,0) 855, a airy 4 a qq 4 ; 2,04} : Q,a,| 1 Q,0,) x alee se aalx |x Natt x ant ffs xf"]x aol |) xi}x 1, = @.@% Q17, Design a decade synchronous UP counter. Use T flip-flops 2,0, a Se etn sn nan ,0] x" | x" 2,0,] Te= AQn + O4Op andT, = 1 Q.18. Explain Twisted Ring counter with the help of Timing Diagram. (2015) ter, the complement of the first flip-flop. This number of flip-flop. The 3 lo, , atl [ [ f : ‘Truth Table CLK | Q, | Q, | Qs | Q | Qs o jojojojojr 1 fifofojols afrfifofojr a fifafafofa afarfafrtrfo sjolifr}ijo 6 jofofijajo 7 lolojojijo s lojojojo|r38-2021 ‘Third Semester, Digital Logic and Computer Design Q19. Design a sequence detector that sequence should be Overlapping that will detect the sequence 1011 ang ‘Ans. Given sequence is 1011 (2015),2016) ae 5 " juming two flip-flops to con: dotectar has geal araps 0 construct the sequence detector creuit. The sequena We choose T flip flop Let A=00,B =01,€=10,D=11 XAB = XA B)+ AB Y= sAB for sequence detector LP. University-{B/Tech}~Akash Books 2021-39 Q.20. What is race around condition? How can we overcome this condition? (2014),(2016),(2017) ‘Ans. Race Around Condition: Its important to note that in JK fip-lop, the outpat sta the input, and therefore change in the-output results in « change in the th t, as shown in Fig. (a) is applied, the output will interval At, where propagation delay of two level NAND gates t, = pulse width k= 1andQ= 1 after another At, output Q will become Nate back and forth between 0 and 1 in the duration tp of ‘of the clock pulse, the value of Q is ambiguous, This Ell te Fig. (a) Fig) ‘The race around condition can be avoided when t, < At as shown in Fig. (b). This condition can be obtained by 1. Ift, is reduced 2. Reduction of t, means, we ha ‘a pulse generator to produce less pulse width waveform, butis difficult to get such type of circuit. The value of At can be increased by in veries with feedback connection, which is aguin worthless {tions for reducing race around condition (2016)40-2001 ‘Third Semester, Digital Logie and Computer Design 2021-41 (2016),(2017) . eo" outpu stage fip-op is connected tothe input of ° ° 2 2 J sho ie Desige an SR Flip Flop and explain how it works using truth table. ‘a9 SR Flip Flop can be conv verted to D Flip Flop. Gout ing NAND gate =0 D gates 3 and 4 “no” change” co42-2021 ‘Third Semester, Digital Logic and Computer Design Bot Progr ——] th AND and OR arrays are programmable, OR array is Eued and AND array i programmable. “a Costliest and m« PROMS, Md more complex than PALs and | Cheaper and simpler AND array can be programmed to get desired minterms. Any Boolean function in SOP from van be implemented using PLA. AND array can be programmed to desired minterms “i ‘Any Boolean function in SOP from can bbe implemented using PAL. cues Wives ‘AND yates conn LP. University-{B.Tech|Akash Books 2021-43 Excitation table of RS flip flop Step 3: Conversion table ’ ‘Compute the flip flop inputs by using excitation table of RS flip flop [Given tip tow | PAL circuits (Programmable Array Logic) Q.26. Design a Delay Flip-Flop using S-R flip flop. Ans. Step. Given flip flop is RS ip flop Required flip flop is D flip op Block diagram Rr al Fp top Given eonversion || —P” Mp fop ed is 4 Step 2. Truth table of D flip flop .p simplifieation flip flop inputs and present state are considered for K-map simplification Exproasion for R Expression for S on omen ono 1 o ° * Sliiaa apals q bea / at's r=5 S=0 ‘Step 5: The obtained expression are S = Dand R= 5Q28. A sequential circuit has one input and one output and its state diagram is shown in Fig. (a). Design the sequential circuit using (i) D flip flop and (ii) JK flip flop. (2016) Ans. Mod-8 down asynchronou: inter :LP. University-{B.Tech|-Akash Books 2021-47 flop), we need the excitation table. input equation for flip flop and output equation are summarized as follows which we can develop excitation tabl asain 0 on ee D-A@BOx —Dy= ABs ABs y= A+ ABs rnequentialcireut using D ip-op is obtained by using above equations ax shown in Fig. (b). required circuit as shown, ‘Table (b) Excitation table table for D-fip flop fo, a] 2 (| Or: - xo>nom # £ Fig, (b) Sequentia! logic diagram using D fip-fop, 29. Explain JK flip-flop with the help of truth table, characteristic ‘equation and waveform. 2017) "Ans. JK flip Flop: It is used to remove the invalid condition of S-R Flip-Flop. The logic diagram and truth table is shown below. ’ Lo, oux The fiip-Hop input function and the circuit output functions are obtained by usi K-map simplification. = pele « +—o aN 00 o Q.30. Design a synchronous BCD counter with JK flip-flop. (2017) = ABs Be)+ ABE + Be) 2 ‘Ans. ABCD counter is nothing but a mod-10 counter It has 10 states Considering s = Br+ He, then Bz+Br=z ‘ (0000 to 1001 }. It requires n = 4 flip flop. ‘Simplify the above equation i ee 'Q, 0, 0, , JK — oooo ooo o* ooo1 | oo10 o* coro | oort o* oo11 | 0100 a» ort ox 0110 o* ov o* 1000 o* toot “0 0000 at{B Tech|~Akash Books 2021-61 le of J-K FLIP-FLOP LP.U ‘Table 2: Truth |AJ-K FLIP-FLOP thus obtained ‘Table 1 whichis redoced to Table the possible cerabinations of J and K input ofthe output have been considered Fig I: An $-R FLIP-FLOP Converted into J-K FLIP-FLOP Table 1: Truth Table for Fig. 1 at iS te 4 & ee 8004 Here eH conc “Heo 1 1 1 o ° Shift 0 0 1 ° 1 ee Hore Shift 1 Q7. What are the various registers of 8085? Ans. 5085 Microprocessor has &-bit registers: A.B,C,D.E.H.LF and two 16-bit registers PC and SP. These registers can be classified as 1. General Purpose Registers. 2 Temporary Registers: porary Data Registers ind Z Registers 8. Special Purpose Registers Flag Registers 4 Sixteen Bit Registers eee ory pointer store data in them. The efficient o store intermediate results ‘They are also called Programmer prefersusing 9's complement for (87-39). (2018) BCD Subtraction using 9's complement of (87-39) is 48 Jing diagram for fetch operation ? 16 bet address tras. The higher order 8 bits are tr bower order # buts are translerred to multiplexed A/D Q.10. The content of accumul: are B7H, add both contents. ‘Ans of two Sum(a) = 1 4aH = Status of the flag r Aan oe inning of this state, the RD’ signal goes low to enable te, the selected memory location is placed on D,-D, of the loxed bus, are 93H and the contents of register C (2015) oF content = 99H and content of register C = BTH, then addition CY 07 06 os 04 05 2 bY oo (OUR 8 eae 9 nt 1 ie oe ee ‘ani WS ee Re ee foot 6 «nnd. after addition Flag Register D7 D6 D5 Ds DS D2 DI DO ae =a. = o o 0 ° i 2015, 2017) lementary operation performed with the data stored digital computers are classified inte four categories:- erations which transfer binary information from ene‘Third Semester, Digital Logic and Computer Design 66-2021 Here, P1,F2,F3 : Microoperation fields CD : Condition for Branching Br : Branch field AD: Address field Qs. microprogrammed control? (2015),(2016),(2018) ‘Ans. Micro programmed control: Micro programmed control is # control by using a memory called control (CS), programmed co be advantageous to CISC sophisticated control signals, there is Hard-wired control: signals by using appropriate fi register” and “control storage for the hardwired control. Not combinational logic circuit. We can assi to each address, which can be regarded as the This is a truth table. satus — tttttt tttttt [emer] re | o (0) Microprogrammed contro! (0) Hardwired contro! address field + Q.14. An instruction is stored at location 300 with its @ location ‘The address field has the value 400. A processor resist contains the number 200. Evaluate the effective address if the addressing mode of jction is: oy Gi) Direct (ii) Immediate (iii) Relative (iv) Register Indirect (v) Index, “s018) Ri as the index register? ‘Ans. Location _ Contents 300 _ opcode; the instruction operation code 301 _ 400; address field of the above instruction a conti (a) Direct addressing: Direct addressing means that the address E1 hore a the address of memory location the instruction is:supposed to work with operand “resides”). — Explain the difference between hardwired control and 0 LP. University-IB.Tech]-Akash Books 2021-67 Effective address would therefore be 400 (p) Immediate addressing: Immediate addressing means that the address field contains the operand itself. Biffective address would therefore be 301. (@) Relative addressing: Relative addressing means that the address field contains offet to be added to the program counter to address a memory location of the addressing means that the ld in this case contains just address of an operand is in the regis ‘another operand. 5 index register: There are several possible se (there is an address field) it is co called ing the effective address .dding the contents of th fore be 400 + R1 = 400 + 200 = 600. 2. An address field that designated a memory address or a processor register. 3. A mode field that specifies the way the operand or the effective address is determined. Mode ‘Opeode ‘Address t lengths containing varying truction format of a computer st computers fall into one of Computers may have number of addresses. The num! depends on the internal orgai three types of CPU organization. Q gle Accumulator organization ADD X AC @ AC + M [x} neral Register Organization ADD R1, R2, R3 R® R2 + RS itack Organization PUSH X ‘Three address Instruction: Computer with three addresses instruction format ‘can use each address field to specify either processor register are memory operand. ADD R1,A,B AL®M ADD R2,C,D R2® MULX,R1,R2 M IX] R1* R2 ae eee of the three address formats is that it results in short program luating arithmetic expression. The disadvantage is ‘that the binary-coded instructions require too many bits to specify three addresses. [B] X=(A+B)*(C+A)SO ———=——“‘“‘“‘CS;CSO ae 68-2021 Third Semester, Digital Logie and Computer Design ‘Two Address Instruction: Most common in commercial computers. Each a field can specify either register on a memory word. LP. University-{B.Techl-Akash Books 2021-69 MOV RA RI@MIAl Example: D,T, PC < AR, SC <-0. ADD RIB RI®R1+M [BI BSA: Branch and Save Return Address av tac meiid. x=A:eis(can) As the name lis the function o this Intraton it allows the branching in the : ‘execution of instruction. By branching we mean ye instructions can have sub ADD R2,D R2@R2+M (DI | routine or procedure. When this instruction is executed, it stores the address of the next Siow flea aie aR. instruction to be executed as PC (Program count caer n>” MiCeRT sent Dram the general reser orenination of bac eompeter baying rs. Also show ‘with Arithmetic mi One Address instruction: It used an implied accumulator (AC) register for & and control word? connsodaes min priimelie cecal Une AU data manipulation. For multiplication/division, there is a need for a second register is LOAD A AC@MIAL Clock ADD B AC®@AC + MIB] 4 STORET MIT}@AC X= a memory operand, {All operations are done between the AC register and a the intermediate address of a temporary memory location required for storing LOAD C AC@M(C) ADD D AC®@AC +M(D) ML OT AC@AC + M(T) STORE X M [J@ AC Zero - Address Instruction: A stack organized com field for the instruction ADD and MUL. The PUSH & POP it tan address field to specify the operand that communicates wi of the stack) PUSH A TOS®A PUSH B TOS®B TOS® (A+B) ADD PUSH C PUSH D ADD MUL. pop xX MIX} Q.16, Explain BUN (Branch unconditionally) and BSA (Branch and * | smultiplica tc,) to main memory, perhaps only to for use in the next operation. Access to main memory is slower BUN instruction allows the program and modify the program.ESS ——"~SS—Ss=—s—s&HF— i‘. 70-2021 ‘Third Semester, Digital Logic and Computer Design le general purpose registers that Modern computer systems often have multiple gener ra COmpUNET eytnd the term is no longer aa common as it once was. However, -purpose processors still use a single accumulator for their work, in {@.19. What is the role of implied mode in addressing mode? (2015),(2018) node: In this mode the operands are specised implicitly 1 the struction, For example, the instruetion “complement accumplator” is vstraction because the operand in the accumulator register if ‘implied of an Strack magnetic tape whose speed is 1600 bits/inch? (2018) Q.20. What is the transfer rate | 1s on a track x Rotation time 120 inches/second and densi ‘Ans. We Know, Transfer Rate = Number of Here, Number of Bytes on 1600 rate = 120 = 192000ms/track Q.21. How performance of instruction improved using pipelining? (2018) of | ‘Ans. Pipelining is a technique used to improve the tion throughput of a CPU | nt mi ructions into a series of small independent ‘certain part of the instruction. At a very ‘sie level, these stages can be broken down into: | « Fetch Unit Fetch an instruction from memory « Decode Unit Decode the instruction be executed | « Execute Unit Execute the instruction «s Write Unit Write the result back to register or memory vweructon [1 [| aaa | | texen 7 eect =, \Non-Pipelines = | =e wsneion [1 [2 futen code es Pipeined ete dock st2{sjels portico On a non-pipelined CPU, when a instruction is being processed at 07 i stage, the other stages are at an idle state - which is very inefficient. If you ii LP. University-{B Tech]-Akash Books diagram, when the 1st instruction is being decoded, the Fetch, Execute and Write Units ofthe CPU are not being used and it takes 8 clock cycles to execute the 2 instructions (On the other hand, on a pipelined CPU, all the stages work in parall the ist instruction is being decoded by the Decoder Unit, the 2nd instruction is being fetched by the Fetch Unit. It only takes 5 clock cycles to execute 2 instructions on a pipelined CPU. Increasing the number of stages in the pipeline will not always result in an increase of the execution throughput. Q.22. Represent floating point in IEEE standard format for given No. 1.001010...0x2" and explain difference in Single precision and double precision numbers? (2015),(2019) Ans. 3 © al — ‘Sign of number 8 signed a Osgulies + exponent in regen econ ‘Sgnifes-_excess-127 marissa representation Valve represented = (2) Single precision (000401000001010 Value represented = 1,001010..2"” (0) Example ofa single precision number 64 ie ee a ‘1-it excoss-1023 coun mantssa racion Velue reprosenied = 2 1.M 2 1023 SEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF o1 89 31 ‘The value V represented by the word may be determined as follows: ‘If B=256 and F is nonzero, then V=NaN (“Not a number”) 'E=255 and F is zero and S is 1, then V=-Infinity + IfE=255 and F is 0, then VeInfinity * If 0cB<255 then 2 * (£-127) * (LF) where “LF” is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. * If E=0 and F is nonzero, then V=(-1)"*S * 2 ** (126) * (OF). These are “wonormalized” values,} Third S ¢ and Comy } Semester, Digital Logic and Computer Design } LP. University-{B Tech}-Akash Books 2o21-73 0 and F is zero and S is 1, then V=0 ale pg aa Q24. Register A holds the S-bit binary value 11011001, Determine the B é "perand and the logic micro-operation to be performed in order to change the 72-2021 100000000 00000000000000000000000 = 0 Galue in A to: (2015) 190900000 90000000000000000000000 = -0 Se 9190000000000000000000 = Infinity : Q.25. What are the features of 8086 microprocessor? Explain mode of 8085. (203 ‘Aus. (1) 8085 microprocessor is an 8 bit microprocessor. ie it ean accept or provide Bbit data simultaneously. (2) 8085 microprocessor is a single chip, NMOS device implemented with 6206 transistors. (3) 8085 microprocessor requires a single +5V DC power supply ‘on chip clock generator, therefore there is no need srnal tuned wwo phase, 50% duty evel ke LC, RC or erystal Je, TTL clock. These clock Double Precision: Thy jock generator representation requires a GA bi ‘ney of 8085 microprocessor is 3MHz where as to 63, eft to right | minimum clock frequency 1s 500 KHz. ©The first bit is the sign bit, 8, 1. Immediate Addressing Mode: - An immediate is transferred directly to the * the next eleven bits are the exponent bits, 'F’, and register. (2 bits are the fraction 'F" eee VY FEF FFF PPPY PEF PFE EYEE FF PREFER PEPE PPE JA 3000H (The content at the location 3000H is copied to the register A). data is transferred from the address pointed QZ, An Wit reginter eon value after arithmetic (2015),2017) mertlow vecuuse « negative number chanel— eee” =—3seeesése —— ear pa ETERS eo ane 74-2021 ‘Third Semester, Digital Logic and Computer Design LP. University-{B.Tech}-Akash Books 2021-75 27. An output program resides memory starting from addross 2000. ti ‘The same ADD instruction needs only two register address felds ifthe destination executed after the computer recognizes an interrupt when FGO becomes as | 11 one of the source registers, ie. ifthe operation is 1 (while IENa1). ae (a) What instruction must be placed at address 1? ‘t must be the last two instructions of the output program? (2015) ies inetresion ADD .E IL ES ) : A 3900) ‘The instruction may also contain one memory address field and one register address — eld, For example, the instruction, a ‘ADD Ri, X 1 BUN 0 (Branch indirect with address 0) aaa ne ere tarp etna. poiater end « counter thot slenrs to MEMS st Tn the contents of hexadecimal | 500 through 5FF. Gi) Stack Organization : In this organization, the computers wil! have PUSH ‘Ans. LDA NBR ‘Anitialize counter with and POP instructions which require an address field. For Kathplé, the instruction MA ‘2's compl. of NBR PUSH X will push the word at address Xonto the top of the stack. The operation - type INC instructions do not need any address field. For example, the instruction STA CTR /eave -NBR to counter ADD LDA ADR (Save start address to Consists of only opcode and no address field. It has the effect of popping the top two STAPTR PTR numbers from the stack, adding them, and pushing the sum onto the stack. Thus all the LOP,CLA Wlear AC tack. ‘Most of the computers ‘one of the above three types of organizations, Some STAPTRI ‘Reset memory word Raven cal ate computers combine features from more than one organizational structure nacre Pama store Q.30. Define register transfer language (RTL). (2016) ae PBranch to LOP (CTR <0) ‘Ans, Register transfer language (RTL) is a kind of intermediate representation ea Fae ore Ao) AUR) that is very close to assembly language, such as that which is used in a compiler. SS cribe data flow at the register-transfer ff an architecture. Pete pn ere ware wns ean be expressed in terms of a Register Transfer Language (RTL). § Pounter ; 81. Explain instruction cycle. (2016) a bed eee ‘Ans. An instruction cycle (sometimes called a fetch-decode-execute cycle) is the . Pointer basic operational process of a computer. Itis the process by which a computer retrieves a an. cplaia the three typescf CPU organisation with the help oexamplét | Prevuminstroction from its memory, determines what actions fe inaswatin sabes (2015) and carries out those actions. This cycle is repeated continuously by a computer's: central ‘Ans. Computers may have instructions of several different lengths con! | Processing unit (CPU), from boot-up to when the computer is shut down. varying number of addresses. The number of address: is in the instruction format Q.32. Explain the different shift operations. (2016) ofa computer depends on the internal organization of its registers. Most computers fall ‘Ans. Shift micro operations are the operations in which the contents of the register {nto one of the three types of CPU organizations: aa Shift ‘operations are used for serial transfer of (0) Sage Aosumalater Orgunisntion: Ia tia type of organisation all opera] joujus7 con tio be vase & sapped sa ingle eneonaleter Tho nctrecton irenat voce only CoOSMRMER,. aye There rv eres Ps field. For example, the instruction that loads the accumulator with the contents of * 1. Logical shift: Logical shift be defined as the shift of the bits to the right or ‘memory location, left serially. Let us suppose the symbol for logical right shift as shr and for logical left LoadX shift as shi. Where Xs the address of the source operand. This results in RG ERiA micre operation! ae 2. Cireular shift: Circular shift also named as rotate shift circulates the bits among. the ends of the register without losing information, We can achieve this by connecting the output terminal to the input terminal ofthe register. They also shift only one bit at ‘single time. For example (00. AC is the accumulator and M(X) symbolizes the memory wor fe : ead) General Register Organisation In this organization, the instruction format 20" Seeiser adden Gels according othe operation ‘example, an instruction for addition may be written as ADD R1, R2, R3, Bx Circular micro operationR cirR ‘ 3. Arithmetic Micro-operation: The main purpose of Arithmetic Micro-operation ‘© perform arithmetic operation on numeric data. i denotes the operation RI <2 3 a a