EE247

Lecture 14
• Administrative issues
 Midterm exam postponed to Thurs. Oct. 28th
o You can only bring one 8x11 paper with your
own written notes (please do not photocopy)
o No books, class or any other kind of
handouts/notes, calculators, computers, PDA,
cell phones....
o Midterm includes material covered to end of
lecture 14

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 1

HW2
1st Problem
• 4th order highpass filter SFG

1 V2 1 V4 1 Vout
Vin R*/sL2 R*/sL4
R*/R

-1/sR*C1 -1/sR*C3

V’1 1 V’3 1 V’5

• Almost all have used one or two extra amplifiers for summing e.g. at node V4

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 2
 HW2
1st Problem
• 4th order highpass filter implementation without use of extra summing amplifiers

-Cintg Vo
Cintg -Cintg
-80.72k Cintg -332.7k

- + - +
+ - - +
-Cintg
Cin=-Cintg
83.2k Cintg Cintg
117.6k

Vin

• The four circled capacitors are used for summing of signals to eliminat need for extra
amplifiers
 save power dissipation and Si area , no additional noise

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 3

EE247
Lecture 14
• D/A converters
– D/A converters: Various Architectures (continued)
• Charge scaling DACs
• R-2R type DACs
• Current based DACs
– Static performance of D/As
• Component matching
• Systematic & random errors
– Practical aspects of current-switched DACs
– Segmented current-switched DACs
– DAC dynamic non-idealities
– DAC design considerations
EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 4
 Summary of Last Lecture
• Data Converters
– Data converter testing (continued)
• Dynamic tests
– Spectral testing
– Relationship between: DNL & SNR, INL &
SFDR
• Effective number of bits (ENOB)
–D/A converters: Various Architectures
• Resistor string DACs
• Serial charge redistribution DACs

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 5

Parallel Charge Scaling DAC

• DAC operation based on capacitive voltage division

Vout
Cy Cx C Cx
Vout  Vref
Cx  Cy  C
Vref

 Make Cx & Cy function of incoming DAC digital word

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 6
 Parallel Charge Scaling DAC
reset

Vout
2(B-1) C 8C 4C 2C C C

bB-1 (msb) b3 b2 b1 b0 (lsb)

Vref

B 1
• E.g. “Binary weighted”  bi 2 i C
Vout  i 0 Vref
• B+1 capacitors & B switches 2B C
(Cs built of unit elements 
2B units of C)

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 7

Charge Scaling DAC

Example: 4Bit DAC- Input Code 1011
1- Reset phase 2- Charge phase
reset Vout
Vout

8C 4C 2C C C 8C 4C 2C C C

b3 b2
b3 b2 b1 b1 b0 (lsb)
b0 (lsb)

Vref Vref

20 C  21C  23C 11
Vout  Vref  Vref
24 C 16

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 8
 Charge Scaling DAC
reset CP
Vout
2(B-1) C 8C 4C 2C C C B 1

b 2 C i
i

bB-1 (msb) b3 b2 b1 b0 (lsb)

Vout  i 0
Vref
2 C  CP
B

Vref

• Sensitive to parasitic capacitor @ output

– If Cp constant  gain error
– If Cp voltage dependant  DAC nonlinearity
• Large area of caps for high DAC resolution (10bit DAC ratio
1:512)

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 9

Parasitic Insensitive
Charge Scaling DAC
CI
reset CP
-
2(B-1) C 8C 4C 2C C
+ Vout
bB-1 (msb) b3 b2 b1 b0 (lsb)

Vref
B 1 i B 1 i
 bi 2 C  bi 2
Vout   i  0 Vref , CI  2 B C  Vout   i  0 Vref
CI 2B

• Opamp helps eliminate the parasitic capacitor effect by producing virtual

ground at the sensitive node since CP has zero volts at start & end
– Issue: opamp offset & speed- also double capacitor area

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 10
 Charge Scaling DAC
Incorporating Offset Compensation
CI S2

reset

reset CP S1
-
S3 Vos
2(B-1) C 8C 4C 2C C reset Vout
+

bB-1 (msb) b3 b2 b1 b0 (lsb)

Vref
• During reset phase:
– Opamp disconnected from capacitor array via switch S3
– Opamp connected in unity-gain configuration (S1)
– CI Bottom plate connected to ground (S2)
– Vout ~ - Vos  VCI = -Vos
• This effectively compensates for offset during normal phase

EECS 247 Lecture 13: Data Converters- Testing & DAC Design © 2010 Page 11

Charge Scaling DAC

Utilizing Split Array
reset 8/7C
+
C C 2C 4C C 2C 4C
- Vout
b0 b1 b2 b3 b4 b5

Vref
 all LSB array C
Cseries  C
 all MSB array C
• Split array reduce the total area of the capacitors required for high
resolution DACs
– E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64+~1 unit Cs
– Issue: Sensitive to series capacitance parasitic capacitor

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 12
 Charge Scaling DAC

• Advantages:
– Low power dissipation  capacitor array does not dissipate DC power
– Output is sample and held  no need for additional S/H
– INL function of capacitor ratio
– Possible to trim or calibrate for improved INL
– Offset cancellation almost for free

• Disadvantages:
– Process needs to include good capacitive material  not compatible
with standard digital process
– Requires large capacitor ratios
– If binary-weighted Cs used then not inherently monotonic (more later)

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 13

Segmented DAC
Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
• Example: 12bit
DAC
– 6-bit MSB DAC
R- string reset
– 6-bit LSB DAC  Vout
binary weighted 32 C 16C 8C 4C 2C C C
charge scaling ...
...
• Component count ... b5 b4 b3 b2 b1 b0
much lower .
compared to full R-
string
6-bit
– Full R string
binary weighted
4096 resistors
charge redistribution DAC
– Segmented  64 6bit
R + 7 Cs (64 unit resistor
caps) ladder Switch
Network

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 14
 Current Based DACs
R-2R Ladder Type
• R-2R DAC basics:
R V/2
– Simple R network I/2
I I/2
divides both voltage V
& current by 2 2R 2R

Increase # of bits by replicating circuit

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 15

R-2R Ladder DAC

Iout

VB

2R 2R 2R 2R 2R 2R
R R R R
VEE

Emitter-follower added to convert to high output impedance current

sources

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 16
 R-2R Ladder DAC
How Does it Work?
Consider a simple 3bit R-2R DAC:

Iout

VB 4xAunit 2xAunit 1xAunit 1xAunit

2R 2R 2R 2R
R R
VEE

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 17

R-2R Ladder DAC

How Does it Work?
Simple 3bit DAC:
1- Consolidate first two stages:

I3 I2 I1 IT I3 I2 I1+IT
VB Q3 Q2 Q1 QT VB Q3 Q2

4Aunit 2Aunit Aunit Aunit 4Aunit 2Aunit 2Aunit

2R 2R 2R 2R 2R 2R R
R R R R
VEE VEE

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 18
 R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC-
2- Consolidate next two stages:

I1+IT I2+I1+IT
I3 I2 I3
VB Q3 Q2 VB Q3 Q2

4Aunit 2Aunit 2Aunit 4Aunit 4Aunit

2R 2R R 2R R
R R R
VEE VEE
I I I
I3  I2  I1  IT  I3  Total , I2  Total , I1  Total
2 4 8

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 19

R-2R Ladder DAC

How Does it Work?
Consider a simple 3bit R-2R DAC:

Iout

VB 4Aunit 2Aunit Aunit

Aunit

4I 2R 2I 2R I 2R I 2R
R R
VEE
4I 2I
In most cases need to convert output current to voltage
Note that finite output resistance of the current sources causes gain error
only
Ref: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 20
 R-2R Ladder DAC
RTotal
R
-

+ Vout

VB

16I 2R 8I 2R 4I 2R 2I 2R I 2R I 2R
R R R R
VEE
16I 8I 4I 2I
Trans-resistance amplifier added to:
- Convert current to voltage
- Generate virtual ground @ current summing node so that output
impedance of current sources do not cause error
- Issue: error due to opamp offset

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 21

R-2R Ladder DAC

Opamp Offset Issue
out in 1 R 
Vos  Vos  R T ot al  R
 
RTotal
If R T ot al  l ar g e, -
out
 Vos in
 Vos Vos
+ Vout
If RT ot al  not l ar g e
out in 1 R  Offset
 Vos  Vos  RT ot al 
  Model
Pr obl em :

Si nce RT ot al i s code dependant

out
 Vos w oul d be code dependant

 Gi ves r i s e t o IN L & DN L

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 22
 R-2R Ladder
Summary

• Advantages:
– Resistor ratios only x2
– Does not require precision capacitors
– Implemented both in BJT & MOS

• Disadvantages:
– Total device emitter area  AEunitx 2B
 Not practical for high resolution DACs
– INL/DNL error due to amplifier offset

EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 23

Current based DAC

Unit Element Current Source DAC
……………
Iout

Iref Iref Iref Iref Iref

……………
• “Unit elements” or thermometer
• 2B-1 current sources & switches
• Suited for both MOS and BJT technologies
• Monotonicity does not depend on element matching and is guaranteed
• Output resistance of current source  gain error
– Cascode type current sources higher output resistance  less gain
error

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 24
 Current Source DAC
Unit Element R

…………… -
Vout
+

Iref Iref Iref Iref

……………
• Output resistance of current source  gain error problem
Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed reduction due to amplifier bandwidth
limitations

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 25

Current Source DAC

Binary Weighted
……………
Iout

2B-1 Iref 4 Iref 2Iref Iref

……………

• “Binary weighted”
• B current sources & switches (2B-1 unit current sources but less
# of switches)
• Monotonicity depends on element matching not guaranteed

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 26
 Current Source DAC
DNL/INL Due to Element Mismatch

-
Vout
+

Iref Iref Iref Iref Iref

Iref -D I Iref +D I

• Simplified example:
– 3-bit DAC
– Assume only two of the current sources mismatched (# 4 & #5)

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 27

Current Source DAC

DNL/INL Due to Element Mismatch
s eg men t[ m]  V [ L S B ] Analog
DN L[ m]  Output
V [ LSB] 7 Iref R
s eg men t[ 4 ]  V [ L S B ] 6
DN L[ 4 ] 
V [ LSB]
5
( I  D I )R  IR
 4
IR
DN L[ 4 ]  D I / I [ L S B ] 3

( I  D I )R  IR 2
DN L[ 5] 
IR
1xIref R
DN L[ 5]  D I / I [ L S B ] Digital
Input
 IN Lmax  D I / I [ L S B ] 0
000 001 010 011 100 101 110 111

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 28
 Static DAC Errors -INL / DNL
Static DAC errors mainly due to component mismatch
– Systematic errors
• Contact resistance
• Edge effects in capacitor arrays
• Process gradients
• Finite current source output resistance
– Random variations
• Lithography etc…
• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC
Aug. 1989, pp. 1118-28.

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 29

Component Mismatch
Probability Distribution Function
• Component parameters  Random variables

• Each component is the product of many fabrication steps

• Most fabrication steps includes random variations
Overall component variations product of several random variables

Assuming each of these variables have a uniform pdf distribution:

Joint pdf of a random variable affected by two uniformly
distributed variables  convolution of the two uniform pdfs…….
pdf [f(x1)] pdf [f(x2)] pdf [f(x1,x2)]

* 
pdf [f(x1,x2)] pdf [f(x3,x4)] pdf [f(xm,xn)] Gaussian pdf
..……..
* * 
EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 30
 Gaussian Distribution
0.4

Probability density p(x)

0.3

0.2

0.1
 xm 
2

1  2s 2
p( x )  e
2s 0
-3 -2 -1 0 1 2 3

where: (x-m) /s
m is the expected value and
standard deviation :s  E( X 2 )  m 2
s 2  variance

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 31

Yield
In most cases we are
interested in finding the
Probability density

0.4
percentage of components 0.3
(e.g. R) falling within certain
p(x)

0.2
bounds around a mean
value m 0.1
0
PX  x   X  
2
X x
1
  e 2 dx 1
P(-X x X)

95.4
2 X 0.8
0.6 68.3
 X  0.4
 erf   0.2
38.3
 2
0
Integral has no analytical 0 0.5 1 1.5 2 2.5 3
solution  found by numerical X/s
methods
EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 32
 Yield
X/s P(-X  x  X) [%] X/s P(-X  x  X) [%]

0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 33

Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with s = 2mV and m= 0.

• Find the fraction of opamps with |Vos| < 6mV:

– X/s = 3  99.73 % yield

• Fraction of opamps with |Vos| < 400mV:

– X/s = 0.2  15.85 % yield

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 34
 Component Mismatch
Example: Resistors layouted out 400
side-by-side

No. of resistors
300

……. ……. DR
200
R

100
Nominal value
100 
0
After fabrication large # of 98.8 99.2 99.6 100 100.4 100.8 101.2
devices measured R[  ]
& graphed  typically if E.g. Let us assume in this example 1000 Rs
sample size large shape measured
is Gaussian & 68.5% fall within +-0.4OHM or +-0.4% of
average
 1sfor resistors 0.4%

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 35

Component Mismatch
Example: Two resistors 0.4
Probability density p(x)

layouted out side-by-side 0.35

0.3
0.25 DR
0.2
R
0.15

R1  R2 0.1
R
0.05
2
0
d R  R1  R2 3s 2s s 0 s 2s 3s
dR
For typical technologies & geometries R
1 1s for resistors  0.02 to 5%
s dR
2

A re a
R In the case of resistors s is a function of area

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 36
 DNL Unit Element DAC
E.g. Resistor string DAC: Vref
Assumption: No systematic error- only random error
2B 1
Iref
o Ri
D  Rmedian Iref w here Rmedian 
2B
Di  Ri Iref

Di  Dmedian
DN Li 
Dmedian Di  Ri Iref

Ri  R dR dR
 median
 
R R Ri
median median

s DNL  s dRi
Ri
To first order  DNL of unit element DAC is independent of resolution!
Note: Similar results for other unit-element based DACs
EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 37

DNL Unit Element DAC

E.g. Resistor string DAC:
Example:
If sdR/R = 0.4%, what
s D NL  s dR i
DNL spec goes into
the unit-element DAC
Ri
datasheet so that
99.9% of all converters
meet the spec?

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 38
 Yield
X/s P(-X  x  X) [%] X/s P(-X  x  X) [%]

0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 39

DNL Unit Element DAC

E.g. Resistor string DAC: Example:
If sdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
s D NL  s dR i
the spec?

Ri Answer:
From table or Matlab: for 99.9%
 X/s = 3.3
sDNL = sdR/R = 0.4%
3.3 sDNL = 3.3x0.4%=1.3%

DNL= +/- 0.013 LSB

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 40
 DAC INL Analysis

Ideal Variance
N A=n+E n n.se2
B=N-n-E N-n (N-n).se2
Output [LSB]

E
E = A-n r =n/N N=A+B
n A = A-r(A+B)
= (1-r). A - r.B
 Variance of E:
n
Input [LSB]
N=2B-1 sE2 =(1-r)2 .sA2 r 2 .sB2
=N.r .(1-r).se2 = n .(1- n/N).se2

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 41

DAC INL
sINL/se
 n
sE 2
 n  1   s e 2 (2B-1)0.5/2
 N
ds E 2
T o f i nd max. var i ance : 0
dn
N
 n  N / 2  s E2  s e 2
4
• Error is maximum at mid-scale (N/2):

1 B
s INL
max
 2  1 se 0
2 0 0.5 1
w i t h N  2B  1 n/N
• INL depends on both DAC resolution & element matching se
• While sDNL = seis to first order independent of DAC resolution and is
only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 42
 Untrimmed DAC INL
Example:
1 B
Assume the following requirement s INL  2  1 se
for a DAC: 2
sINL = 0.1 LSB
 s INL 
Find maximum resolution for: B  2  2log 2  
 se 
se  1%  Bmax  8.6bits
se  0.5%  Bmax  10.6bits
se  0.2%  Bmax  13.3bits
se  0.1%  Bmax  15.3bits

Note: In most cases, a number of systematic errors prevents

achievement of above results

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 43

Simulation Example
12 Bit converter DNL and INL
2 se = 1%
B = 12
DNL [LSB]

-0.04 / +0.03 LSB

1
Random #
generator used in
0 MatLab
-1
500 1000 1500 2000 2500 3000 3500 4000 Computed INL:
bin
2 sINLmax = 0.32 LSB
-0.2 / +0.8 LSB
(midscale)
INL LSB]

0
Why is the
results not as
-1 expected per our
500 1000 1500 2000 2500 3000 3500 4000
bin derivation?

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 44
 INL & DNL for Binary Weighted DAC
Iout
• INL same as for unit
element DAC

• DNL depends on transition

–Example: 2B-1 Iref 4 Iref 2Iref Iref
……………
0 to 1 sDNL2 = s(dI/I 2
1 to 2  sDNL2 = 3s(dI/I 2

• Consider MSB transition:

0111 …  1000 …

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 45

DAC DNL
Example: 4bit DAC
..
.
Iout Analog ..
Output [Iref] I8on, I4off ,I2off ,I1off
8
I8off, I4on ,I2on ,I1on
7

I8 I2 I1 6
I4
8Iref 5
4Iref 2Iref Iref
4 I4on ,I2off ,I1off
..
..
.

3 I2on ,I1on
• DNL depends on transition
2 I2on ,I1off
– Example:
0 to 1 sDNL2 = s(dIref/Iref2 1 I1on
Digital
1 to 2  sDNL2 = 3s(dIref/Iref2 0 Input

0000 0001 0010 0011 0100 0101 0110 0111 1000

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 46
 Binary Weighted DAC DNL
• Worst-case transition
DNL for a 4-Bit DAC occurs at mid-scale:
15
s DNL
2
 
 2B1  1 se2  2B1 se2  
sDNL2/se2

0111... 1000...
10
 2Bse2
s DNLmax  2B / 2se
5 1 1
s INLmax  2B  1 s e  s DNLmax
2 2
• Example:
0 2 4 6 8 10 12 14 B = 12, se = 1%

DAC Output [LSB] sDNL = 0.64 LSB

sINL = 0.32 LSB

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 47

MOS Current Source Variations

Due to Device Matching Effects
Id1  Id 2
Id 
2
Id1 Id2
dId Id1  Id 2

Id Id
dId dW L 2  dVth
 
Id W
L VGS Vth

• Current matching depends on:

- Device W/L ratio matching
 Larger device area less mismatch effect
- Current mismatch due to threshold voltage variations:
 Larger gate-overdrive less threshold voltage mismatch effect

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 48
 Current-Switched DACs in CMOS
Iout
Iref Switch Array

dId dW L 2dVth
 
Id W
L VGS  Vth ……

256 128 64 ………..…..1

• Advantages: Example: 8bit Binary Weighted

Can be very fast
Reasonable area for resolution < 9-10bits

• Disadvantages:
Accuracy depends on device W/L & Vth matching

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 49

Unit Element versus Binary Weighted DAC

Unit Element DAC Binary Weighted DAC
B
s DN L  se s DN L  2 2 se  2s IN L

1 B 1B see
s IN L  2 2 se s IN L  2 2 se slide 42

Number of switched elements:

S  2B SB

Key point: Significant difference in performance and complexity!

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 50
 Unit Element versus Binary Weighted DAC
Example: B=10
Unit Element DAC Binary Weighted DAC

s DNL  s e s DNL  2 s e  3 2s e
B
2

1 1
s INL  2 s e  1 6s e s INL  2 s e  16s e
B B
2 2

Number of switched elements:

S  B  10
S  2B  1 0 24

Significant difference in performance and complexity!

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 51

“Another” Random Run …

DNL and INL of 12 Bit converter
2 Now (by chance) worst
-1 / +0.1 LSB, DNL is mid-scale.
DNL [LSB]

1
0
-1
-2 Close to statistical result!
500 1000 1500 2000 2500 3000 3500 4000
bin
2
INL [LSB]

-0.8 / +0.8 LSB

1

-1
500 1000 1500 2000 2500 3000 3500 4000
bin

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 52
 10Bit DAC DNL/INL Comparison
Plots: 100 Matlab Simulation Runs Overlaid

Ref: C. Lin
and K. Bult,
"A 10-b,
500-
MSample/s
CMOS DAC
in 0.6 mm2,"
IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.

Note: se=2%

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 53

10Bit DAC DNL/INL Comparison

Plots: RMS for 100 Simulation Runs

Ref: C. Lin
and K. Bult,
"A 10-b,
500-
MSample/s
CMOS DAC
in 0.6 mm2,"
IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.

Note: se=2%

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 54
 DAC INL/DNL Summary
• DAC choice of architecture has significant impact on
DNL

• INL is independent of DAC architecture and requires

element matching commensurate with overall DAC
precision

• Results assume uncorrelated random element

variations

• Systematic errors and correlations are usually also

important and may affect final DAC performance
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 55

Segmented DAC
Combination of Unit-Element & Binary-Weighted
• Objective:
Compromise between unit-element and binary-weighted DAC

MSB (B1 bits) (B2 bits) LSB

… …

Unit Element Binary Weighted

• Approach: VAnalog
B1 MSB bits  unit elements
B2 LSB bits  binary weighted BTotal = B1+B2

• INL: unaffected same as either architecture

• DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC
element turns on  Same as binary weighted DAC with (B2+1) # of bits
• Number of switched elements: (2B1-1) + B2

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 56
 Comparison
Example:  B2 1
B = 12, B1 = 5, B2 = 7 s DNL  2 2
s e  2s INL
B1 = 6, B2 = 6 1
s INL  2 se
B
2

MSB LSB

S  2B1  1  B2
Assuming: se = 1%

DAC Architecture sINL[LSB] sDNL[LSB] # of switched

(B1+B2) elements
Unit element (12+0) 0.32 0.01 4095
Segmented (6+6) 0.32 0.113 63+6=69
Segmented (5+7) 0.32 0.16 31+7=38
Binary weighted(0+12) 0.32 0.64 12
EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 57

Practical Aspects
Current-Switched DACs
• Unit element DACs ensure
monotonicity by turning on
equal-weighted current
sources in succession
• Typically current switching
performed by differential
pairs
d7 d1
• For each diff pair, only one of
the devices are on switch
device mismatch not an issue Binary Thermometer
b2,b1,b0 d7,d6,d5,d4,d3,d2,d1
• Issue: While binary weighted
000 0000000
DAC can use the incoming 001 0000001
binary digital word directly, 010 0000011
unit element requires a 011 0000111
decoder 100 0001111
101 0011111
110 0111111
 N to (2N-1) decoder 111 1111111

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 58
 Segmented Current-Switched DAC
Example: 8bit4MSB+4LSB
• 4-bit MSB Unit
element DAC +
4-bit binary
weighted DAC

• Note: 4-bit MSB

DAC requires
extra 4-to-16 bit
decoder

• Digital code for

both DACs
stored in a
register

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 59

Segmented Current-Switched DAC

Cont’d
• 4-bit MSB Unit
element DAC + 4-
bit binary weighted
DAC

• Note: 4-bit MSB

DAC requires extra
4-to-16 bit decoder

• Digital code for

both DACs stored
in a register

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 60
 Segmented Current-Switched DAC
Cont’d
Domino Logic
• MSB Decoder
Domino logic
Example: D4,5,6,7=1 OUT=1

IN
• Register
 Latched NAND gate:
 CTRL=1 OUT=INB
Register

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 61

Segmented Current-Switched DAC

Reference Current Considerations
• Iref is referenced
to VDD

 Problem:
Reference
current
varies with +
supply -
voltage

Iref =(VDD-Vref ) / R

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 62
 Segmented Current-Switched DAC
Reference Current Considerations
• Iref is
referenced to
VssGND

+
-

Iref =(Vref -Vss ) / R

0

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 63

DAC Dynamic Non-Idealities

• Finite settling time
– Linear settling issues: (e.g. RC time constants)
– Slew limited settling

• Spurious signal coupling

– Coupling of clock/control signals to the output via
switches

• Timing error related glitches

– Control signal timing skew

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 64
 Dynamic DAC Error: Timing Glitch
• Consider binary weighted DAC Output
DAC transition 011  100 10

Ideal
5
• DAC output depends on
0
timing 10
1 1.5 2 2.5 3

Early
5
• Plot shows situation where
0
the control signals for LSB & 1 1.5 2 2.5 3
10
MSB

Late
– LSB/MSBs on time 5

– LSB early, MSB late 0

1 1.5 2 2.5 3
– LSB late, MSB early Time

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 65

Glitch Energy
• Glitch energy (worst case) proportional to: dt x 2B-1
• dt  error in timing & 2B-1 associated with half of the switches changing
state
• LSB energy proportional to: T=1/fs

• Need dt x 2B-1 << T or dt << 2-B+1 T

• Examples:
fs [MHz] B dt [ps]
1 12 << 488
20 16 << 1.5
1000 12 << 0.5

 Timing accuracy for data converters much more critical compared to digital
circuitry

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 66
 DAC Dynamic Errors
• To suppress effect of non-idealities:
– Retiming of current source control signals
• Each current source has its own clocked latch
incorporated in the current cell
• Minimization of latch clock skew by careful
layout ensuring simultaneous change of bits

– To minimize control and clock feed through

to the output via G-D & G-S of the switches
• Use of low-swing digital circuitry

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 67

DAC Implementation Examples

• Untrimmed segmented
– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC
December 1986, pp. 983
– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering
CMOS D/A Converter,” JSSC March 2001, pp. 315

• Current copiers:
– D. W. J. Groeneveld et al, “A Self-Calibration Technique for
Monolithic High-Resolution D/A Converters,” JSSC December
1989, pp. 1517

• Dynamic element matching:

– R. J. van de Plassche, “Dynamic Element Matching for High-
Accuracy Monolithic D/A Converters,” JSSC December 1976, pp.
795

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 68
 2mtech., 5Vsupply
8x8 array
6+2 segmented

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 69

Two sources of systematic error:

- Finite current source output resistance
- Voltage drop due to finite ground bus resistance

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 70
 Current-Switched DACs in CMOS
Assumptions:
RxI small compared to transistor gate-overdrive
To simplify analysis: Initially, all device currents assumed to be equal to I
VGSM 2  VGSM 1  4RI
Iout
VGSM 3  VGSM 1 7RI

VGSM 4  VGSM 1  9RI VDD

VGSM 5  VGSM 1  10RI VG

M1 I1 M2 I2 M3 I3 M4 I4 M5 I5

I2  k VGSM 2 Vth 
2

Rx4I Rx3I Rx2I RxI

2
 4RI 
I2  I1  1 
 VGS  Vth 
 M1  Example: 5 unit element current sources

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 71

Current-Switched DACs in CMOS

2
 4RI  Iout
I2  k VGSM 2  Vth   I1  1 
2

 VGSM 1  Vth 
2I1 VDD
gmM 1 
VGSM 1  Vth
 4RgmM 1 
2 M1 I1 M2 I2 M3 I3 M4 I4 M5 I5
 I2  I1  1    I1 1  4RgmM 1 
 2 
2
 7RgmM 1 
 I3  I1  1    I1 1  7RgmM 1  Rx4I Rx3I Rx2I RxI
 2 
2
 9RgmM 1 
 I4  I1  1    I1 1  9RgmM 1  Example: 5 unit element current sources
 2 
2
 10RgmM 1 
 I5  I1  1    I1 1  10RgmM 1 
 2 

 Desirable to have gm small

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 72
 Current-Switched DACs in CMOS
Example: INL of 3-Bit unit element DAC
0.3

Sequential current
0.2
source switching
INL [LSB]

0.1 Symmetrical current

source switching
0

-0.1
0 1 2 3 4 5 6 7
Input

Example: 7 unit element current source DAC- assume gmR=1/100

• If switching of current sources arranged sequentially (1-2-3-4-5-6-7)

 INL= +0.25LSB
• If switching of current sources symmetrical (4-3-5-2-6-1-7 )
INL = +0.09, -0.058LSB  INL reduced by a factor of 2.6

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 73

Current-Switched DACs in CMOS

Example: DNL of 7 unit element DAC
0.2

0.1 Sequential current

DNL [LSB]

source switching
0
Symmetrical current
source switching
-0.1

-0.2 1 2 3 4 5 6 7
Input

Example: 7 unit element current source DAC- assume gmR=1/100

• If switching of current sources arranged sequentially (1-2-3-4-5-6-7)
 DNLmax= + 0.15LSB
• If switching of current sources symmetrical (4-3-5-2-6-1-7 )
 DNLmax = + 0.15LSB DNLmax unchanged

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 74
Two sources of systematic error:
- Finite current source output resistance
- Voltage drop due to finite ground bus resistance

EECS 247 Lecture 14: Data Converters- DAC Design © 2010 Page 75