Modelsim Installation & Tutorial: Uc Berkeley Gdgib@Eecs - Berkeley.Edu October 21, 2007
Modelsim Installation & Tutorial: Uc Berkeley Gdgib@Eecs - Berkeley.Edu October 21, 2007
Modelsim Installation & Tutorial: Uc Berkeley Gdgib@Eecs - Berkeley.Edu October 21, 2007
Introduction
In this document I will cover the basics of installing ModelSim (see section 2), compiling the Xilinx simulation libraries, and simulating a simple example project (see section 3). This document is targetted at both RDL users and, more generally, those new to the simulation of digital logic (EECS150 and CS61C students). EECS150 and CS61C users neednt worry about installation, as the relevant Berkeley computers (those in 125 Cory for EECS150 and ilinux1, 2 & 3 for CS61C) already have ModelSim properly installed. Students may wish to read the installation section if they are interested in running ModelSim on their home computers. CS61C students, like all people not using Xilinx FPGAs, should ignore the instructions in this document which mention Xilinx. In general, RDL users will need section 2, but should refer to the CounterExample, distributed with RDLC for use. Section 3 on the other hand is meant for those without ModelSim experience, or those who need a refresher, in particular U.C. Berkeley students in CS61C or EECS150. Note that as of this writing the current versions of various pieces of software mentioned in this document are: RDLC 2.2007.6.7 and ModelSim SE 6.2g.
i. Make ModelSim.ini in c:\Modeltech version writeable (it is marked read-only by the installer). ii. Run compxlib to compile the xilinx libraries. Note that it is best to run from c:\Modeltech version. . This will modify ModelSim.ini in the current directory to include paths to the Xilinx libraries. iii. Not necessary unless you intend to use ModelSim to simulate designs for Xilinx FPGAs. . RDLC2 as of v2.2007.3.26 will require this. Step5. This should complete your installation of ModelSim. Step6. You may test your installation by attempting to simulate, as described below, a simple project with a single verilog le shown in program 1 Program 1 TestVerilog.v
module T e s t V e r i l o g ; i n i t i a l begin 3 $display ( H e l l o , World ! ) ; 4 end 5 endmodule
1 2
Use
The purpose of an HDL simulator is to compile, and then simulate an HDL (hardware description language: Verilog and VHDL are examples) on a standard computer. While this is very slow compared to a real circuit implementation, it allows complete visibility and can be much less expensive, making it ideal for design and debugging. Note that as a circuit grows in complexity an FPGA will generally be a better platform, as the simulator will start to degrade in performance, and has no true IO connections. ModelSim is a very powerful HDL simulation environment, and as such can be dicult to master. To correctly simulate many complex test benches, you will need to create and use a ModelSim project manually. Note that throughout this tutorial we assume you are attempting to simulate a purely Verilog based design. The steps are fairly simple: Step1. Create a directory for your project (section 3.1). Step2. Start ModelSim and create a new project (section 3.2). Step3. Add all your Verilog les to the project (section 3.3). Step4. Compile your Verilog les (section 3.4). Step5. Start the simulation (section 3.5). Step6. Add signals to the wave window (section 3.6). Step7. Recompile changed verilog les (section 3.7). Step8. Restart/Run the simulation (section 3.8).
3.1
3.2
3.3
3.4
b. If you are using Const.v, or Verilog preprocessor ags. Students in CS61C, and anyone else not using Verilog les from RDLC2 or EECS150 may skip this step. i. Use Shift-Click to select all of your Verilog les, and then Right-Click and select Properties ii. Go to the Verilog tab in the properties window. iii. Click the Macro button 3
iv. Enter MODELSIM into the Macro Name box, leaving the Value box empty. v. Click OK until you get to the ModelSim Main Window c. Right-Click in the Project Pane and select Compile Compile Out-of-Date, this will attempt to compile all of the les with ? next to them i. If you change any verilog source les you must recompile them before restarting the simulation. ii. You can also use Compile All, however on projects with a large number of les this may take a while.
3.5
3.6
i. Right-Click on a module in the Sim Panel and select Add Add to Wave. Note that you almost certainly do not want Add All to Wave, as that will add all the signals in your design. ii. This will add all of the signals from that module to the Wave Window. iii. Please, look at signals inside your modules rather than just in the testbench. iv. Remember that when debugging you cannot see too few signals. d. To add individual signals i. Go to the Signals Window, or the Signals Panel (which tends to be in the middle of the main window). This is the window or panel which lists all the signals (wires) in the currently selected module instance. . If it is not visible, use the View Signals window to display it ii. Drag the signals you wish to see to the Wave Window e. You can view busses in any number system, rather than just binary. i. Select a signal, or group of signals ii. Right-Click on them and select Radix Hexadecimal to display those signals in hex. iii. This can allow you to see signicantly more data on one screen and can make it easier to read.
3.7
3.8
More Information
For more information on ModelSim, please check the manuals and documentation that accompany it. For more information on RDLC2 and its interaction with ModelSim please see the CounterExample in the RDLC2 distribution. 5