Chapter 4

Signal Conditioning and Processing

Signal Conditioning and its importance

The signal conditioner takes the output from the sensor and converts it into suitable condition
so that the rest of the element of the measurement system can perform their particular work
satisfactorily. Example: operational Amplifier

It is used for manipulating the signal in such a way that it meets the requirement of the next
stage for further processing.

The signal conditioning equipment may be required to do processes like amplification,

attenuation, integration, differentiation, addition and subtraction and also required to do non-
linear processes like modulation, demodulation, sampling, filtering and wave shaping
(clipping and clamping)

Amplification

Amplifiers increase voltage level to better match the analog to digital converter (ADC) range,
thus increasing the measurement resolution and sensitivity. In addition, using external signal
conditions located loser to the signal source or transducer, improves the measurement signal
to noise ratio by magnifying the voltage level before it is affected by environmental noise.

Attenuation

Attenuation, the opposite of amplification, is necessary when voltages to be digitalized are

beyond the ADC range. This form of signal conditioning decreases the input signal amplitude
so that the conditioned signal is within ADC range. It is typically necessary when measuring
voltages are more than 10V.

Filtering

Filter rejects unwanted noise within a certain frequency range. Oftentimes, low pass filters
are used to block out high frequency noise in electrical measurements such as 60 Hz power. It
is used to prevent aliasing from high frequency signals which is done by using an antialiasing
filter to attenuate signals above the Nyquist frequency.

Clipping and clamping

The diode clamper is a wave shaping circuit that shifts the signal voltage to a desired level.
The clipping circuits are diode-operated wave shaping circuits that change the V-I
characteristics in response to the level of the applied signal. A diode can be considered as a
voltage- controlled switch.

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Operational Amplifier in Instrumentation

OPAMP is an extremely versatile device that does countless works like isolation, inversion,
addition, subtraction, multiplication, division, integration and differentiation. The operational
amplifier manufactured with integrated circuit technology contains transistors, diodes,
resistors and capacitors.

There are two modes of operation of an operational amplifier

1. Non-inverting mode
Here, the input voltage is applied to pin 3 and the ouput voltage has the same sign as
the input.

2. Inverting mode
Here, the voltage is applied to inverting input pin 2 and the output voltage has a sign
which is opposite to that of the input.
One of the most popular OPAMP is the 741 type.

Ideal Operational Amplifier

The properties of an ideal operational amplifier are:

a. It should have an infinite input impedance i.e. Zi = ∞.

b. It should have a zero output impedance i.e Zo = 0
c. It should have an infinite open loop gain i.e Av01= -∞.
d. It should have a flat frequency response over a wide range of frequency i.e. its bandwidth
BW= ∞.
e. It should have a zero output voltage i.e. Vo =0 (equal voltages are applied to inverting and
non-inverting ends of the amplifier)

1. Non-inverting amplifier
Here, V+= Vi …………………..(1)
Vo =If (Rf+R1)
Vo
∴ If = R +R ……………(2)
f 1
V- = If R1
Vo
= R +R ∗ 𝑅1
f 1
R1
= R +R ∗ Vo …………………(3)
f 1
As we know that
Vo
Vo = Av01(V+ - V-) = Av01 (Vi − ∗ Vo )
Rf +R1
Vo 1 R
∴ 𝐴𝑣01 = 𝑉𝑖 − (R +R ) Vo ………………..(4)
f 1

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As the output voltage from the OPAMP will be no more than 15 V i.e. a finite quantity and
o V
open loop gain Av01 is very large, may be taken as infinite, hence the ratio (𝐴𝑣01 )tends to
zero. So equation (4) becomes
1 R
𝑉𝑖 − (R +R ) Vo = 0
f 1
1 R
or, 𝑉𝑖 = (R +R ) Vo
f 1
Vo Rf +R1 R
∴ = = (1 + R f ) …………………..(5)
𝑉𝑖 R1 1

Voltage follower mode/ Isolation mode/Buffer mode

If the feedback resistor R f =0 as shown in the figure,

the circuit is said to be working in isolation mode.
Then from equation (5) we get,
Vo
𝐴= =1
𝑉𝑖

or, Vo =𝑉𝑖 i.e. the output of the OPAMP exactly tracts/copy/ follows the input voltage in sign
and magnitude, so called a voltage follower.

The voltage follower possesses the following characteristics

a. It has large input impedance

b. It has a unity gain
c. It has small value of output impedance

It is used to reduce loading effect as it has high input impedance and a low output impedance,
to serve as an ideal Buffer (isolation circuit) and for impedance matching.

2. Inverting mode

Here, V+ = 0
As we have ,
Vd = V+ - V- = 0
or, V- = V+ = 0…………..(1)
The V- is also virtually grounded . Applying KCL at node V-,
In + If = 0
(𝑉𝑖 −𝑉− ) Vo −𝑉−
Or, + = 0 (using equation 1)
Ri Rf
𝑉 V
Or, R𝑖 + Ro = 0
i f
Vo 𝑉
Or, = − R𝑖
Rf i
Vo Rf
= 𝐴 = − R …………………(2)
𝑉𝑖 i

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 Applications of the operational Amplifier in instrumentation

1. Inverter

We have,

Vo Rf
=𝐴= −
𝑉𝑖 Ri

If R f =R i , then Vo = -𝑉𝑖 i.e. the output voltage is 180° out of phase with the input voltage.

2. Adder

Here, if only the signal V1 is applied, then the output is given by

𝑅𝑓
V01 = − ∗ 𝑉1……………….(1)
𝑅1

𝑅
Similarly, Vo2 = − 𝑅𝑓 ∗ 𝑉2………………..…(2)
2

𝑅
Vo3 = − 𝑅𝑓 ∗ 𝑉3 ………………..(3)
3

If all the three signals are applied simultaneously, then the output can be obtained by
superposition theorem as
𝑅 𝑅 𝑅
Vo = Vo1+Vo2+Vo3 = -(𝑅𝑓 ∗ 𝑉1 + 𝑅𝑓 ∗ 𝑉2 + 𝑅𝑓 ∗ 𝑉3 )
1 2 3

If Rf = R1=R2=R3, the circuit acts as a pure adder and the output voltage is

VO = - (V1+V2+V3) i.e. sum of the individual input voltages.

3. Subtractor

The output from OPAMP (1) is given by

𝑅𝑓1
VO1 = − ∗ 𝑉1 ……….(1)
𝑅1

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and the final output i.e from OPAMP (2 ) is given by
𝑅 𝑅𝑓2
VO = -[ 𝑅𝑓2 ∗ 𝑉2 + ∗ 𝑉01]
2 𝑅3

𝑅 𝑅𝑓2 𝑅𝑓1
= -[ 𝑅𝑓2 ∗ 𝑉2 + ∗ (− ∗ 𝑉1 )]
2 𝑅3 𝑅1

If 𝑅𝑓1 =𝑅𝑓2 = R1 =R 2 =R 3 , the circuit acts as a pure subtractor and the output voltage is

𝑉0= 𝑉1-𝑉2 Using single OPAMP

Here,
𝑅𝑓𝑝
V+ = (R )* 𝑉2………………(1)
2 +𝑅𝑓𝑝

If only V+ is applied, the output is

𝑅𝑓𝑛
Vo+ = (1 + ) ∗ 𝑉+ as non- inverting amplifier.
R1

𝑅𝑓𝑛 𝑅𝑓𝑝
As, VO+ = (1 + ) ∗ (R ) ∗ 𝑉2………………….(2)
R1 2 +𝑅𝑓𝑝

If only V1 is applied , the output is given by

𝑅𝑓𝑛
VO2 = − ∗ 𝑉1 ……………..(3) as inverting amplifier
R1

If both signals are applied simultaneously, the output can be obtained by superposition
theorem as

VO = VO++VO1
𝑅𝑓𝑛 𝑅𝑓𝑝 𝑅
= (1 + ) ∗ (R ) ∗ 𝑉2 − ( R𝑓𝑛 ∗ 𝑉1 )
R1 2 +𝑅𝑓𝑝 1

If 𝑅𝑓𝑛 =𝑅𝑓𝑝 = R1 =R 2 ,

𝑉0= 𝑉2-𝑉1 i.e the circuit performs subtraction without amplification.

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4. Multiplier and Divider
−𝑅𝑓
The output voltage of an OPAMP in inverting mode is 𝑉0= ∗ 𝑉1
R1

If Rf >R, then the circuit works as multiplier. Suppose, Rf =100 MΩ and R1=10 MΩ, then

VO=-10V1 i.e. the input gets multiplier by a factor 10.

If Rf<R, the circuit acts as divider.

𝑉
Suppose, Rf=10 MΩ and R1 = 100 MΩ then VO = 101 i.e the input gets divided by a factor of
10.

5. Integrator

Here, V+=0

Since for ideal OPAMP, the output voltage VO is zero, so

Vd =V+-V- = 0

or, V+=V-=0

Applying KCL at mode V-,

IC= In
𝑑 𝑉
Or, C𝑑𝑡 (𝑉0 − 𝑉− ) = − 𝑅𝑖

𝑑𝑉0 𝑉
Or, 𝐶 = − 𝑅𝑖
𝑑𝑡

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 𝑑𝑉0 𝑉
Or, = − 𝐶𝑅𝑖
𝑑𝑡

Integrating both sides w.r.to t, we get

1 1
𝑉0 = − 𝑅𝑐 ʃ𝑉𝑖 𝑑𝑡 = − 𝝉 ʃ𝑉𝑖 𝑑𝑡

Where,

𝝉 = RC is the time constant of the RC circuit.

Example

Design an integrator which gives a ramp output of -10 V/ms.

Solution:

As the output is a ramp voltage, the input signal 𝑉𝑖 should be a dc voltage.

Let 𝑉𝑖 =10 V

We know,
1 10
𝑉0=− 𝑅𝐶 ∫ 𝑉𝑖 𝑑𝑡 = − 𝑅𝐶 ∗ 𝑡

𝑉0 10
or, = − 𝑅𝐶 = 10−4
𝑡

If R = 1 KΩ then C=10-6 F=1 μF.

Therefore, RC=10−3

6. Differentiator
Here, V+ = 0 and
V+ - V-= 0
or, V- = V+ = 0
Applying KCL at node V-, we get
IC + If = 0
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 𝑑 𝑉𝑜−𝑉−
Or, 𝐶 𝑑𝑡 (𝑉𝑖 − 𝑉 −) + =0
𝑅
𝑑𝑉𝑖 𝑉𝑜
or, 𝐶 = −
𝑑𝑡 𝑅
𝑑𝑉𝑖
or, 𝑉0 = −𝑅𝐶 𝑑𝑡
𝑑𝑉𝑖
∴ 𝑉0 = −𝜏 where, 𝜏 = 𝑅𝐶
𝑑𝑡

Example
Sketch the circuit of summing Amplifier using OPAMP to get
𝑉0 = -𝑉1+2𝑉2-3𝑉3

Solution,

Here –ve sign of 𝑉0 = -𝑉1+2𝑉2-3𝑉3 indicates inverting terminal input and +ve sign parts of the
given output equation indicates non-inverting terminal input.

Now, 𝑉0 = -𝑉1+2𝑉2-3𝑉3 ……………….(1)

where, -1,+2,-3 indicates the gain.

The resistance between output and inverting terminals i.e Rf and ground and non-inverting
terminals i.e R4 should be identical. Suppose, Rf = R4 = 100 KΩ
Using Superposition theorem, for inverting terminals
𝑅
VO1 = − 𝑅𝑓 ∗ 𝑉1
1
𝑉𝑜1 𝑅
or, = − 𝑅𝑓 = 𝐴 (𝐶𝑙𝑜𝑠𝑒𝑑 𝑙𝑜𝑜𝑝 𝑔𝑎𝑖𝑛)
𝑉1 1
Comparing with equation (1)
𝑅𝑓
− = −1
𝑅1
𝑅1 = 𝑅𝑓 = 100 𝐾Ω
Similarly,
𝑅
𝑉03 = − 𝑅𝑓 ∗ 𝑉3
3
𝑉03 𝑅
or, = − 𝑅𝑓 = −3 using equation (1)
𝑉3 3
𝑅𝑓 100
∴ 𝑅3 = = = 33.33𝐾Ω
3 3
Again considering only V2 and applying superposition theorem for nom-inverting terminals,
𝑅𝑓
V02 = (1 + 𝑅 ) ∗ 𝑉2 ′ …………………….(2)
1 ||𝑅3
where,
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𝑅1 ||𝑅3= 100 || 100/3
100
100∗ 10000 3
3
= 100+100/3 = ∗ 400 = 25 𝐾Ω
3
𝑅4
𝑉2 ′ = (𝑅 ) ∗ 𝑉2 So equation (2) becomes,
4 +𝑅2
𝑅𝑓 𝑅4
𝑉𝑜2 = (1 + 𝑅 ) ∗ (𝑅 ) ∗ 𝑉2
1 ||𝑅3 4 +𝑅2
𝑉𝑜2 100 100
= 𝐴 = 2 = (1 + ) (100+𝑅2) using equation (1)
𝑉2 25
100
or, 2 = (1 + 4) (100+𝑅 )
2
100 2
or, 100+𝑅 = 0.4 = 5
2
or, 0.4𝑅2 +40 = 100

∴ 𝑅2 = 150 𝐾Ω

Instrumentation Amplifier (IA)

An instrumentation amplifier is a dedicated differential amplifier optimized for high input

impedance and high common mode rejection ratio (CMRR) . It is typically used in
applications in which a small differential voltage and a large common-mode voltage are the
inputs.

There are several characteristics of an IA that sets it apart from operational amplifier

i. An OPAMP has very large (Ideally infinite) amount of voltage gain. IA has finite
gain. OPAMP can provide integration, differentiation functions but IA cannot
provide these functions.
ii. IA has a high impedance differential input where as OPAMP has high input
impedance
iii. IA has high common mode voltage gain and high CMRR. OPAMP also has high
gain and CMRR but IA is superior over OPAMP.
iv. IA is a closed loop device with carefully set again. OPAMP itself is an open loop
device with very large gain. This allows IA to be optimized for its role as signal
conditioner of low level signals in large amounts of noise.

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IA consists of two stages. The first stage offers very high input impedance to both input
signals (V1 and V2) and allows to set the gain with a single resistor. The second stage is a
differential amplifier with the output, negative feedback and ground connections.

The above figure shows that the input stage consists of two carefully matched OPAMPs.
Each input V1 and V2 is applied to the non-inverting input terminal of its OPAMP. The
outputs of OPAMPs are connected together through a string of resistors. The two resistors R1,
are internal to integrated circuit while 𝑅𝑔 is the gain setting resistor which may be internal or
externally connected.

Now, V+2= V2

As we know

Vd = V+2 - V-2=0 (For ideal OPAMP, VO = 0 i.e. Vd =0)

V-2=V+2=V2

Similarly

V+1=V1 and

V+1-V-1 = 0

V-1=V+1=𝑉1
𝑉2 −𝑉1
𝐼𝑔 = ……………………(1)
𝑅𝑔

𝑉2 −𝑉1
𝑉01 = 𝐼𝑔 (𝑅𝑔 + 2𝑅1 ) = ( )(𝑅𝑔 + 2𝑅1 ) using equation (1)
𝑅𝑔

2𝑅1
= (𝑉2-𝑉1)(1 + )
𝑅𝑔
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As the second stage is unity gain differential amplifier, the output from second stage is given
by

2𝑅1
𝑉0= 𝑉01 = (𝑉2 − 𝑉1 ) (1 + )
𝑅𝑔

2𝑅1
∴ 𝑉0 = (1 + ) ∗ (𝑉2 − 𝑉1 )
𝑅𝑔

The differential voltage gain is

𝑉0 2𝑅1
= (1 + )
𝑉2 −𝑉1 𝑅𝑔

Thus, by varying the value of 𝑅𝑔 , the gain can be varied.

Signal Conversion

General Consideration of A/D and D/A Conversion

A/D and D/A converters relate analog quantities to digital quantities and vice versa through
an appropriate code called the binary code in which a number is represented by

N=dn-1×2n-1+dn-2×2n-2+……..+d2×22+d1×21+d0×20 ……..(1)

where, the coefficient dn-1,dn-2……………..d2,d1,d0 assume the values of either 0 or 1

In a four bit system converter, it permits a number from 0-15. Hence, the maximum count for
a bit converter is 24-1. Therefore, for n-nit system , maximum count =2n-1.
𝑊𝑒𝑖𝑔ℎ𝑡 𝑜𝑓 𝐿𝑆𝐵 20 1 1
Resolution = 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑐𝑜𝑢𝑛𝑡 = 2𝑛−1 = 2𝑛−1 ≃ 2𝑛

If ER be the full range of the converter (referenced voltage) then the weight (range) of
1
MSB = 2 ∗ 𝑟𝑎𝑛𝑔𝑒 𝑜𝑓 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟

𝐸𝑅
= and
2

1 𝐸
The weight (range) of the LSB = 2𝑛 ∗ 𝑅𝑎𝑛𝑔𝑒 𝑜𝑓 𝑐𝑜𝑛𝑣𝑒𝑟𝑡𝑒𝑟 = 2𝑛𝑅

For a four bit converter having ER as reference or full range voltage, the analog output for
different digital inputs are given as follows:

Digital inputs Analog Inputs

1000 𝐸𝑅 /2
0100 𝐸𝑅 /22
0010 𝐸𝑅 /23
0001 ER/24

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If all bits are high i.e. input is 1111, then the analog output can be obtained by superposition
theorem i.e
𝐸𝑅 𝐸 𝐸 𝐸
𝐸0 = + 2𝑅2 + 2𝑅3 + 2𝑅4
2

= 𝐸𝑅 (1 × 2−1 + 1 × 2−2 + 1 × 2−3 + 1 × 2−4 )

= 𝐸𝑅 (𝑑3 2−1 + 𝑑2 2−2 + 𝑑1 2−3 + 𝑑0 2−4 )

𝐸
= 24𝑅 (𝑑3 23 + 𝑑2 22 + 𝑑1 21 + 𝑑0 20 )

Hence, for n-bit system, output voltage (analog) is given by

𝐸𝑅
𝐸𝑜 = [𝑑 2𝑛−1 + 𝑑𝑛∗2 2𝑛−2 + ⋯ + 𝑑0 20 ]
2𝑛 𝑛−1
Example:

Find out the analog output for a digital input of 1010 if the reference voltage is 8 volt.

Solution,

We know

𝐸𝑅
𝐸𝑜 = [𝐷 23 + 𝑑2 22 + 𝑑1 21 + 𝑑0 20 ]
24 3
8
= 16 [1 ∗ 23 + 0 ∗ 20 + 1 ∗ 21 + 0 ∗ 20 ]

1 10
= 12 (8 + 2) = = 5 𝑉𝑜𝑙𝑡𝑠
2

Analog to Digital Converters (ADC)

Why analog signal is converted to digital form?

1. Most of the real world physical quantities such as voltage, current, temperature, time
etc are available in analog form. But it is difficult to process, store or transmit them
without introducing considerable error. So , for processing, transmission and storage
purposes , it is often convenient to express these variables into digital form.
2. Digital form gives better accuracy and reduces noise.

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 i. Successive Approximation ADC (Potentiometric Type)

Successive approximation ADC consists of comparator, control logic SAR (Successive

Approximation Resistor), DAC and Reference source.
VA represents the analog input voltage,. When START button is pressed, SAR sets the MSB
high i.e. with all other bits to zero so that the trial code becomes 1000 (for 4-bit). DAC
converts the trial code into analog equivalent output of DAC given as
𝐸𝑅
𝐸𝑜 = 𝑛 [𝑑𝑛−1 2𝑛−1 + 𝑑𝑛∗2 2𝑛−2 + ⋯ + 𝐷0 20 ] 𝑓𝑜𝑟 𝑛 − 𝑏𝑖𝑡𝑠
2
Eo is compared with VA by comparator.
If VA> EO, then SAR lefts MSB at 1 and makes the next lower significant bit 1 and further
compares.
If VA < EO, then SAR resets MSB at 0 and makes the next lower significant bit 1. This
procedure is continued for all subsequent bits one at a time until all bit positions have been
tested.
When VA= EO, the comparator changes the state and this can be taken as the End-of-
conversion (EoC)
For example, for 4-bits signal
1st approximation,
Input to DAC = 1000
𝐸
Output from DAC = EO = 2𝑛𝑅 [𝐷3 23 + 𝑑2 22 + 𝑑1 21 + 𝑑0 20 ]
𝐸𝑅
= [1 ∗ 23 + 0 ∗ 20 + 1 ∗ 21 + 0 ∗ 20 ]
24
8
= 16 𝐸𝑅
Now, VA>EO, then the bit D3 remains at 1 and the next bit i.e. d2 is set to 1.

2nd Approximation
Input to DAC = 1100
𝐸𝑅 12
Output from DAC = EO = [1 × 23 + 1 × 22 ] = 𝐸𝑅
24 16
Now, VA<EO, the the bit d2 is reset to 0 and the next bit i.e. is set to 1.

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3rd approximation
Input to DAC = 1010
𝐸 10
Output from DAC = EO= 16𝑅 (1 × 23 + 1 × 21 ) = 16 𝐸𝑅
Now VA>EO then the bit d1 remains at 1 and the next bit dO is set to 1.

4th approximation
Input to DAC = 1011
𝐸𝑅 11
Output from DAC= 𝐸𝑂 = (1 ∗ 23 + 1 ∗ 21 + 1 ∗ 20 ) = 𝐸𝑅
16 16

Now, VA<EO, then the bit dO is reset to 0 and digital equivalent of the analog input voltage
will be 𝑑3 𝑑2 𝑑1 𝑑0 = 1010

Example:

Find the successive approximation A/D output for a 4 bit converter to a 3.217 volt input if the
reference voltage is 5 Volt.

Solution

i. Set 𝑑3 = 1
𝐸𝑅
∴ 𝑜𝑢𝑡𝑝𝑢𝑡 = 𝐸𝑂 = 𝑛
[𝐷3 23 + 𝑑2 22 + 𝑑1 21 + 𝑑0 20 ]
2
5
𝐸𝑂 = 24 (1 ∗ 23 ) = 2.5 𝑉

Now, 3.218>2.5 and ∴ 𝑠𝑒𝑡 𝑑3 = 1

ii. Set 𝑑2 = 1
5 5
∴ 𝑜𝑢𝑡𝑝𝑢𝑡 (𝐸𝑂 ) = (1 ∗ 23 + 1 ∗ 22 ) = ∗ 12 = 3.75𝑉
16 16
Now, 3.217<3.75 and set d2=0
iii. Set d1=1
5 5
∴ 𝑜𝑢𝑡𝑝𝑢𝑡 (𝐸𝑂 ) = (1 × 23 + 1 × 21 ) = ∗ 10 = 3.125𝑉
16 16
Now, 3.217>3.125 and set d1=1
iv. Set dO=1
5 5
∴ 𝑜𝑢𝑡𝑝𝑢𝑡 (𝐸𝑂 ) = (1 ∗ 23 + 1 ∗ 21 + 1 ∗ 20 ) = ∗ 11 = 3.4375𝑉
16 16
Now, 3.217<3.4375 and set dO = 0
Thus, the output of A/D converter is 1010

Successive Approximation Type ADC are widely applied because of their combination of
high resolution and speed. They can perform conversions within 1 to 50 micro seconds rather

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than milliseconds required by stair case Ramp, Dual slope and Voltage to frequency
converter types. However, they are more expensive than these slower types.

ii. Dual Ramp (Dual Slope) ADC

The circuit diagram shows, the integrating type Dual Ramp(Dual Slope) ADC. It
performs conversion in an indirect manner first changing analog input to a linear
function of time or frequency and then to a digital code. Dual slope ADC is the most
widely used integrating type ADC. Binary counter is RESET and results 0000 digital
output (4 bits) switch (SW) moves to 0 position and Vin is fed to an integrator which
𝑉𝑖𝑛
produces a Ramp output wave from (𝑉𝑂 = − ∗ 𝑡) . The capacitor charges. The
𝑇
ramp signal starts at zero and increases for fixed interval of time T1, equal to the
maximum count of the counter multiplied by the clock frequency. The slope of the
ramp signal is proportional to Vin. It results VC (Comparator output) high. AND gate
enables and the counting starts (0000………….1111) where 2n-1 pulses are applied.
For pulse 2n i.e. at the end of the ineterval T1, counter resets. Carry Bit (CO) of the
ripple counter causes the switch to move to –VRef position. In this position, a constant
current –VRef/R begins to discharge the capacitor. The count continues until capacitor
C being discharged completely i.e. VO<0. As VO becomes positive , VC becomes low
which disables AND gate and counting stops. The resultant count is proportional to
the input voltage Vin.

Advantages:
The main advantages are :
- Good accuracy of conversion
- Low cost

Disadvantage:

-slow speed of operation

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 Now, Qcharging = Qdischarging
𝑖𝑇1 𝑖𝑡𝑟 𝑉𝑖𝑛 𝑉𝑅𝑒𝑓
Q= CV = 𝑜𝑟, 𝑇1 = 𝑡𝑟
𝐶 𝐶 𝑅 𝑅

𝑡
Or, 𝑉𝑖𝑛 = 𝑉𝑅𝑒𝑓 (𝑇𝑟 ) ∴ 𝑉𝑖𝑛 ∝ 𝑡𝑟 i.e. The count recorded is proportional to the input
1
voltage.

iii. Stair case Tamp Type (Counting Type ) ADC

Binary counter is reset to zero count by the reset pulse. The digital output is zero
equivalent. So, the output of DAC is zero i.e. Vd=0. Since Va(input analog voltage)
>Vd, output of the comparator is high i.e. x is high (1). When START button is
pressed, AND gate is enabled and the clock pulse is counted by the Binary counter.
There is Digital output. But the counting does not stop here. The equivalent DAC
output (Vd) is compared with Va by the comparator.
If Va>vd , x is high, AND gate is enabled. The clock pulses are passed through the
AND gate and counted by the Binary counter. Digital output is obtained which are fed
to the computer or any other signal processing.
If Va<Vd , x is low i.e. 0 and AND gate is disabled. This stops the counting. At the
time Vd>̲ Va, the digital output of the counter represents the analog input voltage.

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 For a new value of analog input Va , a second RESET pulse is applied to clear the
counter. Upon the end of the RESET and with START button ON, the counting
begins again.

Serious Drawbacks:
a. The counter frequency must be low enough to give sufficient time for the
DAC to settle and for the comparator to respond.
b. When Va>Vd, x is high and AND gate is enabled and counter counts and
digital output is one bit more than the exact value. To remove this problem,,
we can use UP/DOWN counter. In this process, when DAC output is more
than Va , the counter reverses the direction and count down by one count and it
decreases the count by 1 LSB.

iv. Flash or parallel Type ADC

The circuit diagram of the 3 bit parallel type (Flash Type) ADC is shown above. In
this technique, the input voltage is fed simultaneously to one input of each
comparator. The other input of the comparator is a reference voltage. The circuit
consists of a resistive divider network, 8 OPAMP comparators and 8 to 3 line
encoder. Its truth table is given below;

Advantages:
It has very high speed because the conversion takes place simultaneously rather than
sequentially .Typical conversion time is 100 ns or less.

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 Disadvantages:
i. Large no. of comparators are required.
ii. No. of comparators required almost doubles for each added bit
iii. The larger the no. of bit, the more complex is the priority encoder.

Input voltage X7 X6 X5 X4 X3 X2 X1 X0 Y2 Y1 Y0
(Va)
0 – VR/8 0 0 0 0 0 0 0 1 0 0 0
VR/8 - 2 VR/8 0 0 0 0 0 0 1 1 0 0 1
2 VR/8- 3 0 0 0 0 0 1 1 1 0 1 0
VR/8
3 VR/8 - 4 0 0 0 0 1 1 1 1 0 1 1
VR/8
4 VR/ 8- 5 0 0 0 1 1 1 1 1 1 0 0
VR/8
5 VR/8-6 VR/8 0 0 1 1 1 1 1 1 1 0 0
6 VR/8-7 VR/8 0 1 1 1 1 1 1 1 1 1 0
7 VR/8 -8 1 1 1 1 1 1 1 1 1 1 1
VR/8

Digital to Analog Conversion (DAC)

Typical applications of DAC include microcomputer interfacing, CRT graphics generation,

programmable power supplies, digitally controlled gain circuits, digital filters etc.

i. Weighted Resistor Network (WRN) DAC

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 In the WRN DAC, the resistance are weighted reverse eight binary system i.e the
resistance associated with the MSB has the least value and as we move from MSB to
LSB, the resistance value increases by a factor of 2 as shown.
Let resistance associated with MSB for n-bit is R i.e
𝐷𝑛−1 → 20 𝑅
𝐷𝑛−2 → 21 𝑅
𝐷(𝑛−3) → 22 𝑅
.

.
𝐷0 → 2𝑛−1 𝑅
Hence, for 4 bit system we have
𝐷3 → 20 𝑅
𝐷2 → 21 𝑅
𝐷1 → 22 𝑅
𝐷0 → 23 𝑅
Vref is applied to all resistors through electronic switches and another input to the
electronic switch is the digital input. Suppose if digital input is 1001, the switches
associated with D3 and DO are only closed i.e. these switches respond to binary 1. If
the input is 1000, then the current is given by
𝑖3 = 𝑉𝑟𝑒𝑓 /20 𝑅
Similarly for other inputs,
𝑉𝑟𝑒𝑓
0100 → 𝑖2 = 2 𝑅
0010 → 𝑖1 = 𝑉𝑟𝑒𝑓 /22 𝑅
𝑉𝑟𝑒𝑓
001 → 𝑖0 = 23 𝑅
If all the input bits are high (1111) , then total current i can be obtained by
superposition theorem.
𝑖 = 𝑖3 + 𝑖2 + 𝑖1 + 𝑖0
𝑉𝑟𝑒𝑓
= (1 + 1 ∗ 2−1 + 1 ∗ 2−2 + 1 ∗ 2−3 )
𝑅

𝑉𝑟𝑒𝑓
= (1 ∗ 23 + 1 ∗ 22 + 1 ∗ 21 + 1 ∗ 20 )
23 𝑅
𝑉𝑟𝑒𝑓
= 3 (𝐷3 23 + 𝐷2 22 + 𝐷1 21 + 𝐷0 20 )
2 𝑅

Advantages:
- easy principle/construction
- fast conversion

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 𝑉𝑟𝑒𝑓
∴ 𝑉𝑂 = −𝑖𝑅𝑓 = − ∗ 𝑅𝑓 (𝐷3 23 + 𝐷2 22 + 𝐷1 21 + 𝐷0 20 )
23 𝑅
Hence, for n-bits system

𝑉𝑟𝑒𝑓
𝑉𝑂 = − 𝑛−1
∗ 𝑅𝑓 (𝐷𝑛−1 2𝑛−1 + ⋯ … … … . . +𝐷0 20 )
2 𝑅
Disadvantages:

1. As the number of n-bit goes on increasing, the resistance values as well as the
complexity of the circuit increases. So, cost will be high.
2. As the number of bit increases, the tolerance of the resistance associated with LSB
may exceed the value of resistance in MSB.
3. As the number of bit increases, the variation in the value of the resistance will be
large and so the power rating. This is not required in the process of IC
manufacturing.

ii. R-2R Ladder Network DAC

In a ladder network right of each node, there are two equal resistors and each having
the value 2R and placed across. Hence, the current entering to the node is divided as
I/2n where n is the number of nodes starting from MSB to LSB i.e. it generates a
current given by I/2, I/22, I/23, …………………, i/2n . So, the ladder network
generates a binary sequence of current. If all bits of digital inputs are high i.e. for a 4-
bit converter, digital input is 1111, then the total current I is obtained by superposition
theorem
𝐼 𝐼 𝐼 𝐼
𝑖= + 2+ 3+ 4
2 2 2 2
= 𝐼(1 ∗ 2−1 + 1 ∗ 2−2 + 1 ∗ 2−3 + 1 ∗ 2−4 )
𝑉𝑟𝑒𝑓
= (𝐷3 2−1 + 𝐷2 2−2 + 𝐷1 2−3 + 𝐷0 2−4 )
𝑅
𝑉𝑟𝑒𝑓
= 4 (𝐷3 23 + 𝐷2 22 + 𝐷1 21 + 𝐷0 20 )
2 𝑅
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 Now, the analog output voltage VO is given by
𝑉𝑟𝑒𝑓
𝑉𝑂 = −𝑖𝑅𝑓 = − 4 ∗ 𝑅𝑓 [𝐷3 23 + 𝐷2 22 + 𝐷1 21 + 𝐷0 20 ]
2 𝑅
Therefore, for n-bits
𝑉
VO = − 2𝑟𝑒𝑓
𝑛𝑅
∗ 𝑅𝑓 [𝐷𝑛−1 2𝑛−1 + 𝐷𝑛−2 2𝑛−2 + ⋯ + 𝐷0 20 ]

Advantages:
- Only two resistor values
- Does not need as precision resistors as Binary weighted DAC
- Cheap and easy to manufacture.

Disadvantage:
- Slower conversion rate

Interference Signals and their elimination

Interference is contamination by extraneous signals. This may be signals from other

transmitter, power cables, machineries, switching, circuits, human sources and many more.

Appropriate filtering can remove interference to the extent that the interfering signals occupy
different frequency bands than the desired signal. Interference may be the coherent signals
from other systems (and sometimes the circuit itself) that enters into the desired system.
Interference is external signals in opposition to noise. For this reason, the best way to
minimize its effects is to identify the interference paths to our circuits/systems. Its major
limitation is in precision measurements and the detectability (resolution).

The major parts for interference are:

i. Signals coupled in inputs and outputs

ii. Capacitive coupling
iii. Inductive coupling

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 iv. Magnetic coupling
v. RF coupling

Capacitive coupling

- Conductors in the close proximity interference with each other

- Implements high pass RC filter across the noise source and the signal
- Noise appearing on the signal proportional to the noise source level
- Problem with high frequency and high impedance signals

Inductive coupling

- Magnetic flux generated due to noise circuit will induce current in neighboring circuits
- Roughly proportional to the areas of the two circuits
- Noise generated is an added voltage in parallel, therefore independent of signal level.
- Can be differentiated from capacitance by changing the load impedance (if noise level
stays the same, then we have inductive coupling)

Minimizing of interference Effects

- Avoid direct capacitive coupling between signals tracks using ground planes and guard
rings.
- Avoid magnetic coupling avoiding loops(use of twisted pair)
- Protecting power supply inputs with feedthroughs to avoid interference signal paths
through supply voltages.
- use shielding to avoid RF coupling when necessary.
- Use separate grounds for digital/analog signals
- Use only one point to ground the circuit.
- Use separate power supply when possible

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