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DSD With FPGA Mid - I QP

The document outlines the structure and content of the M.Tech I Year I-Semester Mid-I Examinations for the subject Digital System Design with FPGA at Jayamukhi Institute of Technological Sciences. It includes course outcomes, a two-part question paper with multiple-choice questions and descriptive questions, and assessment criteria. The exam focuses on FPGA design approaches, fault models, test pattern generation, and fault diagnosis in sequential circuits.

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thouti meghana
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15 views3 pages

DSD With FPGA Mid - I QP

The document outlines the structure and content of the M.Tech I Year I-Semester Mid-I Examinations for the subject Digital System Design with FPGA at Jayamukhi Institute of Technological Sciences. It includes course outcomes, a two-part question paper with multiple-choice questions and descriptive questions, and assessment criteria. The exam focuses on FPGA design approaches, fault models, test pattern generation, and fault diagnosis in sequential circuits.

Uploaded by

thouti meghana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES

(AUTONOMOUS)
M.Tech- I Year I-Semester Mid-I Examinations, DEC - 2024
Subject : Digital System Design with FPGA
Time : 2 Hours
Branch: Embedded Systems Max.Marks:30
Note: This question paper contains two parts. Part A&B
Course Outcomes for Assessment in this Test:
COs Description of Course outcome
1 To exposes the design approaches using FPGAs..
2 To provide in depth understanding of Fault models.
3 To understands test pattern generation techniques for fault detection
4 To design fault diagnosis in sequential circuits
5 To provide understanding in the design of flow using case studies
PART- A (20X1/2=10 Marks)
Marks
1. The FPGA is a programmable logic that combines the characteristics of ½
a. RAM & PROM
b. ROM & PLA
c. RAM & PAL
d. RAM & ROM
2. Programmable Logic array has ½
a. Fixed OR plane followed by a programmable AND gate
b. Fixed AND plane followed by a programmable OR gate
c. Programmable OR gate followed by a fixed AND gate
d. Programmable AND gate followed by a fixed OR gate
3. Programmable array Logic has ½
e. Fixed OR plane followed by a programmable AND gate
f. Fixed AND plane followed by a programmable OR gate
g. Programmable OR gate followed by a fixed AND gate
h. Programmable AND gate followed by a fixed OR gate
4. What is another name for digital circuitry called sequential logic? ½
a) logic macrocell
b) logic array
c) flip-flop memory circuitry
d) inverter

5. SPLDs, CPLDs, and FPGAs are all which type of device? ½


a) PAL
b) PLD
c) EPROM
d) SRAM

6. A GAL is essentially a ________. ½


a) non-reprogrammable PAL
b) PAL that is programmed only by the manufacturer
c) very large PAL
d) reprogrammable PAL

7. ________ are used at the inputs of PAL/GAL devices in order to prevent ½


input loading from a large number of AND gates.
a) Simplified AND gates
b) Fuses
c) Buffers
d) Latches

8. The GAL16V8 has: ½


a) 16 dedicated inputs.
b) 8 special function pins.
c) 8 pins that are used as inputs or outputs.
d) All of the above

9. How many macrocells are in a MAX700S LAB? ½


a) 8
b) 16
c) 32
d) 64

10. An SPLD listed as 16H8 would have ________. ½


a) active-HIGH outputs
b) active-LOW outputs
c) variable-level outputs
d) latches at the outputs

11. The complex programmable logic device (CPLD) contains several PAL-type ½
simple programmable logic devices (SPLDs) called:
a) macrocells
b) microcells
c) AND/OR arrays
d) fuse-link arrays

12. FPGA stands for ½


13. Number of user I/O pins for XC9500 ½
a. 36-288
b. 32-512
14. The Altera MAX 7000 series ________. ½
a) uses an E2PROM process technology
b) can have between 2 and 16 LABS and I/O control blocks
c) is available with DC supply voltages between 2.5 V and 5 V
d) all of the above

15. What programmable technology is used in FPGA devices? ½


a) SRAM
b) FLASH
c) Antifuse
d) All of the above

16. How many combinations are handled in an LUT? ½


a) 4
b) 8
c) 16
d) 32

17. Macrocell consist of _____________ ½


18. CLB stands for ½
19. Which of the following testing procedures uses the JTAG IEEE standard? ½
a) Bed-of-nails
b) Flying probe
c) EXTEST
d) Boundary scan

20. Field-programmable gate arrays (FGPAs) use ________ memory technology, ½


which is ________.
a) DRAM, nonvolatile
b) SRAM, nonvolatile
c) SRAM, volatile
d) RAM, volatile

PART-B (4x5=20) Mapping Bloom’s Marks


Answer any 4 questions Cos Taxanomy
Levels
1 Briefly explain the main differences between PAL CO1 L1 4
and PLA
2 Draw and Explain the FPGA architecture CO4 L4 4
3 Describe the process of Clock Management in CO2 L2 4
Programmable Logic Devices
4 Design the sequence Detector CO3 L3 4
5 What is the need and design strategies for multi clock CO1 L1 4
sequential circuits?
6 Explain the Analysis by signal tracing and timing charts. CO4 L4 4
Assessment Summary
Cos Remember Understand Apply Analyze Evaluate Create Total
1 1 1
2 1 1
3 1 1 2
4 1 1

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