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Printed Copy - Vlsi & Chip Design Lab

The document outlines the objectives and experiments for a VLSI and Chip Design Laboratory course, focusing on Hardware Descriptive Language (HDL) and VLSI circuit design in both digital and analog domains. It includes a list of experiments that involve designing and simulating various digital circuits using HDL and implementing them on FPGA. The expected outcomes detail the skills students will acquire, including HDL coding, FPGA integration, and IC design testing and verification.

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30 views2 pages

Printed Copy - Vlsi & Chip Design Lab

The document outlines the objectives and experiments for a VLSI and Chip Design Laboratory course, focusing on Hardware Descriptive Language (HDL) and VLSI circuit design in both digital and analog domains. It includes a list of experiments that involve designing and simulating various digital circuits using HDL and implementing them on FPGA. The expected outcomes detail the skills students will acquire, including HDL coding, FPGA integration, and IC design testing and verification.

Uploaded by

vieeralingaam.g
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EV23521 VLSI and Chip Design Laboratory LTP

C00
21

OBJECTIVES:
 To learn Hardware Descriptive Language (Verilog/VHDL).
 To Study the fundamental principles of Digital System Design using HDL and FPGA.
 To learn the fundamental principles of VLSI circuit design in the digital domain
 To Study the fundamental principles of VLSI circuit design in the analog domain
 To provide hands-on design experience with EDA
LIST OF EXPERIMENTS
1. Design of basic combinational and sequential (Flip-flops) circuits using HDL.
Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
2. Design an Adder; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
3. Design and implement a Universal Shift Register using HDL. Simulate it using
Xilinx/Altera Software
4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
5. Design a Finite State Machine (Moore/Mealy) using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
6. Design a 3-bit synchronous up/down counter using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
7. Design a 4-bit Asynchronous up/down counter using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate
Manual/Automatic Layout.
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate
Manual/Automatic Layout
10. Design and Simulate a CMOS Inverting Amplifier.
11. Design and Simulate basic Common Source, Common Gate, and Common Drain
Amplifiers.
12. Design and simulate simple 5 transistor differential amplifier.
TOTAL: 30 PERIODS
OUTCOMES:
At the end of the course, the students will be able to
CO1: Understand and write HDL code for basic as well as advanced digital integrated circuit
CO2: Import the logic modules into FPGA Boards
CO3: Understand Synthesize Place and Route the digital Ips
CO4: Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDA
tools
CO5: Test and Verification of IC design

1
COs-POs & PSOs MAPPING
PO PSO
CO 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
1 2 - - - - - - - - - - - 2 3 2
2 3 3 1 1 - - - - - - - - 2 1 2
3 1 2 2 2 - - - - - - 1 1 2 2 2
4 - 1 3 3 1 - - - - - 1 1 2 2 2
5 3 3 3 3 1 - - - - - 1 1 2 2 2
Avg. 2.2 2.2 2.2 2.2 1 - - - - - 1 1 2 2 2

1 - Low, 2 - medium, 3 - high, ‘-“- no correlation

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