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Unit2 OnlineResources

The document covers the communication interface of the Internet of Things course, focusing on interfacing with the 8086 microprocessor and its features, including instruction queue, pipelining, and memory interfacing. It also details the Programmable Peripheral Interface (PPI) 8255 architecture, its operating modes, and interfacing methods for various components like DAC, ADC, and stepper motors. Key aspects include the configuration of ports and modes of operation for effective data handling.

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simrandnagraj
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3 views23 pages

Unit2 OnlineResources

The document covers the communication interface of the Internet of Things course, focusing on interfacing with the 8086 microprocessor and its features, including instruction queue, pipelining, and memory interfacing. It also details the Programmable Peripheral Interface (PPI) 8255 architecture, its operating modes, and interfacing methods for various components like DAC, ADC, and stepper motors. Key aspects include the configuration of ports and modes of operation for effective data handling.

Uploaded by

simrandnagraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Course:

Internet of Things
(217529)

Unit 2- Communication Interface


Contents

❖ Basic Peripherals & their interfacing with 8086


❖ Semiconductor Memory Interfacing-Dynamic RAM Interfacing
❖ Interfacing I/O ports-PIO-8255
❖ Modes of operation
❖ interfacing Analog-Digital Data converter
❖ stepper motor interfacing
8086 Microprrocessor
Features of 8086

● The most prominent features of a 8086 microprocessor are as follows −


● It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
● It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
● It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz
o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
● It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
● Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
● Execute stage executes these instructions. It has 256 vectored interrupts. It
consists of 29,000 transistors.
Interfacing 8 bit input Port
Interfacing 16 bit input Port
Interfacing 8 bit Output Port
Interfacing 16 bit Output Port
Semiconductor memory Interfacing
Minimum Mode 8086 System
Interfacing 128K RAM & 2K ROM with 8086 in
Minimum Mode
Interfacing Memory with 8086 in Minimum Mode
DRAM Interfacing
Programmable Peripheral Interface
PPI 8255 Architecture

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
● Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
● Port B is similar to PORT A.
● Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be
programmed in three different modes, i.e. the first mode is named as mode 0, the
second mode is named as Mode 1 and the third mode is named as Mode 2.
Programmable Peripheral Interface
PPI 8255 Architecture

Operating Modes
8255A has three different operating modes −
● Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports. Each port can be programmed in either input mode or output mode where
outputs are latched and inputs are not latched. Ports do not have interrupt capability.
● Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured
as either input or output ports. Each port uses three lines from port C as handshake
signals. Inputs and outputs are latched.
● Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B.
Programmable Peripheral Interface
PPI 8255 Architecture

Features of 8255A
The prominent features of 8255A are as follows −
● It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
● Address/data bus must be externally demux'd.
● It is TTL compatible.
● It has improved DC driving capability.
Programmable Peripheral Interface
PPI 8255 Architecture

View
Control Word Format- For Bit/Reset Mode
Control Word Format- For I/O Mode
Interfacing DAC
Interfacing ADC
Interfacing DAC
Interfacing Stepper Motor

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