Sequential Logic Circuits

Advanced design principles

Ing. Michal Lucki, PhD.

Czech Technical University in Prague
Faculty of Electrical Engineering
Department of Telecommunication
Sequential finite state machine
Design stages
Synchronous Moore machine.
Transient and output functions.
From verbal task to functions / circuit
 Sequential finite state machine
• In combinational logics, a current state of outputs depends only on current values at the inputs
• In sequential logics, different output values can be assigned for the same inputs. This is because a
current state of outputs depends not only on current inputs, but also on the past value or on the
sequence of past input values.
• a finite number of states is determined by a current internal state and values at the inputs, is
known as Mealy machine - asynchronous
• In a finite state Moore machine - synchronous, an output is determined only when the internal
state is updated (which is still dependent on the inputs).
• Combinational logiccircuit
Output = f (inputs)
• Sequential synchronous Moore machine
Output = f (internal memory)
Internal memory = f (inputs)
• Sequential asynchronous Mealy machine
Output = f(internal memory, inputs)
Internal memory = f (inputs)
Ing. Michal Lucki, PhD. 3
In the following practical designs, we will focus on
SYNCHRONOUS solution (Moore machines) only

Ing. Michal Lucki, PhD. 4

Case study 1 - design of a Moore machine
Design a synchronous sequential machine for a door lock (Fig.
1.), which unlocks it by using two buttons: a and b. When a
button is pressed or hold, a variable associated with it is logical
1. Revealed button means logical 0.
 The right sequence to open the lock is 00, 10, 11.The
unlocking takes place while pressing last right combination
(not after it so it doesn’t wait for revealing the buttons).
 The wrong combination pressed at the keyboard starts an
alert and the lock remains locked.
 Once it is opened, any combination of buttons does not
affect the lock, it remains unlocked (for simplicity and good
readability of solution).

A door lock with two keys a and b to

unlock and clr to clear
Ing. Michal Lucki, PhD. 5
Case study 1 - design of a Moore machine
There are two input variables a and b corresponding to
two buttons at the keyboard.
Internal state: A
The transitions A→A’ required to unlock: 00,10,11.
The outputs are Y1 and Y2:
1, 𝑢𝑛𝑙𝑜𝑐𝑘 𝑖𝑡
𝑌1 = ቊ
0, 𝑙𝑜𝑐𝑘𝑒𝑑
1, 𝑎𝑙𝑒𝑟𝑡
𝑌2 = ቊ
0, 𝑛𝑜 𝑎𝑙𝑒𝑟𝑡

Commercially available locks have more keys and require longer sequences, our goal here is to
display the general procedure, avoid huge number of tables and obtain a readable scheme.
Ing. Michal Lucki, PhD. 6
 State diagram
There are two input variables a and b corresponding to
two buttons at the keyboard.
Internal state: A
The transitions A→A’ required to unlock: 00,10,11.
The outputs are Y1 and Y2:
1, 𝑢𝑛𝑙𝑜𝑐𝑘 𝑖𝑡
𝑌1 = ቊ
0, 𝑙𝑜𝑐𝑘𝑒𝑑
1, 𝑎𝑙𝑒𝑟𝑡
𝑌2 = ቊ
0, 𝑛𝑜 𝑎𝑙𝑒𝑟𝑡

State diagram of a Moore machine, where outputs are the

functions of internal state.
Ing. Michal Lucki, PhD. 7
Transition table
ab
A 00 01 11 10 Y1Y2

1 1 4 4 2 00

2 4 4 3 2 00

3 3 3 3 3 10

4 4 4 4 4 01

A’
Transition table of a Moore machine containing
information on internal states and the outputs

Ing. Michal Lucki, PhD. 8

Encoding Encoded transition table containing information
about Q1→Q1’ and Q2→Q2’ transitions.
ab
A 00 01 11 10 Y1Y2 ab
Q1Q2 00 01 11 10 Y1Y2
1 1 4 4 2 00 00 00 10 10 01 00
1 → 00
2 4 4 3 2 00
2 → 01 01 10 10 11 01 00

3 3 3 3 3 10 3 → 11
11 11 11 11 11 10
4 → 10
4 4 4 4 4 01 10 10 10 10 10 01
A’ Q1’Q2’
Note that it is not the conversion from decimal to binary values. One can name the states using any symbols instead
of decimal numbers, and assign them any binary string. However, to make further processing easier, it is
recommended to assign code words of a Gray code to avoid swapping rows in future Karnaugh maps. Then, the
particular rows in a transition table will become neighbor rows in Karnaugh maps.
Ing. Michal Lucki, PhD. 9
 We need to find hardware to
implement transient functions
(store/update 0s and 1s):
Flip-flops
with the focus on D-type flip-flop
RS latch (RS = reset, set)

Example: reset goes active:

Ing. Michal Lucki, PhD. 11

D-latch (D = data type) – RS + ENABLE

Ing. Michal Lucki, PhD. 12

D-type flip-flop
Positive edge triggered D-type flip flop -
whenever it’s a rising edge of the clock, data
from D is copied
to Q. Non-Q is complementary to Q. Otherwise,
i.e. during the clock or at its falling edge, data are
not copied and the state value at Q and non-Q
are remembered.

Negative edge triggered D-type flip flop -

whenever it’s a falling edge of the clock, data
from D is copied to Q. Non-Q is
complementary to Q. Otherwise, i.e. during
the clock or at its rising edge, data are not
copied and the state value at Q and non-Q are
remembered.
Ing. Michal Lucki, PhD. 13
Negative vs. positive edge triggered flip-flop

Ing. Michal Lucki, PhD. 14

D-type flip-flop with
asynchronous/synchronous clear
Some flip-flops have an additional
input called ~clear, which forces q to
0, irrespective of the value on the data
input. In the asynchronous case, the
effect of ~clear going active is
immediate.

In the synchronous case the

effect of ~clear is
synchronized to the active
edge of the clock.

Ing. Michal Lucki, PhD.

 D-type flip-flop in a TTL series

Note that for a D-type flip-flop, D is identical to Q’ value. It makes the design simpler – to
implement any transition between Q and Q’ values, you must know what binary data at
D must be sent to it to trigger such transition. Practically, you know that D is equal to Q’.
This shortcut can be used only in D-type flip-flops.
Ing. Michal Lucki, PhD. 16
Let us go back to our desing
and use D-type flip-flops
We will use two D-type flip-flops, i.e. we can use 7474 TTL components.
Practically we specify data for D to implement Q-> Q’, but D = Q’

Transitions of a D-type
flip-flop (general).
D is same as Q’
 Selection of HW components: D-type flip-flops
What value must be sent to D so that transition from Q to Q’ is observed?
ab ab ab
00 01 11 10 Y1Y2 Q1Q2 00 01 11 10
Q1Q2 Q1Q2 00 01 11 10
00 00 10 10 01 00 00 0 1 1 0 00 0 0 0 1

01 10 10 11 01 00 01 1 1 1 0 01 0 0 1 1

11 11 11 11 11 10
11 1 1 1 1 11 1 1 1 1

10 1 1 1 1 10 0 0 0 0
10 10 10 10 10 01
D1 D2
Q1’Q2’ D1 D2 𝐷1 = 𝑏 ∣ 𝑄1 ∣ 𝑎ത 𝑄2 ത
𝐷2 = 𝑄1 𝑄2 ∣ 𝑎 𝑄2 ∣ 𝑎 𝑏𝑄1
Note that for a D-type flip-flop, D is
Karnaugh maps for D1 and D2 function
identical to Q’ value.
implemented by two flip-flops.
This simplification works only for D-type flip-flop Ing. Michal Lucki, PhD. 18
 Outputs
In synchronous designs, outputs depend only on the memory, not inputs.
Inputs go first to the memory and then at the next clock, the output is updated
based on the memory (flip-flops).
ab
Q1Q2 00 01 11 10 Y1Y2
Q1 Q1
Q2 0 1 0 1
00 00 10 10 01 00 Q2
0 0 0 0 0 1
Outputs do not
01 10 10 11 01 00
depend on a , b
1 0 1 1 0 0
11 11 11 11 11 10
Y1 Y2
10 10 10 10 10 01
𝑌1 = 𝑄1 𝑄2 𝑌2 = 𝑄1 𝑄2
Q1’Q2’
Note that outputs are functions of Functions of outputs of the lock.
internal memory ONLY (not the
function of inputs) Ing. Michal Lucki, PhD. 19
Final scheme of a machine
a b CLK CLR

CLR

& CLK Q1

D1 Q1 y1
&

CLR
y2
& &
CLK Q2

& D2 Q2

&

Synchronous sequential logical circuit for the designed finite state machine
Ing. Michal Lucki, PhD. 20
JK flip-flop

Ing. Michal Lucki, PhD.

T flip-flop (Toggle)

Ing. Michal Lucki, PhD.

Transition tables for flip-flops

Note that for a D-type flip-flop, D is identical to Q’ value. It makes the design simpler – to implement any
transition between Q and Q’ values, you must know what binary data at D must be sent to it to trigger such
transition. Practically, you know that D is equal to Q’. So if you want the flip-flop to set a 1, send it a 1 at the D
input, if you want the flip-flop to set a 0, send it a 0 at the D input. This shortcut cannot be used for the
remaining flip-flops, you have to carefully check up with the above tables, what to send in order to achieve the
required updates at the output(s)

Ing. Michal Lucki, PhD.

Sequential Mealy machine
Transient and output functions

Ing. Michal Lucki, PhD.

Czech Technical University in Prague
Faculty of Electrical Engineering
Department of Telecommunication

Ing. Michal Lucki, PhD. 24

 Sequential Mealy machine
A finite number of states is determined by a In a finite state Moore machine, an output is
current internal state and values at the inputs, is determined when the internal state is updated
known as Mealy machine (based on inputs)

Mealy finite state machine Moore finite state machine

Note that inputs influence both: internal states and Note that inputs influence internal states only, outputs
outputs – without waiting for the update update of state are updated synchronously based on the updated state
information, i.e. without waiting for the next rising edge of information, i.e. when the next rising edge of a clock is
a clock (can be done in an aynchronous mode, during the detected (synchronously). Inputs influence outputs in
transition). Inputs influence outputs in two ways: directly one way: only through the internal states
and through the internal states Ing. Michal Lucki, PhD. 25
Binary adder solved as asynchronous
sequential Mealy machine
There are two internal states:
A1 – an addition without carry in (p = 0)
A2 – an addition with carry in (p = 1)

0 + 0 + no carry in from the previous operation

results in 0 without new carry in
0 + 0 + carry in from the previous operation
results in 1 without new carry in

0 + 1 (or 1 + 0) + no carry in from the previous operation results in 1 without new carry in
0 + 1 (or 1 + 0) + carry in from the previous operation results in 0 with new carry in
1 + 1 + no carry in from the previous operation results in 0 with new carry in to the more significant bit
1 + 1 + carry in from the previous operation results in 1 with new carry in to the more significant bit
Ing. Michal Lucki, PhD. 26
Binary adder solved as sequential Mealy
machine

Ing. Michal Lucki, PhD. 27

The homework file is on Moodle
Good luck!

28
Thank you for your attention

Ing. Michal Lucki, PhD. 29