VLSI Design and Testing

(VI Semester E&C)

Sub Code: 21EC63

Prepared by : Dr.Savitha.M
Professor
EC Department
KVGCE- Sullia

Department of Electronics & Communication Engineering

E OF ENGINEERING SULLIA – 574 327 D.K
Academic Year: 2023-24
03.10.2022

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester

VLSI Design and Testing

Course Code 21EC63 CIE Marks 50
Teaching Hours/Week (L:T:P:S) 3:0:0:1 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 3 Exam Hours 3
Course objectives:
 Impart knowledge of MOS transistor theory and CMOS technology
 Learn the operation principles and analysis of inverter circuits.
 Infer the operation of Semiconductor memory circuits.
 Demonstrate the concept of CMOS testing.
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Arrange visits to nearby PSUs and industries.
3. Show Video/animation films to explain the functioning of various fabrication & testing techniques.
4. Encourage collaborative (Group) Learning in the class
5. Topics will be introduced in multiple representations.
6. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
Module-1
Introduction: A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT1)
MOS Transistor Theory: Introduction, Long-channel I-V Characteristics, Non-ideal I-V Effects, DC
Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT1).
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos, Videos on
Process transistor working
Self-study topics: MOSFET Scaling and Small-Geometry Effects
RBT Level: L1, L2, L3
Module-2
Fabrication: CMOS Fabrication and Layout, Introduction, CMOS Technologies, Layout Design Rules, (1.5
and 3.1 to 3.3 of TEXT1).
Delay: Introduction, Transient Response, RC Delay Model, Linear Delay Model, Logical Efforts of Paths
(4.1 to 4.5 of TEXT1, except sub-sections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and 4.5.6).
Teaching-Learning Chalk and talk method, Power point presentation, YouTube videos, Videos on
Process fabrication
Self-study topics: Layouts of complex design using Euler’s method
RBT Level: L1, L2, L3
Module-3
Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM) and Static Random
Access Memory (SRAM), Nonvolatile Memory, Flash Memory, Ferroelectric Random Access Memory
(FRAM) (10.1 to 10.6 of TEXT2)
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos on Standard

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Process cell memory Design

Self-study topics: Memory array design
RBT Level: L1, L2, L3
Module-4
Faults in digital circuits: Failures and faults, Modelling of faults, Temporary faults
Test generation for combinational logic circuits: Fault diagnosis of digital circuits, test generation
techniques for combinational circuits, Detection of multiple faults in combinational logic circuits.
(1.1 to 1.3, 2.1 to 2.3 of TEXT3)
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos, videos on
Process testing algorithms for test generation
Self-study topics: Testable combinational logic circuits
RBT Level: L1, L2, L3
Module-5
Test generation for sequential circuits: Testing of sequential circuits as iterative combinational
circuits, state table verification, test generation based on circuits structure, functional fault models, test
generation based on functional fault models.
Design of testable sequential circuits: Controllability and Observability, Adhoc design rules, design of
diagnosable sequential circuits, The scan path technique, LSSD, Random Access scan technique, partial
scan.
(4.1 to 4.5, 5.1 to 5.7 of TEXT3)
Teaching-Learning Chalk and talk method/Power point presentation, YouTube videos
Process Self-study topics: Memory testing techniques
RBT Level: L1, L2, L3
Course outcomes (Course Skill Set)
At the end of the course the student will be able to:
1. Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology
scaling.
2. Draw the basic gates using the stick and layout diagram with the knowledge of physical design
aspects.
3. Interpret memory elements along with timing considerations.
4. Interpret testing and testability issues in combinational logic design.
5. Interpret testing and testability issues in combinational logic design.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20

19.09.2023
03.10.2022

Marks (duration 01 hours)

6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks
and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module..Marks scored
out of 100 shall be reduced proportionally to 50 marks

Suggested Learning Resources:

Text Books:
1. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, and David Money Harris 4 th
Edition, Pearson Education.
2. “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang & Yosuf Leblebici, Third
Edition, Tata McGraw-Hill.
3. “Digital Circuit Testing and Testability”, Lala Parag K, New York, Academic Press, 1997.
Reference Books:
1. “Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall of India
publication, 2005.
2. “Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits”, Vishwani D Agarwal,
Springer, 2002.
Web links and Video Lectures (e-Resources)
 https://www.youtube.com/watch?v=oL8SKNxEaHs&list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM
 https://www.youtube.com/watch?v=lRpt1fCHd8Y&list=PLCmoXVuSEVHlEJi3SwdyJ4EICffuyqpjk
 https://www.youtube.com/watch?v=yLqLD8Y4-Qc
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
 Model displayed for clear understanding of fabrication process of MOS transistor
 Practise session can be held to understand the significance of various layers in MOS process, with
the help of coloured layouts

19.09.2023
Non ideal characteristics :
The long-channel I-V model , equation of drain current , neglects many effects that are important to
devices with channel lengths below 1 micron. This section summarises the non -deal behaviour of
MOSFET

following non ideal characteristics of MOSFEt

1. Mobility degradation

2. Velocity Saturation

3. Body effect

4. Drain induced barrier lowering (DIBL)

5. Channel length modulation

6. Sub-threshold Conduction

7. Gate leakage
Mobility Degradation:
ν=μE where ν is the carrier drift velocity and μ is mobility
The mobility term in the above equation was assumed to be independent of the
vertical electric field E. This is a reasonable approximation when the electric field
is weak but it breaks down for stronger electric fields. Stronger vertical electric
fields (produced by a high gate voltage) can attract the charge carriers travelling
along the inversion layer and cause it to collide with the oxide interface. This effect
causes mobility degradation, where the effective mobility decrease with increase in
Vgs.
Velocity Saturation:
Under strong lateral electric fields (produced by Vds), the charge carriers are
accelerated and the collisions between the charge carriers and the silicon lattice
increases. Beyond a certain level of electric field, the carrier drift velocity saturates
at νsat. This is called velocity saturation. Note that transistor saturation and
velocity saturation are two different phenomenons but both of them result in the
saturation of current through the channel (with respect to Vds).
ν=μE

E= Vds/L where L is the length of the channel

With decrease in the length of the channel, the effective electric field for the same
Vds increases. With increase in the strength of the lateral electric field, the charge
carriers of a short channel device becomes velocity saturated at a much lower Vds
as compared to a long channel device.

In the above graph, we can see that the long channel device has linear relationship
between Ids and Vds until Vds=Vgs-Vt. After Vds=Vgs-Vt , the long channel
enters into saturation region. In the case of the short channel device, it enters into
velocity saturation region much before the drain pinch-off saturation region. In
short channel devices, depending upon which is lower VdsSAT or (Vgs-Vt), the
device can go into velocity saturation or drain pinch-off saturation. If VdsSAT is
smaller, then the short channel device enters into velocity saturation first. If (Vgs-
Vt) is smaller, it enters into drain pinch-off saturation first.
Body Effect:
So far we considered that source and body terminals are both connected together
and into ground. But what if the body is not connected to the source?

If the body is not connected to the source and it is connected to a different

potential, then this causes the threshold voltage to vary according to the below
forumla
Vt=Vt0+γ( (Φs+Vsb)1/2 – Φs1/2 )
where Vt0 is the threshold voltage when Vsb=0, γ is the body effect coefficient and
Φs is the surface potential at threshold.
From the above formula, we can infer that the threshold voltage increases with
source voltage and decreases with body voltage.

Drain-induced barrier lowering (DIBL):

The drain and the body form a PN junction. If the voltage on the drain is positive
and the voltage on the body is 0 or negative, then this PN junction is reverse
biased. With increase in Vds, this reverse bias keeps increasing. With increase in
the reverse bias, the depletion region increases in size and starts infringing on the
channel. The depletion region is devoid of mobile charge carriers and it occupies a
part of the channel during high Vds voltages. This means the gate voltage has less
of the channel to deplete (as a portion of the channel is depleted by the depletion
region). As a result, the threshold voltage decreases. However this effect is not
very prominent in long channel devices because their channels are very long with
respect to the length of the depletion region. However short channel devices have
shorter channels whose lengths are comparable with the length of the depletion
region and as such the DIBL effect is prominent.

a) A long
channel device. The dotted lines represent the depletion region. b) A short channel device

Vt=Vt0+γ( (Φs+Vsb)1/2 – Φs1/2 ) – ηVds

where η is the DIBL coefficient.
Channel Length Modulation:
As Vds increases, the depletion region increases and the channel length becomes
shorter. The current through the channel Ids is inversely proportional to the length
of the channel. With decrease in the channel length, the current increases. Just like
the DIBL effect, this effect is also most prominently seen in short channel devices
as opposed to long channel devices. Incorporating the channel length modulation,
the current equation for the saturation region (Channel length modulation comes
into play only at high Vds hence the transistor is already at saturation when this
effect becomes prominent) becomes,

where λ is a CLM (Channel length modulation) parameter.

Notice how the current in the saturation region is no longer perfectly constant.
Because of the CLM effect, current increases slightly with increase with V ds.

Sub-threshold conduction:
So far we assumed that Ids=0 for Vgs<Vt. But current doesn’t cut off abruptly once
Vgs becomes less than Vt. As Vgs decreases below Vt, Ids decreases exponentially. If
we were to plot a logarithmic graph of Ids vs Vgs for Vgs less than Vt, it would be a
straight line. This is called the sub-threshold conduction. This effect is exacerbated
by the DIBL effect.
The region below Vt is called the sub threshold region. The graph shows the IV
characteristics for two different Vds: Vds=0.1 and Vds=1. Both the plots have non
zero current in the sub threshold region but Vds=1 plot has a higher current due to
the DIBL effect.
Gate leakage:
The gate and the channel form a capacitor. No current should pass through the
capacitor ideally. But with the decrease in the oxide thickness between the gate and
the channel, the electrons tunnel across and this constitutes the gate leakage
current.
 Gate leakage current vs
VDD for different values of oxide thickness

From the above graph, we can see that the gate leakage increases by a factor of 2.7
or more per angstrom reduction in thickness. To keep the gate leakage below 100
A/cm2, the oxide thickness tox must be at least 10.5 A.
Gate leakage current can be reduced by substituting the silicon dioxide with higher
dielectric constant material.
 2.5 DC Transfer Characteristics

The DC transfer characteristics of a circuit relate the output voltage to the input voltage,
assuming the input changes slowly enough that capacitances have plenty of time to charge or
discharge. Specific ranges of input and output voltages are defined as valid 0 and 1 logic levels.

Table 2.2, which outlines various regions of operation for the n- and p-transistors. In this table, Vtn is the
threshold voltage of the n-channel device, and Vtp is the threshold voltage of the p-channel device
.
The operation of the CMOS inverter can be divided into five regions indicated on Figure
2.26(c). The state of each transistor in each region is shown in Table 2.3. In region A,
the nMOS transistor is OFF so the pMOS transistor pulls the output to VDD. In region
B, the nMOS transistor starts to turn ON, pulling the output down. In region C, both
transistors are in saturation. Notice that ideal transistors are only in region C for Vin =
VDD/2 and that the slope of the transfer curve in this example is Vin is infinity in this
region, corresponding to infinite gain. Real transistors have finite output resistances on
account of channel length modulation, described in Section 2.4.2, and thus have finite
slopes over a broader region C. In region D, the pMOS transistor is partially ON in
region E.

90 Chapter 2 MOS Transistor Theory

 VDD
2.5.2 Beta Ratio Effects
We have seen that for p  n, the inverter threshold voltage Vinv is VDD /2. This may be
desirable because it maximizes noise margins (see Section 2.5.3) and allows a capacitive
load to charge and discharge in equal times by providing equal current source and sink
capabilities (see Section 4.2). Inverters with different beta ratios r  p /n are called
skewed inverters [Sutherland99]. If r  1, the inverter is HI-skewed. If r  1,
the inverter is LO-skewed. If r  1, the inverter has normal skew or is
unskewed.
A HI-skew inverter has a stronger pMOS transistor. Therefore, if the
p
n = 10
input is VDD /2, we would expect the output will be greater than V DD /2. In other
words, the input threshold must be higher than for an unskewed inverter.
2
Vout Similarly, a LO-skew inverter has a weaker pMOS transistor and thus a
1
0.5 lower switching threshold.
p
Figure 2.28 explores the impact of skewing the beta ratio on the DC
n = 0.1
transfer characteristics. As the beta ratio is changed, the switching thresh-
0 old moves. However, the output voltage transition remains sharp. Gates are
VDD
usually skewed by adjusting the widths of transistors while maintaining
Vin
minimum length for speed.
FIGURE 2.28 Transfer characteristics of
skewed inverters The inverter threshold can also be computed analytically. If the long-
channel models of EQ (2.10) for saturated transistors are valid:
n
Idn  V V 2

2 inv tn
p 2
(2.54)
Idp 
2
V inv V DD Vtp 
By setting the currents to be equal and opposite, we can solve for Vinv as a function of r :

V V V
Vinv 

(2.55)

In the limit that the transistors are fully velocity saturated, EQ (2.29) shows
Idn  WnCoxvsatn (Vinv  Vtn )
Idp  WpCoxvsat p (Vinv VDD  Vtp )

Redefining r  Wpvsat-p / Wnvsat-n, we can again find the inverter threshold

(2.5
6)
1
V V V
DD tp tn
Vinv  r
1
1
r (2.57)
 In either case, if Vtn  –Vtp and r  1, Vinv  V DD /2 as expected. However, velocity sat-
urated inverters are more sensitive to skewing because their DC transfer characteristics are
not as sharp.
DC transfer characteristics of other static CMOS gates can be understood by collaps-
ing the gates into an equivalent inverter. Series transistors can be viewed as a single tran-
sistor of greater length. If only one of several parallel transistors is ON, the other

transistors can be ignored. If several parallel transistors are ON, the collection can be
viewed as a single transistor of greater width.

2.5.3 Noise Margin

Noise margin is closely related to the DC voltage characteristics [Wakerly00]. This param-eter
allows you to determine the allowable noise voltage on the input of a gate so that the
output will not be corrupted. The specification most commonly used to describe noise
margin (or noise immunity) uses two parameters: the LOW noise margin, NML, and the
HIGH noise margin, NMH. With reference to Figure 2.29, NML is defined as the differ-
ence in maximum LOW input voltage recognized by the receiving gate and the maximum
LOW output voltage produced by the driving gate.

NML  VIL VOL

(2.
58)
The value of NMH is the difference between the minimum HIGH output voltage of
the driving gate and the minimum HIGH input voltage recognized by the receiving gate.
Thus,

NMH  VOH VIH

where
(2.59)
VIH  minimum HIGH input voltage
VIL  maximum LOW input voltage
VOH minimum HIGH output voltage
VOL  maximum LOW output voltage

Output Characteristics Input Characteristics

VDD
Logical High

Output Range VOH Logical High

Input Range
NMH
VIH Indeterminate
Region
VI
L
Logical Low
Logical Low Output NM
Input Range
Range L
VOL
GND
 5

FIGURE 2.29 Noise margin definitions

 V L S I D E S I G N | M O D U L E 2: F A B R I C A T I O N, M O S F E T S C A L I N G 18EC72

λ
Module 2 1st chapter
FABRICATION
Transistors are fabricated on thin silicon wafers that serve as both a mechanical support and an
electrical common point called the substrate. We can examine the physical layout of transistors from two
perspectives. One is the top view, obtained by looking down on a wafer. The other is the cross-
section, obtained by slicing the wafer through the middle of a transistor and looking at it edgewise.
We begin by looking at the cross-section of a complete CMOS inverter. We then look at the top view
of the same inverter and define a set of masks used to manufacture the different parts of the inverter.
The size of the transistors and wires is set by the mask dimensions and is limited by the resolution of
the manufacturing process. Continual advancements in this resolution have fuelled the exponential
growth of the semiconductor industry.

2.1 Inverter Cross-Section

Figure 2.1 shows a cross-section and corresponding schematic of an inverter. In this diagram, the
inverter is built on a p-type substrate. The pMOS transistor requires an n-type body region, so an n-
well is diffused into the substrate in its vicinity. The nMOS transistor has heavily doped n-type source
and drain regions and a polysilicon gate over a thin layer of silicon dioxide (SiO2, also called gate
oxide). n+ and p+ diffusion regions indicate heavily doped n-type and p-type silicon. The pMOS
transistor is a similar structure with p-type source and drain regions. The polysilicon gates of the two
transistors are tied together somewhere off the page and form the input A. The source of the nMOS
transistor is connected to a metal ground line and the source of the pMOS transistor is connected to
a metal VDD line. The drains of the two transistors are connected with metal to form the output Y.
A thick layer of SiO2 called field oxide prevents metal from shorting to other layers except where
contacts are explicitly etched.

Fig 2.1 Inverter cross-section with well and substrate contacts.

The inverter could be defined by a hypothetical set of six masks: n-well, polysilicon, n+ diffusion, p+
diffusion, contacts, and metal. Masks specify where the components will be manufactured on the
chip. Figure 2.3(a) shows a top view of the six masks. The cross-section of the inverter from Figure
2.1 was taken along the dashed line.
1
 Fig 2.2 Inverter mask set.

2.2 CMOS Fabrication Process

Consider a simple fabrication process to illustrate the concept. The process begins with the creation
of an n-well on a bare p-type silicon wafer.
Figure 2.3 shows cross-sections of the wafer after each processing step involved in forming the n-
well; Figure 2.3(a) illustrates the bare substrate before processing. Forming the n-well requires adding
nough Group V dopants into the silicon substrate to change the substrate from p-type to n-type in
the region of the well.

The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that causes Si and O2
to react and become SiO2 on the wafer surface as shown in Figure 2.3(b).
The oxide must be patterned to define the n-well. Figure 2.3(c) shows an organic photoresist that
softens when exposed to light is spun onto the wafer.
Figure 2.3(d) shows, the photoresist is exposed through the n-well mask that allows light to pass
through only where the well should be.
The oxide is etched with hydrofluoric acid (HF) where it is not protected by the photoresist is as
shown in Figure 2.3(e).
Figure 2.3(f) shows the remaining photoresist is stripped away using a mixture of acids called piranha
2
etch. The well is formed where the substrate is not covered with oxide.
Two ways to add dopants are diffusion and ion implantation. In the diffusion process, the wafer is
placed in a furnace with a gas containing the dopants. When heated, dopant atoms diffuse into the
substrate. Notice how the well is wider than the hole in the oxide on account of lateral diffusion
Figure 2.3(g). With ion implantation, dopant ions are accelerated through an electric field and blasted
into the substrate. In either method, the oxide layer prevents dopant atoms from entering the
substrate where no well is intended. Finally, the remaining oxide is stripped with HF to leave the bare
wafer with wells in the appropriate places.

Fig 2.3 Cross-sections while manufacturing the n-well

3
The transistor gates are formed next. These consist of polycrystalline silicon, generally called
polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then the wafer is placed in
a reactor with silane gas (SiH4) and heated again to grow the polysilicon layer through a process
called chemical vapor deposition. The polysilicon is heavily doped to form a reasonably good conductor.
The resulting cross-section is shown in Figure 2.4(a).
Figure 2.4(b) shows the wafer which is patterned with photoresist and the polysilicon mask leaving
the polysilicon gates atop the thin gate oxide. The n+ regions are introduced for the transistor active
area and the well contact.
Figure 2.4(c) shows the well, a protective layer of oxide is formed and patterned with the n-diffusion
mask.
Figure 2.4(d) shows the areas exposed where the dopants are needed.
Although the n+ regions in Figure 2.4(e) are typically formed with ion implantation, they were
historically diffused and thus still are often called n-diffusion. Notice that the polysilicon gate over the
nMOS transistor blocks the diffusion so the source and drain are separated by a channel under the
gate. This is called a self-aligned process because the source and drain of the transistor are automatically
formed adjacent to the gate without the need to precisely align the masks.
Finally, the protective oxide is stripped as shown in Figure 2.4(f).

Fig 2.4 Cross-sections while manufacturing polysilicon and n-diffusion

4
The process is repeated for the p-diffusion mask to give the structure of Figure 2.5(a).
Oxide is used for masking in the same way, and thus is not shown. The field oxide is grown to
insulate the wafer from metal and patterned with the contact mask to leave contact cuts where metal
should attach to diffusion or polysilicon as shown in Figure 2.5(b).
Figure 2.5 (c) shows aluminium is sputtered over the entire wafer, filling the contact cuts as well.
Sputtering involves blasting aluminum into a vapor that evenly coats the wafer. The metal is
patterned with the metal mask and plasma etched to remove metal everywhere except where wires
should remain.

F
i
g
2.5 Cross-sections while manufacturing p-diffusion, contacts, and metal

2.3 Layout Design Rules

Layout design rules describe how small features can be and how closely they can be reliably packed in
a particular manufacturing process. Industrial design rules are usually specified in microns.
Universities sometimes simplify design by using scalable design rules that are conservative enough to
apply to many manufacturing processes. Mead and Conway popularized scalable design rules basedon
a single parameter, λ, that characterizes the resolution of the process. λ is generally half of the
minimum drawn transistor channel length. This length is the distance between the source and drain
of a transistor and is set by the minimum width of a polysilicon wire.
For example, a 180 nm process has a minimum polysilicon width (and hence transistor length) of
0.18 nm and uses design rules with λ = 0.09 nm3. Lambda-based rules are necessarily conservative
because they round up dimensions to an integer multiple of λ. Designers often describe a process
byits feature size. Feature size refers to minimum transistor length, so λ is half the feature size.

5
2.3.1 Lambda Based Rules
A conservative but easy-to-use set of design rules for layouts with two metal layers in an n-well
process is as follows:
Metal and diffusion have minimum width and spacing of 4 λ
Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
Polysilicon uses a width of 2 λ.
Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing of 1 λ
away where no transistor is desired.
Polysilicon and contacts have a spacing of 3 λ from other polysilicon or contacts.
N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

2.4 Gate layout

This section presents a simple layout style based on a “line of diffusion” rule that is commonly used
for standard cells in automated layout systems. This style consists of four horizontal strips: metal
ground at the bottom of the cell, n-diffusion, p-diffusion, and metal power at the top. The power and
ground lines are often called supply rails. Polysilicon lines run vertically to form transistor gates. Metal
wires within the cell connect the transistors appropriately.
Figure 2.7(a) shows such a layout for an inverter. The input A can be connected from the top, bottom,
or left in polysilicon. The output Y is available at the right side of the cell in metal. Figure 2.7(b)
shows the same inverter with well and substrate taps placed under the power and ground rails,
respectively. Figure 2.8 shows a 3-input NAND gate. Notice how the nMOS transistors are
connected in series while the pMOS transistors are connected in parallel. Power and ground extend
2 λ on each side so if two gates were abutted the contents would be separated by 4 λ, satisfying design
rules. The height of the cell is 36 λ, or 40 λ if the 4 λ space between the cell and another wire above
6
it is counted.

7
Fig 2.7 Inverter cell layout Fig 2.8 3-input NAND standard cell gate layouts

2.5 Stick Diagrams

• Stick diagrams are a means of capturing topography and layer information using simple
diagrams.
• They convey layer information through color codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and the actual layout.
• Stick diagrams do show all components/vias(contacts), relative placement of components
and helps in planning and routing. It goes one step closer to layout.
• However, they do not show exact placement of components, transistor sizes, length and
width of wires also the boundaries. Thus, we can say that it does not give any low-level
details.
Procedure to draw Stick Diagram:
1. Draw two metal lines/ power rails providing sufficient space to accommodate all
transistors. i.e: Vdd & Gnd.
2. Draw demarcation line in the middle of the two power lines.
3. Draw P+ diffusion above demarcation and N+ diffusion below demarcation
4. Draw polysilicon to represent Pmos and Nmos which represents gates of the transistor.
5. Connect source terminal of transistors to supply.
6. Drain terminals of transistor are connected using metal 1.
7. Place contact cuts wherever necessary.
8. Draw X which represents substrate and P-well contact on power lines.

8
CMOS Inverter

NOTE

Red: Polysilicon
Green: n-diffusion
Yellow: p-diffusion
Blue: M1
Purple (Magenta):M2
Blue (Cyan):M3
Black: Contacts & Taps

Fig 2.9 Stick diagram of CMOS Inverter

CMOS NAND Gate

Fig 2.10 Stick diagram of CMOS NAND gate

9
 CMOS NOR Gate

Fig 2.11 Stick diagram of CMOS NAND gate

Track Pitch:
Transistors are merely widgets that fit under the wires. We define a routing track as enough space to
place a wire and the required spacing to the next wire. If our wires have a width of 4 λ and a
spacing of 4 λ to the next wire, the track pitch is 8 λ. Therefore, it is reasonable to estimate the
height and width of a cell by counting the number of metal tracks and multiplying by 8 λ

Fig 2.12 Pitch of routing tracks

A slight complication is the required spacing of 12 λ between nMOS and pMOS transistors set by
the well, as shown in Figure 2.13(a). This space can be occupied by an additional track of wire,
shown in Figure 2.13(b). Therefore, an extra track must be allocated between nMOS and pMOS
transistors regardless of whether wire is actually used in that track.

Fig 2.13 Spacing between nMOS and pMOS transistors

10
 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Problem 1: Sketch a stick diagram for a 3 input CMOS NAND gate ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ and estimate the ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ cell width
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
and ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
height. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Fig 2.14 Stick diagram of 3 input ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ CMOS NAND gate and ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ area estimation̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Problem 2: Sketch a stick diagram for a CMOS̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ gate computing Y= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (𝐴 + 𝐵 + 𝐶). 𝐷 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
and estimate the cell width and height. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Fig 2.15 CMOS compound gate Function Y= (𝐴 and+area 𝐶). 𝐷 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐵 +estimation

2.6 CMOS Technologies

CMOS processing steps can be broadly divided into two parts. Transistors are formed in the Front-
End-of-Line (FEOL) phase, while wires are built in the Back-End-of-Line (BEOL) phase. This section
examines the steps used through both phases of the manufacturing process.

Wafer Formation
The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm to 300 mm in
diameter and less than 1 mm thick. Wafers are cut from boules, cylindrical ingots of single-crystal
silicon, that have been pulled from a crucible of pure molten silicon. This is known as the Czochralski
method. Controlled amounts of impurities are added to the melt to provide the crystal with the
11
 required electrical properties. A seed crystal is dipped into the melt to initiate crystal growth. The
silicon ingot takes on the same crystal orientation as the seed. A graphite radiator heated by radio-
frequency induction surrounds the quartz crucible and maintains the temperature a few degrees
above the melting point of silicon (1425 °C). The atmosphere is typically helium or argon to prevent
the silicon from oxidizing.
The seed is gradually withdrawn vertically from the melt while simultaneously being rotated, as
shown in Figure 2.17. The molten silicon attaches itself to the seed and recrystallizes as it is
withdrawn. The seed withdrawal and rotation rates determine the diameter of the ingot. Growth rates
vary from 30 to 180 mm/hour.

Fig 2.17 Czochralski system for growing Si boules

Photolithography
In places covered by the mask, ion implantation might not occur or the dielectric or metal layer might be
left intact. In areas where the mask is absent, the implantation can occur, or dielectric or metal could
be etched away. The patterning is achieved by a process called photolithography. The primary method
for defining areas of interest (i.e., where we want material to be present or absent) on a waferis by the
use of photoresists. The wafer is coated with the photoresist and subjected to selective illumination
through the photomask.
A photomask is constructed with chromium (chrome) covered quartz glass. A UV light source is
used to expose the photoresist. Figure 2.18 illustrates the lithography process. The photomask has
chrome where light should be blocked. The UV light floods the mask from the backside and passes
through the clear sections of the mask to expose the organic photoresist (PR) that has been coated
on the wafer. A developer solvent is then used to dissolve the soluble unexposed photoresist, leaving
islands of insoluble exposed photoresist.This is termed a negative photoresist. A positive resist is
initially insoluble, and when exposed to UV becomes soluble. Positive resists provide for higher
resolution than negative resists, but are less sensitive to light. As feature sizes become smaller, the
photoresist layers have to be made thinner.

12
Fig 2.18 Photomasking with a negative resist (lens system between mask and wafer omitted to
improve clarity and avoid diffracting the reader)
Well and Channel Formation
The following are main CMOS technologies:
n-well process
p-well process
twin-well process
triple-well process

In a p-well process, the nMOS transistors are built in a p-well and the pMOS transistor is placed in
the n-type substrate. p-well processes were used to optimize the pMOS transistor performance.
In the n-well process, pMOS transistors are fabricated in an n-well, each group of pMOS transistors
in an n-well shares the same body node but is isolated from the bodies of pMOS transistors in
different wells. However, all the nMOS transistors on the chip share the same body, which is the
substrate. Noise injected into the substrate by digital circuits can disturb sensitive analog or memory
circuits.
Twin-well processes accompanied the emergence of n-well processes. A twin-well process allows the
optimization of each transistor type.
A third well can be added to create a triple-well process. The triple-well process has emerged to
provide good isolation between analog and digital blocks in mixed-signal chips; it is also used to
isolate high-density dynamic memory from logic.

Silicon Dioxide (SiO2)

Various thicknesses of SiO2 may be required, depending on the particular process. Thin oxides are
required for transistor gates; thicker oxides might be required for higher voltage devices, while even
thicker oxide layers might be required to ensure that transistors are not formed unintentionally in the
silicon beneath polysilicon wires
The following are some common approaches:
Wet oxidation––when the oxidizing atmosphere contains water vapor. The temperature is usually
between 900 °C and 1000 °C. This is also called pyrogenic oxidation when a 2:1 mixture of hydrogen
and oxygen is used. Wet oxidation is a rapid process.
13
Dry oxidation - when the oxidizing atmosphere is pure oxygen. Temperatures are in the region of 1200
°C to achieve an acceptable growth rate. Dry oxidation forms a better-quality oxide than wet
oxidation. It is used to form thin, highly controlled gate oxides, while wet oxidation may be used to
form thick field oxides.
Atomic layer deposition (ALD)––when a thin chemical layer (material A) is attached to a surface and
then a chemical (material B) is introduced to produce a thin layer of the required layer (i.e., SiO2––
this can also be used for other various dielectrics and metals). The process is then repeated and the
required layer is built up layer by layer.

Isolation
Individual devices in a CMOS process need to be isolated from one another so that they do not have
unexpected interactions. The transistor gate consists of a thin gate oxide layer. Elsewhere, a thicker
layer of field oxide separates polysilicon and metal wires from the substrate. The MOS sandwich
formed by the wire, thick oxide, and substrate behaves as an unwanted parasitic transistor. However,
the thick oxide effectively sets a threshold voltage greater than VDD that prevents the transistor
from turning ON during normal operation. Actually, these field devices can be used for I/O protection.
The thick oxide used to be formed by a process called Local Oxidation of Silicon (LOCOS). A
problem with LOCOS-based processes is the transition between thick and thin oxide, which
extended some distance laterally to form a so-called bird’s beak. The lateral distance is proportional to
the oxide thickness, which limits the packing density of transistors.
STI starts with a pad oxide and a silicon nitride layer, which act as the masking layers, as shown
in Figure 2.19. Openings in the pad oxide are then used to etch into the well or substrate region (this
process can also be used for source/drain diffusion). A liner oxide is then grown to cover the
exposed silicon (Figure 2.19(b)). The trenches are filled with SiO2 or other fillers using CVD that
does not consume the underlying silicon (Figure 2.19(c)). The pad oxide and nitride are removed and
a Chemical Mechanical Polishing (CMP) step is used to planarize the structure (Figure 2.19(d)).

14
 Fig 2.19 Shallow trench isolation
Gate Oxide
The next step in the process is to form the gate oxide for the transistors. As mentioned, this is most
commonly in the form of silicon dioxide (SiO2).
In the case of STI-defined source/drain regions, the gate oxide is grown on top of the planarized
structure that occurs at the stage shown in Figure 2.19(d). This is shown in Figure 2.20.

Fig 2.20 Gate oxide formation

The oxide structure is called the gate stack. This term arises because current processes seldom use a
pure SiO2 gate oxide, but prefer to produce a stack that consists of a few atomic layers, each 3–4 Å
thick, of SiO2 for reliability, overlaid with a few layers of an oxynitrided oxide (one with nitrogen
added). The presence of the nitrogen increases the dielectric constant, which decreases the effective
oxide thickness (EOT); this means that for a given oxide thickness, it performs like a thinner oxide.
Being able to use a thicker oxide improves the robustness of the process.

Gate and Source/Drain Formations

When silicon is deposited on SiO2 or other surfaces without crystal orientation, it forms
polycrystalline silicon, commonly called polysilicon or simply poly. Undoped polysilicon has high
resistivity. The resistance can be reduced by implanting it with dopants and/or combining it with a
refractory metal. The polysilicon gate serves as a mask to allow precise alignment of the source and
drain on either side of the gate. This process is called a self-aligned polysilicon gate process.
As a historical note, early metal-gate processes first diffused source and drain regions, and then
formed a metal gate. If the gate was misaligned, it could fail to cover the entire channel and lead to a
transistor that never turned ON. To prevent this, the metal gate had to overhang the source and drain
by more than the alignment tolerance of the process. This created large parasitic gate-to-source and gate-
to-drain overlap capacitances that degraded switching speeds.
17
The steps to define the gate, source, and drain in a self-aligned polysilicon gate are as follows:
Grow gate oxide wherever transistors are required (area = source + drain + gate) - elsewhere
there will be thick oxide or trench isolation (Figure 2.21(a))
Deposit polysilicon on chip (Figure 2.21(b))
Pattern polysilicon (both gates and interconnect) (Figure 2.21(c))
Etch exposed gate oxide—i.e., the area of gate oxide where transistors are required that was
not covered by polysilicon; at this stage, the chip has windows down to the well or substrate
wherever a source/drain diffusion is required (Figure 2.21(d))
Implant pMOS and nMOS source/drain regions (Figure 2.21(e))

Fig 2.21 Gate and shallow source/drain definition

Contacts and Metallization
Contact cuts are made to source, drain, and gate according to the contact mask. These are holes
etched in the dielectric after the source/drain step. Older processes commonly use aluminum (Al) for
wires, although newer ones offer copper (Cu) for lower resistance. Tungsten (W) can be used as a plug
to fill the contact holes. In some processes, the tungsten can also be used as a local interconnect
layer.
Metallization is the process of building wires to connect the devices. conventional metallization uses
aluminum. Aluminum can be deposited either by evaporation or sputtering. Evaporation is performed by
passing a high electrical current through a thick aluminum wire in a vacuum chamber. Some of the
aluminum atoms are vaporized and deposited on the wafer. Sputtering is achieved by generating a gas
plasma by ionizing an inert gas using an RF or DC electric field. The ions are focused on an
aluminum target and the plasma dislodges metal atoms, which are then deposited on the wafer.

Fig 2.22 Aluminium Metallization

18
 2.7 Layout Design Rules
Layout rules, also referred to as design rules, and can be considered a prescription for preparing the
photomasks that are used in the fabrication of integrated circuits. The rules are defined in terms of
feature sizes (widths), separations, and overlaps. The main objective of the layout rules is to build reliably
functional circuits in as small an area as possible. In general, design rules represent a compromise
between performance and yield. The more conservative the rules are, the more likely it is that the
circuit will function. However, the more aggressive the rules are, the greater the opportunity for
improvements in circuit performance and size.

Well Rules
The n-well is usually a deeper implant (especially a deep n-well) than the transistor source/drain
implants, and therefore, it is necessary to provide sufficient clearance between the n-well edges and
the adjacent n+ diffusions. The clearance between the well edge and an enclosed diffusion is
determined by the transition of the field oxide across the well boundary. Processes that use STI may
permit zero inside clearance.

Transistor Rules
CMOS transistors are generally defined by at least four physical masks. These are active (also called
diffusion, diff, thinox, OD, or RX), n-select (also called n-implant, nimp, or nplus), p-select (also
called p-implant, pimp, or pplus) and polysilicon (also called poly, polyg, PO, or PC). The active mask
defines all areas where either n- or p type diffusion is to be placed or where the gates of transistors are to
be placed. The gates of transistors are defined by the logical AND of the polysilicon mask and the
active mask, i.e., where polysilicon crosses diffusion. The select layers define what type of diffusion is
required. n-select surrounds active regions where n-type diffusion is required. p-select surrounds
areas where p-type diffusion is required. n-diffusion areas inside p-well regions define nMOS
transistors (or n-diffusion wires). n-diffusion areas inside n-well regions define n-well contacts.
Likewise, p-diffusion areas inside n-wells define pMOS transistors (or p-diffusion wires). p-diffusion
areas inside p-wells define substrate contacts (or p-well contacts).
Figure 2.23(a) shows the mask construction for the final structures that appear in Figure 2.23(b).

19
 Fig 2.23 CMOS n-well process transistor and well/substrate contact construction

Contact Rules
There are several generally available contacts:
Metal to p-active (p-diffusion)
Metal to n-active (n-diffusion)
Metal to polysilicon
Metal to well or substrate
Depending on the process, other contacts such as buried polysilicon-active contacts may be allowedfor
local interconnect.
Because the substrate is divided into well regions, each isolated well must be tied to the appropriate
supply voltage; i.e., the n-well must be tied to VDD and the substrate or p-well must be tied to GND
with well or substrate contacts.
Mask Summary: The only mask involved with contacts to active or poly is the contact mask,
commonly called CONT or CA. Contacts are normally of uniform size to allow for consistent
etching of very small features.

Metal Rules
Metal spacing may vary with the width of the metal line (so called fat-metal rules). That is, above
some metal wire width, the minimum spacing may be increased. This is due to etch characteristics of
small versus large metal wires. There may also be maximum metal width rules. That is, single metal
wires cannot be greater than a certain width. If wider wires are desired, they are constructed by
paralleling a number of smaller wires and adding checkerboard links to tie the wires together.

Mask Summary: Metal rules may be complicated by varying spacing dependent on width: As the
width increases, the spacing increases. Metal overlap over contact might be zero or nonzero.
20
Via Rules
Processes may vary in whether they allow stacked vias to be placed over polysilicon and diffusion
regions. Some processes allow vias to be placed within these areas, but do not allow the vias to
straddle the boundary of polysilicon or diffusion.
Mask Summary: Vias are normally of uniform size within a layer. They may increase in size toward
the top of a metal stack. For instance, large vias required on power busses are constructed from an
array of uniformly sized vias.

Other Rules
The passivation or overglass layer is a protective layer of SiO2 (glass) that covers the final chip.
Appropriately sized openings are required at pads and any internal test points.
Some additional rules that might be present in some processes are as follows:
Extension of polysilicon or metal beyond a contact or via
Differing gate poly extensions depending on the device length

21
Micron Design Rules
Table 2.1 lists a set of micron design rules for a hypothetical 65 nm process representing an
amalgamation of several real processes. Observe that the rules differ slightly but not immensely from
lambda-based rules with = 0.035 µm. A complete set of micron design rules in this generation fills
hundreds of pages. Note that upper-level metal rules are highly variable depending on the metal
thickness; thicker wires require greater widths and spacings and bigger vias.

TABLE 2.1 Micron design rules for 65 nm process

22
Delay :
 4.2 Transient Response 2

The two most common metrics for a good chip are speed and power,. Delay and
power are influenced as much by the wires as by the transistors, so Chapter 6
delves into interconnect analysis and design.

A timing analyzer computes the arrival times, i.e., the latest time
at which each node in a block of logic will switch. The nodes are classified as inputs,
outputs, and internal nodes. The user must specify the arrival time of inputs and the time
data is required at the outputs. The arrival time ai at internal node i depends on the
propagation delay of the gate driving i and the arrival times of the inputs to the gate:
 4.2 Transient Response 3

Figure 4.2 shows nodes annotated with arrival times. If the outputs are all required at 200 ps,
the circuit has 60 ps of slack.

4.1.1 Timing Optimization

In most designs there will be many logic paths that do not require any
conscious effort when it comes to speed. These paths are already fast
enough for the timing goals of the system. However, there will be a number
of critical paths that limit the operating speed of the system and require
attention to timing details. The critical paths can be affected at four main levels:
◉ The architectural/microarchitectural level
◉ The logic level
◉ The circuit level
◉ The layout level

.
RC Delay Model:

RC delay models approximate the nonlinear transistor I-V and C-V characteristics
with an average resistance and capacitance over the switching range of the gate.

Effective Resistance:
 4.2 Transient Response 4

The RC delay model treats a transistor as a switch in series with a resistor. The
effective resistance is the ratio of Vds to Ids averaged across the switching interval of
interest.

A unit nMOS transistor is defined to have effective resistance R. The size of the unit
transistor is arbitrary but conventionally refers to a transistor with minimum length
and minimum contacted diffusion width (W/L ratio).. A unit pMOS transistor has
greater resistance, generally in the range of 2R–3R, because of its lower mobility.
4.2 Transient Response 5
4.2 Transient Response 6
Module -3 Semiconductor Memories
• Objectives:
Introduction to Semiconductor Memories
Dynamic Random Access Memory (DRAM)
Static Random Access Memory (SRAM)
Nonvolatile Memory (ROM)
Flash Memory
Ferroelectric Random Access Memory(FRAM)
Introduction
• Semiconductor memory arrays capable of storing large quantities of
digital information are essential to all digital systems.
• The amount of memory required in a particular system depends on
the type of application, but, in general, the number of transistors
utilized for the information (data) storage function is much larger
than the number of transistors used in logic operations and for other
purposes.
• The area efficiency of the memory array, i.e., the number of stored
data bits per unit area, is one of the key design criteria that determine
the overall storage capacity and, hence, the memory cost per bit.
• Another important issue is the memory access time, i.e., the time
required to store and/or retrieve a particular data bit in the memory
array
• The access time determines the memory speed, which is an important
performance criterion of the memory array.
• Finally, the static and dynamic power consumption of the memory
array is a significant factor to be considered in the design, because of
the increasing importance of low-power applications.
• Memory circuit s are generally classified according to the type of data
storage and the type of data access.
Overview of semiconductor memory types
ROM
• Read-Only Memory (ROM) circuits allow, as the name implies, only
the retrieval of previously stored data and do not permit
modifications of the stored information contents during normal
operation.
• ROMs are non-volatile memories, i.e., the data storage function is not
lost even when the power supply voltage is off.
• Depending on the type of data storage (data write) method, ROMs
are classified as mask-programmed ROMs, Programmable ROMs
(PROM), Erasable PROMs (EPROM), and Electrically Erasable PROMs
(EEPROM)
RAM
• Read-write (R/W) memory circuits, on the other hand, must permit
the modification (writing) of data bits stored in the memory array, as
well as their retrieval (reading) on demand.
• This requires that the data storage function be volatile, i.e., the stored
data are lost when the power supply voltage is turned off.
• The read-write memory circuit is commonly called Random Access
Memory (RAM),
• Based on the operation type of individual data storage cells, RAMs are
classified into two main categories:
Static RAMs (SRAM) and Dynamic RAMs (DRAM).
A typical memory array organization is shown in Figure
• The data storage structure, consists of individual memory cells arranged in
an array of horizontal rows and vertical columns.
• Each cell is capable of storing one bit of binary information.
• Also, each memory cell shares a common connection with the other cells in
the same row, and another common connection with the other cells in the
same column.
• In this structure, there are 2𝑁 rows, also called word lines, and 2𝑀 columns,
also called bit lines. Thus, the total number of memory cells in this array is
2𝑁 x 2𝑀 .
• To access a particular memory cell, i.e., a particular data bit in this array,
the corresponding bit line and the corresponding word line must be
activated (selected).
• The row and column selection operations are accomplished by row and
column decoders, respectively.
• The row decoder circuit selects one out of 2𝑁 word lines according to an N-
bit row address,
• while the column decoder circuit selects one out of 2𝑀 bit lines according
to an M-bit column address.
• Once a memory cell or a group of memory cells are selected in this
fashion, a data read and/or a data write operation may be performed
on the selected single bit or multiple bits on a particular row.
• The column decoder circuit serves the double duties of selecting the
particular columns and routing the corresponding data content in a
selected row to the output.
• We can see from this simple discussion that individual memory cells
can be accessed for data read and/or data write operations in random
order, independent of their physical locations in the memory array.
• Thus, the array organization examined here is called a Random
Access Memory (RAM) structure.
• Notice that this organization can be used for both read-write memory
arrays and read-only memory arrays.
Dynamic Read-Write Memory (DRAM) Circuits
• As the trend for high-density RAM arrays forces the memory cell size
to shrink, alternative data storage concepts must be considered to
accommodate these demands.
• In a dynamic RAM cell, binary data is stored simply as charge in a
capacitor, where the presence or absence of stored charge
determines the value of the stored bit.
• Note that the data stored as charge in a capacitor cannot be retained
indefinitely, because the leakage currents eventually remove or
modify the stored charge.
• Thus, all dynamic memory cells require a periodic refreshing of the
stored data, so that unwanted modifications due to leakage are
prevented before they occur.
• The use of a capacitor as the primary storage device generally enables
the DRAM to be realized on a much smaller silicon area compared to
the typical SRAM cell.
• Notice that even as the binary data is stored as charge in a capacitor,
the DRAM cell must have access devices, or switches, which can be
activated externally for "read" and "write“ operations.
• Note that a DRAM array also requires additional peripheral circuitry
for scheduling and performing the periodic data refresh operations.
• Following circuits shows some of the steps in the historical evolution
of the DRAM cell.
The four-transistor cell
• 4T DRAM is the simplest and one of the earliest dynamic memory
cells.
• This cell is derived from the six-transistor static RAM cell by removing
the load devices.
• The cell has in fact two storage nodes, i.e., the parasitic oxide and
diffusion capacitances of the nodes indicated in the circuit diagram.
• Since no current path is provided to the storage nodes for restoring
the charge being lost to leakage, the cell must be refreshed
periodically.
The three-transistor DRAM cell
• 3T DRAM cell is the first widely used dynamic memory cell.
• It utilizes a single transistor as the storage device (where the
transistor is turned on or off depending on the charge stored on its
gate capacitance)
• And one transistor each for the "read" and "write" access switches.
• The cell has two control and two I/O lines. Its separate read and write
select lines make it relatively fast, but the four lines with their
additional contacts tend to increase the cell area.
The one-transistor DRAM cell
• 1T DRAM cell has become the industry standard dynamic RAM cell in high-
density DRAM arrays. With only one transistor and one capacitor, it has the
lowest component count and, hence, the smallest silicon area of all the
dynamic memory cells.
• The cell has one read-write control line (word line) and one I/O line (bit
line).
• unlike in the other dynamic memory cells, the storage capacitance of the
one transistor DRAM cell is explicit.
• This means that a separate capacitor must be manufactured for each
storage cell, instead of relying on the parasitic oxide and diffusion
capacitances of the transistors for data storage.
• The word line of the one-transistor DRAM cell is controlled by the row
address decoder. Once the selected transistor is turned on, the charge
stored in the capacitor can be detected and/or modified through the bit
line.
Three-Transistor DRAM Cell Operation
• The circuit diagram of a typical three-transistor dynamic RAM cell is
shown in Fig. as well as the column pull-up (precharge) transistors
and the column read/write circuitry.
• Here, the binary information is stored in the form of charge in the
parasitic node capacitance C1. The storage transistor M2 is turned on
or off depending on the charge stored in C1, and the pass transistors
M1 and M3 act as access switches for data read and write operations.
• The cell has two separate bit lines for "data read" and "data write,"
and two separate word lines to control the access transistors.
• The operation of the three-transistor DRAM cell and its peripheral
circuitry is based on a two-phase non-overlapping clock scheme.
• The precharge events are driven by φ1,whereas the "read" and
"write" events are driven by φ2.
• Every "data read" and "data write“ operation is preceded by a
precharge cycle, which is initiated with the precharge signal PC going
high.
• During the precharge cycle, the column pull-up transistors are
activated, and the corresponding column capacitances C2 and C3 are
charged up to logic-high level.
• With typical enhancement type nMOS pull-up transistors (Vt= 1V) and
a power supply voltage of 5 V, the voltage level of both columns after
the precharge is approximately equal to 3.5 V.
• All "data read" and "data write" operations are performed during the
active φ2 phase, i.e., when PC is low.
Typical voltage waveforms associated with the 3-T DRAM cell during four consecutive operations:
write "1," read "1," write "0," and read “0."
Column capacitances C2 and C3 are being charged-up through MP1
and MP2 during the precharge cycle.
• For the write "1" operation, the inverse data input is at the logic-low
level, because the data to be written onto the DRAM cell is logic "1."
• Consequently, the "data write“ transistor MD is turned off, and the
voltage level on column Din remains high.
• Now, the"write select" signal WS is pulled high during the active
phase of φ2.
• As a result, the write access transistor M1 is turned on. With M1
conducting, the charge on C2 is now shared with C1.
• Since the capacitance C2 is very large compared to C1, the storage
node capacitance C1 attains approximately the same logic-high level
as the column capacitance C2 at the end of the charge-sharing
process.
Charge sharing between C2 and Cl during the write " 1 "
sequence.
• After the write "1" operation is completed, the write access transistor
M1 is turned off. With the storage capacitance C1 charged-up to a
logic-high level, transistor M2 is now conducting.
• In order to read this stored "1," the "read select" signal RS must be
pulled high during the active phase of φ2, following a precharge cycle.
• As the read access transistor M3 turns on, M2 and M3 create a
conducting path between the "data read“ column capacitance C3 and
the ground.
• The capacitance C3 discharges through M2 and M3, and the falling
column voltage is interpreted by the "data read" circuitry as a stored
logic "1."
• The active portion of the DRAM cell during the read "1" cycle is
shown in Figure below
The column capacitance C3 is discharged through the
transistors M2 and M3 during the read "1" operation

Note that the 3-T DRAM cell may be read repeatedly in this fashion without disturbing the charge
stored in C1.
• For the write "0" operation, the inverse data input is at the logic-high
level, because the data to be written onto the DRAM cell is a logic "0.“
• Consequently, the data write transistor is turned on, and the voltage
level on column Din is pulled to logic "0."
• Now, the "write select" signal WS is pulled high during the active
phase of φ2.
• As a result, the write access transistor M1 is turned on.
• The voltage level on C2, as well as that on the storage node C1, is
pulled to logic "0" through M1 and the data write transistor, as shown
in Figure below.
Both C1 and C2 are discharged via M1 and the data
write transistor during the write "0" sequence.
• Thus, at the end of the write "0" sequence, the storage capacitance
C1 contains a very low charge, and the transistor M2 is turned off
since its gate voltage is approximately equal to zero.
• In order to read this stored "0," the "read select" signal RS must be
pulled high during the active phase of φ2, following a precharge cycle.
• The read access transistor M3 turns on, but since M2 is off, there is
no conducting path between the column capacitance C3 and the
ground (as shown in Fig. below)
• Consequently, C3 does not discharge, and the logic-high level on the
Dout column is interpreted by the data read circuitry as a stored "0"
bit.
The column capacitance C3 cannot discharge during the read
"0" cycle
Operation of One-Transistor DRAM Cell
• The circuit diagram of the one-transistor (1-T) DRAM cell consisting of
one explicit storage capacitor and one access transistor is shown in
Fig. above
• Here, C1 represents the storage capacitor and Capacitor C2
represents the much larger parasitic column capacitance associated
with the word line.
• Charge sharing between this large capacitance and the very small
storage capacitance plays a very important role in the operation of
the 1-T DRAM cell.
• For the write "1"operation, the bit line (D) is raised to logic " 1 " by
the write circuitry, while the selected word line is pulled high by the
row address decoder.
• The access transistor M1 turns on, allowing the storage capacitor C1
to charge up to a logic-high level.
• For the write “0“ operation, the bit line (D) is pulled to logic “0" and
the word line is pulled high by the row address decoder.
• In this case, the storage capacitor C1 discharges through the access
transistor, resulting in a stored “0" bit.
• In order to read stored data out of a 1-T DRAM cell, on the other hand, we
have to build a fairly elaborate read-refresh circuit.
• The reason for this is the fact that the "data read" operation on the one-
transistor DRAM cell is by necessity a "destructive readout."
• This means that the stored data must be destroyed or lost during the read
operation.
• Typically, the read operation starts with precharging the column
capacitance C2.
• Then, the word line is pulled high in order to activate the access transistor
M1.
• Charge sharing between C1 and C2 occurs and, depending on the amount
of stored charge on C1, the column voltage either increases or decreases
slightly.
• Note that charge sharing inevitably destroys the stored charge on C1.
Hence, we also have to refresh data every time we perform a "data read"
operation.
1T DRAM cell array with control circuits
• A typical memory structure consisting of one transistor DRAM cell
array and the control circuits is shown in the above figure
• In recent DRAM architectures, the bit lines are folded and precharged
to ½ VDD to improve noise immunity and reduce power consumption
• In addition, the amplifier to sense the perturbed signal at the bit line
is shared by adjacent blocks
• Bit lines (BL and BLB) and sensing nodes (SA and SAB) are set to a
precharge level, half-VDD through bit and sensing line
equalizers,respectively
• Timing diagram of DRAM read operation for data “ 1” is shown,
• Before the read operation,the signals to precharge the bit lines(PEQ)
and bit line sense amplifier (PSAEQ) are disabled.
• The bit line amplifier is shared by two adjacent memory array blocks
to reduce the chip size.
• Thus, the memory array select signal (PISOi) is set to boosted
voltage(Vpp). Vpp is on chip boosted voltage
• A word line in the memory array block is selected according to the
row address
• When the word line is enabled,the charge at the cell capacitor Cs is
shared with bit line capacitance.since the bit line is precharged to ½
VDD a small voltage differenceis developed at the bit line
• The control signals(PSA and PSAB) are activated sequentially to
reduce the charge injection and short circuit current due to
simultaneous activation of N and P latches in the bit line sense
amplifiers
• Hence the BLB node is discharged to the ground and signal is
amplified
• The level of BLB and BL nodes eventually reaches the ground and the
operating voltage respectively and the voltage of storage node is
recovered, this is called restoring operation of the cell data
• The data on the bit lines are read by transferring the voltage levels to
the secondary data lines BL_IO and BL_IOB.
• After the voltage difference on the bit lines are amplified,the column
switch transistors are enabled by activating a column select line by
the column decoder.
• To sense the small signal difference, a latch amplifier is used.
• The sense nodes (SA and SAB) are connected together in the same
block and the source transistors(MNS and MPS) are placed per
memory array segment
• Typically, BL_IO and BL_IOB lines are precharged at VDD or VDD-Vtn,
since BLB is discharged to the ground the level of BL_IOB is slowly
discharged due to its large capacitance e,g., 10 times CBL through
MNC2.
• The level of BLB is affected slightly by the BL_IOB line. The voltage
difference on secondary data line is amplified by the read amplifier to
the full CMOS output level and transferred to the Memory interface
circuit drive the off chip load.
Static Read-Write Memory (SRAM) Circuits

• read-write (R/W) memory circuits are designed to permit the

modification (writing) of data bits to be stored in the memory array,
as well as their retrieval (reading) on demand.
• The memory circuit is said to be static if the stored data can be
retained indefinitely (as long as a sufficient power supply voltage is
provided), without any need for a periodic refresh operation.
• We will examine the circuit structure and the operation of simple
SRAM cells, as well as the peripheral circuits designed to read and
write the data.
• The data storage cell, i.e., the 1-bit memory cell in static RAM arrays,
invariably consists of a simple latch circuit with two stable operating
points (states).
• Depending on the preserved state of the two-inverter latch circuit,
the data being held in the memory cell will be interpreted either as a
logic "0" or as a logic " 1."
• To access (read and write) the data contained in the memory cell via
the bit line, we need at least one switch, which is controlled by the
corresponding word line, i.e., the row address selection signal
Symbolic representation of the two-inverter latch circuit
with access switches
Generic circuit topology of the MOS static RAM cell
Resistive-load SRAM cell
Depletion-load nMOS SRAM cell
Full CMOS SRAM cell
Full CMOS SRAM Cell
• A low-power SRAM cell may be designed simply by using cross-
coupled CMOS inverters instead of the resistive-load or nMOS
inverters.
• In this case, the stand-by power consumption of the memory cell will
be limited to the relatively small leakage currents of both CMOS
inverters.
• The possible drawback of using CMOS SRAM cells, on the other hand,
is that the cell area tends to increase in order to accommodate the n-
well for the pMOS transistors and the polysilicon contacts.
The circuit structure of the full CMOS static
RAM cell
• The circuit structure of the full CMOS static RAM cell is shown in the
figure above along with the pMOS column pull up transistors on the
complementary bit lines
• The memory cell consists of simple CMOS latch(two inverters
connected back to back),and two complementary access
transistors(M3 and M4)
• The cell will preserve one of its possible stable states, as long as the
power supply is available
• The access transistors are turned on whenever a word line(row) is
activated for read or write operation, connecting the cell to the
complementary bit-line columns
Operation of SRAM
SRAM Read and Write Timing Diagram
• The figure shows the memory structure of SRAM and timing diagrams
for the Read and Write operations
• In read operation, a word line is selected by arrow address
• Before the read operation, the bit lines are precharged to VDD or
VDD-Vtn.
• When word line is enabled, one of the bit lines is discharged through
an nMOS transistor connected to a ”0” node of the cell
• The sense amplifier to detect the voltage difference on the bit lines is
shared by the multiple bit lines(eg.,32) and the connection of sense
amplifier to a bit line pair is controlled by a column selection line
• A high gain voltage or current mode amplifier is used as the first stage
amplifier and voltage mode amplifier to generate CMOS level signals
DIO and 𝐷𝐼𝑂 with large current driving capability is used as the last
stage amplifiers
• In the write operation, the data to be written in to a cell and provided
by external devices and DIO and 𝐷𝐼𝑂 and DL and 𝐷𝐿 lines are set
according to the data
• When the column gates are opened the write buffer stars to write
data in to the cell.
Read-Only Memory (ROM) Circuits

Example of a 4-bit x 4-bit NOR-based ROM array

• The read-only memory array can also be seen as a simple
combinational Boolean network which produces a specified output
value for each input combination, i.e., for each address.
• Thus, storing binary information at a particular address location can
be achieved by the presence or absence of a data path from the
selected row (word line) to the selected column (bit line), which is
equivalent to the presence or absence of a device at that particular
location.
• Consider first the 4-bit x 4-bit memory array shown in Fig. Here, each
column consists of a pseudo-nMOS NOR gate driven by some of the
row signals, i.e., the word lines.
• only one word line is activated (selected) at a time by raising its
voltage to VDD, while all other rows are held at a low voltage level.
• If an active transistor exists at the cross point of a column and the
selected row, the column voltage is pulled down to the logic low level
by that transistor.
• If no active transistor exists at the cross point, the column voltage is
pulled high by the pMOS load device.
• Thus, a logic " 1 "-bit is stored as the absence of an active transistor,
while a logic “0"-bit is stored as the presence of an active transistor at
the cross point.
• Next, we will examine a significantly different ROM array design, which is
also called a NAND ROM. Here, each bit line consists of a depletion-load
NAND gate, driven by some of the row signals, i.e., the word lines.
• In normal operation, all word lines are held at the logic-high voltage level
except for the selected line, which is pulled down to logic-low level.
• If a transistor exists at the cross-point of a column and the selected row,
that transistor is turned off and the column voltage is pulled high by the
load device.
• On the other hand, if no transistor exists (shorted) at that particular cross-
point, the column voltage is pulled low by the other nMOS transistors in
the multi-input NAND structure.
• Thus, a logic "1 "-bit is stored by the presence of a transistor that can be
deactivated,
• While a logic "0"-bit is stored by a shorted or normally on transistor at the
cross-point.
NAND Based ROM array
Design of Row and Column Decoders
• We will examine the circuit structures of row and column address
decoders, which select a particular memory location in the array,
based on the binary row and column addresses.
• A row decoder designed to drive a NOR ROM array must, by
definition, select one of the 2𝑁 word lines by raising its voltage to
VOH.
• As an example, consider the simple row address decoder shown in
Fig., which decodes a two-bit row address and selects one out of four
word lines by raising its level.
Row address decoder example for 2 address bits and 4 word
lines
• A most straightforward implementation of this decoder is another
NOR array, consisting of 4 rows (outputs) and 4 columns (two address
bits and their complements).
• Note that this NOR-based decoder array can be built just like the NOR
ROM array, using the same selective programming approach
NOR-based row decoder circuit for 2 address
bits and 4 word lines.
Implementation of the row decoder circuit and the ROM array
as two adjacent NOR planes
• A row decoder designed to drive a NAND ROM, on the other hand, must
lower the voltage level of the selected row to logic "0" while keeping all
other rows at a logic-high level.
• This function can be implemented by using an N-input NAND gate for each
of the row outputs.
• The truth table of a simple address decoder for four rows and the double
NAND-array implementation of the decoder and the ROM are shown in Fig.
below
• As in the NOR ROM case, the row address decoder of the NAND ROM array
can thus be realized using the same layout strategy as the memory array
itself.
Truth table of a row decoder for the NAND ROM array, and
implementation of the row decoder circuit and the ROM array as two
adjacent NAND planes
Bit-line (column) decoder arrangement using a NOR address
decoder and nMOS pass transistors for every bit line.
FLASH memory cell
 MODULE 4
FAILURE AND FAULTS

INTRODUCTION:

 A failure is said to have occurred in a circuit or system if it deviates from its specified
behavior.A fault, on the other hand, is a physical defect that may or may not cause a
failure.

 A fault is characterized by its nature, value, extent, and duration. The nature of a fault
can be classified as logical or non logical. A logical fault causes the logic value at a point
in a circuit to become opposite to the specified value.Non logical faults include the rest
of the faults, such as the malfunction of the clock signal, power failure, and so forth.

 The value of a logical fault at a point in the circuit indicates whether the fault creates
fixed or varying erroneous logical values.The extent of a fault specifies whether the
effect of the fault is localized or distributed.

 A local fault affects only a single variable, whereas a distributed fault affects more than
on
 When testing digital circuits, two distinct philosophies are commonly used:

 1.Functional Testing: This approach involves performing a series of functional tests to

check whether the circuit produces the correct (fault-free) 0 or 1 output responses. It
doesn’t consider the circuit’s design details but focuses solely on correct outputs during
testing.
 2.Fault Modelling: Here, we consider possible faults that may occur during the
manufacture of integrated circuits (ICs). We compute the circuit’s output with and
without each fault present. Specific tests are then designed to detect or rule out the
presence of particular faults. If none of the chosen faults is detected, the IC is considered
fault-free

Terminology:

 Fault: A physical defect in the circuit.

 Error: The manifestation of a fault causing incorrect outputs.
 Failure: Occurs when a circuit deviates from its specified behavior due to an error
 MODELING OF FAULTS

Faults in a circuit may occur due to defective components, breaks in signal lines, lines
shortened to ground or power supply, short-circuiting of signal lines, ex- cessive delays, and
so forth.Besides errors or ambiguities in design specifications, design rule violations, among
other things, also result in faults.

Faults in Digital Circuits:

The total faults encountered during the commissioning of subsystems of a mid-range
mainframe computer implemented using MSI (Medium Scale Integration); however, during
the system validation such faults constituted 44% of the total.

Poor designs may also result in hazards, races, or metastable flip-flop behavior in a circuit;
such faults manifest themselves as "intermittents" through- out the life of the circuit.

In general, the effect of a fault is represented by means of a model, which represents the
change the fault produces in circuit signals.

The fault models in use today are

 Stuck-at fault
 Bridging fault
 Stuck-on and Stuck-open fault
 Delay fault
 Temporary fault

For the above fault models are explained in detailed:

1. STUCK AT FAULTS:

 Stuck-at Fault (SAF) is a type of fault analysis in which a node/pin in a digital circuit is
assumed to be fixed at logic 0 or logic 1.

 Stuck-at fault model is also called a permanent fault model because the faulty effect is
assumed to be permanent.

 Stuck-at fault occurs in logic gates which results in one of the inputs or the output being
fixed to either a logic 0 (stuck-at 0) or logic 1 (stuck-at 1).
LOGIC 1 ( STUCK AT 1)

A-> Logic 0 , B-> Logic 1

NAND Logic Table
A B Y Y’
0 0 1 1
0 1 1 0
1 0 1 1
1 1 0 0

EXPLAINATION:
 The most common model used for logical faults is the single stuck-at fault. It assumes
that a fault in a logic gate results in one of its inputs or the output being fixed to either a
logic 0 (stuck-at-0) or a logic 1 (stuck-at-1).

 Stuck-at-0 and stuck- at-1 faults are often abbreviated to s-a-0 and s-a-1, respectively,
and these abbreviations will be adopted here.

 Let us consider a NAND gate with input A s-a-1. The NAND gate perceives the input A
as a 1 irrespective of the logic value placed on the input.

 The output of the NAND gate in is 0 for the input pattern shown above, when the s-a-1
fault is present. The fault-free gate has an output of 1. Therefore, the pattern shown in
can be used as a test for the A input s-a-1, because there is a difference between the
output of the fault-free and the faulty gate.

 The stuck-at model, often referred to as classical fault model, offers good representation
for the most common types of failures, for example, short-circuits (shorts) and open
circuits (opens) in many technologies.

 Illustrates the CMOS (Complementary Metal Oxide Semiconductor) realization of a

NAND gate, the numbers 1, 2, 3, and 4 indicating places where opens have occurred.
2.BRIDGING FAULTS:
 With the increase in the number or devices on the VLSI chips, the probability of shorts
between two or more signal lines has been significantly increased.

 Unintended shorts between the lines form a class of permanent faults, known as bridging
faults.

 It has been observed that physical defects in MOS (Metal Oxide Semiconductor) circuits
are manifested as bridging faults more than as any other type of fault.

 Bridging faults can be categorized into three groups:

 Input bridging, Feedback bridging, Non feedback bridging.

 An input bridging fault corresponds to the shorting of a certain number of primary input
lines.

 Feedback bridging fault occurs if there is a short between an output line to an input line.
 A non feedback bridging fault identifies a bridging fault that does not belong to either of
the two previous categories.

 From these definitions, it will be clear that the probability of two lines getting bridged is
higher if they are physically close to each other.

 In general, a bridging fault in positive logic is assumed to behave as a wired-AND

(where 0 is the dominant logic value), and a bridging fault in negative logic behaves as a
wired-OR (where I is the dominant logic value).

 The presence of a feedback bridging fault can cause a circuit to oscillate or convert it into
a sequential circuit.

 The probable bridging fault in this circuit (or in any other CMOS circuit) can be grouped
into four categories:

1.Metal polysilicon short (a in Figs. 1.8(a) and (b))

2. Polysilicon n-diffusion short (c.d in Figs. 1.8(a) and (b))
3. Polysilicon p-diffusion short (e,f in Figs. 1.8(a) and (b))
4. Metal polysilicon short (g in Figs. 1.8(a) and (b))
 On the position of a break, that the gates of both transistors may float, in which case one
transistor may conduct and the other remain in a nonconducting state , this type of break
can be modeled as a stuck-at fault.

 On the other hand, if two transistors with floating gates are permanently conducting, one
of them can be considered as stuck on.

 If a transistor with a floating gate remains in a nonconducting state due to a signal line
break, the circuit will behave in a similar fashion as it does in the presence of the
integrate break b₂.
3.STUCK-ON AND STUCK-OPEN FAULTS

STUCK-ON FAULTS:

 A stuck-on fault occurs when a transistor remains permanently turned on (conducting)

regardless of its input.

 The faulty gate output is difficult to predict because the stuck-on transistor competes
with its complementary transistors for control of the output.

 Sometimes this competition doesn’t lead to catastrophic failure, but it can disrupt normal
circuit behavior.

STUCK-OPEN FAULTS

 A stuck-open fault creates an unintended high-impedance state on the output node of a

gate.

 The faulty gate output remains open (disconnected) even when it should be driving a
logic value.

 Stuck-open faults are modeled as additional non-classical faults alongside the standard
stuck-at faults.

4.DELAY FAULTS

Delay faults occur when a circuit is too slow to propagate signals through certain paths or
gates.
Even if the logic operations within the circuit are correct, the output may not be reached
within the allotted time due to delays.

Types:
 Gate Delay Faults (GDF)
 Path Delay Faults (PDF)
 Transition Delay Faults

1.Gate Delay Faults (GDF):

 GDFs occur due to variations in gate delays within a circuit.

 When a gate’s delay is significantly different from the expected value, it can lead to
incorrect timing behavior.
 These faults impact the propagation delay of signals through gates, affecting overall
circuit performance.

2.Path Delay Faults (PDF):

 PDF involve delays along specific signal paths within a circuit.

 A path may have longer or shorter delays than anticipated, leading to timing violations.
 Detecting PDF is crucial for ensuring reliable operation, especially in high-speed
designs.

3.Transition Delay Faults:

 Transition delay faults occur during signal transitions (rising or falling edges).
 These faults affect the timing between input and output transitions.
 Detecting and mitigating transition delay faults is essential for maintaining correct circuit
behavior.

5.TEMPORARY FAULTS:

● Temporary faults are the faults or errors that occur unpredictably and temporarily affect
the VLSI or electronic circuits.
● Temporary faults are often referred to as intermittent or transient faults with the same
meaning.
● Transient faults are non-recurring temporary faults.
● They are not repairable because there is no physical damage to the hardware.

CAUSES OF TRANSIENT FAULTS:

● They are the major source of failures in semiconductor memory chips.

● They are usually caused by alpha-particle radiation or power supply fluctuation.
INTERMITTENT FAULT:

● Intermittent faults are recurring faults that reappear regularly.

● An intermittent fault in a circuit causes a circuit malfunction only if it is active; if it is
inactive, the circuit operates correctly.
● A circuit is said to be in a fault-active state if a fault present in the circuit is active.
● It is said to be in the fault-not-active state if a fault is present but inactive.
CAUSES OF THE INTERMITTENT FAULT:

● Due to loose connections, partially defective components, or poor designs.

● Faults also occur due to environmental conditions such as temperature, humidity, and
vibration.
● Intermittent depend on how well the system is protected from its physical environment
through shielding, filtering, and cooling.

VTU QUESTIONS
MODULE 4 VDT

VLSI Design and Testing

Module 4
Part 2

Test generation for combinational logic circuits: Fault diagnosis of digital

circuits, test generation techniques for combinational circuits, detection of
multiple faults in combinational circuits.

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MODULE 4 VDT

FAULT DIAGNOSIS OF DIGITAL CIRCUITS

 Fault diagnosis includes fault detection and fault location. 

 Fault detection means the discovery of something wrong in a digital system
or circuit.
 Fault location means the identification of the faults with components,
functional modules, or subsystems, depending on the requirements.
 Any fault in a non redundant n-input combinational circuit can be
completely tested by applying all 2n input combinations to it; 2n increase
rapidly as n increases.
 A circuit is said to be non- redundant if the function realized by the circuit is
not same as the function realized by the circuit in the presence of fault.
 For eg: a sequential circuit
o With ‘n’ inputs and ‘m’
flip-flops

o Therefore, total number of input combinations to test the

circuitis given by 2m * 2n = 2m+n.

 To determine which faults have been detected by a set of test patterns a

process known as fault- simulation.
 For eg, a circuit has ‘x’- stuck at faults

 When all test patterns, done detected faults F used to compute fault coverage
(Fc).

 Fc=F / x

 Instead of simulating one fault at a time, parallel simulation is done, which

uses the word size N of a host computer to process N faults at a time.

2
MODULE 4 VDT

TEST GENERATION TECHNIQUES FOR COMBINATIONAL

CIRCUITS

ONE DIMENSIONAL PATH SENSITIZATION

• Basic principle involved in 1D path sensitization is to choose a path at the
point of failure to the output of the circuit.

• The path is said to be sentisized if we apply inputs to the gates along that
particular path under consideration.

Example 1:

 The fault is line X3 for S-a-1.

 To test X3 for S-a-1

 STEP 1:

Set X5=G2=1

X3=0
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MODULE 4 VDT

Then G5 = 1(note: if fault is absent)

 There are two ways of propagation from G5 that is G7G9 and G8G9

 STEP 2: Propagation through G7G9

Set G4 = G8 =1

Since G4=1, the output of G7 depends on the output of G5

 Similarly if G8=1 then the ckt output depends on G7 only. This is called
forward trace.

 STEP 3: the next phase is called the backward trace.

In backward trace the gate conditions to propagate the fault along the
sentisised path is established.

To set G4=1,

X1=G1=1,

Which implies X2=0

To set G2=1

X4=0

To set G8 to be 1

G6=0

Which requires either X2=0 or G3=0

 NOTE:

1. G6 cannot be set by making 0, because this would imply X3=1 but

previously we had taken the value of X3=0. So there is fault in the
circuit . The test X1X2X3X4X5=10001 detects fault X3-S-a-1.

2. If the output of the circuit is 0 then it is fault free circuit, if the output
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MODULE 4 VDT

is 1 then there will be fault in the circuit.

Example 2

 STEP 1: X2=X3=0,

Then G2=1

 STEP 2:X4=0

Then G6=0

 STEP 3:

To propagate through gate G8,

Set G4=G5=G7=0

X4=X2=0

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 MODULE 4 VDT

Then G3 =1

To make G5=0, set X1=1

G1=0 which implies X2=0

Makes G4=1

• We are unable to propagate through G8

• Similarly it is impossible to sentisize two paths simultaneously and also

make G4=G7=0

• Two inputs to G8 change from 0 to 1

• While the remaining two inputs remain fixed at 0

BOOLEAN DIFFERENCE
 The basic principle of the Boolean Difference is to derive two Boolean expressions- one of
which represents normal fault-free behaviour of the circuit, and the other, the logical
behaviour under assumed single s-a-1 or s-a-0 fault condition. 

 Let F(X) F(x1,....,xn) be a logic function of a variables. If one of the inputs to the logic
function, for example, input x, is faulty, then the output would be F(x1,...,xi,...,xn). The
Boolean difference of F(X) with respect to xi is defined as

 The function dF(X)/dxi is called the Boolean difference of F(X) with respect to xi.





 Some useful properties of Boolean difference are

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MODULE 4 VDT

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 MODULE 4 VDT





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 MODULE 4 VDT















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 MODULE 4 VDT














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 MODULE 4 VDT















D-A LGORITHM
 The D-algorithm is the first algorithmic method for generating tests
for nonre- dundant combinational circuits [2.7]. If a test exists for
detecting a fault, the D-algorithm is guaranteed to find this test.
Before the D-algorithm can be dis- cussed in detail, certain new
terms must be defined.
SINGULAR COVER
 The singular cover of a logic gate is basically a compact version of
the truth table. Figure 2.6 shows the singular cover for a two-input
NOR gate; Xs or blanks are used to denote that the position may be
either 0 or 1. Each row in the singular cover is termed a singular
cube. The singular cover of a network is just the set of singular
covers of each of its gates on separate rows in the table. This is
illustrated by the example in Fig. 2.7.

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MODULE 4 VDT

PROPAGATION OF D CUBES

 D-cubes represent the input-output behavior of the good and the

faulty circuit.

 The symbol D may assume only one value 0 or 1; D takes on the

value opposite to D; that is, if D = 1 overline D = 0 . and if D = 0
D1. The definitions of D and Dcould be interchanged, but they
consistent throughout the circuit.

 Thus, all Ds in a circuit imply the same value (0 or 1), and all Ds
will have the opposite value. The propagation D-cubes of a gate are
those that cause the output of the gate to depend only on one or
more of its specified inputs (and hence to propagate fault on these
inputs to the output). The propagation D-cubes for a two-input
NOR gate are

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MODULE 4 VDT

PRIMITIVE D CUBES OF A FAULT

 The primitive D-cube of a fault is used to specify the existence of a given

fault. It consists of an input pattern that brings the influence of a fault to
the output of the gate. For example, if the output of the NOR gate shown
in Fig. 2.6 is s - a + 0 the corresponding primitive D-cube of a fault is

 Here, the Dis interpreted as being a 1 if the circuit if fault-free and a 0 if

the fault is present. The primitive D-cubes for the NOR gate output s - a -
1 are

 The primitive D-cube of any fault in a gate can be obtained from the
singular covers of the normal and the faulty gates in the following manner:

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MODULE 4 VDT

 Form the singular covers of the fault-free and the faulty gate. Let alpha_{0}
and be sets of cubes in the singular covers of the fault-free gate the output
alpha_{1}
 Test Generation for Combinational Logic Circuits coordinates of which are
0 and 1, respectively, and let beta_{0} and beta_{1} be the corresponding
sets in the singular covers of the faulty gate. 2. Intersect members of
alpha_{1} with members of beta_{0} and members of alpha_{0} with
members of The intersection rules are similar to those u beta_{1} gation
D-cubes.

D INTERSECTION
 Finally, we need to consider the concept of D-intersection, which provides
the tool for building sensitized paths. This is first explained by a simple
example. Consider the simple circuit shown in Fig. 2.9. We attempt to
generate a test for the 2s - a + 0 fault, described by the D-cube of the fault:

 To transmit the overline D on line 4 through G_{2}*x we must try and

match, that is, intersect, the overline D specification with one of the
propagation D-cubes for G_{2} * Such a match is possible if we use the
propagation D-cube:

 This produces a full circuit D-cube:

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MODULE 4 VDT

Problem 1:

 Step 1: to find singular cover, primitive and propagation of d cubes

 Step 2 : to find d drive and consistency operations

15
MODULE 4 VDT

https://www.youtube.com/watch?v=mVoxhnDWM_w&t=180s

note : refer above link for D algorithm

PROBLEM 2

Step 1:

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MODULE 4 VDT

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MODULE 4 VDT

Step 2:

Step 3:

Step 4:

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MODULE 4 VDT

PODEM (path oriented decision making)

 PODEM is an enumeration algorithm in which all input patterns are
examined as tests for a given fault [2.8]. The search for a test continues till
the search space is exhausted or a test pattem is found. If no test pattern is
found, the fault is considered to be untestable. PODEM uses logic
schematic diagrams in a manner similur to the D-algorithm for deriving
tests, The high-level description of PODEM is shown in Fig. 2.12. The
functions of each box in the diagram are as explained below
 Box 1 Initially, all primary inputs (Pls) are at x; that is, they are
unassigned.One of the PIs is assigned a 0 or L, and the PI is recorded as an
unflagged node in a decision tree. Thus, the process is similar to branch in
the context of branch and bound ulgorithms.
 Box 2 The value at the selected primary input is forward traced in
conjunction with i's it the rest of the primary inputs, by using the five-
valued logic 0, 1, x,D. D.
 Box 3 If the input pattern of Box 2 constitutes a test, then the test generation
process is completed.
 Box 4 The decision tree increases in depth; that is, one more primary input
is assigned a () or 1 to check if it is possible to generate a test. Two possible
situations may arise while evaluating Box 4:

1. The signal line (on which a stuck-at fault is assumed to be present) has
the same logic value as the stuck-at value.

2. There is no signal path from an internal signal line to a primary output

such that the line is at D or D and all the lines are at x.

 In the first case, the fault remains masked in the presence of the assigned
input values, whereas in the second case the input patter cannot be a test,
because D or D cannot be propagated to the output. Therefore, only when
none of the foregoing situations occurs is a test possible with the current
assignment of Pls
 Box 5 If all primary inputs have been assigned values and a test patter is
still not found, it is checked whether an untried combination values at the
inputs might generate a test or not.

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MODULE 4 VDT

It is clear from the preceding discussion that the decision tree is an ordered ' list
of nodes (Fig. 2.13) having the following features:

1. Each node identifies a current assignment of 0 or 1 to a primary input.

2. The ordering reflects the sequence in which the current assignments have been
made.

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0
MODULE 4 VDT

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MODULE 4 VDT

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2
MODULE 4 VDT

FAN(Fanout-Oriented Test Generation)

 The FAN algorithm is in principle similar to PODEM, but more
efficient. The efficiencyis achieved by reducing the number of
backtracks in the search tree. Unlike PODEM, where the
backtracking is done along a single path, FAN uses the concept
of multiple back trace.
 A bound line is a gate output that is part of reconvergent fan-
out loop, a line that is notbound is considered to be free.
 A headline is a free line that drives a gate that is part of a reconvergent
fan-out loop.
 In Fig. 2.18, for example, nodes H, I, and J are bound lines, A

21
3
MODULE 4 VDT

through H are free lines, and G, H, and F are headlines. Because

by definition headlines are free lines, they can beconsidered as
primary input lines and can always be assigned values
arbitrarily. Thus, during the back- trace operation, if a headline
is reached, the back tree stops; it is not necessary to reach a
primary input to complete the back trace.
 FAN uses a technique called multiple back trace to reduce the
number of backtracks that must be made during the search
process.

DELAY FAULT DETECTION

o A delay fault in a combinational logic circuit can be detected only
by applying a sequence of two test patters. The first pattern, known
as an initialization pattern, sets up the initial condition in a circuit so
that the fault slow-to-rise or slow-to-fall signal at the input or output
of a gate can affect an output of the circuit. The second patter, known
as a transition or propagation pattern, propigtes the effect of the
activated transition to a primary output of the circuit.
o To illustrate, let us consider a delay (slow-to-rise) fault at the input
1 of the circuit shown in Fig. 2.21. The lest for slow-to-rise fault
consists of the initialization pattern ABC = 001, followed by the
transition pattern ABC = 101. Similarly, the two pattern tests for a
slow-to-fall delay fault at input A will be ABC = 101, 001. Note that
the slow-to-rise fuult (slow-to-fall fault) corresponds to a trunsient
stuck-at-0 (stuck-at-1) fault.

21
4
MODULE 4 VDT

 To identify the presence of a delay fault in a combinational circuit, the

hardware model shown in Fig. 2.22 is frequently used in literature.
 The initialization pattern is first loaded into the input latches. After the
circuit has stabilized, the transition patter is clocked into the input latches
by using C1. The output pattern of the circuit is next loaded into the output
latches by setting the clock C2 at logic 1 for a period equal to or greater
than the time required for the output patter to be loaded into the latch and
stabilize.
 The possible presence of a delay fault is confirmed if the output value is
different from the expected value.
 Delay tests can be classified into two groups: nonrobust and robust [2.10].
 A delay fault is nonrobust if it can detect a fault in the path under
consideration provided there are no delay faults along other paths. For
example, the input vector pair (111, 101) can detect the slow-to-rise fault
at e in Fig. 2.23(a) as long as the path b- / does not have a delay fault.
However, if there is a slow-to-fall fault at d, the output of the cireuit will
be correct for the input pair, thereby invalidating the test for the delay fault
at e. Therefore, the test (111, 101) is nonrobust.

21
5
MODULE 4 VDT

 A deny test is considered to be robust if it detects the fault in a path

independent of delay faults that may exist in other paths of the circuit.
 For example, let us assume a slow-to-fall delay fault at d in the path a-c-d-
f of the circuit shown in Fig. 2.23(b). The input vector pair (01, 11)
constitutes a robust test for the delay fault because the output of any gate
on the other paths does not change when the second vector of the input pair
is applied to the circuit.
 Thus, any possible delay fault in these paths will not affect the circuit
output. Robust tests do not exist for many paths in large circuits
[2,11,2.12). Significant research in recent years has concentrated on the
design of circuits that are fully testable for all path delay faults using robust
tests [2.13-2.16].

DETECTION OF MULTIPLE FAULTS IN COMBINATIONAL

LOGIC CIRCUITS
 One of the assumptions normally made in test generation schemes is that
only a single fault is present in the circuit under test. This assumption is
Valid only if the circuit is frequently tested, when the probability of more
than one fault occurring is small.
 However, this is not true when a newly manufactured circuit is tested for
the first time. Multiple-fault assumption is also more realistic in the VLSI
environment, where faults occurring during manufacture frequently affect
several parts of a circuit. Some statistical studies have shown that multiple
faults, composed of at least six single faults, must be tested in a chip to
establish its reliability [2.17).
 Designing multiple-fault detection tests for a logic network is difficult
because of the extremely large number of faults that have to be considered.
In a circuit having k lines there are 2k possible single faults, but a total of
3* - 1 multiple faults (2.18). Hence, test generation for all possible multiple
faults is impractical even for small networks. One approach that reduces
the number of faults that need be tested in a network is fault collapsing
which uses the concept of equivalent faults [2.19,2.20).

21
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MODULE 4 VDT

 For example, an x-input logic gate can have 2x + 2 possible faults; however,
for certain input faults, a gate output would be forced into a state that is
indistinguishable from one of the s-a-0/s-a-1 output faults. Thus, for an
AND gate any input s-a-0 fault is indistinguishable from the output s-a-0
fault, and for an OR gate any input s-a-1 fault is indistinguishable for the
output s-a-1 fault. Such faults are said to be equivalent. For a NAND
(NOR) gate, the set of input s-a-0 (s-a-1) faults and the set of outputs faults
s-a-1 (s-a-0) are equivalent. Thus, an x-input gate has to be tested for x + 2
logically distinct faults.
 A systematic approach that reduces the number of faults that have to be
considered in test generation is the process of fault folding (2.21). The
central idea behind the process is to form fault equivalence classes for a
given circuit by folding faults toward the primary inputs. For non
reconvergent fan-out circuits, the folding operation produces a set of faults
on primary inputs, and this set test covers all faults in the circuit. For
reconvergent fan-out circuits, the set of faults at the primary inputs, fan-
out origins, and fan-out branches test cover all faults in the circuit.
 Another approach that results in a significant reduction in the number of
faults to be tested uses the concept of prime faults (2.22). The set of prime
faults for a network can be generated by the following procedure: 1. Assign
a fault to every gate input line if that is a primary input line or a fan-out
branch line. The fault is s-a-1 for AND/NAND gate inputs, und 6-a-0 for
OR/NOR gate inputs. Treat an inverter as a single input NANI/ NOR gate
if its output is a primary output; otherwise, no fault value should be
assigned to an inverter input line.
 2. Identify every gate that has faults assigned to all its input lines as a prime
gate. Assign a fault to the output line of every prime gate that does not fan
out. The fault is s-a-0 for AND/NOR gate outputs, and s-a-1 for OR/NAND
gate outputs.

21
7
MODULE 4 VDT

 The number of prime faults in a network is significantly fewer than the

number of single faults, because many single faults can be represented by
equivalent multiple prime faults. In general, test sets derived under the
single-fault assumption can detect a large number of multiple faults.
However, there is no guarantee that a multiple fault will be detected by a
single-fault-detecting test set, although all the single-fault components of
the multiple fault may be individually detected; this is due to masking
relations between faults [2.23].
 Schertz et al. (2.24] have shown that for a restricted fan-out-free network,.
Every single-fault detection test set is also a multiple-fault detection test
set. Any network that does not contain the network of Fig. 2.24 (or its
equivalent) as a subnetwork is called a restricted fan-out-free network. It
has been proved that the. network of Fig. 2.24 is the smallest fan-out-free
network that can contain multiple faults that are not detected by every
single-fault detection test set [2.18]. Bossen and Hong [2.25] have shown
that any multiple fault in a network can be represented by an equivalent
fault, the components of which are faults on certain checkpoints in the
network. Checkpoints are associated with each fan-out point and each
primary input. Agarwal and Fung [2.26] have shown that the commonly
used hypothesis about testing multiple faults by single-fault tests is not
correct for reconvergent fan-out circuits. They suggested that the only way
to test for multiple faults in VLSI chips is to design them so that they will
be easily testable for multiple faults.

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MODULE 4 VDT

MODEL PAPER QUESTIONS

1. For the circuit shown in Fig.2 using Boolean difference (i) detect
s@0 and s@1 at x2, (ii) determine partial Boolean difference for
x2-l-n-p-F.

2. What is fault diagnosis? Explain one dimensional path sensitization

technique for combinational circuits with an example.

3. Find the test pattern for line 6 s@0 for the circuit shown in Fig.3
using D Algorithm.

31
MODULE 4 VDT

32
 Module -5 Part a
Test generation for sequential circuit
EX:1 Homing sequence

To find the terminal node:

1. If the node obtained if it is identical to earlier node is called
homogenous node. Then it is terminal node
2. Anode which each group consist of just single state, then that is a
trivial component
Response of machine M in homing sequence:

Distinguish sequence:
Distinguishing tree:

Sequence is “ 10”

Response of machine M in distinguishing sequence:

For detail visit

https://www.youtube.com/watch?v=jiK42XKC9Yo&t=6s
https://www.youtube.com/watch?v=hk37zJcec9I
Module 5 VLSI Design (21EC63)

Module-05 (part 2)
Design of Testable Sequential Circuits

TOPICS
1. Controllability and Observability
2. Adhoc Design Rules
3. Diagnosable Sequential Circuits
4. Scan Path Technique
5. LSSD
6. Random Access Scan
7. Partial Scan

Dept of ECE, AIT Page 1

Module 5 VLSI Design (21EC63)

Module-05 (part 2)
Design of Testable Sequential Circuits

5.1 Controllability and Observability

 There are two key concepts in designing for testability: controllability and observability.
Controllability refers to the ability to apply test patterns to the inputs of a subcircuit
via the primary inputs of the circuit. For example, in Fig. 5.1(a) if the output of the
equality checker circuit is always in the state of equal, it is not possible to test whether
the equality checker is operating correctly or not. If a control gate is added to the circuit
(Fig. 5.1(b)), the input of the equality checker and hence, the operation of the circuit
can be controlled. Therefore, to enhance the controllability of a circuit, the state that
cannot be controlled from its primary inputs has to be reduced.

Figure 5.1 Controllability

 Observability refers to the ability to observe the response of a subcircuit via the
primary outputs of the circuit or at some other output points. For example, in Fig. 5.2
the outputs of all three AND gates are connected to the inputs of the OR gate. A stuck-
at-0 fault at the output of the AND gate 3 is not detectable because the effect of the fault
is masked and cannot be observed at the primary output. To enhance the observability,
we must observe the output of the gate Separately as shown.

Dept of ECE, AIT Page 2

Module 5 VLSI Design (21EC63)

Figure 5.2 Observability

 In general, the controllability/observability of a circuit can be enhanced by

incorporating some control gates and input lines (controllability), and by adding some
output lines (observability).

5.2 Ad Hoc Design Rules for Improving Testability

Ad hoc rules are used to improve testability of specific circuits. One of the simplest ways of
achieving this is to incorporate additional control and observation points in a circuit. For
example, the fault o stuck-at-1 in the circuit of Fig. 5,3(a)is undetectable at the circuit output.
The addition of an extra-output line in the circuit makes the fault detectable (Fig, 5.3(b)).

The usefulness of inserting a control point can be understood from the circuit shown in Fig.
5.4(a). The output of the NOR gate is always 0; therefore, it is not possible to determine whether
the gate is functioning correctly or not. If a control point is added to the circuit as shown in Fig.
5.4(b), the NOR gate can be easily tested for single stuck-at fault.

Another way of improving testability is to insert; multiplexers to increase the number of

internal points that can be controlled or observed from the external pins. For example, in the
circuit of Fig. 5.5(a) the fault a stuck-at-0 is undetectable at the primary output Z. By
incorporating a multiplexer as shown in Fig. 5.5(b), input combination 010 can be applied to
detect the fault via the multiplexer output.

A different way of achieving access to internal points is to use tristate drivers as shown in Fig.
5.6. A test mode signal could be used to put the driver into the high impedance state. In this
mode, the internal point could be used as a control point. When the driver is activated, the
internal point becomes a test point.

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Another approach to improve, testability is to permit access to a subset of the logic as shown
in Fig. 5.7 [5.1,5.2]. Module 8 is physically embedded between the two modules A and C. A
set of gates G and H is inserted into each of the inputs and outputs, respectively, of module B.
In normal operation, the test control signal is such that modules A, B, and C are connected and
the complete network performs its desired function. In the test mode, the test control input is
changed;

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module B is connected to the primary inputs and outputs of the board. In this mode, the control
signal also causes the Outputs of module C to assume a high impedance state, and hence C
does not interfere with the test results generated by B, Basically, this approach is similar to the
previously discussed technique of using multiplexers to improve testability.

The test mode signals required by the 4 hardware such as multiplexers, tristate drivers, and so
forth cannot always be applied via the edge pins, because there may not be enough of them. To
overcome this problem, a “test state register” may be incorporated in the design. This could in
fact be a shift register that is loaded and controlled by just a few signals, The various testability
hardware in the circuit can then be controlled by the parallel outputs of the shift register.

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Frequently, flip-flops, counter, shift registers, and other memory elements assume
unpredictable states when power is applied, and they must be set to known states before testing
can begin, Ideally, all memory elements should be reset from the external pins of the circuit,
whereas in some cases additional logic may be required (Fig, 5.8), With complex circuits it
may be desirable to set memory elements in several known states, This not only allows
independent initialization, it also simplifies generation of certain internal states required to test
the board adequately.

A long counter chain presents another practical test problem. For example, the counter chain
shown in Fig. 5.9 requires thousands of clock pulses to go through all the states, One way to
avoid this problem is to break up the long chain into smaller ones by using a multiplexer. When
the control input c of the multiplexer is al logic 0, the counter functions normally, When c is at
logic 1, the counter is partitioned into two smaller counters.

A feedback loop is difficult to test, because it hides the source of a fault. The Source can be
located by breaking the loop physically and bringing both lines to external pins that can be
short-circuited for normal operation. When not short-circuited, the separated lines provide a
control point and a test point. An alternative way of breaking a feedback loop, rather than using
more costly test/control points, is to add to the feedback path a gate that can be interrupted by
a signal from the tester (Fig. 5.10).

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5.3 Design of Diagnosable Sequential Circuits

The use of checking experiments to determine whether a sequential circuit represents the
behavior specified by its state table yields good results provided that

1. The circuit is reduced and strongly connected.

2. The circuit has a distinguishing sequence.
3. The actual circuit has no more states than the correctly operating circuit.

For circuits that do not have any distinguishing sequences, the checking experiments are very
long and consequently hard to apply in any practical situation. One approach to this problem
is to modify a given circuit by adding extra outputs so that the modified circuit has a
distinguishing sequence. A sequential circuit which possesses one or more distinguishing
sequences is said to be diagnosable.
A procedure for modifying a sequential circuit to possess a distinguishing
sequence if it does not already do so has been presented by Kohavi and Lavelle [5.3]. Let us
explain the procedure by considering the state table of Circuit M shown in Fig. 5.11(a); Circuit
M does not have a distinguishing sequence. The procedure begins with the construction of the
testing table of the circuit; the testing table for Circuit M is shown in Fig. 5.11(b). The column
headings consist of all input/output combinations, where the pair X/Z corresponds to input X
and output Z. The entries of the table are the ‘‘next state.’’ For example, from state A under
input the circuit goes to state 8 with an output of 0. This is denoted by entering B in column
1/0 and a dash (—) in column 1/1. In a similar manner, the next states of A are entered in the
upper half of the table.

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The lower half of the table is derived in a straightforward manner from the upper half. If the
entries in rows Si, and Sj column Xk/Z1 of the upper half are Sp and Sq respectively, the entry
in row SiSj, column Xk/Z1, of the lower half, is SrSq. For example, because the entries in rows
A and B, column 1/0, B and C, respectively, the corresponding entry in row AB, column 1/0,
is BC and so on. If for a pair Si and Sj either one or both corresponding entries in some column
Xk/Z1 are dashes, the corresponding entry in row SiSj, column Xk/Z1, is a dash. For example,
the entry in row BD, column 0/0, is a dash, because the, entry in row D, column 0/0, is a dash.
Whenever an entry in the testing table consists of a repeated state (e.g., AA in row AB), that
entry is circled. A circle around AA implies that both states A and B are merged under input 0
into state A and hence are indistinguishable by any experiment Starting with an input 0.

The next step of the procedure is to form the testing graph of the circuit. The testing graph is a
directed graph with each node corresponding to a row in the lower half of the testing table. A
directed edge labeled Xk/Z1 is drawn from node SiSj to node SpSq, where p not equal q, if
there exists an entry in row SiSj column Xk/Z1 of the testing table. Figure 5.12 shows the
testing graph for Circuit M.
A circuit is definitely diagnosable if and only if its testing graph has no loops and there
are no repeated states, that is, no circled entries in its testing table. Circuit M is therefore not
definitely diagnosable, because AA exists in its testing table and its testing graph contains tow
loops: AB-BC-CD-AD-AB and AC-BD-AC.

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To make the circuit definitely diagnosable, additional output variables are required to
eliminate all repeated entries from its testing table and to open all loops in its testing graph.
The maximum number of extra output terminals re- quired to make a 2^k state circuit definitely
diagnosable is k; however, the addition of one output terminal is sufficient to make Circuit M
definitely diagnosable. The modified state table of Circuit M is shown in Fig. 5.13; this version
possesses the distinguishing sequences 0 and 11. The checking experiment for a definitely
diagnosable circuit can be derived as follows:
1. Apply a homing sequence, followed by a transfer sequence (Si, So) is necessary, to bring the
circuit into an initial state So.
2. Choose a distinguishing sequence so that it is the shorter one of the sequences of all 0s or all
1s.
3. Apply the distinguishing sequence followed by a 1. (If the all-0s sequence has been chosen,
apply a 0 instead of a 1.)
4. If S01, that is, the 1-successor of S0, is different from S0, apply another 1 to check the
transition from S01, under a 1 input. Similarly, if S011 not equal to S01 and S011 not equal to
S0, apply another 1.Continue to apply 1 inputs in the same manner as long as new transitions
are c

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5. When an additional 1 input does not yield any new transition, apply an input of 0 followed
by the distinguishing sequence.
6. Apply inputs of 1s as long as new transitions can be checked. Repeat steps 5 and 6 when no
new transitions can be checked.
7. When steps 5 and 6 do not yield any new transitions and the circuit, which is in state Si, is
not yet completely checked, apply the transfer sequence T(Si, Sk), where Sk is a state the
transition of which has not been checked, such that T(Si, Sk) passes through checked transitions
only,
8. Repeat the last three steps until all transitions have been checked.

The checking experiment for the definitely diagnosable circuit of Fig. 5.13 has been designed
using the foregoing procedure. It required only 23 symbols and is illustrated here:

5.4 The Scan-Path Technique for Testable Sequential Circuit Design

The testing of sequential circuits is complicated because of the difficulties in setting and
checking the states of the memory elements. These problems can be overcome by modifying
the design of a general sequential circuit so that it will have the following two properties [5.4]:
1. The circuit can easily be set to any desired internal state.
2. It is easy to find a sequence of input patterns such that the resulting out- put sequence will
indicate the internal state of the circuit. In other words: the circuit has a distinguishing
sequence.

The basic idea is to add an extra input c to the memory excitation logic in order to control the
mode of a circuit, When c = 0, the circuit operates in its normal mode, but when c = 1, the
circuit enters into a mode in which the elements are connected together to form a shift register.
This facility is incorporated by inserting a double-throw switch in each input lead of every
memory element.

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All these switches are grouped together, and the circuit can operate either in its normal mode
or shift register mode. Figure 5.14 shows a sequential circuit using D flip-flops; the circuit is
modified as shown in Fig. 5.15, Each of the double throw switches may be realized as in Fig
5.16.

eae : eae ‘ ee
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In the shift register mode, the first flip-flop can be set directly from the primary inputs
(scan-in inputs) and the output of the last flip-flop can be directly monitored on the primary
output (scan-out output). This means that the circuit can be set to any desired state via the scan-
in inputs, and that the internal state can be determined via the scan-out output. The procedure
for testing the circuit is as follows:

1 Set c = 1 to switch the circuit to shift register mode.

2. Check operation as a shift register by using scan-in inputs, scan-out out-
put, and the clock.
3. Set the initial state of the shift register.
4. Set c = 0 to return to normal mode.
5. Apply test input pattern to the combinational logic.
6. Set c = 1 to return to shift register mode.
7. Shift out the final state while setting the Starting state for the next test.
8. Go to step 4.

The main advantage of the scan-path approach is that a sequential circuit can be transformed
into a combinational circuit, thus making test generation for the circuit relatively easy. Besides,
very few extra gates or pins are required for this transformation.

Another implementation of the scan-path technique has been described by Funatsu et al. [5.5].
The basic memory element used in this approach is known as a raceless D-type flip-flop with
scan path [5.6] Figure 5.17(a) shows such a memory element, which consists of two latches L/
and L2. The two clock signals Cl and C2 operate exclusively, During normal operation, C2
remains at logic 1 and C/ is set to logic 0 for sufficient time to latch up the data at the data input
D1. The output of L1 is latched into L2 when C1 returns to logic 1.
Scan-in operation is realized by clocking the test input value at D2 into the latch L1 by
setting C2 to logic 0. The output of the L1 latch is clocked into L2 when C2 returns to logic 1.

The configuration of the scan-path approach used at logic card level is shown in Fig.
5.17(b). All the flip-flops on a logic card are connected as a shift register, such that for each
card there is one scan path. In addition, there is provision for selecting a specified card in a
subsystem with many cards by X-Y address signals (Fig. 5.17(b)). If a card is not selected, its
output is blocked; thus, a number of card outputs in a subsystem can be put together with only
a particular card having control of the test output for that subsystem. The Nippon Electric
Company in Japan has adopted this version of the scan path approach to improve the testability
of their FLT-700 processor system.

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5.5 Level-Sensitive Scan Design (LSSD)

One of the best known and the most widely practiced methods for synthesizing testable
sequential circuits is the IBM LSSD (level-sensitive scan design).

5.5.1 CLOCKED HAZARD-FREE LATCHES

In LSSD, all internal Storage is implemented in hazard-free polarity-hold latch. The

polarity-hold latch has two input signals as shown in Fig. 5.18(a). The latch cannot change state
if C = 0. If C is set to 1, the internal stateof the latch takes the value of the excitation input D.
A flow table for this sequential network, along with an excitation table and a logic
implementation shown in Fig. 5.18.

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The clock signal C will normally occur (change from 0 to 1) after the data signal D has
become stable at either a 1 or a 0. The output of the latch is set to the new value of the data
signal at the time the clock signal occurs. The correct changing of the latch does not depend on
the rise or fall time of the clock signal, only on the clock signal being 1 for a period equal to or
greater than the time Required for the data signal to propagate through the latch and stabilize.
A shift register latch (SRL) can be formed by adding a clocked input to the polarity-
hold latch L1 and including a second latch L2 to act as intermediate storage during shifting
(Fig. 5.19). As long as the clock signals A and B are both 0, the L1 latch operates exactly like
a polarity-hold latch. Terminal 1 is the scan-in input for the shift register latch and +L2 is the
output. The logic implementation of the SRL is shown in Fig. 5.20.

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When the latch is operating as a shift register, data from the preceding Stage are gated
into the polarity-hold switch via l, through a change of the clock A from 0 to 1. After A has
changed back to 0, clock B gates the data in the latch L1 into the output latch L2 Clearly, A
and B can never both be 1 at the same time if the shift register latch is to operate properly.
The SRLs can be interconnected to form a shift register as shown in Fig. 5.21. The input
l and the output +L2 are strung together in a loop, and the clocks A and B are connected in
parallel.

5.5.2 LSSD DESIGN RULES

A specific set of design rules has been defined to provide level-sensitive logic subsystems with
a scannable design that would aid testing [5.8).

Rule 1: All intemal storage is implemented in hazard-free polarity-hold latches.

Rule 2: The latches are controlled by two or more nonoverlapping clocks such that
(a) Two latches, where one feeds the other, cannot have the same clock (see Fig.
5.22(a)).

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Rule 3: It must be possible to identify a set of clock primary inputs from which the clock
inputs to SRLs are controlled either through simple powering trees or through logic that is
gated by SRLs and/or non-clock primary inputs (see Fig. 5.23). Given this structure, the
following rules must hold:

(a) All clock inputs to all SRLs must be at their OFF states when all clock primary inputs
are held to their OFF states (bee Fig. 5.23(a)).

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(b) The clock signal that appears at any clock input of any SRL must be controllable from
one or more clock primary inputs, such that it is possible to set the clock input of the SRL to
an ON state by turning any one of the corresponding clock primary inputs to its ON state and
also setting the required gating condition from SRLs and/or non-clock primary inputs.

(c) No clock can be ANDed with either the true value or the complement value of another
clock (see Fig. 5.23(b)).

Rule 4: Clock primary inputs may not feed the data inputs to latches either directly or through
combinational logic, but they may only feed the clock input the latches or the primary outputs.
A sequential logic network designed in accordance with Rules 1-4 would be level-
sensitive. To simplify testing and minimize the primary inputs and outputs, it must also be
possible to shift data into and out of the latches in the system. Therefore, two more rules must
be observed:

Rule 5: All SRLs must be interconnected into one or more shift registers, each of which has
an input, an output, and clocks available at the terminals of the module.

Rule 6: There must exist some primary input sensitizing condition (referred to as the scan state)
such that
(a) Each SRL or scan-out primary output is a function of only the preceding SRL or scan-
in primary input in its shift register during the shifting operation.
(b) All clocks except the shift clocks are held OFF at the SRL inputs.
(c) Any shift clock to an SRL may be turned ON and OFF by changing the corresponding
clock primary input for each clock.

A sequential logic network that is level-sensitive and also has the scan Capability as per
Rules 1 to 6 is called a level-sensitive scan design (LSSD). Figure 5.24(a) depicts a general
structure for an LSSD system in which all system Output are taken from the L2 latch; hence, it
is called a double-latch design. In the double-latch configuration, each SRL operates in a
master-slave mode. Data transfer occurs under system clock and scan clock B during normal
operation, and under scan clock A and scan clock B during scan-path operation. Both latches
are therefore required during system operation. In the single-latch configuration, the
combinational logic is partitioned into two disjoint sets, Comb1 and Comb2 (Fig. 5.24(b)). The
system clocks used for SRLs in. Comb1 and Comb2 are denoted by Clock1 and Clock2,
respectively; they are nonoverlapping.
The outputs of the SRLs in Comb1 are fed back as secondary variable inputs to Comb2, and
vice versa. This configuration uses this output of latch L1 as the system output;

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the £2

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The L2 latch is used only for shifting. In other words, the L2 latches are redundant and
represent an overhead for testability. However, the basic SRL design can be modified to reduce
the overhead. The modified latch galled the L1/L2* SRL is shown in Fig. 5.25. The main
difference between the basic SRL and the L1/L2* SRL is that L2* has an alternative system
data input D2 clocked in by a separate system clock C2. The original data input D in Fig. 5.19
is also available and is now identified as D1 in Fig. 5.25. D1 is clocked in by the original system
clock, which is now called C1. Clock signals C1 and C2 are nonoverlapping. The single-latch
configuration of Fig. 5.25(b) can now be modified to the configuration of Fig. 5.26, in which
the system output can be taken from either the L1 output or the L2* output. In other words,
both L1 and L2* are utilized, which means fewer latches are required in the system. As a result,
there is a significant reduction in the silicon cost when L1/L2* SRLs are used to implement the
LSSD. Although both latches in L1/L2* SRLs can be used for system functions, it is absolutely
essential, as in conventional LSSD, that both L1 and L2* outputs do not feed the same
combinational logic.

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5.5.3 ADVANTAGES OF THE LSSD TECHNIQUE

The LSSD approach is very similar to the scan-path approach used by the NEC, except that it
has the level-sensitive attribute and requires two separate clocks to operate latches LJ and L2.
The use of LSSD alleviates the testing problems in the following ways:

1. The correct operation of the logic network is independent of a.c. characteristics such as
clock edge rise time and fall time.
2. Network is combinational in nature as far as test generation and testing is concerned.
3. The elimination of all hazards and races greatly simplifies both test gen eration and fault
simulation.

Any desired pattern of 1s and 0s can be shifted into the polarity-hold latches inputs to the
combinational network. For example, the combinational network of Fig. 5.24(a) is tested by
shifting part of each required pattern into the SRLs, with the remainder applied through the
primary inputs. Then the system clock is turned on for one cycle, the test pattern is propagated
through the combinational logic, and the result of the test is captured in the register and at the
primary outputs. The result of the test captured in the register is then scanned out and compared
with the expected response. The shift register must also be tested, and accomplished by shifting
a short sequence of 1s and 0s through the shifted latches.

5.6 Random Access Scan Technique

The design methods discussed in Secs. 5.4 and 5.5 use sequential access scan-in techniques to
improve testability; that is, all flip-flops are connected in testing to form a shift register or
registers. In an alternative approach, known as random access scan each flip-flop in a logic

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network is selected in an address for control and observation of its state [5.11]. The basic
memory element in a random access scan-in/scan-out network is an addressable latch. The
circuit diagram of an addressable latch is shown in Fig. 5.27. A latch Y address signals, the
state of which can then be controlled and scan-in/scan-out lines. When a latch is selected and
its scan 0 to 1, the scan data input is transferred through the network to output, where the
inverted value of the scan data can be observed. DATA line is transferred to the latch output Q
during the negative transition (1 to 0) of the clock. The scan data out lines from all latches are
produce the chip scan-out signal, the scan-out line of a latch remains at logic 1 unless the latch
is selected by the X-Y signals.
A different type of addressable latch—the set/reset type—is shown in Fig. 5.28. the “clear”
signal clears the latch during its negative transition. Prior to scan-in operation, all latches are
cleared. Then, a latch is addressed by the X-Y lines and the preset signal is applied to set the
latch state.

The basic model of a sequential circuit with random access scan-in/scan-out network is shown
in Fig. 5.29. The X- and Y-address decoders are used to access an addressable latch—like a
cell in random access memory. A tree of AND gates is used to combine all scan-out signals.
Clear input of all latches are tied together to form a master reset signal. Preset inputs of all
latches receive the same scan- in signal gated by the scan clock; however, only the latch
accessed by the X-Y addresses is affected
.

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The test procedure of a network with random access scan-in/scan-out network is us follows:

1. Set test input to all test points.

2. Apply the master reset signal to initialize all memory elements.
3. Set scan-in address and data, and then apply the scan clock.
4. Repeat step 3 until all internal test inputs are scanned in.
5. Clock once for normal operation.
6. Check states of the output points.
7. Read the scan-out states of all memory elements by applying appropriate X—Y signals.

The random access scan-in/scan-out technique has several advantages:

1. The observability and controllability of all system latches are allowed.

2. Any point in a combinational network can be observed with one additional gate and
one address per observation point.
3. A memory array in a logic network can be tested through a scan-in/scan- out network.
The scan address inputs are applied directly to the memory array. The data input and the write-
enable input of the array receive the scan data and the scan clock, respectively. The output of
the memory array is ANDed into the scan-out tree to be observed.

The technique has also a few disadvantages:

1. Extra logic in the form of two address gates for each memory element, plus the address
decoders and output AND trees, result in 3—4 gates overhead per memory element.
2. Scan control, data, and address pins add up to 10-20 extra pins. By using a serially loadable
address counter, the number of pins can be reduced to around 6.
3. Some constraints are imposed on the logic design, such as the exclusion of asynchronous
latch operation.

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5.7 Partial Scan

In full scan, all flip-flops in a circuit are connected into one or more shift registers: thus, the
states of a circuit can be controlled and observed via the primary inputs and outputs,
respectively. In partial scan, only a subset of the circuit flip-flops are included in the scan chain
in order to reduce the overhead associated with full scan design [5.12]. Figure 5.30 shows a
structure of partial scan design. This structure has two separate clocks: a system clock and a
scan clock. The scan clock controls only the scan flip-flops. Note that the scan clock is derived
by gating the system clock with the scan-enable signal; no external clock is necessary. During
the normal mode of operation, namely, scan-enable signal at logic 0, both scan and non-scan
flip-flops update their states when the system clock is applied. In the scan mode operation, only
the state of the shift register (constructed from the scan flip-flops) is shifted one bit with the
application of the scan Nip-flop; the non-scan flip-flops do not change their states.

The disadvantage of two-clock partial scan is that the routing of two separate clocks
with small skews is very difficult to achieve. Also, the use of a separate scan clock docs not
allow the testing of the circuit at its normal Operating speed. Cheng [5.13] proposed a partial
scan scheme, shown in Fig. 5.31, in which the system clock is also used as the scan clock. Both
scan and non-scan flip-flops move to their next states when the system clock is applied.

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A test sequence is derived by shifting data into the scan flip-flops. This data together with
the contents of non-scan flip-flops constitute the Starting state of the test sequence, The other
patterns in the sequence are obtained by single-bit shifting of the contents of scan flip-flops,
which form part of the required circuit states. The remaining bits of the states, that is, the
contents of non-scan flip-flops, are determined by the functional logic. Note that this form of
partial scan scheme allows only a limited methods. Trischler [5.14] has used testability analysis
to show that the fault coverage in a circuit can be significantly increased by including 15-25%
of the flip flops in the partial scan. Agrawal et al. [5.15] have shown that the fault coverage
can be increased to as high as 95% by including less than 65% of the flip-flops in the partial
scan.

5.8 Testable Sequential Circuit Design Using Non-scan Techniques

Full and partial scan techniques improve the controllability and observability of flip-flops in
sequential circuit, and therefore the test generation for such circuits is considerably simplified.
However, a scan-based circuit cannot be tested at its

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IMPORTANT QUESTIONS:

1) Define the terms controllability and observability with an example.

2) With a neat logic diagram, explain clocked hazard free latches used in
LSSD Technique.

3) Explain any two Adhoc design rules for improving testability.

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normal speed, because test data have to be shifted in and out via the scan path.

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