ISSN: 2096-3246

Volume 55, Issue 02, September, 2023

DLAU: A SCALABLE DEEP LEARNING ACCELERATOR UNIT ON FPGA

1N.Vimala, 2B.Alekya Himabindu, 3Y.Mallikarjuna Rao, 4G.Sowmya, 5S.Girish Babu,

6M.Mahesh Kumar
1
M.Tech Student, Santhiram Engineering College,Nandyal
2,5,6
Assistant Professor, Santhiram Engineering College,Nandyal
3,4
Associate Professor, Santhiram Engineering College,Nandyal
ABSTRACT
As a new subfield of neural networks, deep learning has proven to be highly effective at tackling
difficult learning challenges. It is becoming increasingly difficult to build high-performance
solutions of neural networks with deep learning as the dimension of the nodes grows in response to
the needs of actual applications. In this study, we propose a deep neural accelerator unit (DLAU), a
scalable accelerating architecture for large-scale neural networks using deep learning that uses field-
programmable gate matrix (FPGA) as the computer chip prototype, to achieve both performance
gains and reduced power consumption. The DLAU accelerator uses tiling approaches to investigate
locality in deep learning applications and makes use of three pipelined computing units to increase
throughput. The DLAU accelerated is capable of speeds comparable to those of Intel Core2 CPUs,
as shown by experiments conducted on a cutting-edge Xilinx FPGA board.
Index Terms-Deep learning, field-programmable gate array (FPGA), hardware accelerator, neural
network.

INTRODUCTION
In recent years, machine learning has seen widespread implementation in several software and cloud
services. It has been known since 2006 that a certain class of neural networks made up of algorithms
outperforms previous state-of-the-art techniques in a variety of machine learning tasks. The artificial
neural networks known as CNNs, or Convolutional Ne have been shown to be highly effective in
addressing difficult machine learning problems like image and audio recognition. The acronym DL
describes the computing algorithm used. Deep Learning, or multilayer neural networks, are
notoriously resource-hungry due to their many hidden layers. Google's cat-recognition system (1 a
billion dollars neuronal connections) and Baidu's Brain system (100 billion dollars neuronal
connections) are just two examples of how the size of Deep Learning wireless networks is growing
in tandem with the accuracy requirements and intricate nature of practical applications. As a result,
optimizing the performance of large-scale neural networks trained using deep learning has emerged
as a central area of study.
FPGA (Field-Programmable Logic Array) is a key way to speed up deep learning algorithms because
of its high performance along with low power consumption. Due to the exponential growth of data,
data centers consume a lot of energy. In example, it is expected that by 2020 [4] the United States'
data centers' yearly power usage would have increased to almost 140 billion kilowatt-hours.
Therefore, particularly for large-scale deep learned neural network models, it presents major
problems when creating high-performance deep learning systems with minimal electrical
consumption. Field programmable gate arrays, application specialized integrated circuits, and

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graphics processing units are now state-of-the-art methods for speeding up deep learning procedures.
Hardware accelerators, including FPGAs and ASICs, can deliver at least reasonable performance
with reduced power consumption compared to GPU acceleration. Building large and complicated
DNNs on hardware accelerators is difficult because of the hardware's restricted processing power,
memory, and input/output (I/O) bandwidths. The ASIC design process is more time-consuming, and
the resulting lack of adaptability leaves designers wanting. DianNao, introduced by Chen et al. [6]
as a ubiquitous algorithmic learning silicon accelerator, is widely credited with launching the deep
learning processor industry. This shifts the paradigm for neural network-focused hardware
accelerators for machine learning. However, DianNao cannot adjust to the needs of various
applications since it is not built on programmable hardware like FPGA. Current work on FPGA
acceleration includes a technique to speed up the Boltzmann machine with limited capabilities
(RBM) that was built by Ly and Chow [5]. The RBM method was optimized by designing special
hardware processing cores. The RBM was also the subject of an FPGA-based accelerator built by
Kim et al. [7]. Each RBM processing module handles a tiny subset of the network's nodes, allowing
for parallel processing. Similar FPGA-based artificial intelligence acceleration are shown in other
research [9]. The FPGA-based accelerator reported by Yu et al. [8] is limited in its ability to adapt to
dynamic changes in network size and topology. In conclusion, these research efforts center on
effectively executing a single deep learning algorithm, but the question of how to scale up the size
of neural networks while maintaining their adaptability remains unanswered.
To address these issues, we introduce a deep learning accelerate unit (DLAU) that can be scaled up
to accelerate the computationally intensive kernels of deep learned algorithms. To design large-scale
neural networks, we make use of tiling methods, FIFO buffers, and streams to reduce memory
transfer operations and maximize CPU utilisation. The following are some of the ways in which this
method differs from that of the aforementioned literatures.

1) We use tiling approaches to split the large-scale input data in order to investigate the localization
of the learning application. To optimize for performance against cost, the DLAU framework may be
set up to run on a variety of tile sizes. As a result, the FPGA-based accelerator may be easily adjusted
to work with a wide variety of machine learning programs.
Activation function accelerate unit (AFAU), part sum collection unit (PSAU), and tiled matrices
multiplication unit (TMMU) are the three completely pipelined processing units that make up the
DLAU accelerator. These building blocks may be used to construct a wide variety of more complex
networks, including conventional and deep neural networks. Because of this, FPGA-based
accelerators are more scalable than ASIC-based ones.

Motivation for FPGA implementation.

There have been several attempts to improve the speed of neural networks by implementing them in
hardware. From analog computers to very large scale integration (VLSI) systems, many have tried
and failed to create widely used hardware. Common issues with such systems include low resolution,
small networks, and a cumbersome or nonexistent user interface.
The Basics of Neural Networks

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Layering is a common method for structuring neural networks. 'Nodes' are the building blocks of a
layer; each one contains a 'activation function' and is connected to others via "links." The 'input layer'
receives patterns from the user and relays them to the 'hidden layers' via a set of weighted
'connections,' where the real processing occurs. In the diagram below, the inferred solution is
produced from the 'output layer' to which the hidden layers join.

Fig.1 Neural Network.

Applications of neural networks.

To get the most out of a neural network, the algorithm you are trying to simulate should have a high
tolerance for error, as neural systems are general approximators. Hence, artificial neural networks
shouldn't be used to keep financial records straight. In cases when the data volume, number of
variables, or variety are exceptionally high, however, these methods excel at: capturing correlations,
or detecting regularities within a group of patterns.
the connections between the variables are not clearly understood, or cannot be fully described using
traditional methods.

LITERATURE SURVEY
DjiNN and Tonic: Distributed Neural Networks as a Service and Its Effect on Future Large-
Scale Computers in Warehouses.
Abstract: As voice-activated assistants like Apple's Siri, Google Now, Microsoft's Cortana, and
Amazon's Echo gain popularity, online service providers are turning to massive neural networks, or
deep neural networks (DNN) to tackle difficult machine learning tasks like image processing,
detection of speech, and NLP. There are many unanswered problems regarding the optimal
configuration of today's warehouse-scale computers (WSCs) and the construction of a server
architecture tailored specifically for DNN applications. Tonic Suite is a set of seven end-to-end apps
for processing images, voice, and language, and DjiNN is an open architecture for DNN as a service
in WSCs that we introduce in this work. We utilize DjiNN to plan a high-throughput DNN solution
based on huge GPU server architectures, and we shed light on the wide range of application-specific
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features. We examine numerous design issues for future WSC designs after analyzing the
performance, bandwidth, and power features of DjiNN / Tonic Suite. We compare a WSC with an
aggregated GPU pool to one made up of homogenous integrated GPU servers, and we calculate the
resulting difference in total cost of ownership. We increase DNN speed by over 120x on a Gtx K40
GPU for all but a single app (Facial Recognition, by 40x). For three of the seven applications, we
see near-linear scalability on a GPU server built from eight NVIDIA K40s (an gain of roughly a
thousand times in throughput). We also discover that, depending on the workload's makeup, the total
cost of acquisition for GPU-enabled WSCs is 4-20 lower than for CPU-only implementations.
Johann Hauswald penned the work. Cang Yiping Laurenzano, Michael A. Trevor Mudge Quan
Cheng Li Dreslinski, Ronald G. University of Michigan, Ann Arbor, MI, USA Brian Mars Lingjia
Tan Clarity Lab
Deep convolutional neural network acceleration by field-programmable gate array
optimization.

abstract: Since convolutional neural networks (CNNs) may achieve great accuracy by modeling the
actions of biological optic neurons, they have found widespread usage in the field of image
recognition. Rapid development of new applications based on artificial intelligence algorithms has
helped advance both theory and practice in this area. With its excellent performance, ease of
reconfigurability, and rapid creation round, etc., the FPGA technology has inspired a number of
suggested accelerators for deep CNN. The accelerator design area has not been fully utilized, despite
the fact that existing FPGA accelerators have proven to offer superior performance than generic
processors. The memory bandwidth offered by an FPGA platform may not be adequate for the
calculation throughput, which is a major issue. Therefore, current methods are not optimal due to
inefficient use of logic resources and memory bandwidth. Meanwhile, this issue is made worse by
the growing complexity the scalability of systems that employ deep learning. To address this issue,
we provide a method of analytical design based on the roofline model. We use several optimization
strategies, such as loop tiles and transformation, to do a quantitative analysis of the compute
throughput and needed memory bandwidth of each variation of a CNN architecture. The rooine
model may then be used to determine which option achieves the desired results while using the fewest
available FPGA resources. We use the creation of a CNN accelerator on a VC707 FPGA board as a
case study, contrasting our method with others. Our solution is substantially more efficient than prior
methods, with a peak performance of 61.62 GFLOPS at a working frequency of 100MHz.
Jason Cong, Peng Li, and Chen Zhang wrote the paper.

A high-performance FPGA architecture for restricted Boltzmann machines.

Abstract: Although neural networks have been widely used and have shown impressive
results in academic settings, they have seen very few commercial or industrial applications. The fact
the neural systems are frequently implemented as program running on processors that are general-
purpose is a major factor in their slow rate of adoption. Due to the fact that most software algorithms
for implementing a neural network are O(n2) issues, neural networks fall short in terms of the
scalability and efficiency needed in real-world applications. In this research, we look at how FPGAs

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may be utilized to improve the scalability and performance of neural network implementations by
using the networks' intrinsic parallelism. One common neural network architecture that lends itself
well to hardware implementations is the Restricted Danube machine, which we shall explore in
detail. With the suggested general-purpose hardware architecture, the O(n22) issue can be solved
with just O(n) resources, making it feasible to implement. A 100MHz Xilinx Virtex II-Pro XC2VP70
FPGA is used to test the framework. With these means, a Restricted Boltzmann machine with 128
by 128 nodes may operate at a pace of 1.02 billion connection-updates per second, which is a 35-
fold increase in speed over an optimized C code running on a 2.8 GHz Intel CPU.
Authors: D. L. Ly and P. Chow.

DEEP NERUAL NETWORKS

"Stacked neural networks," or multi-layered networks, are what we mean when we talk about "deep
learning." Nodes are what make up the layers. A node is only a location for computing, and it is
based on the analogy of a neurons in the mind of a person, which "fires" when it receives enough
stimulation. For the purpose of learning a task, a node combines data input wit a set of coefficients,
and or weights, that either boost or reduce the relevance of that input. (Which input is best for error-
free data classification, for instance?) The activation function of a node decides whether or not the
signal from its input-weight product should be passed on to subsequent layers of the network to
influence the final outcome, such as a classification.

The number of node layers through which input flows in a multistep process of pattern recognition
is what sets deep-learning networks apart from the more conventional single-hidden-layer neural
networks.

Figure 2. The schematic diagram of DNNs for Mnist

Fig.2 illustrates a deep neural network for handwritten digits recognition which composed of Mnist
is an array of handwritten digits, and its structure is as follows: one input layer, numerous hidden
layers, and one output layer. In this study, DNNs serve as an illustration. Both the prediction process
and the training process are computational modes in DNNs. The weight coefficients obtained during
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the training phase are used to calculate the output for each input during the prediction step, which is
a feed forward calculation. There are two phases to the training process: pre-training, in which the
connection weights connecting the units in neighboring layers are tuned locally using the training
datasets [4]; and global training, in which the connection weights are tuned worldwide using the
Back Spreading algorithm (BP algorithm). We use the prediction method instead of the training
procedure due to technological and commercial constraints.

3.2 RESTRICTED BOLTZMANN MACHINE THEORY.

This section provides a high-level overview of RBM mechanics, including some of the basic
vocabulary, mathematical foundation, and technique involved. A RBM is a type of stochastic,
generative neural network. Given a set of patterns, a neural network is going to able to construct an
internal model that can recognize fresh data in the same distribution, making it useful for modeling
the statistical habits of a given collection of data.

Figure 3: A schematic diagram of a Restricted Boltzmann machine with labelled components.

Additionally, the network may produce data from that distribution thanks to the underlying model's
generative characteristic. Because it employs a probabilistic strategy, the RBM may be thought of as
stochastic. The RBM uses statistical procedures to ascertain the probability distribution of statistical
attributes of a dataset. RBMs are distinct from conventional neural networks in both their design and
their applications due to their generative and stochastic qualities.
The RBM may be trained like any other neural network. The settings can be adjusted repeatedly in
accordance with a particular data set using the learning rules rather than being set manually. As a
result, the RBM is applied to a collection of data vectors that serve as the training set. The RBM uses
iterative processing of the training data to get the desired result. The RBM has reached an adequate
level of training at this point. The test data is a fresh collection of data vectors that haven't been used
in training yet, and they're used to check the model's behavior.
The RBM is a synthesis of neural network theory and statistical mechanics, therefore its language
reflects the origins of these two disciplines. Nodes are commonly used to describe processing
components in neural networks. The nodes can be in one of two possible states—on or off. There are
two sets of nodes in an RBM—the external layer and the internal layer. The data in the network's
hidden layer is represented internally, while the data in the visible layer is used for input/output.
Nodes on the same layer are not connected to one another, but all other nodes are. The weights
assigned to these associations are what the RBM uses to train itself.

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The ith and jth nodes' binary states in the visible and hidden layers, respectively, are denoted by vi
and hj, whereas wi,j represents the connection weight between the ith and jth nodes. In Fig. 3 we
have a simplified diagram that encapsulates all of the relevant vocabulary and nomenclature.

PROPOSED SYSTEM
To address these issues, we introduce DLAU, a scalable deep learning accelerator unit designed to
expedite the algorithm's kernel computations. In particular, we design large-scale neural networks
by making use of tiling methods, FIFO buffers, and pipelines to reduce the number of memory
transfer operations and maximize the reusability of the computational nodes. The following
contributions set this method apart from its predecessors.
First, we use tiling methods to divide up the massive input data so that we may investigate the
application's locality using deep learning. To take advantage of the tradeoffs between speedup and
hardware costs, the DLAU architecture may be set up to handle multiple amounts of tile data.
Therefore, the accelerator based on FPGAs is more flexible in its ability to adapt to various machine
learning tasks.
2) The DLAU accelerator has a tiling matrix multiplication unit (TMMU), a part sum accumulation
unit (PSAU), and an activation function acceleration unit (AFAU), all of which work in parallel.
Various System

Fig. 6. DLAU accelerator architecture. topologies

such as CNN, DNN, or even emerging neural networks can be composed from these basic modules.
Consequently, the scalability of FPGA-based accelerator is higher than ASIC-based accelerator.

TILE TECHNIQUES AND HOT SPOT PROFILING.

In order to train each layer of a deep network quickly and effectively, RBMs have become
popular. There is often just one input layer, numerous hidden layers, and then a single classifier layer
in a DNN. There is a weighted connection between all the nodes in neighbouring layers. With the
existing network configurations, prediction involves feedforward computation from input neurons to
output neurons. In the training process, the connection weights between units in neighboring layers
are tuned locally during pretraining, and then globally during global training via the back propagation
(BP) technique.

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Iterative calculations with minimal conditional branch operations are common in large-scale
DNNs, making them a good candidate for hardware parallelization. In this study, we begin by
utilizing the profiler to investigate the hotspot. Matrix multiplication (MM), activation, and vector
operations account for a large fraction of the total execution time, as seen in Fig. 1. MM are crucial
to the success of the three most emblematic activities, which are feed forward, RBM, and BP. In
particular, it necessitates 99.1% of all BP activities, 100% of RBM operations, and 98.6% of all feed
forward operations. Only 1.40 percent, 1.48 percent, and 0.42 percent of the three operations are used
by the activation function. Profiling experiments show that MM accelerators may greatly boost
system speedup when properly designed and implemented.
However, in comparison to GPU and CPU optimization approaches, FPGA implementations
face a substantial difficulty due to the large memory bandwidth and compute resources required to
enable the parallel processing. In this study, we apply tile algorithms to split the enormous input data
set into tiled subsets and thereby attack the problem. Each custom hardware accelerator can store the
tiled portion of data in its own buffer before processing it. The accelerator design is utilized to support
the massive neural networks. Also, the hardware accelerators can be used in parallel with the data
access for each tiled subset.
In particular, the output neurons in one iteration become the input neurons in the following
iteration. At each iteration, the weights matrix is multiplied by each column of input neurons to
produce a new set of output neurons. Algorithm 1 shows how the input values are tiled and multiplied
by the matching

TABLE I PROFILING OF HOT SPOTS OF DNN

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weights. After each component's sum is determined, the total is tallied. We additionally tiled the
weight matrix to match to the neuron input/output sizes. This results in a huge reduction in hardware
requirements for the accelerator, as its price is now just proportional to the size of the tiles. The tiling
approach is effective because it permits the deployment of extensive networks while making use of
relatively few physical resources. FPGA technology has an additional benefit over GPU design
because of its pipelined hardware implementation, which utilizes huge parallel SIMD architectures
to boost overall speed and throughput. In this paper, we implement the specialized accelerator to
speed up the MM and activation functions, which, as shown in Table I of the profiling results, are
common but important computational parts during the prediction process and the training process in
deep learning algorithms.
DUAL ARCHITECTURE AND EXECUTION MODELL.
The DLAU accelerator, DDR3 memory controller, direct memory access module, and
integrated processor are all shown in Fig. 6. The embedded processor talks to DLAU through JTAG-
UART and provides a programming interface for the users. The DLAU accelerator is activated, input
data and weight matrix are stored in internal BRAM blocks, and the results are delivered to the user
after execution. The DLAU is designed as a modular component that may be configured for a wide
variety of uses. The DLAU is made up of three processing units set up in a sequential fashion:
1) TMMU;
2) PSAU; and
3) AFAU.

When executed, DLAU retrieves tiled data from memory through DMA, processes it using
each of the three processors in turn, and then stores the processed data back in memory. The
following are distinguishing characteristics of the DLAU accelerator design.

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Fig. 7. TMMU schematic.

To receive or transmit data in FIFO order, each processing unit in DLAU is equipped with
an input buffer and an output buffer. These buffers are used to avoid information loss due to varying
throughput between CPUs.
Different machine learning tasks may call for different-sized neural networks, which may be
accommodated via tiling techniques. To make the accelerator suitable for networks of varying sizes,
we tile the data into manageable chunks that can be cached in-chip. Therefore, the accelerator based
on FPGAs is more flexible in its ability to adapt to various machine learning tasks.
As a result of our pipeline accelerator, the TMMU, PSAU, and AFAU are able to perform
computations in a streaming-like manner by exchanging data with one another via a stream-like data
passing mechanism (for example, AXI-Stream for demonstration). The Total Weights and Tiled
Nodes Data is read by the TMMU, which is the primary computing unit, and the calculations are
performed. The intermediate part sum results are then sent to the PSAU. PSAU compiles and totals
up the sums of the individual parts. Once the data has been accumulated, it will be sent to AFAU.
Piecewise linear interpolation techniques are used by AFAU to carry out the activation function. The
remaining text of this article will focus on the third, second, and first CPUs and how they were each
implemented.

TMMU Architecture
Multiplication and adding up are TMMU's responsibilities. Part sums are calculated using
TMMU, which is tailored to take use of the weights' data localisation. The component sums are sent
to PSAU through an output FIFO buffer, while the input FIFO buffer gets data via DMA. In Fig.7,
we show the TMMU diagram in more detail by specifying a tile size of 32. The weight matrix is read
by TMMU from the input buffer and then distributed across the BRAMs in a 32 by i fashion, where
n is the total number of BRAMs and i is the row number of the weight matrix. Then, TMMU will
start storing the tiled node data in a buffer. When TMMU initially begins execution, it loads the tiled
32 values into register Reg_a. Every cycle, TMMU receives the next node from the input buffer and
writes it to the registers named Reg_b in parallel with the calculation. As a result, Reg_a and Reg_b
are interchangeable registers.
We employ a pipelined binary adder tree structure to execute the computation quickly and
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efficiently. Figure 7 shows that BRAMs and registers are used to store information about nodes and
their associated weights. Coarse-grained accelerators are used in a time-sharing pipeline. As a result,
the TMMU unit is able to generate a part sum result at the end of each clock cycle using this approach.

Fig. 8. PSAU schematic.

PSAU Architecture
The task of accumulation falls on PSAU's shoulders. The PSAU shown in Fig. 8 is the hardware used
to store the total of the TMMU's output parts. If the total of the parts is the final value, PSAU will
store it in the output buffer before sending the pipelined results to AFAU. The throughput of PSAU
accumulation is equivalent to the rate at which the part sum is generated in TMMU, as PSAU may
accumulate one part sum each clock cycle.
AFAU Architecture
At last, AFAU uses piecewise linear interpolation to realize the activation function (y = ai x
+ bi, x [x1, xi+1]). When the difference between xi and xi+1 doesn't matter much, this approach has
been used extensively to design activation functions. As an example of a sigmoid function equation,
consider (1). When x is more than 8 and less than -8, the answers are sufficiently close to the limits
of 1 and 0, respectively. Different functions are set up for the ranges 8 x 0 and 0 x 8. In total, we cut
the sigmoid into four distinct chunks.

To keep the throughput with other processing units constant, AFAU, like PSAU, employs input and
output buffers. To be more specific, we keep a and b's values in two different BRAMs. Every time
the clock ticks over, the sigmoid function used in the AFAU calculation gets put through its paces.
Therefore, the DLAU accelerator architecture's maximum throughput is guaranteed by completely
pipelined operation across all three processing units.

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RESULTS

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CONCLUSION

In this study, we introduce DLAU, an FPGA-based deep learning accelerator designed for scalability
and adaptability. For large-scale neural networks, the DLAU's three pipelined processing units come
in handy. In order to compute frequently by time-sharing the arithmetic logic, DLAU utilizes tile
methods to split the input node data into smaller groupings. In experiments conducted on a prototype
Xilinx FPGA, it was shown that DLAU could yield a speedup of 36.1% with a little increase in
hardware cost and minimal increase in power consumption.
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