AN INDUSTRIAL INTERNSHIP REPORT ON

VLSI- DESIGN FOR TESTABILITY

Submitted in partial fulfilment of the requirements for the award of
the degree of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by
BURLU MOUNIKA(21U91A0414)
Under the esteemed guidance of
Mr. B. HANISH CHAITANYA, M. Tech, (Ph. D)
Assoc. Prof. of the ECE Department

Department of ELECTRONICS & COMMUNICATION

ENGINNERING
SRI MITTAPALLI COLLEGE OF ENGINEERING
Affiliated to Jawaharlal Nehru Technological University, Kakinada
(Accredited by NBA and NAAC A+)
THUMMALAPALEM, NH-16, GUNTUR-522233,
A.P.
Academic Year: 2023-24
i
 SRI MITTAPALLI COLLEGE OF ENGINEERING
Affiliated to Jawaharlal Nehru Technological University, Kakinada
(Accredited by NBA and NAAC A+)
THUMMALAPALEM, NH-16, GUNTUR-522233, A.P. 2023-2024.

CERTIFICATE
This is to certify that semester industrial internship report entitled “VLSI-
DESIGN FOR TESTABILITY” is being submitted by BURLU
MOUNIKA(21U91A0414) in the partial fulfilment of the requirement for the
degree Bachelor of Technology in Electronics and Communication
Engineering of Jawaharlal Nehru Technological University, Kakinada during
the academic year 2023-2024. This work is done under my supervision and
guidance.

Signature of the guide: Signature of the Head of Department:

Mr. B. HANISH CHAITANYA, M. Tech, (Ph. D) Mr.P.MAHABUB SUBHANI, M. Tech., (Ph.D)

Date:
Place:
Certified that the candidate was examined by us in the viva voice examination held at SRI

MITTAPALLI COLLEGE OF ENGINEERING, Guntur on ………………....................

INTERNAL EXAMINER EXTERNAL EXAMINER

ii
 AN INTERNSHIP REPORT ON

VLSI- DESIGN FOR TESTABILITY

Submitted in accordance with the requirement for the degree of B. TECH

Name of the College : SRI MITTAPALLI COLLEGE OF ENGINEERING

Department : ECE

Name of the Faculty Guide : Mr. B. HANISH CHAITANYA, M. Tech, (Ph. D )

Duration of the Internship : 08 weeks from: 03-06-2024 To: 27-07-2024

Name of student : BURLU MOUNIKA

Program of study : B.TECH

Year of Study : 3rd YEAR

Register Number : 21U91A0414

Date of submission :

iii
 STUDENT DECLARATION

I am BURLU MOUNIKA a student of B.TECH Program,Roll.No:21U91A0414

Of the Department of ECE. I hereby declare that I have completed the mandatory industrial

internship from 03-06-2024 To 27-07-2024 in BIST TECHNOLOGIES in accordance with

APSCHE (Andhra Pradesh State Council of Higher Education) under the Faculty Guideship Mr.

B. HANISH CHAITANYA, M. Tech, (Ph. D )

of Department of ECE in SRI MITTAPALLI COLLEGE OF ENGINEERING.

(Signature and Date)

iv
 OFFICIAL CERTIFICATION

This is to certify that BURLU MOUNIKA Reg. No: 21U91A0414 has completed her
internship in accordance with APSCHE on BIST TECHNOLOGIES under my supervision as
a part of partial fulfillment of the requirement for the Degree of B. TECH in the Department of
ELECTRONICS AND COMMUNICATION ENGINEERING in SRI MITTAPALLI
COLLEGE OF ENGINEERING. This is accepted for evaluation.

(Signature with date)

Endorsements

FACULTY GUIDE: Mr. B. HANISH CHAITANYA, M. Tech, (Ph. D )

HEAD OF THE DEPARTMENT: Mr.P.MAHABUB SUBHANI M.Tech.,(Ph.D.)

PRINCIPAL: Dr. S. GOPI KRISHNA, M.Tech, Ph.D.

v
CERTIFICATE FROM INTERN ORGANIZATION

Fig: Internship Certificate

vi
 ACKNOWLEDGMENT

First and foremost, I sincerely salute to my esteemed institution “SRI MITTAPALLI

COLLEGE OF ENGINEERING” for giving this golden opportunity to fulfilling my dreams of
becoming an Engineer.

I express my gratitude towards our secretary Sri.M.B.V.Satyanarayana, Sri Mittapalli College

of Engineering, for providing necessary facilities for the dissertation work by being behind the
screen.

It is a great privilege for me to convey my sincere gratitude to Prof Dr.S. Gopi krishna,.M.Tech
Ph.D. principal of my college for his encouragement and for providing excellent lab facilities.

I would like to gratefully acknowledge my Head of the Department of Electronics and

Communication Engineering Mr.MAHABUB SUBHANI ,M.Tech.,(Ph.D.) has been abundantly
helpful and has assisted me in numerous ways.

I would like to express my sincere thanks to my entire Industrial Internship guide Mr. B. HANISH

CHAITANYA, M. Tech, (Ph. D ) for his valuable guidance, best suggestions and constant encouragement right to
inception to the end of this report which is also enabled to complete the semester internship successfully in time.

I wish to thank all the Staff Members in the department for their kind cooperation and my parents
for giving support throughout the industrial internship.

Finally, I acknowledge sincerely the effective services rendered by one and all involved directly
and indirectly in the entire industrial internship.

By
BURLU MOUNIKA
21U91A0414

vii
 INDEX

CONTENTS: Pg. No

CHAPTER-1: EXECUTIVE SUMMARY

1.1: INTRODUCTION 1
1.2: LEARNING OBJECTIVES 2
CHAPTER-2: OVERVIEW OF THE ORGANIZATION
2.1: ABOUT ORGANIZATION 3
2.2: VISION OF ORGANIZATION 4
2.3: MISSION OF ORGANIZATION 4
CHAPTER-3: INTERNSHIP PART
3.1: ABOUT INTERNSHIP 5
3.2: SUMMARY OF ACTIVITIES 6
CHAPTER-4: WEEKLY ACTIVITIES
4.1 WEEK-1: INTRODUCTION TO ASIC & DFT 8
4.2 WEEK-2: BASICS IN RTL & CODE CONVERSIONS 10
4.3 WEEK-3: ENCODERS, DECODERS & PROCESSES STATEMENTS 12
4.4 WEEK-4: OPERATION MODES & DFT DESIGN FLOW 14
4.5 WEEK-5: GOALS & LIBRARIES IN DFT 16
4.6 WEEK-6: IC DESIGN FLOW & QUALITY TEST PATTERNS 18
4.7 WEEK-7: BIST & JTAG TECHNIQUES 20
4.8 WEEK-8: REPORT SUBMISSION AND PRESENTATION 22

viii
CHAPTER-5: OUTCOMES DESCRIPTION
5.1: WORK ENVIRONMENT 24
5.2: TECHNICAL SKILLS 25
5.3: MANAGERIAL SKILLS 26
5.4: IMPROVEMENT ON COMMUNICATION SKILLS 27
5.5: TECHNOLOGICAL DEVELPMENTS 29

INTERNAL ASSESMENT STATEMENT 34

ix
 CHAPTER 1: EXECUTIVE SUMMARY
1.1 : INTRODUCTION: -
In its broadest definition, Design for Testability (DFT) is a process for designing
integrated circuits (ICs) that ensures efficient testing and identification of manufacturing
problems. DFT attempts to enhance product quality, lower production costs, and boost overall
yield by using specialized test circuitry and techniques such scan chains, built-in self-test
(BIST), and boundary scan (JTAG). Despite potential trade-offs in terms of area, power, and
complexity, DFT is crucial in modern integrated circuit design because it allows for complete
validation and testing processes.
As IC complexity increases, current DFT research and development focuses on
improving approaches to solve increasing issues and improve testability for future generations
of integrated circuits. The basic purpose of DFT is to ensure that manufactured integrated
circuits can be extensively and efficiently tested to detect any faults introduced during
fabrication. Early discovery of flaws improves product quality, lowers production costs, and
increases overall yield. One of the most often utilized DFT strategies is to incorporate scan
chains into the design.
These chains are made up of serially connected flip-flops, which allows for simple access to
internal circuit nodes during testing. BIST entails integrating test circuitry within the IC itself.
This enables self-testing of the device without the need for external test equipment, making it
especially beneficial for applications that require regular testing. Joint Test Action Group
(JTAG) is a standardized boundary scan approach for testing and programming integrated
circuits (ICs) after they have been connected onto a printed circuit board (PCB). This technique
is particularly useful for validating the interconnections of several ICs on a PCB.
Specifically designed for testing embedded memories within ICs, this technique
involves incorporating dedicated circuitry for testing memory blocks. While DFT techniques
improve testability, they may also introduce overhead in terms of area, power, and design
complexity. Therefore, designers must carefully balance these trade-offs to ensure that the
benefits of DFT outweigh its costs. DFT is integrated into the design process alongside other
design considerations such as power optimization, timing closure, and area minimization.
Designers use specialized tools and methodologies to incorporate DFT features
seamlessly into the overall chip design flow. Once DFT features are integrated into the design,
they undergo rigorous validation to ensure their effectiveness in detecting manufacturing
defects. This involves running extensive simulations and test patterns to verify the functionality
of the test circuitry under various conditions.

1
 With the rising complexity of current integrated circuits, DFT approaches are evolving
to handle new issues such as process fluctuations, aging effects, and heterogeneous component
integration. This field's research focuses on building more efficient and robust DFT solutions to
fulfil the needs of emerging technology.

1.2 : LEARNING OBJECTIVES: -

Learning Objectives for Design for Testability encompasses a range of topics aimed at
providing students or professionals with a comprehensive understanding of the principles,
techniques and applications of DFT in the design and testing of Integrated Circuits (ICs).
The main learning Objectives for DFT Engineer are:
➢ Recognize the challenges associated with testing modern integrated circuits, including
increasing complexity, shrinking geometries, and manufacturing variability.
➢ Understand the fundamental concepts of DFT, including scan chains, test access
mechanisms, test patterns, fault models, and fault simulation techniques.
➢ Gain familiarity with various DFT techniques such as scan design, boundary scan
(JTAG), built-in self-test (BIST), memory BIST, and at-speed testing.
➢ Learn how to apply DFT methods effectively during the design phase to enhance
testability without compromising other design objectives such as area, power, and
performance.
➢ Understand the architecture and implementation of DFT features within IC designs,
including how scan chains and other test structures are inserted and optimized.
➢ Learn techniques for generating efficient test patterns to achieve high fault coverage
while minimizing test time and test data volume, including test pattern compression
methods.
➢ Understand different fault models used in DFT, such as stuck-at faults, transition faults,
and delay faults, and learn how to simulate these faults to assess test coverage.
➢ Gain knowledge of validation and verification techniques for DFT features, including
simulation-based verification, formal verification, and hardware emulation.
➢ Learn how to integrate DFT seamlessly into the overall IC design flow, including design
synthesis, place-and-route, and timing closure processes.
➢ Understand different testing strategies such as structural testing, functional testing, and
in-system testing, and learn how to evaluate testability using metrics such as fault
coverage, test generation efficiency, and test time.
➢ Explore advanced topics in DFT, such as DFT for analog/mixed-signal circuits, DFT for
system-on-chip (SoC) designs, DFT for 3D integrated circuits, and emerging trends in
DFT research.

2
 CHAPTER 2: OVERVIEW OF THE ORGANIZATION
2.1 : ABOUT ORGANIZATION: -

BIST TECHNOLOGIES PVT LTD is a profitable organization that facilitates the

development of an Industry 4.0 ready digital workforce in India. Their platform vision is to
bridge the gap between academia and industry by providing access to world-class curriculum
for our respective faculties and students. They aim to completely transform the ICT-based
education system and teaching methodologies in India. They collaborate closely with all the key
players in the ecosystem, including students, faculties, education institutions, and Central or
State Governments, bringing them together through skilling interventions.
Their goal is to accurately identify students' skill gaps and map them with the newest
and most advanced technical skills. Their values are to connect industry-ready professionals,
researchers, and advanced important stakeholders in the ecosystem Students, Faculties,
Education Institutions and Central or State Governments by bringing them together through our
skilling interventions. Their mission is comprehensive identification of skills gaps in the
students and mapping them with latest and world’s best technical skills.
Their values are to connect industry-ready professionals, researchers, advanced learners,
educators and entrepreneurs who can take best care of stake holders. BIST TECHNOLOGIES is
a social enterprise which was founded and focuses on bridging the academia-industry divide,
enhancing student employability, promoting innovation and creating an entrepreneurial
ecosystem in India. Working primarily with emerging technologies, and striving to leverage
them to augment, upgrade the knowledge ecosystem and equip the beneficiaries to become
contributors themselves.
BIST TECHNOLOGIES is a very enthusiastic platform to use own ideas for innovation
and provides training by experts from the industry. It provides the students or professional a
very high application-oriented training which enables with 24/7 technical support in digital
format along with cent percent of placement support for students and professionals with short
term and long-term internship whether it is online or offline. BIST TECHNOLOGIES provides
a unique platform which is affordable and accessible.
Their purpose is to accurately detect students' ability gaps and align them with the most
recent and advanced technical skills. Their values are to bring together industry-ready experts,
researchers, and advanced critical stakeholders in the ecosystem, including students, faculties,
education institutions, and central or state governments, through our skilling initiatives. Their
objective is to comprehensively identify students' skill gaps and map them to the latest and best
technical capabilities in the globe.

3
2.2 : VISION OF ORGANIZATION: -
BIST TECHNOLOGIES having the appropriate and absolute vision on their
organization which empowers the students and professionals to dedicate their excellence,
integrity and social responsibility towards the society for positive change and creating lasting
impact and leaving a legacy of hope and possibility for generations to come across India.
At BIST TECHNOLOGIES, we envision a future where every individual has the
opportunity to thrive in a world of limitless possibilities and seen a society where equality,
justice and sustainability are not just aspirations but fundamental realities ingrained in every
aspect of life. Our vision is of a world where innovation and collaboration drive positive
change, where diverse voices are heard and respected, and where every person is empowered to
reach their full potential. We imagine communities that are vibrant, inclusive, and resilient,
where people come together to solve challenges and celebrate successes.
Through our dedication to excellence, integrity, and social responsibility, we aim to be a
catalyst for positive change, creating lasting impact and leaving a legacy of hope and possibility
for generations to come. Our vision is not just a dream; it's a shared commitment and a guiding
light that inspires everything we do. Together, we will make this vision a reality, building a
brighter, more sustainable future for all.
2.3 : MISSION OF ORGANIZATION: -
At BIST TECHNOLOGIES, our mission is to provide aspiring professionals with
transformative internship experiences that equip them with the skills, knowledge and networks
necessary to succeed in their chosen fields. By dedicating fostering personal and professional
growth by offering hands-on learning opportunities, mentorship from industry experts and
exposure to real-world challenges. Main goal is to empower like us interns to discover our
passions, develop our talents and skills and build the confidence needed to excel in today’s
dynamic job market.
Central to our mission is the belief in the power of diversity, equity, and inclusion. We
are committed to providing equal access to opportunities for all individuals, regardless of
background or circumstance, and to fostering a culture of belonging where every voice is heard
and valued. Driven by our core values of excellence, integrity, and innovation, we continuously
seek to improve and innovate our programs to better meet the evolving needs of our interns and
partners. We measure our success not only by the skills gained and connections made but also
by the lasting impact our interns have on their communities and the world. Ultimately, our
mission is to empower the next generation of leaders, change-makers, and lifelong learners,
creating a brighter future for individuals and societies worldwide.

4
 CHAPTER 3: INTERNSHIP PART
3.1 : ABOUT INTERNSHIP: -

In this internship training I had learnt many of the activities in the part of VLSI –
Design for Testability intern under BIST TECHNOLOGIES in accordance with the
APSCHE (Andhra Pradesh State Council of Higher Education), I have been actively
engaged in acquiring the skills necessary to excel in this role. I am having a solid
understanding of digital design concepts, including Boolean Algebra, logic gates, flip-
flops, sequential and combinational logic principles and synchronous design principles.

This foundational knowledge has given me a clear understanding of the platform's

structure. I've been utilizing Microwind and DSCH tools or platforms to enhance my
skills. I've been utilizing the several modules of content and along with the professional
skills and communication skills in this digital world to enhance my skills. During the
initial weeks of my internship, I received comprehensive training on the understanding
transistor-level circuit design, CMOS technology, layout design, and design hierarchy.

This included understanding the importance of Design for Testability domain in

VLSI. Later, started the basic understanding of semiconductor testing fundamentals, including
fault models, test coverage metrics, test patterns, and test equipment. This knowledge helps
interns grasp the importance of DFT in ensuring effective testing of integrated circuits.
Proficiency in programming languages commonly used in DFT automation and verification is
beneficial. This may include scripting languages such as Python, TCL (Tool Command
Language), or Perl, as well as familiarity with hardware description languages (HDLs) like
Verilog or VHDL.

I exposure to Electronic Design Automation (EDA) tools commonly used in DFT, such
as synthesis tools, simulation tools, and DFT tools like ATPG (Automatic Test Pattern
Generation) and scan insertion tools. Experience with tools such as Synopsys Design Compiler,
Cadence Encounter, or Mentor Graphics would be advantageous. Basic knowledge of DFT
techniques and methodologies is essential. This includes understanding concepts such as scan
chains, built-in self-test (BIST), boundary scan (JTAG), memory BIST, and other DFT
structures and algorithms used to enhance testability and fault coverage in integrated circuits.

I have a strong desire to learn and grow in the field of DFT. This includes being
proactive in seeking out opportunities for skill development, staying updated on industry trends
and advancements, and actively contributing to project teams and discussions. The critical
nature

5
od’s DFT in ensuring the quality and reliability of integrated circuits and ensured the DFT
features are implemented correctly and meet design requirements.

3.2 : SUMMARY OF ACTIVITIES: -

During my long-term semester internship in the VLSI - Design for Testability domain, I
mostly concentrated on scan chain construction, scan insertion approaches, and models.
Introduction to ASIC (Application Specific Integrated Circuit), Design under Test, Threshold
voltages, Manufacturing flaws, and Physical Design. By examining existing integrated circuit
designs to find testability enhancement opportunities. Reviewing design specifications,
schematics, and layouts to determine the feasibility of including DFT features.
Working on incorporating DFT characteristics into IC designs with industry-standard
tools and processes. This could include inserting scan chains, adding boundary scan cells,
integrating BIST controllers, and improving test access mechanisms. Creating and simulating
quality test patterns to validate the functionality and coverage of the DFT features that have
been introduced. This may involve using automated test pattern generation (ATPG)
technologies to build efficient test vectors for various failure models.
To make it easier to test internal nodes, all of the design's flip-flops should be connected
in a serial scan chain. Ensure that scan chain signals are properly connected and routed to
reduce test data volume while increasing test coverage. To avoid excessive test data amount and
save test application time, keep scan chain lengths moderate. The number of flip-flops in each
scan chain should be balanced to ensure uniform test coverage across the design. Handle clock
gating and reset signals effectively to guarantee that scan chains behave consistently in both test
and functional modes.
Avoid clock gating or reset settings, as these might create scan chain instability and
introduce testability difficulties. Implement a strong test access mechanism (TAM) to ensure
quick access to scan chains and other test structures. Ensure that TAM signals are appropriately
routed and synchronized to save test application time and eliminate test conflicts. Ensure that
boundary scan cells are properly connected to enable interconnect testing and PCB-level
diagnostics. Integrate built-in self-test (BIST) structures into the design to allow for on-chip
testing without the use of external test equipment. Create BIST controllers and test pattern
generators that handle several test modes and fault models with little overhead.
Configure embedded memories with built-in self-test (BIST) capabilities to allow for
more efficient memory array testing. Optimize memory BIST configurations to achieve a
balance between test coverage, test time, and area overhead. Define unambiguous and
consistent test mode control signals to ensure a smooth transition between functional and test
modes.
6
 Verifying adherence to design specifications and industry standards by conducting
design rule checks (DRC) in accordance with DFT principles. Resolve any DFT-related
infractions found during DRC audits in order to preserve testability and design integrity. To
produce thorough design documentation, record the DFT regulations and guidelines that were
adhered to during the design process. To assess how well DFT is being implemented, report
DFT-related metrics including test coverage, test data volume, and test application time.
In DFT, the most used kind of scan technique is serial scan chain, or shift register scan.
This technique enables the serial shifting of test patterns into and out of the design by
connecting the flip-flops inside the design in a chain. In test mode, the flip-flops are set up to
form a shift register by disconnecting their scan inputs from their regular inputs. Test patterns
are applied to the circuit by serially shifting them into the scan chain; the response is then
recorded by serially shifting the values out of the scan chain.
The process of parallel scanning entails splitting up the flip-flops in the design into
several scan chains that run concurrently. This method is utilized, especially in designs with a
lot of flip- flops, to shorten test application times and increase test efficiency. In test mode,
multiple scan chains run concurrently, allowing test patterns to be loaded and responses to be
recorded in parallel. It is possible for each scan chain to cover a distinct section of the design,
enabling effective testing of several locations.
Combinational scan, sometimes referred to as structural test, is a scan method for testing
the design's combinational logic circuits. This approach takes intermediate values straight from
combinational logic routes, without the need to capture state information from flip-flops. Test
patterns can be applied because, in test mode, the scan inputs govern the inputs to the
combinational logic circuits. Dedicated scan flip-flops are used to collect the outputs of the
combinational logic routes so that they can be compared to the predicted values.
Applying scan structures only to some areas of the design as opposed to the complete
circuit is known as partial scan. This method is employed in designs with intricate hierarchical
structures to strike a compromise between test overhead and coverage. Scan chains are only
present in specific parts of the design, usually aimed at memory elements, critical routes, or
other high-risk places. Other test approaches, including functional testing, are used to test the
remaining components of the design.

7
 CHAPTER 4: WEEKLY ACTIVITIES
4.1 : ACTIVITY LOG FOR THE FIRST WEEK

DAY& Brief description of the Person

DATE dailyactivity Learning Outcome In-
Charge
Signature
I had learnt the Introduction to
Day – 1
Application Specific Integrated Introduction to ASIC
(03-06-2024)
Circuit in VLSI Domain

I had learnt about the Designs or

Day – 2
Circuits which are under going to Test About Design Under Test
(04-06-2024)

I had learnt about the Lower, Medium

Day – 3
and Higher Threshold Voltages Threshold Voltages
(05-06-2024)

I had learnt about the Introduction to

Day – 4
Design for Testability Introduction to DFT
(06-06-2024)

I had learnt about the Defects in

Day – 5
design while Manufacturing Manufacturing Defects
(07-06-2024)

I had learnt about the Physical

Day –6
Design Engineer role and about About Physical Design
(08-06-2024)
Layouts creation

8
 WEEKLY REPORT
WEEK – 1 (From 03-06-2024 to 08-06-2024)

Objective of the Activity Done: Introduction to ASIC & DFT

Detailed Report:
In this detailed report for this week, I have gained the knowledge on familiarizing
myself with Application-Specific Integrated Circuits (ASICs). ASICs are custom-designed
integrated circuits tailored to perform specific functions. I delved into understanding the
fundamentals of ASIC design, including its advantages over general-purpose integrated circuits
and its various applications in different industries such as automotive, telecommunications, and
consumer electronics.

I dedicated my time to grasping the concept of Design Under Test (DUT). The DUT
refers to the specific component or module within an integrated circuit that is undergoing
testing. I learned about the importance of designing robust test benches and methodologies to
effectively verify and validate the functionality of the DUT. Understanding DUT is crucial for
ensuring the reliability and quality of ASICs. I focused on exploring threshold voltages in
semiconductor devices, particularly in the context of ASIC design.

Threshold voltage is a critical parameter that determines the operation of transistors in

an integrated circuit. I learned about the significance of threshold voltage in achieving desired
performance characteristics such as speed, power consumption, and noise margin.
Understanding and optimizing threshold voltages are essential for achieving high-performance
ASIC designs. I delved into the concept of Design for Testability (DFT). DFT encompasses
various techniques and methodologies integrated into the ASIC design process to facilitate
efficient testing and diagnosis of manufacturing defects.

I familiarized myself with DFT principles such as scan chains, built-in self-test (BIST),
and boundary scan, which are essential for enhancing test coverage and reducing test costs in
ASIC manufacturing. I focused on investigating manufacturing defects that can occur during the
fabrication process of ASICs. I studied different types of defects such as process variations,
material impurities, and physical abnormalities that can adversely impact the functionality and
reliability of integrated circuits. Understanding manufacturing defects is crucial for
implementing effective quality assurance measures and yield enhancement techniques in ASIC
production.

9
 4.2 : ACTIVITY LOG FOR THE SECOND WEEK

DAY& Brief description of the Person

DATE dailyactivity Learning Outcome In-
Charge
Signature
I had learnt about the System on Chip
Day – 1
and its applications Basics in RTL
(10-06-2024)

I had learnt about the Goals of Design

Day – 2
for Testability by considering the Number Conversions
(11-06-2024)
observability and controllability in
the
circuit design
I had learnt about the different types of
Day – 3
structures in designing which is used Number Conversions
(12-06-2024)
for Test

I had learnt about the Verilog code

Day – 4
for Flip-Flop which is used to design Number Conversions
(13-06-2024)
by the RTL engineer and Netlist

I had learnt about the different

Day – 5
libraries in Design for Testability Basic Logic Gates
(14-06-2024)

I had learnt about the different

Day –6
functionalities in both RTL and Code Conversions
(15-06-2024)
Netlist parameters

10
 WEEKLY REPORT
WEEK – 2 (From 10 - 06 - 2024 to 15 - 06 - 2024 )

Objective of the Activity Done: Basics in RTL & Code Conversions

Detailed Report:
In this detailed report for this week, I delved into the fundamentals of Register-Transfer
Level (RTL) design, which serves as a crucial abstraction in digital circuit design. RTL is a
level of abstraction that represents a digital circuit in terms of the flow of data between
registers, along with the logical operations performed on this data. Registers are basic storage
elements in digital circuits, capable of storing binary data.

They form the backbone of RTL designs, facilitating the transfer of data between
different components. RTL describes the flow of data between registers, indicating how data is
transferred and manipulated within a digital circuit. This data flow is represented using
symbolic notation, aiding in the visualization and analysis of circuit behavior. RTL
encompasses various logical and arithmetic operations performed on data as it flows through
the circuit.

These operations include addition, subtraction, AND, OR, and more, which are applied
to data stored in registers. RTL provides a higher level of abstraction compared to gate-level or
transistor-level designs. It enables designers to focus on functionality rather than
implementation details, thus simplifying the design process. Gain a solid understanding of RTL
fundamentals, including registers, data flow, and operations. Learned how to translate high-
level designs into RTL representations. Develop problem-solving skills through hands-on
exercises and analysis of RTL designs.

During this week, the focus was on understanding different numbering systems and
mastering the art of converting numbers between them. This knowledge lays a strong
foundation for various digital design tasks and helps in effectively representing data in different
contexts. the focus shifted to more advanced number conversions, including octal, Binary
Coded Decimal (BCD), and gray code.

Additionally, the basics of logic gates were introduced, laying the groundwork for
understanding digital logic and circuit design. The focus was on combinational logic design and
Register-Transfer Level (RTL) basics. Combinational logic circuits form the foundation of
digital systems, while RTL provides an abstraction for describing digital circuits in terms of
data flow and operations.
11
 4.3 : ACTIVITY LOG FOR THE THIRD WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature
I had learnt about the Integrated
Day – 1
Circuit Design Flow for Adders, Subtractors
(17-06-2024)
Designing and Testing

I had learnt about the Defects,

Day – 2
advantages and disadvantages Encoders, Decoders
(18-06-2024)
for both Silicon and Germanium

I had learnt about the Site testing

Day – 3
and multisite testing in DFT Data Types in Verilog HDL
(19-06-2024)

I had learnt about the IC foundry &

Day – 4
Quality patterns generation Operators in Verilog
(20-06-2024)

I had learnt about the Testing patterns

Day – 5
before manufacturing Continuous & Procedural
(21-06-2024)
Processes Statements

I had learnt about the Goals of Design

Day –6
for Testability by considering the Timing Controlled
(22-06-2024)
observability and controllability in Statements
the circuit design

12
 WEEKLY REPORT
WEEK – 3 (From 17-06-2024 to 22-06-2024)

Objective of the Activity Done: Encoders, Decoders & Processes Statements

Detailed Report:
In this detailed report for this week, I delved into understanding the fundamentals of
adders and subtractors in digital design. I studied various types of adders such as half-adders,
full-adders, ripple carry adders, and carry lookahead adders. Additionally, I explored different
subtraction methods including 2's complement and borrow-based subtraction. Through
simulations and hands-on exercises, I gained insight into the functionality and performance of
these arithmetic circuits in Verilog HDL.

I focused on encoders and decoders, essential components in digital systems. I learned

about priority encoders, binary encoders, and decimal encoders, understanding their design
principles and applications. Additionally, I studied different types of decoders such as binary
decoders and 3-to-8-line decoders. Through practical exercises, I implemented encoders and
decoders using Verilog HDL, gaining proficiency in their design and usage.

I dedicated my time to comprehensively understanding data types in Verilog HDL. I

explored scalar types such as bit and logic, as well as composite types including vectors and
arrays. Additionally, I delved into signed and unsigned data types, and their implications for
arithmetic operations. Through coding exercises, I practiced declaring and manipulating data
types in Verilog, gaining hands-on experience in data representation and manipulation.

I focused on operators in Verilog HDL, crucial for expressing digital logic operations. I
studied arithmetic operators, logical operators, bitwise operators, and relational operators,
understanding their usage and precedence rules. Additionally, I explored their application in
various Verilog constructs such as assignment statements and conditional expressions. Through
coding assignments, I implemented Verilog modules utilizing different types of operators,
enhancing my proficiency in Verilog programming.

I delved into continuous and procedural process statements in Verilog. I differentiated

between continuous assignments and procedural assignments, understanding their roles in
modeling combinational and sequential logic, respectively. Additionally, I explored initial and
always blocks for specifying procedural behavior and state machines. Through practical
exercises, I gained hands-on experience in using these statements to model complex digital
circuits accurately.
13
 4.4 : ACTIVITY LOG FOR THE FORTH WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature
I had learnt about the ASCI Design
Day – 1
Flow ASIC Design Flow
(24-06-2024)

I had learnt about the Metal Oxide

Day – 2
Semiconductor Devices MOS Device (JFET,
(25-06-2024)
MOSFET)

I had learnt about the n- Metal Oxide

Day – 3
Semiconductor Field Effect Transistor n-MOSFET
(26-06-2024)

I had learnt about the different types of

Day – 4
Modes of Operation in Design for Modes of Operation
(27-06-2024)
Testability

I had learnt about the Complementary

Day – 5
Metal Oxide Semiconductor Inverter CMOS Inverter
(28-06-2024)
along with truth table & Operation

I had learnt about the Design for

Day –6
Testability Design Flow DFT Design Flow
(29-06-2024)

14
 WEEKLY REPORT
WEEK – 4 (From 24 - 06 - 2024 to 29 - 06 - 2024 )

Objective of the Activity Done: Operation Modes & DFT Design Flow
Detailed Report:
In this detailed report for this week, I embarked on understanding the ASIC Design
Flow, a systematic process used to design and manufacture Application-Specific Integrated
Circuits. The ASIC design flow typically involves several stages including requirements
analysis, architectural design, logic design, verification, synthesis, physical design, and
fabrication. I familiarized myself with each stage and gained insights into the tools and
methodologies commonly employed in ASIC design, setting a solid foundation for my future
tasks.

I have I focused on comprehending the ASIC Design Flow. ASIC Design Flow outlines
the step-by-step process involved in designing Application-Specific Integrated Circuits
(ASICs), from initial specification to fabrication. I familiarized myself with the various stages
of ASIC Design Flow, including requirements analysis, architecture design, RTL coding,
synthesis, physical design, verification, and manufacturing. Understanding ASIC Design Flow
is crucial for efficiently managing ASIC projects and ensuring the successful development of
custom integrated circuits.

I delved into the world of Metal-Oxide-Semiconductor (MOS) devices, including

Junction Field-Effect Transistors (JFETs) and Metal-Oxide-Semiconductor Field-Effect
Transistors (MOSFETs). I studied the principles of operation, characteristics, and applications
of these semiconductor devices. Understanding MOS devices is essential as they form the
building blocks of modern integrated circuits, playing a vital role in amplification, switching,
and digital logic functions.

I concentrated on n-MOSFET (N-channel Metal-Oxide-Semiconductor Field-Effect

Transistor) and its modes of operation. I learned about the operation of n-MOSFET in
enhancement mode and depletion mode, and how its conductivity can be controlled by the gate
voltage. Understanding the modes of operation of n-MOSFET is crucial for designing various
logic gates and analog circuits in CMOS technology, which forms the basis of modern digital
integrated circuits. I studied their operating principles, characteristics, and applications in
integrated circuit design. Understanding MOS devices is crucial as they form the building
blocks of modern semiconductor technology, playing a pivotal role in ASIC design and

15
implementation.

16
 4.5 : ACTIVITY LOG FOR THE FIFTH WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature
I had learnt about the System on Chip
Day – 1
and its applications System on Chip
(01-07-2024)

I had learnt about the Goals of Design

Day – 2
for Testability by considering the Goals of DFT
(02-07-2024)
observability and controllability in
the circuit design
I had learnt about the different types of
Day – 3
structures in designing which is used Design Structures
(03-07-2024)
for Test

I had learnt about the Verilog code

Day – 4
for Flip-Flop which is used to design Verilog code for Flip-Flop
(04-07-2024)
by the RTL engineer and Netlist in both RTL & Netlist

I had learnt about the different

Day – 5
libraries in Design for Testability Libraries in DFT
(05-07-2024)

I had learnt about the different

Day –6
functionalities in both RTL and RTL &
(06-07-2024)
Netlist parameters Netlist
Functionality

17
 WEEKLY REPORT
WEEK – 5 (From 01 - 07- 2024 to 06 - 07 - 2024 )

Objective of the Activity Done: Goals & Libraries in DFT

Detailed Report:
In this detailed report for this week, I began by familiarizing myself with the concept of
System on Chip (SoC). SoC integrates various components such as processors, memory,
peripherals, and interfaces onto a single integrated circuit (IC). I learned about the architecture,
design considerations, and applications of SoCs in diverse fields including mobile devices, IoT,
automotive, and aerospace. Understanding SoC lays the groundwork for comprehending
complex integrated circuit designs.

I focused on understanding the goals of Design for Testability (DFT) in ASIC design.
DFT aims to enhance the testability of integrated circuits by incorporating design features and
structures that facilitate efficient testing and fault detection during manufacturing. I delved into
the objectives of DFT such as achieving high test coverage, reducing test time and cost, and
improving fault diagnosis capabilities. Understanding the goals of DFT is essential for
implementing effective testing strategies in ASIC designs.

I dedicated my efforts to studying various design structures commonly used in ASIC

design. I explored hierarchical design methodologies, modular design approaches, and design
reuse techniques. Understanding design structures is crucial for organizing complex designs
into manageable and scalable modules, facilitating efficient collaboration among design teams,
and improving productivity in ASIC development.

I focused on writing Verilog code for a Flip-Flop, a fundamental sequential logic

element used in digital circuit design. I developed Verilog code for Flip-Flop in both Register
Transfer Level (RTL) and Netlist representations. RTL code describes the behavior of the Flip-
Flop at a higher abstraction level, while Netlist code represents the Flip-Flop's implementation
in terms of gates and interconnections. Writing Verilog code for Flip-Flop enhanced my
understanding of digital logic design and Verilog programming.

I had learnt about the libraries; Libraries play a crucial role in DFT by providing a
collection of pre-characterized standard cells optimized for testability features. These libraries
contain a variety of functional elements such as flip-flops, multiplexers, and logic gates, each
designed to meet specific testability requirements.

18
 4.6 : ACTIVITY LOG FOR THE SIXTH WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature
I had learnt about the Integrated
Day – 1
Circuit Design Flow for IC Design Flow
(08-07-2024)
Designing and Testing

I had learnt about the Defects,

Day – 2
advantages and disadvantages Defects in Silicon &
(09-07-2024)
for both Silicon and Germanium Germanium

I had learnt about the Site testing

Day – 3
and multisite testing in DFT Testing and Multisite
(10-07-2024)
Testing

I had learnt about the IC foundry &

Day – 4
Quality patterns generation IC Foundry & Quality
(11-07-2024)
Patterns Generation

I had learnt about the Testing patterns

Day – 5
before manufacturing Manufacturing Test
(12-07-2024)

I had learnt about the Goals of Design

Day –6
for Testability by considering the Goals for DFT
(13-07-2024)
observability and controllability in
the circuit design

19
 WEEKLY REPORT
WEEK – 6 (From 08-07-2024 to 13-07-2024)

Objective of the Activity Done: IC Design Flow & Quality Test Patterns
Detailed Report:
In this detailed report for this week, I have gained the knowledge on IC Design Flow &
Quality Test Patterns. During this week of my internship, I immersed myself in understanding
the Integrated Circuit (IC) Design Flow. The IC Design Flow is a systematic process that
outlines the steps involved in designing and fabricating integrated circuits. I familiarized
myself with various stages of the design flow, including specification, architecture, design,
verification, synthesis, layout, and fabrication. Understanding the IC Design Flow provided me
with a comprehensive overview of the entire process, laying the foundation for my future tasks.

I delved into studying defects that occur in semiconductor materials such as Silicon and
Germanium. I learned about different types of defects, including point defects, line defects, and
surface defects, and their impact on semiconductor device performance. Understanding defects
is crucial for optimizing manufacturing processes and improving the quality and reliability of
integrated circuits. I gained insights into defect analysis techniques and methodologies used in
semiconductor fabrication facilities.

I focused on understanding testing methodologies employed in the semiconductor

industry, particularly Multisite Testing. Multisite Testing involves testing multiple integrated
circuits simultaneously, thereby improving test throughput and reducing test time and cost. I
learned about the challenges and advantages of Multisite Testing and explored techniques for
implementing efficient and reliable testing strategies. Understanding testing methodologies is
essential for ensuring the quality and reliability of integrated circuits during manufacturing.

I dedicated my efforts to studying IC Foundry operations and Quality Patterns Generation.

IC Foundries are specialized facilities that manufacture integrated circuits on behalf of
semiconductor companies. I gained insights into the processes and services offered by IC
Foundries, including wafer fabrication, packaging, and testing. Quality Patterns Generation
involves designing test patterns that are used to detect and diagnose defects during
manufacturing testing. I learned about techniques for generating high-quality test patterns and
ensuring comprehensive test coverage for manufactured integrated circuits.

20
 4.7 : ACTIVITY LOG FOR THE SEVENTH WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature
I have completed the learning of
Day – 1
concept named Built in Self - Built in Self-Test
(15-07-2024)
Test (BIST)

Day – 2
I have completed the learning of Boundary Scan
(16-07-2024)
concept named Boundary Scan

Day – 3
I have completed the learning of Memory Test and Repair
(17-07-2024)
concept named Memory Test &
Repair

Day – 4
I have completed the learning of Design for debugging
(18-07-2024)
concept named Design for debugging

I have completed the learning of

Day – 5
concept named Advanced Advanced Testability
(19-07-2024)
Testability Techniques Techniques

I have completed the learning of Post-Silicon Validation

Day –6
(20-07-2024) concept named Post-Silicon
Validation

21
 WEEKLY REPORT
WEEK – 07 (From 15-07-2024 to 20-07-2024)

Objective of the Activity Done: BIST & JTAG Techniques

Detailed Report:

In this detailed report for this week, I I had the opportunity to explore Built-in Self-Test
(BIST) techniques for enhancing testability in integrated circuits (ICs). BIST is a methodology
that enables ICs to test themselves without the need for external test equipment. I learned about
the design and implementation of BIST structures, including on-chip test pattern generators and
result analyzers.

Through hands-on projects, I gained experience in integrating BIST features into IC

designs and optimizing them for various fault models. I also studied BIST architectures for
different types of circuits, including digital, analog, and mixed-signal designs. Overall, the
BIST module provided valuable insights into self-testing strategies and their role in improving
IC testability and reliability.

Another important aspect of testability that I explored during the internship was
Boundary Scan, also known as Joint Test Action Group (JTAG). Boundary Scan is a
standardizedmethod for testing and debugging ICs, particularly for verifying interconnects on
printed circuit boards (PCBs). I learned about the architecture and operation of JTAG chains,
scan cells, and Test Access Ports (TAPs).

Through practical exercises, I gained proficiency in writing and executing boundary

scan test patterns using industry-standard tools. Additionally, I studied advanced JTAG features
such as IEEE 1149.6 for testing high-speed serial interconnects. The knowledge gained from
the boundary scan module equipped me with valuable skills for diagnosing and debugging
complex IC and PCB designs.
Memory testing and repair are critical aspects of IC manufacturing and testing,
especially in systems with large memory arrays. During the internship, I delved into memory
test and repair techniques for identifying and correcting defects in memory devices. I learned
about built-in memory test features such as March algorithms and memory built-in self-repair
(BISR) mechanisms. Through simulation and emulation exercises, I gained practical experience
in detecting and diagnosing faults in memory arrays, including stuck-at faults, transition faults,
and coupling faults.

22
 4.8 : ACTIVITY LOG FOR THE EIGHTH WEEK

DAY& Brief description of the Person

DATE Daily activity Learning Outcome In-
Charge
Signature

Day – 1
From all the modules, I had attempted Attempted Test-01
(22-07-2024)
the test-01

Day – 2
From all the modules, I had attempted Attempted Test-02
(23-07-2024)
the test-02

Day – 3
By completing all the modules in this Received Certificate from
(24-07-2024)
course and received certificate Intern Organization

By considering all the actions and

Day – 4
tasks from the day-1 and collected Report Preparation for
(25-07-2024)
Certificate to attach them in the Industrial Internship
report. part

Day – 5
By placing all the gathered Working on
(26-07-2024)
information in to the detailed report Internship
by day-wise Detailed Report

The Detailed Industrial Internship Report

Day –6
(27-07-2024) Internship report is ready to Submission
submit in the department

23
 WEEKLY REPORT
WEEK – 08 (From 22-07-2024 to 27-07-2024)

Objective of the Activity Done: REPORT SUBMISSION & PRESENTATION

Detailed Report:

In this detailed report for this week, I attempted the first test, which assessed my
understanding of fundamental concepts related to digital design and Verilog HDL. The test
covered topics such as adders, subtractors, encoders, decoders, data types, operators, and
procedural statements. I prepared for the test by reviewing lecture materials, completing
practice problems, and participating in study sessions with fellow interns. During the test, I
demonstrated proficiency in applying theoretical knowledge to solve practical problems and
accurately implementing Verilog code to simulate digital circuits. While I encountered some
challenges, such as time constraints and complex problem scenarios, I successfully completed
the test and gained valuable insights into areas for further improvement.

The second test in the internship focused on advanced topics in digital design and
Verilog HDL, including timing control, state machines, memory elements, and design
optimization techniques. Leading up to the test, I dedicated significant time to studying
advanced concepts, experimenting with advanced Verilog constructs, and seeking clarification
on complex topics from mentors and colleagues. During the test, I encountered challenging
scenarios that required careful analysis and creative problem-solving skills. Despite facing
some difficulties, I approached each problem methodically and leveraged my understanding of
digital design principles to devise effective solutions. Overall, the second test provided an
opportunity to deepen my knowledge and skills in advanced areas of digital design and Verilog
programming.

As a testament to my successful completion of the internship program, I was awarded a

certificate from the intern organization. The certificate recognized my dedication, hard work,
and contributions to the internship projects and activities. It served as formal acknowledgment
of my participation in the program and demonstrated my commitment to professional
development in the field of digital design and Verilog HDL. I proudly displayed the certificate
as a symbol of my achievement and as a reminder of the valuable experiences gained during the
internship.

As part of the industrial internship, I was tasked with preparing a comprehensive report
documenting my experiences, learnings, and contributions throughout the internship.
24
 CHAPTER 5: OUTCOMES DESCRIPTION

5.1 : The work environment I have experienced: -

The real time work experience is great, and it is very positive towards our studies, and
it helps me a lot in maintaining time. From one day to another I am able to transition from
online classes without falling behind schedule. Mentors are very helpful and approachable to
complete my virtual internship. It is very surprising to see how quickly I adapted to them in
thisaspect of internship. This online or virtual learning provides more time flexibility. I
wanted to provide you with an overview of my work experience during my internship as an
Intern in VLSIDESIGN FOR TESTABILITY domain.
It has been an incredibly enriching journey, and I am grateful for the opportunity to
learn and contribute to the team. Throughout my internship, I was fortunate to work on several
projects that allowed me to apply my theoretical knowledge of Design for Testability to real-
world scenarios. I have been assigned a dedicated workspace equipped with the necessary
hardware and software tools. During my internship, I have participated in incident response
activities. This includes monitoring the test cases by checking controllability and observability
to the RTL design which is not allowed to modified by the DFT engineer.
I had the opportunity to review and contribute to the organization's security policies
and procedures, particularly in areas related to best practices, compliance, and incident
handling. encourages ongoing learning and development. I have been provided access to
training materials and resources to prepare for building my career in this Very Large-Scale
Integration (VLSI) domain. In this some of the modules and project codes taught me valuable
problem- solving skills. Collaborating with senior developers to find solutions was a great
learning experience.
Design for Test is a critical aspect of integrated circuit (IC) design, focusing on
ensuring that semiconductor chips are designed in such a way that they can be easily and
effectively tested during manufacturing to ensure quality and reliability. Internships in DFT
typically offer valuable hands-on experience in various aspects of IC testing and design
verification. I collaborated with other team members, including administrators and business
analysts, to understand project requirements and provide updates on my progress. This
improved my communication skills and gave me insight into the cross-functional nature of
Testing development. I am incredibly grateful for the support and mentorship provided by the
team during this internship. Thank you for giving me the opportunity to be a part of this
dynamic team and contribute to meaningful projects.

25
5.2 : Technical skills I have acquired: -

I had acquired a diverse set of technical skills that would prepare me for a career in
semiconductor design, testing, and verification. These skills would enable me to contribute
effectively to the development of high-quality and reliable integrated circuits in various
industries. I have acquired the real time technical skills are gaining expertise in performing
physical or digital tasks. There are many different kinds of technical skills, I had the
privilege of acquiring during this journey. Your guidance and support have been
invaluable in shaping my learning experience. I've gained proficiency in VLSI – Design
for Testability domain of having a strong understanding of DFT principles, including
various testing methodologies such as scan-based testing, built-in self-test (BIST), and
boundary scan (JTAG).

I would learn about fault models, test coverage metrics, and the importance of
designing testable integrated circuits. I would become familiar with different DFT
techniques and methodologies used to enhance testability and fault coverage in integrated
circuits. This would include understanding the operation and implementation of scan
chains, memory BIST, logic BIST, and other DFT structures and algorithms. I would gain
proficiency in using Electronic Design Automation (EDA) tools specifically designed for
DFT tasks. This might include tools for scan insertion, ATPG (Automatic Test Pattern
Generation), fault simulation, and test coverage analysis. I would become adept at
navigating and utilizing tools such as Mentor Graphics, Synopsys' DFTMAX, and
Cadence's Encounter Test.

I had developed some of programming and scripting skills necessary for

automating DFT tasks and working with DFT tools. This might involve learning
languages such as Python, TCL (Tool Command Language), or Perl to write scripts for
tasks like test pattern generation, test coverage analysis, and DFT optimization. I would
gain experience in running simulations and performing verification tasks to ensure the
correctness and effectiveness of DFT features within integrated circuits. This could
include conducting functional simulations, gate-level simulations, and fault simulations to
verify DFT functionality and testability.

I would learn techniques for debugging DFT-related issues and optimizing DFT
implementations. This might involve identifying and resolving issues such as timing
violations, test pattern failures, and DFT-related design errors. I would acquire the ability
to modify and optimize existing IC designs to incorporate DFT features effectively.

26
5.3 : The managerial skills I have acquired: -

I have acquired the best managerial skills from the institution which I have performed
and gave my best in as part of internship. In this I have learnt about the managerial skills that
are technical skills, conceptual skills, human management skills. in part of internship, I had
learnt that defining the abilities that can executive should possess in order to fulfill specific
tasks in an organization. I've had the opportunity to develop and hone various managerial
skills that are crucial for effective leadership and team management.

I have learned to effectively communicate with team members, supervisors, and clients
both verbally and in writing. I can articulate ideas clearly, listen actively to others, and
provide constructive feedback. Through regular team meetings and project updates, I have
ensured that everyone is on the same page regarding project goals, timelines, and
expectations. I have demonstrated the ability to lead and motivate team members towards
common goals. By setting clear objectives, delegating tasks effectively, and providing
guidance and support, I have helped my team achieve success in various projects.

I have also fostered a collaborative and inclusive work environment where everyone
feels valued and empowered to contribute their ideas. Managing multiple tasks and deadlines
has been a significant aspect of my internship experience. I have learned to prioritize tasks
based on their importance and urgency, allocate time and resources efficiently, and adapt to
changing priorities. Through careful planning and organization, I've been able to meet project
deadlines and deliver high-quality work consistently.

I have developed strong analytical and critical thinking skills that enable me to identify
issues, analyse root causes, and develop effective solutions. Whether it's resolving conflicts
within the team, overcoming obstacles in a project, or addressing challenges faced by clients, I
approach problems with a proactive and solution-oriented mindset. I have gained experience
in making informed and timely decisions by weighing various factors and considering
potential outcomes. I have learned to gather relevant information, evaluate different options,
and choose the course of action that aligns with project objectives and organizational goals.

Additionally, I have become more confident in my decision-making abilities through

feedback and reflection on past experiences. The dynamic nature of the work environment has
taught me to be adaptable and flexible in the face of uncertainty and change. I have learned to
embrace new challenges, adjust to shifting priorities, and thrive in situations that require quick
thinking and agile responses. By staying open-minded and proactive, I have been able to
navigate unforeseen circumstances and maintain productivity in challenging situations.

27
5.4 : Improvement on my communication skills: -

During my internship period I have learnt many of the skills like verbal
communication, listening skills, written communication, interpersonal communication,
presentation skills, negotiation and persuasion, conflict resolution, feedback solicitation and
incorporation, cross- cultural communication, time management communication, remote
communication all these skills are a part from the communication skills which I have
acquired during my period of internship.

In this internship training I learnt many of the communication skills, I learnt about the
oral communication, written communication, conversational abilities, confidence levels
while communicating. by the above-mentioned skills, I can make my resume powerful and to
notice by the interviewer. By listening, I learnt many of the things about the subject related
topics and to speak fluently with others and among them I learnt that to speak with others in
understandable language and in this the body language also matters.

It is very important in the face-to-face meetings and interviews and also in the video
conferences. Making that the appear accessible, that should not cross arms by making the
eye contact the other person will knows the attention. The main skill is noting the notes
which is delivering by another person. It is the main to treat every person equally,
communication communicate effectively is a teachable skill, ready to communicate, be sure
that you are in right frame of mind, tiredness, frustration, sadness, and anger, among the
other range of emotions can hamper.

Sometimes the direct communication is required to maintain a good relation or to be

thankful. By articulating the information in good matter to deliver to other person then the
other person appreciates and be thankful to others who helps us to make our own way to get
into it. By noticing the close conversations, I learnt many of things from the higher officials
and participating in the many of group discussions and debates will improve me to make a
right choice and made a right place to speak.

Giving greetings to the others also main theme in the communication skills. be always
thankful to others who have given you chance to prove what you are and to stand by yourself
in that particular field. Without going with the negative information who spreads the
negative more then don’t be the tail of them be positive and maintain your ideas and
strategies very secretly and appreciate others without ego tic issues in mind. As the skill
developer student, I have and will to take more actions to grew more and more.

28
 I've learned to express ideas and convey information in a clear and concise manner,
ensuring that my messages are easily understood by others. By practicing effective
communication techniques such as structuring my thoughts logically and using simple
language, I've minimized misunderstandings and improved overall clarity in my
communication. I've developed active listening skills, which involve fully focusing on what
others are saying without interrupting, judging, or formulating responses prematurely.

Actively listening to colleagues, supervisors, and clients has allowed me to

gainvaluable insights, understand different perspectives, and establish stronger rapport with
others. I've become more adaptable in tailoring my communication style to suit different
audiences and situations. Whether communicating with team members, presenting to senior
management, or engaging with clients, I adjust my tone, language, and level of detail to
effectively connect with my audience and achieve desired outcomes.

I've actively sought feedback on my communication skills from supervisors, peers, and
mentors, recognizing it as a valuable opportunity for improvement. Incorporating
constructive feedback, I've worked on areas such as vocal tone, body language, and
presentation style to enhance the impact of my communication. Through various written
communication tasks such as emails, reports, and presentations, I've improved my writing
skills, ensuring clarity, coherence, and professionalism in my written correspondence.

I've also learned to adapt my writing style based on the purpose and audience, whether
it's drafting formal reports for stakeholders or composing concise emails for team members.
I've gained confidence in public speaking through opportunities such as team presentations,
client meetings, and internal workshops. By practicing techniques such as maintaining eye
contact, controlling nervousness, and using visual aids effectively, I've become more
comfortable and proficient in delivering engaging presentations. I've developed
communication skills specifically tailored for conflict resolution situations, such as active
listening, empathy, and assertiveness.

When addressing conflicts within the team or managing challenging conversations, I

prioritize open communication, mutual respect, and collaborative problem-solving to reach
satisfactory resolutions. Overall, my internship experience has been instrumental in refining
my communication skills, enabling me to effectively convey ideas, build relationships, and
contribute to the success of projects and teams. I continue to actively seek opportunities for
further growth and refinement in this essential skill set.

29
5.5 : Technological developments I have observed: -

In this internship training I had observed the best developments in Very Large-Scale
Integration, there have been several significant technological developments in recent years,
driven by the continuous demand for smaller, faster and more power-efficient semiconductor
devices and In the domain of Design for Testability (DFT) within Very Large Scale Integration
(VLSI), there have been several notable technological developments aimed at enhancing the
efficiency, accuracy, and effectiveness of testing semiconductor devices.
3D integration has emerged as a promising approach to overcome the limitations of
traditional planar scaling. Through technologies such as Through-Silicon Vias (TSVs) and
Wafer-on-Wafer (WoW) bonding, multiple layers of active devices can be vertically stacked,
enabling higher integration density, shorter interconnect lengths, and improved performance
while reducing power consumption. Innovations in semiconductor packaging have played a
crucial role in enhancing the performance and functionality of VLSI devices.
Techniques such as System-in-Package (Sip), Chip-on-Wafer-on-Substrate (Co-WOS),
and Fan-Out Wafer-Level Packaging (FOWLP) enable the integration of diverse functionalities,
including memory, sensors, and RF components, into a single package, offering improved
system-level performance and efficiency. With the proliferation of battery-powered and energy-
constrained devices, low-power design has become increasingly important in VLSI. Advanced
power management techniques, such as dynamic voltage and frequency scaling (DVFS), power
gating, and adaptive clocking, are being employed to minimize energy consumption while
maintaining or improving performance.
The demand for high-density, low-latency, and non-volatile memory solutions has
driven the development of emerging memory technologies. Technologies such as Resistive
Random- Access Memory (ReRAM), Phase-Change Memory (PCM), and Magnetic Random-
Access Memory (MRAM) offer potential advantages in terms of scalability, endurance, and
power efficiency compared to traditional memory technologies like DRAM and NAND flash.
Heterogeneous integration involves combining diverse semiconductor technologies, such as
CMOS logic, Analog, RF, and MEMS, within a single chip or package.
By integrating different functionalities on a single platform, heterogeneous integration
enables the development of highly integrated and versatile systems-on-chip (SoCs) for
applications ranging from smartphones and IoT devices to automotive and aerospace systems.
Design automation tools and methodologies continue to evolve to address the increasing
complexity and time-to-market pressures associated CHAPTER 6: VIDEO LINKS

30
 INTERNAL ASSESMENT STATEMENT

Name of the Student: BURLU MOUNIKA

Program of study: BACHELOR OF TECHNOLOGY

Year of study: III-Year (2023-24)

Branch: ELECTRONICS & COMMUNICATION ENGINEERING

Register No: 21U91A0414

Name of the College: SRI MITTAPALLI COLLEGE OF ENGINEERING

University: JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY,
KAKINADA(JNTUK)

EVALUATION MAXIMUM MARKS

S.NO CRITERION MARKS AWARDED
1 Activity Log
2 Internship Evaluation
3 Oral Presentation
GRAND TOTAL

Date:

Signature of the Guide

Signature of the Head of the Department

CERTIFIED BY
Date:

Seal:

Signature of the Principal

31