Introduction

In our previous sections, we learned about combinational circuit and their working. The
combinational circuits have set of outputs, which depends only on the present combination of
inputs. Below is the block diagram of the synchronous logic circuit.

Combinational Circuits Sequential Circuits

The outputs of the sequential circuits

The outputs of the combinational circuit
1) depend on both present inputs and
depend only on the present inputs.
present state(previous output).

The feedback path is not present in the The feedback path is present in the
2)
combinational circuit. sequential circuits.

In the sequential circuit, memory

In combinational circuits, memory
3) elements play an important role and
elements are not required.
require.

The clock signal is not required for The clock signal is required for
4)
combinational circuits. sequential circuits.

The combinational circuit is simple to It is not simple to design a sequential

5)
design. circuit.

The sequential circuit is a special type of circuit that has a series of inputs and outputs. The
outputs of the sequential circuits depend on both the combination of present inputs and previous
outputs. The previous output is treated as the present state. So, the sequential circuit contains
the combinational circuit and its memory storage elements. A sequential circuit doesn't need to
always contain a combinational circuit. So, the sequential circuit can contain only the memory
element.

1
Difference between the combinational circuits and sequential circuits are given below:

Types of Sequential Circuits

Asynchronous sequential circuits

The clock signals are not used by the Asynchronous sequential circuits. The asynchronous
circuit is operated through the pulses. So, the changes in the input can change the state of the
circuit. The asynchronous circuits do not use clock pulses. The internal state is changed when
the input variable is changed. The un-clocked flip-flops or time-delayed are the memory
elements of asynchronous sequential circuits. The asynchronous sequential circuit is similar to
the combinational circuits with feedback.

Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's state is done by

the clock signal. The output is stored in either flip-flops or latches(memory devices). The
synchronization of the outputs is done with either only negative edges of the clock signal or
only positive edges.

Clock Signal and Triggering

Clock signal

A clock signal is a periodic signal in which ON time and OFF time need not be the same. When
ON time and OFF time of the clock signal are the same, a square wave is used to represent the
clock signal. Below is a diagram which represents the clock signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at logic, either
high 5V or low 0V, to an equal amount of time. It repeats with a certain time period, which
will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering

These are two types of triggering in sequential circuits:

Level triggering

The logic High and logic Low are the two levels in the clock signal. In level triggering, when
the clock pulse is at a particular level, only then the circuit is activated. There are the following
types of level triggering:

Positive level triggering

2
In a positive level triggering, the signal with Logic High occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of positive level
triggering:

Negative level triggering

In negative level triggering, the signal with Logic Low occurs. So, in this triggering, the circuit
is operated with such type of clock signal. Below is the diagram of Negative level triggering:

Edge triggering

In clock signal of edge triggering, two types of transitions occur, i.e., transition either from
Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive edge
triggering. So, in positive edge triggering, the circuit is operated with such type of clock signal.
The diagram of positive edge triggering is given below.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative edge
triggering. So, in negative edge triggering, the circuit is operated with such type of clock signal.
The diagram of negative edge triggering is given below.

3
Latches

A latch is an asynchronous sequential circuit whose output changes immediately with the
change in the applied input. A latch is used to store 1 bit information in a digital system, so it
is considered as the most elementary memory element.

In this chapter, we will explain in detail about latches in digital electronics along with their
types and applications.

What is a Latch?

In digital electronics, a latch is an asynchronous sequential circuit that can store 1-bit
information. It is used as the fundamental memory element in digital circuits.

A latch can have two stable states namely, set and reset. The set state is denoted by the logic
1 and the reset state is represented by the logic 0. Due to these two stable states, a latch is also
known as a bistable-multivibrator. The state of a latch toggles according to the applied input.

The most important thing to be noted about latches is that they do not have a clock signal for
synchronization. That is why they are called asynchronous sequential circuits.

The logic gates are the fundamental building blocks of latches. Since there is no
synchronization and clock signal used. Hence, the latches operate immediately on the
application of input signals.

Characteristics of Latches

Some key characteristics of latches are explained below −

• Latches can store 1-bit of digital information that can be represented using either logic
0 or logic 1. Thus, the latches are mainly used as memory elements in digital circuits.
• Latches have a feedback mechanism that allows them to maintain their current state as
it is until the next input is applied.
• The operation of latches is completely controlled by applied inputs that means the
output of the latches updates based on the change in the input signals.

Types of Latches

The following are the main types of latches that used in digital circuits and systems −

• SR Latch
• JK Latch
• D Latch
• T Latch

Let us now discuss about each type of latch in detail.

4
SR Latch

The SR latch is a type of latch which has two input lines designated as S and R. Where, S
represents the Set input and R represents the Reset input. Thus, it is also known as Set-Reset
Latch.

The SR latch has two stable states namely Set state (S) and Reset state (R). The block diagram
of the SR latch is shown in the following figure.

In the case of SR latch, the S input sets the output Q to 1 and Q' to 0. On the other hand, the R
input sets the output Q to 0 and Q' to 1. In case, when both S and R inputs are high, the latch is
said to be in forbidden state.

The complete operation of the SR latch for different input combinations is described in the
following truth table −

Inputs Outputs
Comment
S R Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

1 0 1 0 Set state

1 1 X X Forbidden state

The SR latch can be implemented by connecting two NOR gates in a cross-coupled manner as
shown in the following figure.

5
JK Latch

The JK latch is another type of latch which has two inputs namely, J and K. Here, the input J
is similar to S input and the input K is similar to R input in an SR latch.

The operation of the JK latch is similar to that of the SR latch but it does not have the forbidden
state. Instead, it has a toggle state in which the outputs Q and Q' swap their states when both
inputs J and K are 1.

Therefor, the JK latch is mainly designed to overcome the problem of forbidden state in the SR
latch.

The block diagram of the JK latch is shown in the following figure −

The truth table given below describes the operation of the JK latch for different input
combinations −

Inputs Outputs
Comment
J K Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

6
 1 0 1 0 Set state

1 1 Q' Q Toggle state

From this truth table, it is clear that the problem of forbidden state is addressed by
implementing the toggle state.

The logic circuit of the JK latch consists of a combination of two NOR gates and two AND
gates as shown in the following figure.

D Latch

The D Latch, also known as Data latch or transparent latch, is a type of bistable multivibrator
which has two input signals namely, D (Data) input and E (Enable) input.

The output Q of the D latch is same as the input applied at the D input line as long as the E
input is high. When the E input goes low, the output of the D latch is held as it is until the new
input is applied to the D input.

The block diagram of the D latch is shown in the following figure.

7
The truth table given below explains the operation of the D latch −

Inputs Outputs
Comment
D E Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

1 0 Q Q' No change

1 1 1 0 Set state

The logic circuit diagram of the D latch is depicted in the following figure −

T Latch

T latch is a type of latch that toggles its output state (Q) when a logic 1 is applied to its input
line. Hence, it is also known as toggle latch.

The T latch is implemented by connecting the J and K inputs of the JK latch together as shown
in the following block diagram.

8
The truth table describing the operation of the T latch is shown below −

Input Present State Next State

T Q Q' Q Q'

0 0 1 0 1

0 1 0 1 0

1 0 1 1 0

1 1 0 0 1

The logic circuit diagram of the T latch is shown in the following figure −

Applications of Latches

The latches find several applications in the field of digital electronics. They are most
elementary storage components used to store one bit of information in digital systems.

Some of the common applications of latches are listed here −

• Latches are used as 1-bit memory element in digital systems.

• Latches are used to design digital registers which are employed for storage and
manipulation of data in microprocessors and microcontrollers.
• Latches are used to design flip-flops which are basically the synchronized latches.
• Latches are also used in communication systems for temporary data storage or buffering
purposes.

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Flip-Flops

A flip-flop is a sequential digital electronic circuit having two stable states that can be used to
store one bit of binary data. Flip-flops are the fundamental building blocks of all memory
devices.

Types of Flip-Flops

• S-R Flip-Flop
• J-K Flip-Flop
• D Flip-Flop
• T Flip-Flop

S-R Flip-Flop

This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R). When in this
circuit when S is set as active, the output Q would be high and the Q' will be low. If R is set to
active then the output Q is low and the Q' is high. Once the outputs are established, the results
of the circuit are maintained until S or R get changed, or the power is turned off.

Truth Table of S-R Flip-Flop

S R Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

1 1 X

Characteristics Table of S-R Flip-Flop

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 S R Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

Characteristics Equation of S-R Flip-Flop

Q(t+1)=S+R′Q(t)

J-K Flip-Flop

Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need of
another flip-flop. The JK flip-flop operates with only positive or negative clock transitions. The
operation of the JK flip-flop is similar to the SR flip-flop. When the input J and K are different
then the output Q takes the value of J at the next clock edge.

When J and K both are low then NO change occurs at the output. If both J and K are high, then
at the clock edge, the output will toggle from one state to the other.

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Truth Table of JK Flip-Flop

J K Q State

0 0 0 No Change

0 1 0 Reset

1 0 1 Set

1 1 Toggles Toggle

Characteristics Table of JK Flip-Flop

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Characteristics Equation of JK Flip-Flop

Q(t+1)=jkQ(t)′+K′Q(t)

D Flip-Flop

In a D flip-flop, the output can only be changed at positive or negative clock transitions, and
when the inputs changed at other times, the output will remain unaffected. The D flip-flops are
generally used for shift-registers and counters. The change in output state of D flip-flop
depends upon the active transition of clock. The output (Q) is same as input and changes only
at active transition of clock

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Truth Table of D Flip-Flop

D Q

0 0

1 1

Characteristics Equation of D Flip-Flops

Q(t+1)=D

T Flip-Flop

A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained

by connecting the J and K inputs together. The flip-flop has one input terminal and clock input.
These flip-flops are said to be T flip-flops because of their ability to toggle the input state.
Toggle flip-flops are mostly used in counters.

Truth Table of T Flip-Flop

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 T Q(t) Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Characteristics Equation of T Flip-Flop

Q(t+1)=T′Q(t)+TQ(t)′=T⊕Q(t)

Applications of Flip-Flops

• Counters
• Shift Registers
• Storage Registers, etc.

What is Set-Reset (SR) Flip-flop?

What is Set-Reset (SR) Flip-flop?

Flip flops are an application of logic gates. A flip-flop circuit can stay in a binary state
continually (as long as power is transferred to the circuit) before conducted by an input signal
to switch states. S-R flip-flop represents SET-RESET flip-flops. The SET-RESET flip-flop
includes two NOR gates and also two NAND gates. These flip-flops are also known as SR
Latch.

The SR flip-flop has two inputs such as the ‘Set’ input and a ‘Reset’ input. The two outputs of
SR flip-flop are the main output Q and its complement Q’.

The diagram shows the circuit diagram of an SR flip-flop.

14
Truth Table of SR Flip Flop

The truth table of SR flip flop is shown in the table.

S R QN.1 QN⋅1’

0 0 QN QN’

0 1 0 1

1 0 1 0

1 1 Indeterminate Indeterminate

A team of cross-coupled NOR gates can describe an SR flip-flop, wherein, the output of one
gate is related to one of the two inputs of the other gate and vice versa. The complementary
input of one NOR gate is ‘R’ while the complementary input of the other gate is ‘S’.

The input ‘R’ makes the output Q and the gate with the ‘S’ input makes the output Q’.

The logic symbol of the SR flip-flop is shown in the figure.

What is D Flip Flop?

15
The D flip-flop is a clocked flip-flop with a single digital input 'D'. Each time a D flip-flop is
clocked, its output follows the state of 'D'. The D Flip Flop has only two inputs D and CP. The
D inputs go precisely to the S input and its complement is used to the R input.

Considering the pulse input is at 0, the outputs of gates 3 and 4 are at the 1 level and the circuit
cannot convert state regardless of the value of D. The D input is sampled when CP = 1. If D is
1, the Q output goes to 1, locating the circuit in the set state. If D is 0, output Q goes to 0, and
the circuit switches to a clear state.

Truth Table of D Flip Flop

The truth table for D flip-flop is as shown in the table.

S D QN+1

0 0 0

0 1 1

1 0 0

1 1 1

The logic symbol for the D flip-flop is shown in the figure.

16
The D flip flop obtains the destination from its capacity to manage data into its internal storage.
This type of flip-flop is known as a gated D-latch. The CP input is provided given the
destination G (for gate) to denote that this input allows the gated latch to create applicable data
entry into the circuit.

The binary data present at the data input of the D flip flop is changed to the Q output when the
CP input is allowed. The output follows the data input considering the pulse continues in its 1
state. When the pulse goes to 0, the binary data that was displayed at the data input at the time
the pulse transition appeared is retained at the Q output until the pulse input is allowed again.

The truth table for the D flip flop is displayed in the table. It demonstrates that the next state of
the flip flop is independent of the current state since QN+1 is similar to input D whether Q is
similar to 0 or 1. This defines that an input pulse will change the value of input D into the
output of the flip flop independent of the value of the output earlier the pulse was used.

What is JK Flip Flop?

JK flip-flop can be treated as an alteration of the SR flip-flop. J represents SET, and 'K'
represents CLEAR. In the JK flip-flop, the ‘S’ input is known as the ‘J’ input, and the ‘R’ input
is known as the ‘K’ input. The output of the JK flip-flop does not modify if both ‘J’ and ‘K’
are ‘0’. If both the inputs are ‘1’, then the output dial to its free.

The figure shows the circuit diagram of a JK flip-flop.

Truth Table of JK Flip Flop

The truth table of the JK flip-flop is displayed in the table.

S R QN-1

0 0 QN

17
 0 1 0

1 0 1

1 1 QN’

The logic symbol for the JK flip-flop is demonstrated in the diagram.

Print Page

What is T Flip Flop?

The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T flip flop
is received by relating both inputs of a JK flip-flop. The T flip-flop is received by relating the
inputs ‘J’ and ‘K’. When T = 0, both AND gates are disabled. Therefore, there is no change in
the output. When T= 1, the output toggles.

The diagram demonstrates the circuit diagram of a T flip-flop.

Truth Table of T Flip Flop

The truth table of T flip-flop is displayed in the table.

QN T QN+1

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 0 0 0

0 1 1

1 0 1

1 1 0

The logic symbol of the T flip-flop is shown in the figure.

Shift Registers
Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the
storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and
it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one flip-flop to another.
The registers that allow such data transfers are called as shift registers. There are four mode
of operations of a shift register.

• Serial In - Serial Out (SISO) Shift Register

• Serial In - Parallel Out (SIPO) Shift Register
• Parallel In - Serial Out (PISO) Shift Register
• Parallel In - Parallel Out (PIPO) Shift Register

Serial In - Serial Out (SISO) Shift Register

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of
a four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data
input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so
on.

Block Diagram

19
Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to
be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3
is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2
will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative
clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

20
Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the
register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

Waveforms

21
Serial In - Parallel Out (SIPO) Shift Register
• In such types of operations, the data is entered serially and taken out in parallel fashion.
• Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
• As soon as the data loading gets completed, all the flip-flops contain their required data,
the outputs are enabled so that all the loaded data is made available over all the output
lines at the same time.
• 4 clock cycles are required to load a four bit word. Hence the speed of operation of
SIPO mode is same as that of SISO mode.

Block Diagram

22
Parallel In - Serial Out (PISO) Shift Register
• Data bits are entered in parallel fashion.
• The circuit shown below is a four bit parallel input serial output register.
• Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
• The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
• There are two modes in which this circuit can work namely - shift mode or load mode.

Load Mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass
B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary input
B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes
place.

Shift Mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the
parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active.
Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus
the parallel in serial out operation takes place.

Block Diagram

23
Parallel In - Parallel Out (PIPO) Shift Register
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2,
D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.

Block Diagram

Bidirectional Shift Register

• If a binary number is shifted left by one position then it is equivalent to multiplying the
original number by 2. Similarly if a binary number is shifted right by one position then
it is equivalent to dividing the original number by 2.
• Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
• Such a register is called bi-directional register. A four bit bi-directional shift register is
shown in fig.
• There are two serial inputs namely the serial right shift data input DR, and the serial
left shift data input DL along with a mode select input (M).

Block Diagram

24
Operation

Sr.No Condition Operation

If M = 1, then the AND gates 1, 3, 5 and 7 are enabled

whereas the remaining AND gates 2, 4, 6 and 8 will be
With M = 1 − Shift disabled.
1
right operation The data at DR is shifted to right bit by bit from FF-3 to FF-
0 on the application of clock pulses. Thus with M = 1 we get
the serial right shift operation.

When the mode control M is connected to 0 then the AND

gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled.
With M = 0 − Shift
2 The data at DL is shifted left bit by bit from FF-0 to FF-3 on
left operation
the application of clock pulses. Thus with M = 0 we get the
serial right shift operation.

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift the data in both directions is called a bi-directional
shift register. Applying the same logic, a shift register which can shift the data in both directions
as well as load it parallely, is known as a universal shift register. The shift register is capable
of performing the following operation −

• Parallel Loading
• Left Shifting
• Right Shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the universal

25
shift register acts as a bi-directional register. For serial left operation, the input is applied to the
serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation,
the serial input is applied to D input.

Block Diagram

Application of Shift Registers

In previous chapter, we discussed four types of shift registers. Based on the requirement, we
can use one of those shift registers. Following are the applications of shift registers.

Shift register is used as Parallel to serial converter, which converts the parallel data into serial
data. It is utilized at the transmitter section after Analog to Digital Converter (ADC) block.

Shift register is used as Serial to parallel converter, which converts the serial data into parallel
data. It is utilized at the receiver section before Digital to Analog Converter (DAC) block.

Shift register along with some additional gate(s) generate the sequence of zeros and ones.
Hence, it is used as sequence generator.

Shift registers are also used as counters. There are two types of counters based on the type of
output from right most D flip-flop is connected to the serial input. Those are Ring counter and
Johnson Ring counter.

In this chapter, let us discuss about these two counters one by one.

Ring Counter

26
In previous chapter, we discussed the operation of Serial In - Parallel Out (SIPO) shift register.
It accepts the data from outside in serial form and it requires ‘N’ clock pulses in order to shift
‘N’ bit data.

Similarly, ‘N’ bit Ring counter performs the similar operation. But, the only difference is that
the output of rightmost D flip-flop is given as input of leftmost D flip-flop instead of applying
data from outside. Therefore, Ring counter produces a sequence of states (pattern of zeros and
ones) and it repeats for every ‘N’ clock cycles.

The block diagram of 3-bit Ring counter is shown in the following figure.

The 3-bit Ring counter contains only a 3-bit SIPO shift register. The output of rightmost D flip-
flop is connected to serial input of left most D flip-flop.

Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=001.

Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of Ring
counter from the following table.

No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB)

0 - 0 0 1

1 1 1 0 0

2 0 0 1 0

3 0 0 0 1

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=001. This
status repeats for every three positive edge transitions of clock signal.

Therefore, the following operations take place for every positive edge of clock signal.

Serial input of first D flip-flop gets the previous output of third flip-flop. So, the present output
of first D flip-flop is equal to the previous output of third flip-flop.

27
The previous outputs of first and second D flip-flops are right shifted by one bit. That means,
the present outputs of second and third D flip-flops are equal to the previous outputs of first
and second D flip-flops.

Johnson Ring Counter

The operation of Johnson Ring counter is similar to that of Ring counter. But, the only
difference is that the complemented output of rightmost D flip-flop is given as input of leftmost
D flip-flop instead of normal output. Therefore, ‘N’ bit Johnson Ring counter produces a
sequence of states (pattern of zeros and ones) and it repeats for every ‘2N’ clock cycles.

Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring counter.
The block diagram of 3-bit Johnson Ring counter is shown in the following figure.

The 3-bit Johnson Ring counter also contains only a 3-bit SIPO shift register. The
complemented output of rightmost D flip-flop is connected to serial input of left most D flip-
flop.

Assume, initially all the D flip-flops are cleared. So, Q2Q1Q0=000. Here, Q2 & Q0 are
MSB & LSB respectively. We can understand the working of Johnson Ring counter from the
following table.

No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB)

0 - 0 0 0

1 1 1 0 0

2 1 1 1 0

3 1 1 1 1

4 0 0 1 1

5 0 0 0 1

28
 6 0 0 0 0

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000. This
status repeats for every six positive edge transitions of clock signal.

Therefore, the following operations take place for every positive edge of clock signal.

Serial input of first D flip-flop gets the previous complemented output of third flip-flop. So,
the present output of first D flip-flop is equal to the previous complemented output of third
flip-flop.

The previous outputs of first and second D flip-flops are right shifted by one bit. That means,
the present outputs of second and third D flip-flops are equal to the previous outputs of first
and second D flip-flops.

Counters in Digital Logic

A Counter is a device which stores (and sometimes displays) the number of times
a particular event or process has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting purpose, they can count
specific event happening in the circuit. For example, in UP counter a counter
increases count for every rising edge of clock. Not only counting, a counter can
follow the certain sequence based on our design like any random sequence
0,1,3,2… .They can also be designed with the help of flip flops. They are used as
frequency dividers where the frequency of given pulse waveform is divided.
Counters are sequential circuit that count the number of pulses can be either in
binary code or BCD form. The main properties of a counter are timing , sequencing
, and counting. Counter works in two modes
Up counter
Down counter
Counter Classification
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven
by main clock and the clock input of rest of the following flip flop is driven by
output of previous flip flops. We can understand it by following diagram-

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It is evident from timing diagram that Q0 is changing as soon as the rising edge of
clock pulse is encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on. In this
way ripples are generated through Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock input of
the following flip flop
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which
drives each flip flop so output changes in parallel. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher
frequency than asynchronous counter as it does not have cumulative delay because
of same clock is given to each flip flop. It is also called as parallel counter.

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 Synchronous counter circuit

Timing diagram synchronous counter

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From circuit diagram we see that Q0 bit gives response to each falling edge of
clock while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is
dependent on Q2,Q1 and Q0.

Decade Counter
A decade counter counts ten different states and then reset to its initial states. A
simple decade counter will count from 0 to 9 but we can also make the decade
counters which can go through any ten states between 0 to 15(for 4 bit counter).

Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Truth table for simple decade counter

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Decade counter circuit diagram
We see from circuit diagram that we have used nand gate for Q3 and Q1 and
feeding this to clear input line because binary representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input
then counter will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter are always greater than
equal to (log2 n) where n=number of states in counter.

Application of Counters
• Frequency counters
• Digital clock
• Time measurement
• A to D converter
• Frequency divider circuits
• Digital triangular wave generator.

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