Course Administration

• Reading:
• Joseph Yiu, “The Definitive Guide to the ARM Cortex-M0/M0+ processors, 2nd
Ed., Newnes, (Elsevier), 2015
• Gaonkar R. S., "Microprocessor Architecture, Programming and Applications
with 8085", 6th Ed., Penram International, Indian, 2013
• Few handouts from course instructor
• Grading (Theory):
• 30 midsem + 20 internal + 50 endsem
• Total marks=100
• Grading (Practical):
• Practical evaluation (continuous) = 25 (internal) + 25 (external i.e. practical exam)

Dr. Zuber M. Patel, NIT Surat 1

 Historical Perspective
• 1944: Electronic Numerical Integrator And Calculator (ENIAC) computer using Vacuum
tubes
• 1947 : Bardeen, Brattain and Shockley invented transistor at Bell labs
• 1958: Jack Kilbey demonstrated working of integrated transistor
• 1971: Intel introduce 1st processor with 4-bit bus, 8-bit instructions & 12-bit address
• 1978 : John Birkner and H. T. Chua developed easy-to-use programmable array logic
(PAL). The PLA is digital chip with programmable AND gate array but fixed OR gates.
• 1981 => IBM personal computer "Acorn," is introduced. It uses Microsoft's MS-DOS
operating system.
• 1985: ARM introduced its first RISC based Processor core (26 bit address and 32 bit
instructions)

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 Introduction

Microprocessor:
• Programmable general purpose logic device
• Executes set of instruction (software) in well defined manner
• 8-bit to 64-bit variants with variety of computing capabilities
• Architectures: intel x86 CISC, ARM RISC processors, MIPS, PowerPC

Microcomputer:
• Programmable machine having Microprocessor as one of the key element
• It also consists various types of memory, Input devices, Output devices
• Additionally, it contains GPU, Network interfaces, Hard disk drives
• Examples: PC, Mainframe and Super computers

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Dr. Zuber M. Patel, NIT Surat 4
 Introduction

• Many units are connected to common bus.

• Address is used for both memory and I/O devices

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 Introduction
Programming languages that computing system deal with
• Machine Language : Binary code or hex code
• Assembly Language : Mnemonics such as ADD, ADC, LDA, INC etc.
• High level Language : Looks like English vocabulary and grammar

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Introduction

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 Introduction
Instruction Format:
• Mainly contains two fields : Opcode and Operands
• Opcode => control code that tells CPU what to do
• Operand => Constant data or Memory Address
• CISC instructions are variable size (1 byte or 2 byte or 3 byte …)

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 Introduction
Data Format:
• BCD => 4-bit BCD code. A byte can store one (unpacked) or two (packed)
BCD digits
• ASCII => 7-bit ASCII code for a character stored as byte
• Signed Integer => integer data with Sign bit
• Unsigned Integer => integer data without sign bit
• Floating Point => real numbers with mantissa and exponent

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8085 Pin Signals

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8085 Microprocessor

8085 Programming Model

• General purpose registers
• Flags
• PC => Pointer to program
• SP => Pointer to stack memory

• C flag : sets if result of ALU operation exceeds 8-bit

• Z flag : sets if result of ALU operation is zero
• S flag: sets if MSB of result is 1
• P flag: sets if no. of 1s in the result are even

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 8085 Microprocessor

Operations and Machine cycles

• Opcode fetch
• Memory Read / Write
• I/O Read / Write

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 8085: Memory Access

• PC content is placed in address bus, memory content 4Fh is put in buffer register
• Then, 8085 activates the RD control signal that places buffer register value (i.e. 4Fh)
on data bus

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8085: Opcode fetch Operation

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 Few 8085 instructions
• MOV Rd, Rs : copy content of Rs to Rd
• MOV M, Rs : copy content of Rs register to memory pointed by HL
• MOV Rd, M : copy content of memory pointed by HL to register Rd
• MVI Rd, #imm8 : load 8-bit constant to Rd
• LDA #16-bit add. : read memory from 16-bit address location and save in A
• STA #16-bit add. : store value of A register to memory at 16-bit address
• INR Rn : increment 8-bit register Rn
• DCR Rn : decrement Rn
• ANA Rn : bitwise logical AND between A and Rn. Result is saved in A
• ORA Rn : bitwise logical OR between A and Rn. Result is saved in A

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 Few 8085 instructions
• CALL label ; call subroutine named ‘label’
• RET ; return from subroutine (last instruction of subroutine)
• JMP label ; jump to label and execute code from there
• JZ label ; jump to label if Zero flag is set
• JNZ label ; jump to label if Zero flag is reset
• JC label ; jump to label if Zero flag is set
• JNC label ; jump to label if Zero flag is reset
• IN #8-bit ; read data from input port having address #8-bit and save in A
• OUT #8-bit ; write content of A to output port having address #8-bit

Dr. Zuber M. Patel, NIT Surat 16

 8085 Assembly Program
• Load 8-bit numbers in registers B and C. Perform logical AND
between B and C. Save the result in D register.
MVI B, #A3h
MVI C, #2Eh
MOV A, C ; copy value of C to A
ANA B ; logical AND operation, A = A AND B
MOV D, A ; save result in D

Mem. Add Mnemonics Hex code

2100 h MVI B, #A3 h 06 h

2101 h A3 h
2102 h MVI C, #2E h 0E h
2103 h 2E h
2104 h MOV A, C 79 h
2105 h ANA B A0 h
2106 h MOV D, A 57 h
2107 h HLT 76 h

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 Read & Write control signals

• Memories (RAM and ROM chips) are interfaced using Address bus, Data bus and
Control signals (MEMR & MEMW)
• Each memory has chip enable (CE) pin. Memory chip can be enabled /disabled by
applying LOW or HIGH on CE pin
• Input /Output devices use IOR and IOW control signals

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 Memory Interfacing

• N address line can access 2N bytes of memory

• For example, if 4K ROM chip is used, 12 lower address lines (A11. . . A0) are connected to
memory chip. Upper lines will be decoded with logic that will generate chip enable signal
(connected to CE of chip)
• Tristate buffer are required to keep output port of memory in high impedance state when no
read/write operation is performed

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 Memory Interfacing

• The total memory map of 8085 : 0x0000 to 0xFFFF (64 Kbytes)

• Above ROM chip occupies range : 0x8000 to 0x8FFF (4K bytes)

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 Memory Interfacing
• Problem 1: Design and draw interfacing circuit to interface 4K EEPROM and 4K RAM
chip to 8085 with 2x4 Decoder (with active low En) and NAND gates. The starting
address of EEPROM is C000H and that of RAM is D000H. Use control signals directly.
Assume active LOW chip enable (CE) for memory chips.

Address Decoding:
• To interface 4K ROM and 4K RAM, lower twelve address lines A11A10 . . . A0 will be connected
to each chip. Higher address lines A 15 to A12 are used to generate chip enable signal.

• Next two address lines A13 and A12 are connected to input of 2x4 decoder. Two outputs (O 0
and O1) of decoder are connected to chip enable (CE) input of ROM and RAM.

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 Memory Interfacing

• The remaining upper address lines A15A14 are decoded to generate active low
signal to be connected to En input of 2x4 decoder. Since A15 and A14 are high,
Logical NAND operation is performed between A15 and A14 to generate low signal.

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Instruction Timing for MVI A, 32H

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Timing diagram – OUT instruction

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 I/O Interfacing
• Problem 2: Interface one input port of I/O address 44H and one output port having I/O address 55H
using NAND based decoding logic. Eight simple LEDs and eight keys are connected to output and
input port respectively. Assume active HIGH enable for Latches and Buffers.

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 I/O Interfacing
Steps using NAND only gates:
• Generate a unique IO address pulse using 8 address lines (either upper or
lower) using 8 input NAND gate. E.g. for interfacing input port (address
01000100), a unique low address pulse will be generated by inverting all
address lines except A14 and A10.
• For input port: A small logic is the used such that only when both add. Pulse
and IOR signals are LOW, high EN signal for buffer is generated. This is NOR
logic which is realized using NAND gates only.
• For output port: Only when both IOW and Address pulse are Low, latch enable
EN should go High. This is also NOR logic.

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 8085- Subroutine call and Stack

• Subroutine Call
A small segment of code which
is part of software. It can be
called several times from main
program using CALL instruction.
This small segment of code is
called subroutine.
• Stack
A dedicated section of RAM for
storing values temporality.
When first CALL instruction is
executed, return address (that is
30B2h) is automatically stored
in stack memory as shown.

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 8051 Architecture (8-bit Microcontroller)

• Above block diagram is of “Basic or Generic 8051 microcontroller”.

• Advanced 8051 microcontrollers may have additional peripherals, more timers, large memory,
less number of clocks per instruction, less number of pins etc.

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 ARM based MCUs
MCU chips based on ARM CPU cores:
• ST Microelectronics
• NXP
• Texas Instruments
• Microchip
• Infineon

There are many factors to be considered when

selecting a microcontroller device for a product.
• 32/64 bit architectures
• Peripherals and interface features
• Low power requirements
• Performance and maximum frequency
• Operation conditions (voltage, temperature,
electromagnetic interference)
• Future upgradability

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 Performance
DMIPS:
• Dhryston is a benchmark program that includes integer arithmetic, string manipulation,
logic and memory access operations
• The Dhrystone figure of given computing system is calculated by measuring the number
of Dhrystones executed per second and dividing that by 1757. So if a computing system
able to execute 140560 dhrystones per second, then its DMIPS rating is 140560/1757 =
80 DMIPS.
• Above figure can be normalized by Clock freq. E.g. if clock freq. is 50MHz then
performance of computing system 1.6 DMIPS/MHz
Coremark:
• Core mark is new Bench mark program for embedded processors that also
accommodates commonly used algorithms such as Matrix multiplication, Linked list, FSM
and CRC (cyclic redundancy check)
• Performance in terms of Coremarks or Coremarks /MHz
Power/Performance metric:
GOPS/mW (@ Clk freq., Tech., Supply),
nA/MHz (@ Tech., Supply),
mW/MHz (@ Tech., Supply)

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