TimeVision Constraints User Guide

January 2015 Ausdia, Inc © 2015

 TimeVision Constraints User Guide

Copyright 2014 Ausdia, Inc. All rights reserved.

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All technical data contained in this publication is subject to the export control laws of the United
States of America.
Trademarks
TimeVision is a trademark of Ausdia Inc.
Magma and Blast Fusion are registered trademarks of Magma Design Automation
Synopsys, IC Compiler, and Liberty are registered trademarks of Synopsys, Inc.
Cadence, Verilog, and SOC Encounter are registered trademarks of Cadence Design Systems
Disclaimer
Information contained in this publication is subject to change without notice and does not
repre-sent a commitment on the part of Ausdia. The information in this document is the
proprietary and confidential information of Ausdia and its licensors, and may be used only by
Ausdia customers in accordance with a written statement between Ausdia and its customer.
Ausdia does not make any representation or warranties as to the completeness, usefulness, or
accuracy of the informa-tion in this document, nor does Ausdia assume any liability for
damages or costs of any kind that results from use of this information.

Revision Date Description

1.0 7/07/2014 Establish New Document Format
1.1 10/28/2014 Added CGIN-INF Rules
1.2 12/4/2014 Added LOOP rules and CLK-WAV05 rule
1.3 2/8/2015 Added rules CLK-MRG01 and CLK-MRG02. Fixed CLK-INC016
and expounded CGWP-INC011 description.
1.4 5/7/2015 Add SDC Lint Rules
1.5 7/12/2015 Add more SDC Lint Rules
1.6 9/27/2015 Add more SDC Lint Rules

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 TimeVision Constraints User Guide
1 Table of Contents
2 Preface .................................................................................................................................................. 9
2.1 Related Documentation ............................................................................................................................................ 9
2.2 Documentation Conventions .................................................................................................................................. 10
3 Constraints Verification ...................................................................................................................... 12
3.1 Introduction ............................................................................................................................................................. 12
3.2 Setting up the design and running constraint verification: ................................................................................... 14
3.2.1 Design intentional cells variables ....................................................................................................................... 16
3.2.2 Design intentional clock cells variables .............................................................................................................. 18
3.2.3 Auto-generate waivers ........................................................................................................................................ 19
3.3 Timevision Output: .................................................................................................................................................. 19
3.3.1 List of All Rules ..................................................................................................................................................... 21
3.4 Missing clocks rules ................................................................................................................................................. 25
3.4.1 Rule CLK-MIS001 ................................................................................................................................................. 25
3.4.2 Rule CLK-MIS002 ................................................................................................................................................. 27
3.4.3 Rule CLK-MIS003 ................................................................................................................................................. 29
3.4.4 Rule CLK-MIS004 ................................................................................................................................................. 31
3.5 Incorrect clock rules................................................................................................................................................. 33
3.5.1 Rule CLK-INC001 .................................................................................................................................................. 33
3.5.2 Rule CLK-INC002 .................................................................................................................................................. 34
3.5.3 Rule CLK-INC003 .................................................................................................................................................. 36
3.5.4 Rule CLK-INC004 .................................................................................................................................................. 37
3.5.5 Rule CLK-INC005 .................................................................................................................................................. 38
3.5.6 Rule CLK-INC006 .................................................................................................................................................. 40
3.5.7 Rule CLK-INC007 .................................................................................................................................................. 42
3.5.8 Rule CLK-INC008 .................................................................................................................................................. 44
3.5.9 Rule CLK-INC009 .................................................................................................................................................. 46
3.5.10 Rule CLK-INC010 .................................................................................................................................................. 48
3.5.11 Rule CLK-INC011 .................................................................................................................................................. 50
3.5.12 Rule CLK-INC012 .................................................................................................................................................. 52
3.5.13 Rule CLK-INC013 .................................................................................................................................................. 54
3.5.14 Rule CLK-INC014 .................................................................................................................................................. 55
3.5.15 Rule CLK-INC015 .................................................................................................................................................. 57
3.5.16 Rule CLK-INC016 .................................................................................................................................................. 59
3.5.17 Rule CLK-INC017 .................................................................................................................................................. 61
3.5.18 Rule CLK-INC018 .................................................................................................................................................. 62
3.5.19 Rule CLK-INC019 .................................................................................................................................................. 64
3.5.20 Rule CLK-INC020 .................................................................................................................................................. 65
3.5.21 Rule CLK-INC021 .................................................................................................................................................. 67
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3.6 Clock wave rules ...................................................................................................................................................... 68
3.6.1 Rule CLK-WAV001................................................................................................................................................ 68
3.6.2 Rule CLK-WAV002................................................................................................................................................ 70
3.6.3 Rule CLK-WAV003................................................................................................................................................ 72
3.6.4 Rule CLK-WAV004................................................................................................................................................ 73
3.6.5 Rule CLK-WAV005................................................................................................................................................ 75
3.7 Incomplete generated clock rules ........................................................................................................................... 77
3.7.1 Rule CLK-IGC001 .................................................................................................................................................. 77
3.7.2 Rule CLK-IGC002 .................................................................................................................................................. 78
3.8 Reconvergent clock rules ........................................................................................................................................ 80
3.8.1 Rule CLK-RCN001 ................................................................................................................................................. 80
3.8.2 Rule CLK-RCN002 ................................................................................................................................................. 82
3.8.3 Rule CLK-PCN001 ................................................................................................................................................. 84
3.8.4 Rule CLK-PCN002 ................................................................................................................................................. 86
3.9 Blocked clock rules .................................................................................................................................................. 88
3.9.1 Rule CLK-BLK001 .................................................................................................................................................. 88
3.9.2 Rule CLK-BLK002 .................................................................................................................................................. 90
3.10 Clock object rule ...................................................................................................................................................... 91
3.10.1 Rule CLK-OBJ001 .................................................................................................................................................. 91
3.10.2 Rule CLK-OBJ002 .................................................................................................................................................. 93
3.11 Clock data rules ........................................................................................................................................................ 95
3.11.1 Rule CLK-DATA01 ................................................................................................................................................. 95
3.11.2 Rule CLK-DATA02 ................................................................................................................................................. 97
3.11.3 Rule CLK-DATA03 ................................................................................................................................................. 99
3.12 Clock merging point rules ......................................................................................................................................101
3.12.1 Rule CLK-MRG01 ................................................................................................................................................101
3.12.2 Rule CLK-MRG02 ................................................................................................................................................104
3.13 Incorrect clock groups and interclock false path rule with paths ........................................................................107
3.13.1 Rule CGWP-INC001/ICFP-INC001 .....................................................................................................................107
3.13.2 Rule CGWP-INC002/ICFP-INC002 .....................................................................................................................109
3.13.3 Rule CGWP-INC003/ICFP-INC003 .....................................................................................................................112
3.13.4 Rule CGWP-INC004/ICFP-INC004 .....................................................................................................................115
3.13.5 Rule CGWP-INC005/ICFP-INC005 .....................................................................................................................118
3.13.6 Rule CGWP-INC006/ICFP-INC006 .....................................................................................................................121
3.13.7 Rule CGWP-INC007/ICFP-INC007 .....................................................................................................................124
3.13.8 Rule CGWP-INC008/ICFP-INC008 .....................................................................................................................127
3.13.9 Rule CGWP-INC009/ICFP-INC009 .....................................................................................................................129
3.13.10 Rule CGWP-INC010............................................................................................................................................131
3.13.11 Rule CGWP-INC011............................................................................................................................................133
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3.14 Missing clock groups and interclock false path rule.............................................................................................135
3.14.1 Rule CGWP-MIS001/ICFP-MIS001 ....................................................................................................................135
3.14.2 Rule CGWP-MIS002/ICFP-MIS002 ....................................................................................................................137
3.14.3 Rule CGWP-MIS003/ICFP-MIS003 ....................................................................................................................140
3.14.4 Rule CGWP-MIS004/ICFP-MIS004 ....................................................................................................................143
3.14.5 Rule CGWP-MIS005/ICFP-MIS005 ....................................................................................................................145
3.14.6 Rule CGWP-MIS006/ICFP-MIS006 ....................................................................................................................148
3.14.7 Rule CGWP-MIS007/ICFP-MIS007 ....................................................................................................................150
3.15 Incorrect clock groups and interclock false path rule with no paths ..................................................................153
3.15.1 Rule CGNP-INC001/ICFP-IRR001 .......................................................................................................................153
3.16 Missing clock groups rule with no paths...............................................................................................................155
3.16.1 Rule CGNP-MIS001 ............................................................................................................................................155
3.17 User inferred clock groups honored from SDC rules ............................................................................................157
3.17.1 Rule CGIN-INF001 ..............................................................................................................................................157
3.17.2 Rule CGIN-INF002 ..............................................................................................................................................159
3.17.3 Rule CGIN-INF003 ..............................................................................................................................................162
3.18 Mode rules .............................................................................................................................................................164
3.18.1 Rule MODE-CNF-01 ...........................................................................................................................................164
3.18.2 Rule MODE-CNF-02 ...........................................................................................................................................165
3.18.3 Rule MODE-OVL-01 ...........................................................................................................................................167
3.18.4 Rule MODE-TBL-01 ............................................................................................................................................169
3.18.5 Rule MODE-TBL-02 ............................................................................................................................................171
3.19 Coverage rules .......................................................................................................................................................172
3.19.1 Rule UNC-001 ....................................................................................................................................................172
3.19.2 Rule UNC-002 ....................................................................................................................................................174
3.19.3 Rule UNC-003 ....................................................................................................................................................175
3.19.4 Rule UNC-004 ....................................................................................................................................................177
3.19.5 Rule UNC-005 ....................................................................................................................................................178
3.20 LOOP rules ..............................................................................................................................................................180
3.20.1 Rule LOOP-01 .....................................................................................................................................................180
3.20.2 Rule LOOP-02 .....................................................................................................................................................181
3.21 Incorrect IO rules ...................................................................................................................................................183
3.21.1 Rule IOC-INC001/IOC-INC004 ...........................................................................................................................183
3.21.2 Rule IOC-INC002/IOC-INC005 ...........................................................................................................................185
3.21.3 Rule IOC-INC003/IOC-INC006 ...........................................................................................................................186
3.22 Missing IO rules ......................................................................................................................................................188
3.22.1 Rule IOC-MIS001/IOC-MIS002 ..........................................................................................................................188
3.23 Under constrained IO rules ...................................................................................................................................190
3.23.1 Rule IOC-UND001/IOC-UND002 .......................................................................................................................190
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3.24 Source Sync IO rules ..............................................................................................................................................192
3.24.1 Rule IOC-SSI001 .................................................................................................................................................192
3.25 Feedthru IO rules ...................................................................................................................................................193
3.25.1 Rule IOC-FTP001 ................................................................................................................................................193
3.25.2 Rule IOC-FTP002 ................................................................................................................................................195
3.25.3 Rule IOC-FTP003 ................................................................................................................................................196
3.25.4 Rule IOC-FTP004 ................................................................................................................................................198
3.25.5 Rule IOC-FTP005 ................................................................................................................................................199
3.25.6 Rule IOC-FTP006 ................................................................................................................................................201
3.26 Point-to-Point exception rules ..............................................................................................................................203
3.26.1 Rule PPFP-001 ....................................................................................................................................................203
3.26.2 Rule PPFP-002 ....................................................................................................................................................205
3.26.3 Rule PPFP-003 ....................................................................................................................................................206
3.26.4 Rule PPFP-004 ....................................................................................................................................................208
3.26.5 Rule PPFP-005 ....................................................................................................................................................210
3.26.6 Rule PPFP-006 ....................................................................................................................................................212
3.27 SDC Exception rules ...............................................................................................................................................214
3.27.1 Rule SDC-FP-01/SDC-MCP-01............................................................................................................................214
3.27.2 Rule SDC-FP-02/SDC-MCP-02............................................................................................................................216
3.27.3 Rule SDC-FP-03/SDC-MCP-03............................................................................................................................217
3.27.4 Rule SDC-FP-04/SDC-MCP-04............................................................................................................................218
3.27.5 Rule SDC-FP-05 ..................................................................................................................................................219
3.27.6 Rule SDC-MCP-05 ..............................................................................................................................................221
3.27.7 Rule SDC-MCP-06 ..............................................................................................................................................222
3.28 Exceptions Object rules .........................................................................................................................................223
3.28.1 Rule SDC-FP-O-01/SDC-MCP-O-01/SDC-MD-O-01/SDC-GP-O-01 ...................................................................223
3.28.2 Rule SDC-FP-O-02/SDC-MCP-O-02/SDC-MD-O-02/SDC-GP-O-02 ...................................................................225
3.28.3 Rule SDC-FP-O-03/SDC-MCP-O-03/SDC-MD-O-03/SDC-GP-O-03 ...................................................................226
3.28.4 Rule SDC-FP-O-04/SDC-MCP-O-04/SDC-MD-O-04/SDC-GP-O-04 ...................................................................228
3.28.5 Rule SDC-FP-O-05/SDC-MCP-O-05/SDC-MD-O-05/SDC-GP-O-05 ...................................................................230
3.28.6 Rule SDC-FP-O-06/SDC-MCP-O-06 ....................................................................................................................232
3.28.7 Rule SDC-FP-O-07/SDC-MCP-O-07 ....................................................................................................................234
3.28.8 Rule SDC-FP-O-08/SDC-MCP-O-08 ....................................................................................................................235
3.28.9 Rule SDC-FP-O-09/SDC-MCP-O-09 ....................................................................................................................237
3.28.11 Rule SDC-FP-O-11/SDC-MCP-O-11 ....................................................................................................................239
3.29 SDC Lint rules .........................................................................................................................................................241
3.29.1 Rule SDC-LNTC-01 ..............................................................................................................................................241
3.29.2 Rule SDC-LNTC-02 ..............................................................................................................................................242
3.29.3 Rule SDC-LNTC-03 ..............................................................................................................................................243
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3.29.4 Rule SDC-LNTC-04 ..............................................................................................................................................243
3.29.5 Rule SDC-LNTO-01 .............................................................................................................................................244
3.29.6 Rule SDC-LNTO-02 .............................................................................................................................................245
3.29.7 Rule SDC-LNTO-03 .............................................................................................................................................246
3.29.8 Rule SDC-LNTO-04 .............................................................................................................................................247
3.29.9 Rule SDC-LNTO-05 .............................................................................................................................................249
3.29.10 Rule SDC-LNTO-06 .............................................................................................................................................250
3.29.11 Rule SDC-LNTO-07 .............................................................................................................................................252
3.29.12 Rule SDC-LNTV-01 .............................................................................................................................................253
3.29.13 Rule SDC-LNTV-02 .............................................................................................................................................254
3.29.14 Rule SDC-LNTV-03 .............................................................................................................................................256
3.29.15 Rule SDC-LNTV-04 .............................................................................................................................................257
3.29.16 Rule SDC-LNTR-01..............................................................................................................................................258
3.29.17 Rule SDC-LNTR-02..............................................................................................................................................259
3.29.18 Rule SDC-LNTR-03..............................................................................................................................................261
3.29.19 Rule SDC-LNTR-04..............................................................................................................................................261
3.29.20 Rule SDC-LNTR-05..............................................................................................................................................262
3.29.21 Rule SDC-LNTR-06..............................................................................................................................................263
3.29.22 Rule CLK-SNK001 ...............................................................................................................................................264
3.29.23 Rule CLK-LAT01 ..................................................................................................................................................266
3.29.24 Rule CLK-LAT02 ..................................................................................................................................................267
3.29.25 Rule CLK-LAT03 ..................................................................................................................................................268
3.29.26 Rule CLK-LAT04 ..................................................................................................................................................269
3.29.27 Rule CLK-UNC01 ................................................................................................................................................270
3.29.28 Rule CLK-UNC02 ................................................................................................................................................271
3.29.29 Rule CLK-UNC03 ................................................................................................................................................272
3.29.30 Rule CLK-UNC04 ................................................................................................................................................273
3.29.31 Rule CLK-OVR01 .................................................................................................................................................274
3.29.32 Rule CLK-OVR02 .................................................................................................................................................275
3.29.33 Rule CLK-VRT01 .................................................................................................................................................275
3.29.34 Rule CLK-VRT02 .................................................................................................................................................276
3.29.35 Rule CLK-TRN01 .................................................................................................................................................277
3.29.36 Rule CLK-TRN02 .................................................................................................................................................278
3.29.37 Rule CLK-TRN03 .................................................................................................................................................279
3.29.38 Rule IO-LD-01 .....................................................................................................................................................280
3.29.39 Rule IO-LD-02 .....................................................................................................................................................280
3.29.40 Rule IO-LD-03 .....................................................................................................................................................281
3.29.41 Rule IO-LD-04 .....................................................................................................................................................282
3.29.42 Rule SDC-MD-01 ................................................................................................................................................282
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3.29.43 Rule SDC-ND-01 .................................................................................................................................................283

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2 Preface
2.1 Related Documentation
TimeVision User Guide
TimeVision MultiMode Coverage User Guide
TimeVision Hierarchical User Guide
TimeVision CDC User Guide

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2.2 Documentation Conventions

In the documentation certain conventions are used. These are described below with examples.

Convention Description
tv_shell> A TimeVision prompt.
Tv_shell> current_scenario
$ A UNIX shell prompt.
$ tv_shell -help
Courier The courier font indicates a command, command option or argument that
you would literally enter.
tv_shell> read_verilog top.v
This is a command (read_verilog) and has a command argu-
ment with a value top.v.
<Courier> If the command argument is displayed between angle brackets it indicates a
user defined input for which you must supply a name or value.
tv_shell> read_verilog <input_file>
You must supply a name or value for <input_file> such as
shown below:
tv_shell> read_verilog top.v
[] Square brackets indicate optional arguments.
tv_shell> write_waiver [-quiet] <file_name>
The above [-quiet] argument is optional.
[|] Vertical bars within the square brackets indicate a set of possible choices of
which one must be specified
tv_shell> check_sdc_rule [-rule value | -all]
In the above example, one of -rule, or -all must be specified.
{} Braces must be entered literally.
tv_shell> for_each_in_collection iter [get U1/*] {
<command1> <command2> }
In the above example the braces {} must be placed around the sequence of
commands.
... Indicates that you can repeat the previous argument. If three dots are
used with brackets ( [<argument>]... ), you can specify zero or more
arguments. If the three dots are used without brackets (<argument> ...),
you must specify at least one argument.

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Convention Description
... Indicates that you can repeat the previous argument. If three dots
are used with brackets ( [<argument>]... ), you can specify zero or
more arguments. If the three dots are used without brackets
(<argument> ...), you must specify at least one argument.
. Indicates an omission in an example of output or input.
.
.
\ Indicates a continuation of a command line.

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3 Constraints Verification
3.1 Introduction
A typical SoC design has very complex timing constraints, having from 10’s to 100’s of clocks with
varying relationships. Determining the relationship of each clock pair is an N2 problem and the odds of
getting them all correct is highly unlikely. Adding to this complexity the issue of design respin where
the constraints are reused but functionality has changed, IP coming from multiple sources, and the
entire constraints verification process becomes a very tedious task.

Using Timevision, designers can easily verify constraints whether in tcl or SDC format, at the RTL or gate
level. After loading the design and all timing constraints, the command “check_constraints” is
run to identify and report all missing or incorrect constraints. This command allocates every violation
into one of several categories. Each category has several rules representing a specific type of violation.
The designer is provided with a summary of all rules pass/fail status and the number of violation. If any
rule fails, a complete list of violating objects is reported for that rule. If neccassary, the designer can
then use the Timevision command “debug_rule” for any reported violation to dump the details of
why that object violates the rule. After debug /analysis the designer can either fix the design or
constraints such that the object does not violation anymore. Or, use the “set_waiver” command to
waive any given violating object. In addition to waiving particular objects, any rule can also be
completely turned-off (inactived). Moreover, each rule is assigned a “severity” level: Fatal, Error,
Warning, or Info. The most serious rules typically have a severity type of “Fatal”. Command
“check_constraints” returns a 0 (FAIL) if there are any violations in any rule with a severity
level of “Fatal”. Otherwise, “check_constraints” returns a 1 (PASS). This PASS / FAIL status
represented by a return value of 1 / 0 respectively allows design teams to run
“check_constraints” in automated batch flows before going into signoff STA to makes sure that
there are no timing issues.

Here is the use model and typical work flow for “check_constraints”

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3.2 Setting up the design and running constraint verification:

Loading a design is done like any other design (beginning at “Chapter 3 – Getting Started” of the
Timevision User Guide).
The basic flow is:
1. Load and link the design (RTL or gate/netlist with .lib files)

2. Load constraints, update the timing graph, and infer each clock pair relationship:
a. load the SDC or Tcl timing constraints
b. build_timing
c. infer_clock_relations

3. Source Tcl configuration file with “set_rule” commands

a. Specify the severity of every check_constraints rule: Fatal, Warning, Error, or Info
b. Inactivate any check_constraints rules that are not of interest
This step is optional. If no Tcl configuration file is sourced, Timevision uses a default severity
levels for each rule. And some rules are “inactive” by default also.

4. Source Tcl waivers file with “set_waiver” commands from previous runs. This step is
optional, and only relevant after constraint verification has been run previously, the designer
has analyzed the results, and decided to “waive” violations associated with any rules.

5. Run constraints verification using command : “check_constraints”

Constraints verification flow:

read_libs <libraries>
read_verilog <top>.v

# to Read RTL designs, use the “read_hdl” + “elaborate_design”

# commands, instead of “read_verilog”
read_hdl <top>.vlist
elaborate_design
.libs paths, load design netlist or RTL
current_design <top> link the design
link_design

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## load constraints, update timing graph, and infer clock

relations
read_sdc ${mode}.sdc
build_timing
infer_clock_groups

## configure "check_constraints" rules:

source ./scripts/rule_settings.tcl

## Fatal rules : most serious constraint violations

set_rule -severity Fatal -rule CLK-MIS001 ;
set_rule -severity Fatal -rule CLK-MIS002 ;
…
…

## Warning rules : not most serious, but worth looking/reviewing

set_rule -severity Warning -rule CLK-INC001 ;
set_rule -severity Warning -rule CLK-INC007 ;
…
…

# Inactive rules: do not care about these, never run and report
set_rule -inactive -rule CLK-INC002 ;
set_rule -inactive -rule CLK-OBJ001 ;

Configure the constraints verification runs

Specify “severity” for each rule
Inactive rules that are not of interest
This is optional. If not specified, default settings are used

## Apply “waivers” from previous runs and results analysis:

set_waiver -rule CLK-MIS001 -obj1 clk_sel
…
Apply waivers based on previous runs/ analysis
This is optional. But often required to converge
and pass constraints verification

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## run "check_constraints"
## Reports are generated in <directory> specified by –directory
## check_constraints_flag returns 0 (FAIL) or 1 (PASS):
set rdir tv_cons_reports
set veri_results [check_constraints -directory $rdir_mm -verbose]
Run “check_constraints”, get either a PASS or FAIL
Look at summary and detailed reports in directory
specified by the –directpory flag

3.2.1 Design intentional cells variables

There are rules in Timevision relating to objects where the user, optionally, desires to know if the
violation occurred on an intentional cell/manually instantiated cell or a synthesized cell. Timevison
accommodates this by providing variables which controls the reporting. The variable are:

set design_intentional_cell_names or settings Build/IntentionalCells

set design_intentional_library_cell_names or settings Build/IntentionalLibraryCells

The value for these variables can be an explicit list or a list of regular expressions. The default
behavior is that if the variables are not set then every cell is considered to be intentional.

Rules impacted by the above variables are:

CLK-RCN001 Warning 1 0 Reconvergent clock path

CLK-RCN002 Error 1 0 Reconvergent clock path through synthesized logic
CLK-PCN001 Error 1 0 Phase-reconvergent clock path
CLK-PCN002 Error 1 0 Phase-reconvergent clock path through synthesized logic
CLK-DATA01 Warning 1 0 First gating pin of data network
CLK-DATA02 Error 1 0 First gating pin of data network is synthesized
CLK-MRG01 Info 1 0 Clock merging point
CLK-MRG02 Error 1 0 Clock merging point is synthesized
SDC-FP-O-03 Warning 1 0 Endpoint of set_false_path is a synthesized timing endpoint.
SDC-FP-O-04 Warning 1 0 Thru-point of set_false_path is a synthesized point.
SDC-MCP-O-03 Warning 1 0 Endpoint of set_false_path is a synthesized timing endpoint.
SDC-MCP-O-04 Warning 1 0 Thru-point of set_multicycle_path is a synthesized point.
SDC-MD-O-03 Warning 1 0 Endpoint of set_max_delay is a synthesized timing endpoint.
SDC-MD-O-04 Warning 1 0 Thru-point of set_max_delay is a synthesized point.
SDC-GP-O-03 Warning 1 0 Endpoint of group_path is a synthesized timing endpoint.
SDC-GP-O-04 Warning 1 0 Thru-point of group_path is a synthesized point.

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Below are examples of the variables and how it impacts the rules from the list above.

Example 1:
Set as intentional cells any cell with instance name that matches regular expression {.*or.*}
set design_intentional_cell_names {.*or.*}

Violation Report:
#********************************************************
#* *
#* report_rule *
#* -rule {CLK-DAT* } *
#* -info *
#* *
#* Design : top *
#********************************************************
Category Rule Severity Status Object_1 Object_2
-----------------------------------------------------------
Sdc.Clock CLK-DATA01 Warning FAIL clk2 or2/A2
Sdc.Clock CLK-DATA02 Error FAIL clk1 i5/a1
clk1 i12/a1

Explaination of report:
Note that rule CLK-DATA01 is violated because the “design_intentional_cell_names” variable is set
to “{.*or.*}”, and since cell “or2” violates the rule it is reported in CLK-DATA01, all other violation
where the cell instance name does not match are reported under rule CLK-DATA02. These cells are
considered synthesized.

Example 2:
Set as intentional cells any library cell with ref_name that matches regular expression {MUX2.*}
settings Build/IntentionalLibraryCells {MUX2.*}

Violation Report:
#********************************************************
#* *
#* report_rule *
#* -fail *
#* -rule {CLK-RCN* CLK-PCN* } *
#* *
#* Design : top *
#********************************************************
Category Rule Severity Status Object_1 Object_2
-----------------------------------------------------------
Sdc.Clock CLK-RCN001 Warning FAIL clk1 u_g0c/Z

tv_shell > get_attr [get_cells u_g0c] ref_name

MUX2_X1

Explaination of report:
The rule CLK-RCN001 is violated because cell “u_g0c” is a mux and matches the regular
expression for library cell name, which is confirmed with the ref_name attribute. Note there are
no CLK-RCN002 violations because all violations are on muxes.

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 TimeVision Constraints User Guide
3.2.2 Design intentional clock cells variables

There is a rule in Timevision relatings to clock cell objects where the user, optionally, desires to know
if there are undesirable cells in the clock path. Timevison accommodates this by providing variables
which controls the reporting. The variable are:

set design_intentional_clock_library_cells or settings Build/IntentionalClockLibraryCells

The value for these variables can be an explicit list or a list of regular expressions. The default
behavior is that if the variables are not set then every cell is considered to be intentional.

Rule impacted by the above variables:

CLK-OBJ001 Warning 1 0 clock network gate is not of allowable type.

Below is an example of the variables and how it impacts the rule above.

Example :
Set as intentional clock cells any library cell with ref_name that matches regular expression
{.*MUX.*}

set design_intentional_clock_library_cells {.*MUX.*}

Violation Report:
#********************************************************
#* *
#* report_rule *
#* -rule {CLK-OBJ001 } *
#* -info *
#* *
#* Design : top *
#********************************************************
Category Rule Severity Status Object_1 Object_2 Object_3
----------------------------------------------------------------------
Sdc.Clock CLK-OBJ001 Warning FAIL clk1 i4 GTV_AND2
clk1 i5 GTV_AND2
clk1 i6 GTV_INV
clk1 or_ck_mux OR2_X1

Explaination of report:
Since the only celltype specified as intentional in the clock path is “{.*MUX.*}” all other cells violate
rule CLK-OBJ001 and are considered unintentional.

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 TimeVision Constraints User Guide
3.2.3 Auto-generate waivers

During early constraint development phase constraints like timing exceptions changes regularly making it
difficult to set a waiver and use it in subsequent runs. If the objects in the exception changes the waiver
becomes invalid. If the user so desires to not see these violations in subsequent runs, even if the exceptions
changes then the exception need to be auto-waived. In order to know which rules to generate waivers a run
without auto-waiver must be run first. Once the rules are violated then the user can setup auto-waiver.

Timevision has the ability to auto-generate waiver while reading the constraints. This feature is unique to
Timevision so the syntax to enable auto-waiver is parsed as a comment to other tools. Auto-waiver is
enabled and disabled with the following syntax:

# tv waive_on <rule(s)>
# tv waive_off

Any constraint between “waive_on” and “waive_off” will be auto-waived for the specified rules and message
“WVR-010” is issued in the shell and the logfile.

Example SDC:
# tv waive_on PPFP-001
set_false_path -from [get_pins f4/CK] -to [get_pins f5/D]
set_false_path -to [get_pins f4/D] -from [get_pins f5/CK]
# tv waive_off

Example shell/logfile message:

[WVR-010] Info: Constraint index 5 has inline waivers : PPFP-001.
[WVR-010] Info: Constraint index 6 has inline waivers : PPFP-001.

The waivers can be written toa file and used in subsequent runs when auto-waiver is removed from the
constraints file.

Example write_waiver output:

set_waiver -rule PPFP-001 -obj1 FP.Fxa3b7d4358475b1Tx28253c9ae2ceb
set_waiver -rule PPFP-001 -obj1 FP.Fxa3b7d435801354Tx28253c9ae1d9a

3.3 Timevision Output:

As described in section 2.0 above, command “check_constraints” write out all reports in the
directory specified by the “-directory” flag. The following reports are generated:

Sdc.Readme
Brief description of the reports and sub-directories created by “check_constraints”

Sdc.Qor_Fatal.rpt
This is a summary report of rules with severity level “Fatal” - they are the most serious violations.
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 TimeVision Constraints User Guide
“check_constraints” returns 0 (FAIL) if any of these rules violate. Otherwise 1 (PASS) is
returned

Sdc.Qor_Fails.rpt
This is a summary report of *all* Sdc rules that were run, and fail due to violations

Sdc.Qor_All.rpt
This is a summary report of *all* rules whether active, inactive, both PASS and FAIL

Sdc.Clock/ Sdc.Coverage/ Sdc.Exception/ Sdc.Interclock/ Sdc.IO/ Sdc.Mode/

<rule1.rpt> <rule1.rpt> <rule1.rpt> <rule1.rpt> <rule1.rpt> <rule1.rpt>
<rule2.rpt> <rule2.rpt> <rule2.rpt> <rule2.rpt> <rule2.rpt> <rule2.rpt>
… … … … … …
… … … … … …
<ruleN.rpt> <ruleN.rpt> <ruleN.rpt> <ruleN.rpt> <ruleN.rpt> <ruleN.rpt>

These directories have a report corresponding to each rule. The user first looks at the summary in one
of the “Qor” tables above, and can go to the detailed report for any rule in that table to see the list of
all violating objects associated with that rule.

Sample QoR report (Sdc.Qor_Fatal.rpt):

Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MIS001 Fatal PASS 0 Sdc.Clock/CLK-MIS001.rpt Missing potential primary clock source
CLK-MIS002 Fatal 1 0 Sdc.Clock/CLK-MIS002.rpt Certain Missing generated clock source
CLK-INC005 Fatal PASS 0 Sdc.Clock/CLK-INC005.rpt Generated clock with no master clock (dead clock)
CLK-INC006 Fatal 1 0 Sdc.Clock/CLK-INC006.rpt Generated clock with ambiguous master clocks of different periods
CLK-INC019 Fatal PASS 0 Sdc.Clock/CLK-INC019.rpt source point of a generated clock is a constant
CLK-BLK001 Fatal 1 0 Sdc.Clock/CLK-BLK001.rpt create_clock blocks clock propagation

Sample report for a rule ( Sdc.IO/IOC-INC001.rpt ):

# Rule: IOC-INC001
# Severity: Fatal
# ==============================
#
# Design : mSoc
# Date : Mon Jul 07 11:01:35 PM PDT 2014
#
# IOC-INC001
# Incorrect & Effectively Unconstrained Input Data port
#

A# Port Current Clock

----------------------------------
A0 dsp_pb_i[15] phyRefClk
----------------------------------

Waived Failures:
W# Port Current Clock
----------------------------------
W0 dsp_pb_i[14] phyRefClk
----------------------------------

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Applicable Waivers:
# Waiver W0
set_waiver -rule IOC-INC001 -obj1 dsp_pb_i[14] -obj2 phyRefClk -author "hollis" -date "07/07/14" -reason "None"

3.3.1 List of All Rules

TV command “list_rules -rule Sdc.*” provides a complete list of constraint rules:

Category Rule Sev. Active User Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MIS001 Fatal 1 0 Missing potential primary clock source
CLK-MIS002 Fatal 1 0 Certain Missing generated clock source
CLK-MIS003 Warning 1 0 Possibly missing primary clock source
CLK-MIS004 Warning 1 0 Possibly missing generated clock source
CLK-INC001 Error 1 0 create_clock defined on output port
CLK-INC002 Warning 1 0 create_clock defined on combinational cell pin
CLK-INC003 Warning 1 0 create_clock/generated_clock defined on multiple points
CLK-INC004 Error 1 0 create_generated_clock defined on input ports with no master
CLK-INC005 Fatal 1 0 Generated clock with no master clock (dead clock)
CLK-INC006 Fatal 1 0 Generated clock with ambiguous master clocks of different periods
CLK-INC007 Warning 1 0 Generated clock with ambiguous master clocks of identical periods
CLK-INC008 Fatal 1 0 -master_clock not present at -source object (no path from -master_clock, no path from -source)
CLK-INC009 Error 1 0 -master_clock not present at -source object (no path from -master_clock, path from -source)
CLK-INC010 Error 1 0 -master_clock not present at -source object (path from -master_clock, no path from -source)
CLK-INC011 Error 1 0 -master_clock not present at -source object (path from -master_clock, path from -source)
CLK-INC012 Fatal 1 0 create_generated_clock has no logic path from -source object (path exist from other clock sources)
CLK-INC013 Fatal 1 0 create_generated_clock has no logic path from -source object (path do not exist from other clock sources)
CLK-INC014 Warning 1 0 Intermediate clock is defined between a generated clock and its master source clock
CLK-INC015 Warning 1 0 Downstream generated clocks with a single source
CLK-INC016 Warning 1 0 Downstream generated clocks with multiple sources
CLK-INC017 Error 1 0 create_generated_clock unateness incompatible w.r.t. its master clock
CLK-INC018 Error 1 0 application point of clock is a constant
CLK-INC019 Fatal 1 0 source point of a generated clock is a constant
CLK-INC020 Warning 1 0 clock propagation overlaps with user-applied case analysis
CLK-INC021 Error 1 0 generated_clock lists -source and application point at same location.
CLK-WAV001 Error 1 0 div-1 or combinational clock on a sequential Q pin
CLK-WAV002 Error 1 0 div-1 or combinational clock on a combinational gate when no clock reaches pin
CLK-WAV003 Error 1 0 div-N clock on combinational gate when master clock reaches the application point directly.
CLK-WAV004 Error 1 0 div-N clock, N>2, on ICG when downstream contains both negative & positive elements.
CLK-IGC001 Error 1 0 Incomplete generated clock w.r.t. fastest incident clock
CLK-IGC002 Warning 1 0 Incomplete generated clock w.r.t. non-critical incident clock
CLK-RCN001 Warning 1 0 Reconvergent clock path
CLK-RCN002 Error 1 0 Reconvergent clock path through synthesized logic
CLK-PCN001 Error 1 0 Phase-reconvergent clock path
CLK-PCN002 Error 1 0 Phase-reconvergent clock path through synthesized logic
CLK-BLK001 Fatal 1 0 create_clock blocks clock propagation
CLK-BLK002 Warning 1 0 create_generated_clock blocks clock propagation
CLK-DATA01 Warning 1 0 First gating pin of data network
CLK-DATA02 Error 1 0 First gating pin of data network is synthesized
CLK-DATA03 Warning 1 0 Clock drives data pins
CLK-MRG01 Info 1 0 Clock merging point
CLK-MRG02 Error 1 0 Clock merging point is synthesized
CLK-OBJ001 Warning 0 0 clock network gate is not of allowable type.
CLK-OBJ002 Error 0 0 Clock is defined on hierarchical (logical) pin.
Sdc.Interclock ICFP-INC001 Fatal 1 0 Incorrect interclock false path, synchronous
ICFP-INC002 Fatal 1 0 Incorrect interclock false path, synchronous logically-exclusive, unique<->common
ICFP-INC003 Fatal 1 0 Incorrect interclock false path, synchronous logically-exclusive, unique<->unique
ICFP-INC004 Fatal 1 0 Incorrect interclock false path, synchronous logically-exclusive, unique<->unique/common
ICFP-INC005 Fatal 1 0 Incorrect interclock false path, synchronous LE inheritance
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ICFP-INC006 Fatal 1 0 Incorrect interclock false path, synchronous partial-LE inheritance
ICFP-INC007 Fatal 1 0 Incorrect interclock false path, source-synchronous
ICFP-INC008 Fatal 1 0 Incorrect interclock false path, asynchronous -allow_paths clock group
ICFP-INC009 Fatal 1 0 Incorrect same-clock false path
ICFP-MIS001 Warning 1 0 Missing interclock false path, physically exclusive
ICFP-MIS002 Warning 1 0 Missing interclock false path, logically exclusive
ICFP-MIS003 Warning 1 0 Missing interclock false path, asynchronous non-harmonic
ICFP-MIS004 Warning 1 0 Missing interclock false path, asynchronous harmonic
ICFP-MIS005 Warning 1 0 Missing interclock false path, asynchronous same-period
ICFP-MIS006 Warning 1 0 Missing interclock false path, physically exclusive:inherit
ICFP-MIS007 Warning 1 0 Missing interclock false path, physically exclusive:branch
ICFP-IRR001 Warning 0 0 Irrelevant interclock false path, no clock-to-clock path
CGWP-INC001 Fatal 1 0 Incorrect set_clock_groups , sync. clocks
CGWP-INC002 Fatal 1 0 Incorrect set_clock_groups , sync. + le clocks (paths from/to common domain)
CGWP-INC003 Fatal 1 0 Incorrect set_clock_groups , sync. + le clocks (paths in cross domain)
CGWP-INC004 Fatal 1 0 Incorrect set_clock_groups , sync. + le clocks (paths in from/to common + cross domain)
CGWP-INC005 Fatal 1 0 Incorrect set_clock_groups , sync. + le through inheritance clocks
CGWP-INC006 Fatal 1 0 Incorrect set_clock_groups , sync. + le through partial inheritance clocks
CGWP-INC007 Fatal 1 0 Incorrect set_clock_groups , source sync clocks
CGWP-INC008 Fatal 1 0 Incorrect set_clock_groups , when user defined allow_path is specified
CGWP-INC009 Fatal 1 0 Incorrect set_clock_groups , between same clocks
CGWP-INC010 Error 1 0 Incorrect set_clock_groups , SDC has incorrect set_clock_group -asynchronous -allow_paths
CGWP-INC011 Error 1 0 Type Incorrect set_clock_groups (Crosstalk / SI impact only) between clocks with timing paths
CGWP-MIS001 Fatal 1 0 Missing physically-exclusive set_clock_group between clocks
CGWP-MIS002 Fatal 1 0 Missing logically-exclusive set_clock_group between clocks
CGWP-MIS003 Fatal 1 0 Missing asynchronous (non-harmonic) set_clock_group between clocks
CGWP-MIS004 Warning 1 0 Missing asynchronous (harmonic) set_clock_group between clocks
CGWP-MIS005 Warning 1 0 Missing asynchronous (same-period) set_clock_group between clocks
CGWP-MIS006 Fatal 1 0 Missing physically-exclusive(inherit) set_clock_group between clocks
CGWP-MIS007 Fatal 1 0 Missing physically-exclusive(branch) set_clock_group between clocks
CGNP-INC001 Warning 0 0 Incorrect set_clock_groups between clocks with NO timing paths
CGNP-MIS001 Warning 0 0 Missing set_clock_groups between clocks with NO timing paths
CGIN-INF001 Info 0 0 User-Inferred synchronous group between primary clocks, non-harmonic
CGIN-INF002 Warning 0 0 User-Inferred synchronous group between primary/generated clocks, overriding asynchronous
CGIN-INF003 Error 0 0 User-Inferred asynchronous group between primary/generated clocks, overriding synchronous
Sdc.Mode MODE-CNF-01 Error 1 0 Conflicting propagated case values
MODE-CNF-02 Error 1 0 Conflicting set_case_analysis
MODE-OVL-01 Warning 1 0 Overlapping propagated/set case values
MODE-TBL-01 Fatal 1 0 No Case setting applied to pin involved with multiple clock selection.
MODE-TBL-02 Info 1 0 No Case setting applied to pin involved with single clock selection.
Sdc.Coverage UNC-001 Fatal 1 0 Floating or Undriven register clock pins
UNC-002 Fatal 1 0 Un-Clocked register clock pins
UNC-003 Fatal 1 0 set_case_analysis or propagated-constant register clock pins
UNC-004 Error 1 0 Un-Clocked Macro Clock pin
UNC-005 Warning 1 0 constant register clock pins due to tie-offs
Sdc.Netlist LOOP-01 Warning 1 0 Datapath loop not broken by SDC
LOOP-02 Warning 1 0 Clock loop not broken by SDC
Sdc.Formal FV-FP-001 Error 0 0 False path fails proof
FV-FP-002 Error 0 0 False path timed out or errored
FV-MCP-001 Error 0 0 Multicycle path fails proof
FV-MCP-002 Error 0 0 Multicycle path timed or errored out
Sdc.IO IOC-INC001 Fatal 1 0 Incorrect & Effectively Unconstrained Input Data port
IOC-INC002 Warning 1 0 Incorrectly Constrained (Non-Harmonic) Input Data port
IOC-INC003 Warning 1 0 Incorrectly Constrained (Harmonic) Input Data port
IOC-INC004 Fatal 1 0 Incorrect & Effectively Unconstrained Output Data port
IOC-INC005 Warning 1 0 Incorrectly Constrained (Non-Harmonic) Output Data port
IOC-INC006 Warning 1 0 Incorrectly Constrained (Harmonic) Output Data port
IOC-MIS001 Warning 1 0 Unconstrained Input Data port
IOC-MIS002 Warning 1 0 Unconstrained Output Data port
IOC-UND001 Warning 1 0 UnderConstrained Input Data port
IOC-UND002 Warning 1 0 UnderConstrained Output Data port
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IOC-SSI001 Warning 1 0 Source-Sync Output Data port not constrained to source-sync clock
IOC-FTP001 Warning 1 0 Unconstrained feedthrough pair.
IOC-FTP002 Warning 1 0 IO constraint conflict on feedthrough pair - input/output delay & max delays
IOC-FTP003 Warning 1 0 Feedthrough pair constrained with non-harmonic clocks.
IOC-FTP004 Warning 1 0 Feedthrough pair effectively unconstrained.
IOC-FTP005 Warning 1 0 Feedthrough pair with inconsistent min/max delay.
IOC-FTP006 Warning 1 0 Feedthrough pair with inconsistent input/output delay.
Sdc.Exception PPFP-001 Warning 1 0 pnt-to-pnt set_false_path between sync_same_period clocks
PPFP-002 Warning 1 0 pnt-to-pnt set_false_path between sync_slow_to_fast_integral clocks
PPFP-003 Warning 1 0 pnt-to-pnt set_false_path between sync_slow_to_fast_nonintegral clocks
PPFP-004 Warning 1 0 pnt-to-pnt set_false_path between sync_fast_to_slow_integral clocks
PPFP-005 Warning 1 0 pnt-to-pnt set_false_path between sync_fast_to_slow_nonintegral clocks
PPFP-006 Warning 1 0 pnt-to-pnt set_false_path between source_sync clocks
SDC-FP-01 Error 1 0 Clock-Clock False path -setup not covered by -hold
SDC-FP-02 Error 1 0 Clock-Clock False path -hold not covered by -setup
SDC-FP-03 Error 1 0 Pt-to-Pt False path -setup not covered by -hold
SDC-FP-04 Error 1 0 Pt-to-Pt False path -hold not covered by -setup
SDC-FP-05 Warning 1 0 False path covers no paths
SDC-MCP-01 Error 1 0 Clock-Clock Multicycle path -setup not covered by -hold
SDC-MCP-02 Error 1 0 Clock-Clock Multicycle path -hold not covered by -setup
SDC-MCP-03 Error 1 0 Pt-to-Pt Multicycle path -setup not covered by -hold
SDC-MCP-04 Error 1 0 Pt-to-Pt Multicycle path -hold not covered by -setup
SDC-MCP-05 Error 1 0 Multicycle path covers multiple clocks without -start or -end specified
SDC-MCP-06 Warning 1 0 Multicycle path covers no paths
SDC-MCP-07 Warning 0 0 Multicycle path hold edge not aligned with launch
SDC-MCP-08 Warning 0 0 Multicycle path reference edge
SDC-FP-O-01 Warning 1 0 Startpoint of set_false_path is not a timing startpoint
SDC-FP-O-02 Warning 1 0 Endpoint of set_false_path is not a timing endpoint.
SDC-FP-O-03 Warning 1 0 Endpoint of set_false_path is a synthesized timing endpoint.
SDC-FP-O-04 Warning 1 0 Thru-point of set_false_path is a synthesized point.
SDC-FP-O-05 Warning 1 0 Thru-point of set_false_path is a hierarchical pin.
SDC-FP-O-06 Warning 1 0 Startpoint of set_false_path covers no paths.
SDC-FP-O-07 Warning 1 0 Endpoint of set_false_path covers no paths.
SDC-FP-O-08 Error 1 0 More than 25% of startpoints in set_false_path cover no paths
SDC-FP-O-09 Error 1 0 More than 25% of endpoints in set_false_path cover no paths
SDC-FP-O-10 Info 0 0 Redundant set_false_path.
SDC-FP-O-11 Error 1 0 set_false_path -through sequential element.
SDC-MCP-O-01 Warning 1 0 Startpoint of set_multicycle_path is not a timing startpoint
SDC-MCP-O-02 Warning 1 0 Endpoint of set_multicycle_path is not a timing endpoint.
SDC-MCP-O-03 Warning 1 0 Endpoint of set_false_path is a synthesized timing endpoint.
SDC-MCP-O-04 Warning 1 0 Thru-point of set_multicycle_path is a synthesized point.
SDC-MCP-O-05 Warning 1 0 Thru-point of set_multicycle_path is a hierarchical pin.
SDC-MCP-O-06 Info 1 0 Startpoint of set_multicycle_path covers no paths.
SDC-MCP-O-07 Info 1 0 Endpoint of set_multicycle_path covers no paths.
SDC-MCP-O-08 Error 1 0 Greater than 25% of startpoints in set_multicycle_path cover no paths
SDC-MCP-O-09 Info 1 0 Greater than 25% of endpoints of set_multicycle_path cover no paths
SDC-MCP-O-10 Info 0 0 Redundant set_multicycle_path.
SDC-MCP-O-11 Error 1 0 set_multicycle_path -through sequential element.
SDC-MD-O-01 Warning 1 0 Startpoint of set_max_delay is not a timing startpoint
SDC-MD-O-02 Warning 1 0 Endpoint of set_max_delay is not a timing endpoint.
SDC-MD-O-03 Warning 1 0 Endpoint of set_max_delay is a synthesized timing endpoint.
SDC-MD-O-04 Warning 1 0 Thru-point of set_max_delay is a synthesized point.
SDC-MD-O-05 Warning 1 0 Thru-point of set_max_delay is a hierarchical pin.
SDC-GP-O-01 Warning 1 0 Startpoint of group_path is not a timing startpoint
SDC-GP-O-02 Warning 1 0 Endpoint of group_path is not a timing endpoint.
SDC-GP-O-03 Warning 1 0 Endpoint of group_path is a synthesized timing endpoint.
SDC-GP-O-04 Warning 1 0 Thru-point of group_path is a synthesized point.
SDC-GP-O-05 Warning 1 0 Thru-point of group_path is a hierarchical pin.
SDC-CG-O-01 Error 1 0 Clock group is extremely broad.
SDC-CG-O-02 Error 1 0 Clock group is broad.

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Sdc.Lint SDC-LNTC-01 Warning 1 0 Unknown command in SDC
SDC-LNTC-02 Warning 1 0 User-disallowed command in SDC
SDC-LNTC-03 Warning 1 0 TCL error in SDC command parsing
SDC-LNTC-04 Warning 1 0 Ambiguous command in SDC
SDC-LNTO-01 Error 1 0 Unknown option to command
SDC-LNTO-02 Error 1 0 User-disallowed option to command
SDC-LNTO-03 Error 1 0 Missing required option
SDC-LNTO-04 Error 1 0 Overlapping mutially-exclusive options
SDC-LNTO-05 Warning 1 0 Multiple usage of same option
SDC-LNTO-06 Error 1 0 Option requires another option when used
SDC-LNTO-07 Error 1 0 Ambiguous option used
SDC-LNTV-01 Error 1 0 Missing required value
SDC-LNTV-02 Error 1 0 Invalid value provided.
SDC-LNTV-03 Error 1 0 Value out of range.
SDC-LNTV-04 Error 1 0 Value list empty or incorrect value count.
SDC-LNTR-04 Error 1 0 Incorrect object value type
SDC-LNTR-05 Error 1 0 Empty collection argument
SDC-LNTR-06 Error 1 0 Incorrect number of objects
CLK-SNK001 Warning 1 0 Clock has no sink
CLK-LAT01 Warning 1 0 port/pin with latency for clock that is not part of clock tree
CLK-LAT02 Warning 1 0 source latency for generated clock less than master clock source latency
CLK-LAT03 Warning 1 0 inconsistent latency specified (min > max | early > late)
CLK-LAT04 Warning 1 0 negative latency value
CLK-UNC01 Warning 1 0 uncertainty set for object not a clock
CLK-UNC02 Warning 1 0 uncertainty greater than available clock time
CLK-UNC03 Warning 1 0 incomplete uncertainty specified
CLK-UNC04 Warning 1 0 negative uncertainty value
CLK-OVR01 Warning 1 0 clock is overridden by another clock with same name
CLK-OVR02 Warning 1 0 clock is overriden because another clock defined at same point without -add
CLK-VRT01 Warning 1 0 virtual mapped clock does not have same period as real
CLK-VRT02 Warning 1 0 virtual clock has no corresponding real clock
CLK-TRN01 Warning 1 0 inconsistent set_clock_transition options (min > max)
CLK-TRN02 Warning 1 0 incomplete set_clock_transition values (-rise without -fall or -min without -max)
CLK-TRN03 Warning 1 0 negative set_clock_transtiion
CLK-TRN04 Warning 1 0 set_clock_transition outside characterized range for receiver(s)
CLK-TRN05 Warning 1 0 set_annotated_transition outside characterized range of receiver in clock tree
IO-DRV-01 Warning 0 0 input/inout port has no input_transition or set_driving_cell or set_drive and is not false path
IO-DRV-02 Warning 0 0 incomplete input_transition options
IO-DRV-03 Warning 0 0 inconsistent input transition (max < min)
IO-DRV-04 Warning 0 0 input transition outside characterization range of receiver
IO-DRV-05 Warning 0 0 input transition inconsistent with related clock_transition
IO-IDL-01 Warning 0 0 incomplete input delay options for input/inout port
IO-IDL-02 Warning 0 0 inconsistent input delays (max < min)
IO-IDL-03 Warning 0 0 input delay removed due to overriding input delay without -add
IO-IDL-04 Warning 0 0 set_input_delay on clock port
IO-ODL-01 Warning 0 0 incomplete input delay options for output/inout port
IO-ODL-02 Warning 0 0 inconsistent output delays (max < min)
IO-ODL-03 Warning 0 0 output delay removed due to overriding input delay without -add
IO-ODL-04 Warning 0 0 set_output_delay on port reached by clock
IO-LD-01 Warning 0 0 undefined set_load on constrained output without set_dont_touch/network specified
IO-LD-02 Warning 0 0 incomplete load options (no -min with -max for example)
IO-LD-03 Warning 0 0 inconsistent load values (min>max)
IO-LD-04 Warning 0 0 load outside char range for driver
SDC-MD-01 Warning 0 0 incomplete set_max_delay
SDC-ND-01 Warning 0 0 incomplete set_min_delay

Notice in the above table, each rule has a “severity” level assigned to it. The severity level for any rule
can be changed using the “set_rule -severity” command as described in Section 2.0 above.

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 TimeVision Constraints User Guide
Also, all rules are “active” by default. Any rule can be made inactive by using the command
“set_rule –inactive” as described in Section 2.0 above
Below is a detailed description for each constraints rule.
3.4 Missing clocks rules

3.4.1 Rule CLK-MIS001

- Missing potential primary clock source

Description:
This rule identifies all ports and macro pins in the designs which should have a “create_clock”
defined on them, but no such “create_clock” definition exists in the current constraints. In order
to reduce noise, Timevision assigns a “score” to all reported ports and macro pins. A score of 100
means that Timevision is 100% sure the object being reported should be a “create_clock” source, and a
score less than 100 means it may be a “create_clock” source.

Design in figure 3.4.1 below shows missing clocks reported under rule CLK-MIS001

Figure 3.4.1

_
D Q

clk1 B1 Q
Missing create_clock

Missing create_clock _
D Q
clk2 FF1
Q
clk3

Missing create_clock

In the above design, ports “clk1”, “clk2”, and “clk3” do not have a “create_clock” defined on them
the register clock pins are not getting a clock.

Therefore, “check_constraints” will report these three ports under rule CLK-INC001.

Reports:

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 TimeVision Constraints User Guide
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MIS001 Fatal 3 0 Sdc.Clock/CLK-MIS001.rpt Missing potential primary clock source

Sdc.Clock/CLK-MIS001.rpt :
# Rule: CLK-MIS001
# Severity: Fatal
# ==============================
#
# Design : mSoc
# CLK-MIS001
# Missing potential primary clock source
#
A# Certain Missing Primary Clock Source
-------------------------------------------------
A0 clk1
A1 clk2
A2 clk3
-------------------------------------------------

Debug
Source the scripts from the scriptWare directory in Timevision install directory then the following command can be
executed.

tv_shell> justify_missing_clock -s [get_ports clk1]

#********************************************************
#* *
#* justify_missing_clock -s { clk1 } *
#* Design : top *
#* *
#********************************************************
#############################################################################################
## Missing Clock source: { clk1 }
#############################################################################################

## Path: Missing clock source --> leaf clock pin :*un-clocked*:

#********************************************************
#* *
#* trace_path *
#* -hier *
#* -to {"ff0/CK"} *
#* -source *
#* -nets *
#* -from { clk1 } *
#* Design : top *
#* *
#********************************************************

Point Type Flags File Line

---------------------------------------------------------------------------------
(Unconstrained Startpoint)
clk1 (port)
clk1 (net)
ff0/CK DFF_X1 verilog/check_cons_CLK-MIS.v 20

Waivers
Any reported violation can be waived using the “set_waiver” command.

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 TimeVision Constraints User Guide
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver –rule CLK-MIS001 –id A2 -reason “will select clk3”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-MIS001 -obj1 clk2 -author "hollis" -date "07/10/14" -reason "will select clk3"

3.4.2 Rule CLK-MIS002

- Missing potential generated clock source

Description:
This rule identifies all pins in the designs which should have a “create_generated_clock”
defined on them, but no such “create_generated_clock” definition exists in the current
constraints. In order to reduce noise, Timevision assigns a “score” to each reported pin. A score of 100
means that Timevision is 100% sure the object reported should be a
“create_generated_clock” source, and a score less than 100 means it may be a
“create_generated_clock” source.

Figure 3.4.2

_ _
D Q D Q
create_clock -name CLK3 FF1 FF3
Q Q
CLK3

Missing create_generated_clock

AOUT

In the above design, a “create_clock” is defined on port “clk3”. The “Q” pin of “FF1” drives the clock
pin of “FF3”, which would require a generated clock to be defined on pin “FF1/Q”. Also, the port “clk3”
dirves output port “AOUT” through a buffer, requiring a generated clock to be defined on output port
“AOUT”.

Therefore, “check_constraints” will report these violations under rule CLK-MIS002.

Reports:

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 TimeVision Constraints User Guide
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
----
Sdc.Clock CLK-MIS002 Fatal 2 0 Sdc.Clock/CLK-MIS002.rpt Certain Missing generated clock source

Sdc.Clock/CLK-MIS002.rpt :
# Rule: CLK-MIS002
# Severity: Fatal
# ==============================
#
# Design : mSoc
# CLK-MIS002
# Certain Missing generated clock source
#
A# Certain Missing Generated Clock Source
---------------------------------------------
A0 FF1/Q
A1 AOUT
---------------------------------------------

Debug
Source the scripts from the scriptWare directory in Timevision install directory then the following command can be
executed.

tv_shell> justify_missing_clock -s [get_pins FF1/Q]

#********************************************************
#* *
#* justify_missing_clock -s { FF1/Q } *
#* Design : top *
#* *
#********************************************************

#############################################################################################
## Missing Clock source: { FF1/Q }
#############################################################################################

## Path: Missing clock source --> leaf clock pin :*un-clocked*:

#********************************************************
#* *
#* trace_path *
#* -hier *
#* -to {"FF3/CK"} *
#* -source *
#* -nets *
#* -from { FF1/Q } *
#* Design : top *
#* *
#********************************************************

Point Type Flags File Line

---------------------------------------------------------------------------------
FF1/Q DFF_X1 verilog/check_cons_CLK-MIS.v 27
gclk1 (net)
FF3/CK DFF_X1 verilog/check_cons_CLK-MIS.v 28

## Path: master clock ( clk3 ) --> missing clock source

#********************************************************
#* *
#* trace_path *
#* -hier *
#* -to {"FF1/CK"} *

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 TimeVision Constraints User Guide
#* -source *
#* -nets *
#* -from { clk3 } *
#* Design : top *
#* *
#********************************************************

Point Type Flags File Line

---------------------------------------------------------------------------------
(Unconstrained Startpoint)
clk3 (port) cs
clk3 (net) ~
FF1/CK DFF_X1 ~ verilog/check_cons_CLK-MIS.v 27

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-MIS002 –id A1
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-MIS002 -obj1 AOUT -author "hollis" -date "07/10/14" -reason "None"

3.4.3 Rule CLK-MIS003

- Missing potential primary clock source with score less than 100

Description:
This rule identifies all ports and macro pins in the designs which should have a “create_clock” defined
on them, but no such “create_clock” definition exists in the current constraints. These primary clock
sources have a score less than 100% because the logic path is ambiguous, however, they still reach leaf
clock pins.
Figure 3.4.3

Possible missing create_clock

_
CLK2 D Q
G0 FF2
SEL
Q
Possible missing create_clock

In the above design, ports “CLK2” and “SEL” goes through an AND gate to the clock pin of a flop, and is
reported as potentially missing primary clocks. The AND gates adds some ambiguity in determining for
certain if these are clock sources forcing, Timevision to reduce the score of the missing clocks.

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 TimeVision Constraints User Guide
Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MIS003 Warning 2 0 Sdc.Clock/CLK-MIS003.rpt Possibly missing primary clock source

Sdc.Clock/CLK-MIS003.rpt :
# Rule: CLK-MIS003
# Severity: Warning
# ==============================
#
# Design : top
# CLK-MIS003
# Possibly missing primary clock source
#
---------------------------------------------
A0 CLK2
A1 SEL
---------------------------------------------

Debug
Source the scripts from the scriptWare directory in Timevision install directory then the following command can be
executed.
tv_shell> justify_missing_clock -s [get_ports SEL]
#********************************************************
#* *
#* justify_missing_clock -s { SEL } *
#* *
#* Design : top *
#* *
#********************************************************
#############################################################################################
## Missing Clock source: { SEL }
#############################################################################################

## Path: Missing clock source --> leaf clock pin :*un-clocked*:

#********************************************************
#* *
#* trace_path *
#* -hier *
#* -to {"FF2/CK"} *
#* -source *
#* -nets *
#* -from { SEL } *
#* Design : top *
#* *
#********************************************************

Point Type Flags File Line

---------------------------------------------------------------------------------
(Unconstrained Startpoint)
SEL (port)
SEL (net)
g0/A2 AND2_X1
g0/ZN AND2_X1 verilog/check_cons_CLK-MIS.v 35
clk2gate (net)
FF2/CK DFF_X1 verilog/check_cons_CLK-MIS.v 42

Waivers
Any reported violation can be waived using the “set_waiver” command.
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 TimeVision Constraints User Guide

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-MIS003 –id A1 –reason “not a clock”
write_waiver top.waivers.tcl
top.waivers.tcl
set_waiver -rule CLK-MIS003 -obj1 SEL -author "hollis" -date "07/10/14" -reason "not a clock"

3.4.4 Rule CLK-MIS004

- Possibly missing generated clock source with score less than 100

Description:
This rule identifies all pins in the designs which should have a “create_generated_clock”
defined on them, but no such “create_generated_clock” definition exists in the current
constraints. These generated clock sources have a score less than 100% because the logic path is
ambiguous, however, they still reach leaf clock pins and can be traced to a master clock.

Figure 3.4.4

Possibly missing
create_clock -name CLK2
create_generated_clock
_
D
_
CLK2 D Q Q
G0 FF2 FF4
SEL
Q Q
G1

In the above design, FF2/Q is a potential missing generated clock because the is a path to a clock pin
through AND gate G1, and a path to a master clock through AND gate G0. The AND gates adds some
ambiguity in determining for certain if FF2/Q is a generated clock source, forcing Timevision to reduce
the score of the potentially missing generated clock.

Therefore, “check_constraints” will report this pin under rule CLK-MIS004

Reports:

MM.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MIS004 Warning 1 0 Sdc.Clock/CLK-MIS004.rpt Possibly missing generated clock source
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Sdc.Clock/CLK-MIS004.rpt :
# Rule: CLK-MIS004
# Severity: Warning
# ==============================
#
# Design : top
# CLK-MIS004
# Possibly missing generated clock source
#
---------------------------------------------
A0 FF2/Q
---------------------------------------------

Debug
Source the scripts from the scriptWare directory in Timevision install directory then the following command can be
executed.

tv_shell> justify_missing_clock -s [get_pins FF2/Q]

#********************************************************
#* *
#* justify_missing_clock -s { FF2/Q } *
#* *
#* Design : top *
#* *
#********************************************************

############################################################################################
## Missing Clock source: { FF2/Q }
############################################################################################

## Path: Missing clock source --> leaf clock pin :*un-clocked*:

#********************************************************
#* *
#* trace_path *
#* -hier *
#* -to {"ff4/CK"} *
#* -source *
#* -nets *
#* -from { ff2/Q } *
#* Design : top *
#* *
#********************************************************

Point Type Flags File Line

---------------------------------------------------------------------------------
FF2/Q DFF_X1 verilog/check_cons_CLK-MIS.v 42
gclk2 (net)
g1/A1 AND2_X1
g1/ZN AND2_X1 verilog/check_cons_CLK-MIS.v 43
gclk2gate (net)
FF4/CK DFF_X1 verilog/check_cons_CLK-MIS.v 44

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

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 TimeVision Constraints User Guide
After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-MIS004 –id A0
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-MIS004 -obj1 FF2/Q -author "hollis" -date "07/10/14" -reason "None"

3.5 Incorrect clock rules

3.5.1 Rule CLK-INC001

- create_clock defined on output port

Description:
This rule identifies all “create_clock” defined on output ports. Often times, clocks go out of the
block or chip and a clock definition is required at output ports. However, these should be defined as
“create_generated_clock” with some master source, and not a “create_clock”.

Design in figure 3.5.1 below shows timing points reported under rule CLK-INC001

Figure 5.1.1

IN1 BUF1 OUT1

create_clock -name CLK_OUT1 [get_ports OUT1]

_
D Q
FF1
clk2 Q OUT2

create_clock -name CLK_OUT2 [get_ports OUT2]

In the above designs, output ports OUT1 and OUT2 incorrectly have create_clocks defined on them.
Therefore, “check_constraints” will report these ports under rule CLK-INC001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC001 Error 2 0 Sdc.Clock/CLK-INC001.rpt create_clock defined on output port

Sdc.Clock/CLK-INC001.rpt :
# Rule: CLK-INC001
# Severity: Error
# ==============================
#
# Design : top
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 TimeVision Constraints User Guide
# CLK-INC001
# create_clock defined on output port
#
A# Port Clock Clock ID Blocked Clocks
-----------------------------------------------------------------
A0 OUT1 CLK_OUT1 1 { }
A1 OUT2 CLK_OUT2 0 { }
-----------------------------------------------------------------

Debug
Get the “source” attribute of the clock and then confirm it is an output port.
tv_shell> get_attribute [get_clocks CLK_OUT1] source
{"OUT1"}

tv_shell> get_attribute [get_ports OUT1] direction

out

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-INC001 -obj1 CLK_OUT1 -obj2 OUT1 -author "hollis" -date "07/10/14" -reason "None"

3.5.2 Rule CLK-INC002

- create_clock defined on combinational cell pin

Description:
This rule identifies all “create_clock” defined at combinational cell pins (for example buffer or mux
pins). Often times clocks needs to be defined at combination cell pins for a variety of reasons – such as
CTS balancing or STA analysis. However, these should be defined as “create_generated_clock”
with some master source, and not a “create_clock”.

Design in figure 3.5.2 below shows timing points reported under rule CLK-INC002.

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 TimeVision Constraints User Guide Figure 3.5.2

clk1

M1

clk2
create_clock -name MCLK [get_pins M1/Z]

In the above design, the create_clock defined on the output of the mux is reported as a warning.
Therefore, “check_constraints” will report this pin under rule CLK-INC002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC002 Warning 1 0 Sdc.Clock/CLK-INC002.rpt create_clock defined on combinational cell pin

Sdc.Clock/CLK-INC002.rpt :

# Rule: CLK-INC002
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC002
# create_clock defined on combinational cell pin
#
A# Pin Clock Clock ID Blocked Clocks
---------------------------------------------
A0 M1/Z MCLK 0 { }
---------------------------------------------

Debug
Use the source of the clock and then confirm cell type.

tv_shell> get_attribute [get_cells M1] ref_name

CKMUX2D0

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC002 –id A0 –reason “Ok for now”
write_waiver top.waivers.tcl

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 TimeVision Constraints User Guide
top.waivers.tcl
set set_waiver -rule CLK-INC002 -obj1 M1/Z -obj2 MCLK -author "hollis" -date "07/10/14" -reason "Ok for now"

3.5.3 Rule CLK-INC003

- create_clock/generated_clock defined on multiple points

Description:
This rule identifies identical “create_clock” defined at multiple pins or ports.

Design in figure 3.5.3 below shows timing points reported under rule CLK-INC003.

Figure 3.5.3

clk1

create_clock -name CLK [get_ports clk1 clk2]

clk2

In the above design, the create_clock “CLK” is defined on two different ports.
Therefore, “check_constraints” will report these ports under rule CLK-INC003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC003 Warning 1 0 Sdc.Clock/CLK-INC003.rpt create_clock/generated_clock defined on multiple points

Sdc.Clock/CLK-INC003.rpt :
# Rule: CLK-INC003
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC003
# create_clock/generated_clock defined on multiple points
#
A# Clock Clock ID Create/Generated Objects
--------------------------------------------------------------------
A0 CLK 1 create_clock {clk1 clk2 }
---------------------------------------------------------------------

Debug
Get the “app_clocks” attribute on the ports/pins to confirm the same clock is defined on multiple
ports/pins

tv_shell> get_attribute [get_ports clk1] app_clocks

{"CLK1"}

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 TimeVision Constraints User Guide
tv_shell> get_attribute [get_ports clk2] app_clocks
{"CLK1"}

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.
Example:
set_waiver -rule CLK-INC003 –id A0 –reason “Ok for now”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC002 -obj1 CLK -author "hollis" -date "07/10/14" -reason "Ok for now"

3.5.4 Rule CLK-INC004

- create_generated_clock defined on input ports with no master

Description:
This rule identifies all “create_generated_clock” defined at input ports. Since an input port is a
primary clock source, any clocks on it should be defined as a “create_clock”. The only exception is
when BOTH, a “create_clock” and “create_generated_clock” are defined on the same
port. And the –source of the “create_generated_clock” is the same port on which a
“create_clock” is also defined.

Design in figure 3.5.4 below shows timing points reported under rule CLK-INC004.

Figure 3.5.4

clk1

create_generated_clock-name gclk1 [get_ports clk1]

In the above design, the create_generated_clock is defined on a primary input port.

Therefore, “check_constraints” will report these ports under rule CLK-INC004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC004 Error 1 0 Sdc.Clock/CLK-INC004.rpt create_generated_clock defined on input ports with no master

Sdc.Clock/CLK-INC004.rpt :
# Rule: CLK-INC004

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 TimeVision Constraints User Guide
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC004
# create_generated_clock defined on input ports with no master
#
A# Port Clock Clock ID
-----------------------------
A0 clk1 gclk1 1
-----------------------------

Debug
1) Get the “printable” attribute of the clock to see if it was defined with a master clock.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC004_test1.tcl:24:1) -name gclk1 -add \
-source [get_ports clk1] -divide_by 2 [get_ports clk1]

2) Note that the –source is the same as the port the generated clock is defined. Check to see if
another clock is defined on the port by checking the “clocks” attribute

tv_shell > get_attribute [get_ports clk1] clocks

{"gclk1"}

3) Note that the only clock defined on the port is the generated clock, so the generated clock has no
master.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC004 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "Ok for now"

3.5.5 Rule CLK-INC005

- Generated clock with no master clock (dead clock)

Description:
This rule identifies all “create_generated_clocks” for which the specified –source pin/port
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 TimeVision Constraints User Guide
has NO clock defined on it, and NO clock reaching it. Hence, it is reported as a “dead” generated clock.

Design in figure 3.5.5 below shows timing points reported under rule CLK-INC005.

Figure 3.5.5

_ _
D Q D Q
FF1
clk1 Q Q
No clock defined
_
D Q
create_generated_clock -source [get_ports clk1]
[get_pins FF1/Q]
Q

In the above design, the create_generated_clock is defined on pin FF1/Q but the source point has no
master clock defined on it.
Therefore, “check_constraints” will report these ports under rule CLK-INC005.
Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC005 Warning 1 0 Sdc.Clock/CLK-INC005.rpt Generated clock with no master clock (dead clock)

Sdc.Clock/CLK-INC005.rpt :
# Rule: CLK-INC005
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC005
# Generated clock with no master clock (dead clock)
#
A# Generated Clock Clock ID Source
---------------------------------------------------
A0 gclk1 1 clk1
----------------------------------------------------

Debug
1) Get the “printable” attribute of the clock to see if it was defined with a master clock.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (design_data/CLK-INC.sdc:7:1) -name gclk1 \
-source [get_ports clk1] [get_pins FF1/Q]

2) Note that the –source is a port that has no clock defined. Confirm that no clock is defined on the
port by checking the “clocks” attribute

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 TimeVision Constraints User Guide

tv_shell > get_attribute [get_ports clk1] clocks

3) Note that no clock is defined on the port, so the generated clock has no master and is considered
dead.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC005 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.6 Rule CLK-INC006

- Generated clock with ambiguous master clocks of different periods

Description:
This rule identifies all “create_generated_clock” for which no –master_clock is defined,
and –source pin/port has multiple clocks of different periods on it. In this case, it is ambiguous which
clock on the –source is the actual master clock, and this may result in incorrect STA analysis. By
default, most tools would assume the first clock defined in the constraints file on the –source
pin/port as the master clock, and that may or may not be the correct assumption. Hence, it is critical
for the user to specify the “-master_clock” in such cases.

Design in figure 3.5.6 below shows timing points reported under rule CLK-INC006.

Figure 3.5.6

create_clock -period 2.3 -name CLKB _ _

[get_ports clk1]
D Q D Q
FF1
clk1 Q Q
create_clock -period 1.0 -name CLKA
[get_ports clk1] _
D Q
create_generated_clock -source [get_ports
clk1] [get_pins FF1/Q]
Q
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 TimeVision Constraints User Guide
In the above design, the create_generated_clock is defined on pin FF1/Q but the source point has
multiple master clock defined on it of different periods and no -master is defined.
Therefore, “check_constraints” will report these ports under rule CLK-INC006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC006 Fatal 1 0 Sdc.Clock/CLK-INC006.rpt Generated clock with ambiguous master clocks of different
periods
Sdc.Clock/CLK-INC006.rpt :
# Rule: CLK-INC006
# Severity: Fatal
# ==============================
#
# Design : top
# CLK-INC006
# Generated clock with ambiguous master clocks of different periods
#

A# Generated Clock Clock ID Source Master Clocks

------------------------------------------------------------------------
A0 gclk1 3 clk1 {CLKA CLKB }
------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of the clock to confirm that it was defined without
“-master”

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC006_test1.tcl:26:3) -name gclk1 -add \
-source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

2) Indeed the generated clock is defined without “-master_clock”. Now trace the path from the
master clocks source to the clock pin of generated clock source to confirm the master clocks reaches
the generated clock source.
tv_shell > trace_path -from [get_ports clk1] -to FF1/CP

Point Type Flags

------------------------------
clk1 (port) cs
FF1/CP SDFCNQD1 ~

3) Both master clocks reaches the clock pin of the generated clock source so either clock could be used,
however, it is recommended to define a generated clock for all master clocks, or use the faster of
the master clock options when redefining the generated clock “-master_clock”.

Waivers
Any reported violation can be waived using the “set_waiver” command.

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 TimeVision Constraints User Guide
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC006 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC006 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.7 Rule CLK-INC007

- Generated clock with ambiguous master clocks of identical periods

Description:
This rule identifies all “create_generated_clock” for which no –master_clock is defined,
and –source pin/port has multiple clocks of identical periods on it. In this case, it is ambiguous which
clock on the –source is the actual master clock, and this may result in incorrect STA analysis. By
default, most tools would assume the first clock defined in the constraints file on the –source
pin/port as the master clock, and that may or may not be the correct assumption. Hence, it is critical
for the user to specify the “-master_clock” in such cases.

Design in figure 3.5.7 below shows timing points reported under rule CLK-INC007.

Figure 3.5.7

create_clock -period 2.3 -name CLKB _ _

[get_ports clk1]
D Q D Q
FF1
clk1 Q Q
create_clock -period 2.3 -name CLKA
[get_ports clk1] _
D Q
create_generated_clock -source [get_ports
clk1] [get_pins FF1/Q]
Q
In the above design, the create_generated_clock is defined on pin FF1/Q but the source point has
multiple master clock defined on it of the same period and no -master is defined.
Therefore, “check_constraints” will report these ports under rule CLK-INC007.

Reports:

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 TimeVision Constraints User Guide
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC007 Warning 1 0 Sdc.Clock/CLK-INC007.rpt Generated clock with ambiguous master clocks of different
periods

Sdc.Clock/CLK-INC007.rpt :
# Rule: CLK-INC007
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC007
# Generated clock with ambiguous master clocks of different periods
#

A# Generated Clock Clock ID Source Master Clocks

------------------------------------------------------------------------
A0 gclk1 3 clk1 {CLKA CLKB }
------------------------------------------------------------------------
Debug
1) Get the “printable” attribute of the clock to confirm that it was defined without
“-master”

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC007_test1.tcl:28:3) -name gclk1 -add \
-source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

2) Indeed the generated clock is defined without “-master_clock”. Now trace the path from the
master clocks source to the clock pin of generated clock source to confirm the master clocks reaches
the generated clock source.
tv_shell > trace_path -from [get_ports clk1] -to FF1/CP

Point Type Flags

------------------------------
clk1 (port) cs
FF1/CP SDFCNQD1 ~

3) Both master clocks reaches the clock pin of the generated clock source so either clock could be used,
however, it is recommended to define a generated clock for all master clocks, or use the faster of
the master clock options when redefining the generated clock “-master_clock”.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
January 2015 43 Ausdia, Inc © 2015
 TimeVision Constraints User Guide
set_waiver -rule CLK-INC007 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC007 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.8 Rule CLK-INC008

- master_clock not present at -source object (no path from -master_clock, no path from -source)

Description:
This rule identifies all “create_generated_clock” for which no –master_clock is defined,
and –source pin/port has multiple clocks of identical periods on it. In this case, it is ambiguous which
clock on the –source is the actual master clock, and this may result in incorrect STA analysis. By
default, most tools would assume the first clock defined in the constraints file on the –source
pin/port as the master clock, and that may or may not be the correct assumption. Hence, it is critical
for the user to specify the “-master_clock” in such cases.

Design in figure 3.5.8 below shows timing points reported under rule CLK-INC008.

Figure 3.5.8

clk1
create_clock -name CLK1
[get_ports clk1]
_ _
D Q D Q
FF1
clk2 Q Q

create_generated_clock -master CLK1 -source

_
D Q
[get_ports clk1] [get_pins FF1/Q]

In the above design, the create_generated_clock is defined on pin FF1/Q but there is no path from
source point where the master clock is defined.
Therefore, “check_constraints” will report these ports under rule CLK-INC008.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC008 Error 1 0 Sdc.Clock/CLK-INC008.rpt -master_clock not present at -source object (no path from -
master_clock, no path
from -source)

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 TimeVision Constraints User Guide
Sdc.Clock/CLK-INC008.rpt :
# Rule: CLK-INC008
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC008
# -master_clock not present at -source object (no path from -master_clock, no path from -source)
#

A# Generated Clock Clock ID Master Clock Source Clocks At Source

-----------------------------------------------------------------------------------------------
A0 gclk1 4 {CLK1 } clk1 {CLK1 }
-----------------------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of clock to determine the “-source” and “-master_clock”.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (design_data/CLK-INC.sdc:18:4) \
-name gclk1 -add -source [get_ports clk1] -divide_by 2 -master [get_clocks CLK1] \
[get_pins FF1/Q]

2) Trace the path from “-source” and “-master” to confirm that neither has a path to the clock pin of
the generated clock source.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins FF1/CP]

3) No path returned, confirming that the generated clock is not defined relative to a legitimate
“-source” or a legitimate “-master_clock”.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC008 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC008 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.5.9 Rule CLK-INC009
- master_clock not present at -source object (no path from -master_clock, path from -source)

Description:
This rule identifies all “create_generated_clock” for which no –master_clock is defined,
and –source pin/port has multiple clocks of identical periods on it. In this case, it is ambiguous which
clock on the –source is the actual master clock, and this may result in incorrect STA analysis. By
default, most tools would assume the first clock defined in the constraints file on the –source
pin/port as the master clock, and that may or may not be the correct assumption. Hence, it is critical
for the user to specify the “-master_clock” in such cases.
Design in figure 3.5.9 below shows timing points reported under rule CLK-INC009.

Figure 3.5.9

clk1

create_clock -name CLK1

[get_ports clk1] _ _
D Q D Q
FF1
clk2 Q Q
create_clock -name CLK2 [get_ports clk2]
_
D Q
create_generated_clock -master CLK1 -source [get_ports
clk2] [get_pins FF1/Q]
Q

In the above design, the create_generated_clock is defined on pin FF1/Q but there is no path from
master clock point but there is a path from the source point.
Therefore, “check_constraints” will report these ports under rule CLK-INC009.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC009 Error 21 0 Sdc.Clock/CLK-INC009.rpt -master_clock not present at -source object (no path from -
master_clock, path
from -source)

Sdc.Clock/CLK-INC009.rpt :
# Rule: CLK-INC009
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC009
# -master_clock not present at -source object (no path from -master_clock, path from -source)
#

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 TimeVision Constraints User Guide

A# Generated Clock Clock ID Master Clock Source Clocks At Source

----------------------------------------------------------------------------------------------
A0 gclk1 3 {CLK1 } clk2 {CLK2 }
----------------------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of the clock to determine the “-source” and “-master_clock”.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC009_test1.tcl:27:3) -name gclk1 -add \
-source [get_ports clk2] -divide_by 2 -master [get_clocks CLK1] [get_pins FF1/Q]

2) Get the “source” attribute of “-master” clock “CLK1” to confirm that it does not exist on the
“-source” object of the create_generated_clock command.

tv_shell > get_attribute [get_clocks CLK1] source

{"clk1"}

3) The “-master_clock” is not defined on the “-source” object. Trace the path from the “-master_clock”
to the clock pin of the generated clock source to confirm there is not path.

tv_shell > trace_path -from [get_clocks clk1] -to [get_pins FF1/CP]

4) No path exist from the “-master_clock” to the clock pin of the generated clock source. Now confirm
that a path does exist from the “-source” object to the clock pin of the generated clock source by
tracing the path.

tv_shell > trace_path -from [get_ports clk2] -to [get_pins FF1/CP]

Point Type Flags
-------------------------------------------
(Unconstrained Startpoint)
clk2 (port) cs
FF1/CP SDFCNQD1 ~

5) Now that the path from “-source” to the clock pin of the generated clock source is confirmed, the
constraint should be fixed by changing the “-master” to the clock defined on the “-source” object.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC009 –id A0 –reason “None”
write_waiver top.waivers.tcl

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 TimeVision Constraints User Guide
top.waivers.tcl
set set_waiver -rule CLK-INC009 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.10 Rule CLK-INC010

-master_clock not present at -source object (path from -master_clock, no path from -source)

Description:
This rule identifies all “create_generated_clock” which have both “–source” and
“–master_clock” defined, however, “-master_clock” is not present at the “–source”
pin/port. There is a logic path from “–master_clock” to the generated clock, but there is NO logic
path from “–source" to the generated clock.

Design in figure 3.5.10 below shows timing points reported under rule CLK-INC010.

Figure 3.5.10

clk1

create_clock -name CLK1 [get_ports clk1]

_ _
D Q D Q
FF1
clk2 Q Q
create_clock -name CLK2 [get_ports clk2]
create_generated_clock -master CLK2 -source [get_ports clk1]
_
D Q
[get_pins FF1/Q]

In the above design, the create_generated_clock is defined on pin FF1/Q but there is a path from
master clock point but there is no path from the source point.
Therefore, “check_constraints” will report these ports under rule CLK-INC010.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC010 Error 1 0 Sdc.Clock/CLK-INC010.rpt -master_clock not present at -source object (path from -
master_clock, no path
from -source)

Sdc.Clock/CLK-INC010.rpt :
# Rule: CLK-INC010
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC010
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 TimeVision Constraints User Guide
# -master_clock not present at -source object (path from -master_clock, no path from -source)
#

A# Generated Clock Clock ID Master Clock Source Clocks At Source

----------------------------------------------------------------------------------------------
A0 gclk1 3 {CLK2 } clk1 {CLK1 }
----------------------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of the clock to determine the “-source” and “-master”.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC010_test1.tcl:27:3) -name gclk1 -add \
-source [get_ports clk1] -divide_by 2 -master [get_clocks CLK2] [get_pins FF1/Q]

2) Get the “clock” attribute of “-source” object “clk1” to confirm that the “-master” clock does not exist
on the “-source” object of the create_generated_clock command.

tv_shell > get_attribute [get_ports clk1] clocks

{"CLK1"}

3) The “-master” clock is not defined on the “-source” object. Trace the path from the “-master” clock
to the clock pin of the generated clock source to confirm there is a path.

tv_shell > trace_path -from [get_clocks CLK2] -to [get_pins FF1/CP]

Point Type Flags
-------------------------------------------
(Unconstrained Startpoint)
clk2 (port) cs
FF1/CP SDFCNQD1 ~

4) Now that the path from “-master” clock to the clock pin of the generated clock source is confirmed,
the constraint should be fixed by changing the “-source” to the object where the “-master” is defined.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC010 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC010 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.5.11 Rule CLK-INC011
-master_clock not present at -source object (path from -master_clock, path from -source)

Description:
This rule identifies all “create_generated_clock” which have both “–source” and
“–master_clock” defined, however, “-master_clock” is not present at the “–source”
pin/port. There is a logic path from “–master_clock” to the generated clock, but there is NO logic
path from “–source" to the generated clock.

Design in figure 3.5.11 below shows timing points reported under rule CLK-INC011.
Figure 3.5.11

create_clock -name CLK1 _ _

[get_ports clk1] D Q D Q
clk1 FF1
Q Q
clk2

create_clock -name CLK2 _

[get_ports clk2]
D Q
create_generated_clock -master CLK2 -source
[get_ports clk1] [get_pins FF1/Q] Q

In the above design, the create_generated_clock is defined on pin FF1/Q but there is a path for the
master clock point is different than the path from the source point.
Therefore, “check_constraints” will report these ports under rule CLK-INC011.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC011 Error 2 0 Sdc.Clock/CLK-INC011.rpt -master_clock not present at -source object (path from -
master_clock, path from
-source)
Sdc.Clock/CLK-INC011.rpt :
# Rule: CLK-INC011
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC011
# -master_clock not present at -source object (path from -master_clock, path from -source)
#

A# Generated Clock Clock ID Master Clock Source Clocks At Source

----------------------------------------------------------------------------------------------
A0 gclk 1 {CLK2 } clk1 {CLK1 }
-----------------------------------------------------------------------------------------------

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 TimeVision Constraints User Guide
Debug
Using the violating clock “gclk", debug using the following steps:
1) Get the “printable” attribute of clock “gclk” to determine the “-source” and “-master”.

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (tests/check_cons_CLK-INC011_test1.tcl:26:2) -name gclk -source
[get_ports clk1] -divide_by 2 -master [get_clocks CLK2] [get_pins FF1/Q]

2) Get the “source” attribute of the generated clock “-master” clock to confirm that the “-master” clock
is not defined on the “-source” object.

tv_shell > get_attribute [get_clocks CLK2] source

{"clk2"}

3) The source of the “-master” clock is different from the “-source” object in the constraint, confirming
that the “-master” clock is not defined on the “-source” object, however, this violation reports that
there are paths from both the “-source” object and the “-master” clock. Confirm the paths by tracing
from both objects to the clock pin of the generated clock source.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins FF1/CP]

Point Type Flags
---------------------------------
clk1 (port) cs
mux/I0 CKMUX2D0 ~
mux/Z CKMUX2D0 ~
FF1/CP SDFCNQD1 ~

tv_shell > trace_path -from [get_clocks CLK2] -to [get_pins FF1/CP]

Point Type Flags
---------------------------------
Clk2 (port) cs
mux/I1 CKMUX2D0 ~
mux/Z CKMUX2D0 ~
FF1/CP SDFCNQD1 ~

4) Both paths exist so the designer must decide which object is the correct source and master of the
generated clock.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC011 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC011 -obj1 gclk1 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"
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 TimeVision Constraints User Guide
3.5.12 Rule CLK-INC012
- create_generated_clock has no logic path from -source object (path exist from other clock
sources)

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has no path to the
“–source” object, however, Timevision identified other potential masters that has logic path to the
“create_generated_clock” that should be considered as master clock.

Design in figure 3.5.12 below shows timing points reported under rule CLK-INC012.

Figure 3.5.12

clk1

create_clock -name CLK1

[get_ports clk1] _ _
D Q D Q
FF1
clk2 Q Q
create_clock -name CLK2
[get_ports clk2] _
D Q
create_generated_clock -source [get_ports clk1]
[get_pins FF1/Q]
Q

In the above design, the create_generated_clock is defined on pin FF1/Q but there is no path from the
source point but a path exist to another clock.
Therefore, “check_constraints” will report these ports under rule CLK-INC012.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC012 Error 1 0 Sdc.Clock/CLK-INC012.rpt create_generated_clock has no logic path from -source object
(path exist from
other clock sources)

Sdc.Clock/CLK-INC012.rpt :
# Rule: CLK-INC012
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC012
# create_generated_clock has no logic path from -source object (path exist from other clock sources)
#

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 TimeVision Constraints User Guide
A# Generated Clock Clock ID Master Clock Source Clocks At Source
----------------------------------------------------------------------------------------------
A0 gclk 6 {CLK1 } clk1 {CLK1 }
----------------------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of clock “gclk” to determine the “-source” and “-master”.

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (tests/check_cons_CLK-INC012_test1.tcl:29:6) -name gclk -source
[get_ports clk1] -divide_by 2 -master [get_clocks CLK1] [get_pins FF1/Q]

2) Trace the path from the “-source” object to the clock pin of the generated clock source to confirm
the path does not exist.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins FF1/CP]

3) No path is returned, confirming the path does not exist. Now do “all_fanin” to see if a path exist to
another master clock.

tv_shell > all_fanin -to [get_pins FF1/CP] -start

{ clk2 }

4) The path does exist. Now confirm a clock is defined on object to “clk2”.

get_attribute [get_ports clk2] clocks

{ CLKL2 }

5) A clock does exist so the designer should make change the source to “clk2” and the master to
“CLK2”.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC012 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC012 -obj1 gclk -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.5.13 Rule CLK-INC013
- create_generated_clock has no logic path from -source object (path do not exist from other
clock sources)

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has no path to the
“–source” object or any other master clock.

Design in figure 3.5.13 below shows timing points reported under rule CLK-INC013.
Figure 3.5.13

clk1

create_clock -name CLK1

[get_ports clk1] _ _
D Q D Q
FF1
clk2 Q Q
No clock defined
create_generated_clock -source [get_ports clk1]
_
D Q
[get_pins FF1/Q]

Q
In the above design, the create_generated_clock is defined on pin FF1/Q but there is no path from the
source point and no path exist to another clock.
Therefore, “check_constraints” will report these ports under rule CLK-INC013.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
----
Sdc.Clock CLK-INC013 Error 1 0 Sdc.Clock/CLK-INC013.rpt create_generated_clock has no logic path from -source object
(path do not exist
from other clock sources)

Sdc.Clock/CLK-INC013.rpt :
# Rule: CLK-INC013
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC013
# create_generated_clock has no logic path from -source object (path do not exist from other clock sources)
#

A# Generated Clock Clock ID Source Clocks At Source

---------------------------------------------------------------------------
A0 gclk 4 clk1 {CLK1 }
---------------------------------------------------------------------------

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 TimeVision Constraints User Guide
Debug
1) Get the “printable” attribute of clock “gclk” to determine the “-source” and “-master”.

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (tests/check_cons_CLK-INC013_test1.tcl:17:4) -name gclk -source
[get_ports clk1] -divide_by 2 [get_pins FF1/Q]

2) Trace the path from the “-source” object to the clock pin of the generated clock source to confirm
the path does not exist.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins FF1/CP]

3) No path is returned, confirming the path does not exist. Now do “all_fanin” to see if a path exist to
another master clock.

tv_shell > all_fanin -to [get_pins FF1/CP] -start

{ clk2 }

4) A path does exist. Now confirm a clock is defined on object to “clk2”.

get_attribute [get_ports clk2] clocks

5) A clock does not exist so the designer should create a clock on “clk2” and make it the master of the
generated clock.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC013 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC013 -obj1 gclk -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.14 Rule CLK-INC014

- Intermediate clock is defined between a generated clock and its master source clock

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has no path to the
defined master clock due to the master clock propagation being blocked by an intermediate clock
defined between the generated clock and its master clock source.
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 TimeVision Constraints User Guide
Design in figure 3.5.14 below shows timing points reported under rule CLK-INC014.
Figure 3.5.14

_ _
D Q D Q
FF1 FF2
clk1 B1 B2 Q Q
create_clock -name CLK1
[get_ports clk1]
create_generated_clock -name gen_CLK1 create_generated_clock -name gen_CLK2
-source [get_ports clk1] B1/Z -source [get_ports clk1] FF1/Q

In the above design, the create_generated_clock is defined on pin FF1/Q and has port clk1 as its source
point but intermediate clock gen_CLK1 blocks propagation to the master clock source.
Therefore, “check_constraints” will report these ports under rule CLK-INC014.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC014 Warning 1 0 Sdc.Clock/CLK-INC014.rpt Intermediate clock is defined between a generated clock and its
master source clock

Sdc.Clock/CLK-INC014.rpt :
# Rule: CLK-INC014
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC014
# Intermediate clock is defined between a generated clock and its master source clock
#

A# Generated Clock Clock ID Source

----------------------------------------------------
A0 gen_CLK2 3 clk1
----------------------------------------------------

Debug
1) Get the “printable” attribute of clock “gen_CLK2” to determine the “-source” or “-master”.

tv_shell > get_attribute [get_clocks gen_CLK2] printable

create_generated_clock (design_data/CLK-INC.sdc:15:3) -name gen_CLK2 -source [get_ports clk1]
-divide_by 2 [get_pins FF1/Q]

2) Trace the path from the “-source” object to the clock pin of the generated clock source.

tv_shell [97] >trace_path -from [get_ports clk1] -to [get_pins FF1/CP] -hier
Point Type Flags
---------------------------------
clk1 (port) cs
B1/I BUFFD1 ~
B1/Z BUFFD1 cs~
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FF1/CP SDFCNQD1 ~
3) Note that in the “Flags” column there are two “cs” flags, which indicates clock sources. The second
clock source is defined between the generated clock source pin and it’s specified “-source” object
“clk1”. To fix this violation pin “B1Z“ should be defined as the “-source” object.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC014 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC014 -obj1 gen_CLK2 -obj2 clk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.15 Rule CLK-INC015

- Downstream generated clocks with a single source

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has been defined
on a “down-stream” logic pin and has only one possible master, however, it should be define “up-
stream”, on the output pin of a register.

Design in figure 3.5.15 below shows timing points reported under rule CLK-INC015.
Figure 3.5.15

_
D
_
Q D Q
FF1
clk1 Q B1 Q
create_clock -name CLK1 [get_ports clk1]

create_generated_clock -master CLK1 -source [get_pins clk1] [get_pins B1/Z]

In the above design, the create_generated_clock is defined on pin B1/Z and has port clk1 as its source
point. Port clk1 has a single clock defined on it but it should be defined up stream on pin FF1/Q.
Therefore, “check_constraints” will report these ports under rule CLK-INC015.

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Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC015 Warning 1 0 Sdc.Clock/CLK-INC015.rpt Downstream generated clocks with a single source

Sdc.Clock/CLK-INC015.rpt :
# Rule: CLK-INC015
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC015
# Downstream generated clocks with a single source
#

A# Generated Clock Clock ID App Point Implied App Point

--------------------------------------------------------------------------------
A0 gclk1 2 {B1/Z } {FF1/CK }
--------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of clock “gclk1” to determine the “-source” or “-master”.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (design_data/CLK-INC.sdc:25:2) -name gclk1 -source [get_ports clk1]
-divide_by 2 [get_pins B1/Z]

2) TimeVision reported an implied application point “FF1/CK”. Trace a path from the implied
application point through the current application point to confirm a path exist to leaf clock pins.

tv_shell > trace_path -from [get_pins FF1/CK] -through [get_pins B1/Z]

Point Type Flags
-------------------------------------------
(Clocked ^ clk )
FF1/CK DFF_X1 ~
FF1/Q DFF_X1
B1/A BUF_X1
B1/Z BUF_X1 cs ~
FF2/CK DFF_X1 ~

3) Since the path only has a buffer between the generated clock source and the recommended
generated clock source, it would be prudent to define the generated clock on the register output pin.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

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Example:
set_waiver -rule CLK-INC015 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC015 -obj1 gclk1 -author "hollis" -date "07/10/14" -reason "None"

3.5.16 Rule CLK-INC016

- Downstream generated clocks with multiple sources

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has been defined on a
“down-stream” logic pin and has multiple possible sources, however, it should be define “up-stream”,
on the output pin of a register.

Design in figure 3.5.16 below shows timing points reported under rule CLK-INC016.
Figure 3.5.16
_
D Q
FF1 _
D Q
Q FF3
M1 Q
D
_
Q A
A1 Z
B
FF2 create_generated_clock -name gclk \
-master CLK1 -source [get_pins A1/A] \
clk1 Q [get_pins M1/Z]
create_clock -name CLK1
[get_ports clk1]

In the above design, the create_generated_clock is defined on pin M1/Z and has pin A1/A as its source
point. However, A1/B is also a potential source point, but, two generated clocks should be created,
one with clk1 as the source on FF1/Q, and the other with clk2 as the source on FF2/Q. Therefore,
“check_constraints” will report these ports under rule CLK-INC016.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC016 Warning 1 0 Sdc.Clock/CLK-INC016.rpt Downstream generated clocks with multiple sources

Sdc.Clock/CLK-INC016.rpt :
# Rule: CLK-INC016
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC016
# Downstream generated clocks with multiple sources
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#

A# Generated Clock Clock ID App Point Implied App Point

---------------------------------------------------------------------------------
A0 gclk 1 {M1/Z } {FF1/CK FF2/CK }
---------------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of clock “gclk1” to determine the “-source” or “-master”.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (design_data/CLK-INC.sdc:25:1) -name gclk -source [get_pins A1/A]
-divide_by 2 [get_pins M1/Z]

2) TimeVision reported two implied application points “FF1/CK, FF2/CK”. Trace a path from the implied
application points through the current application point to confirm a path exist to leaf clock pins.

tv_shell > trace_path -from [get_pins FF1/CK] -through [get_pins M1/Z]

Point Type Flags
-------------------------------------------
(Clocked ^ clk1 )
FF1/CK DFF_X1 ~
FF1/Q DFF_X1
A1/A BUF_X1
A1/Z BUF_X1
M1/I1 MUX_X1
M1/Z MUX_X1 cs ~
FF3/CK DFF_X1 ~

tv_shell > trace_path -from [get_pins FF2/CK] -through [get_pins M1/Z]

Point Type Flags
-------------------------------------------
(Clocked ^ clk2 )
FF2/CK DFF_X1 ~
FF1/Q DFF_X1
A1/B BUF_X1
A1/Z BUF_X1
M1/I1 MUX_X1
M1/Z MUX_X1 cs ~
FF3/CK DFF_X1 ~

3) Both registers have a path to the generated clock source. To resolve this violation a generated clock
should be defined on the output pins of both registers instead of the output pin of the mux.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC016 –id A0 –reason “None”
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write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC016 -obj1 gclk -author "hollis" -date "07/10/14" -reason "None"

3.5.17 Rule CLK-INC017

- create_generated_clock unateness incompatible w.r.t. its master clock

Description:
This rule identifies all pins in the designs where a “create_generated_clock” has been defined
such that its unateness conflicts with the unateness of its master clock.

Design in figure 3.5.17 below shows timing points reported under rule CLK-INC017.
Figure 3.5.17 _
D Q
clk1 I1 FF1
create_clock -name CLK1 M1 Q
[get_ports clk1]
clk2 B1
create_generated_clock -master CLK1
create_clock -name CLK2
-source [get_ports clk1] [get_pins M1/Z]
[get_ports clk2]

In the above design, the create_generated_clock is defined on pin M1/Z but its unateness is
incompatible with the unateness of its master. To be correct the command needs -invert.
Therefore, “check_constraints” will report these ports under rule CLK-INC017.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC017 Error 2 0 Sdc.Clock/CLK-INC017.rpt create_generated_clock unateness incompatible w.r.t. its master
clock

Sdc.Clock/CLK-INC017.rpt :
# Rule: CLK-INC017
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC017
# create_generated_clock unateness incompatible w.r.t. its master clock
#

A# Generated Clock Clock ID Source Unateness@Source App Point Unateness@App Point

-----------------------------------------------------------------------------------------------------------------------------
A0 gclk1 1 clk1 Positive {M1/Z } Negative
-----------------------------------------------------------------------------------------------------------------------------

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Debug
1) Get the “printable” attribute of clock “gclk1” to determine unateness relative to the “-source”
object.

tv_shell > get_attribute [get_clocks gclk1] printable

create_generated_clock (design_data/CLK-INC.sdc:16:1) -name gclk1 -add \
-source [get_ports clk1] -divide_by 1 [get_pins M1/Z]

2) The generated clock is not defined as “-invert” relative to its master. Trace the path to determine if
an inversion actually occurs.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins M1/Z]

Point Type Flags
--------------------------
clk1 (port) cs
I1/I INV1 ~
I1/Z INV1 ~
M1/I0 CKMUX2D0 ~
M1/Z CKMUX2D0 cs ~

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC017 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC017 -obj1 gclk1 -obj2 clk1 -obj3 {\ Positive\ } -obj4 {\ Negative\ } -author "hollis" \
-date "07/11/14" -reason "None"

3.5.18 Rule CLK-INC018

- application point of clock is a constant

Description:
This rule identifies all “create_clock” or “create_generated_clock” defined on application
points that are constant either by “set_case_analysis”, or a constant is propagated to the
application point.

Design in figure 3.5.18 below shows timing points reported under rule CLK-INC018.

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Figure 3.5.18

_
D Q
FF1
clk1 Q
create_clock -name CLK1 [get_ports clk1]
set_case_analysis 0 [get_ports clk1]

In the above design, the create_clock is defined on port clk1 but a set_case_analysis is also defined on
the port.
Therefore, “check_constraints” will report these ports under rule CLK-INC018.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC018 Error 1 0 Sdc.Clock/CLK-INC018.rpt application point of clock is a constant

Sdc.Clock/CLK-INC018.rpt :
# Rule: CLK-INC018
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC018
# application point of clock is a constant
#

A# Clock Clock ID App Point Constant

------------------------------------------------------
A0 CLK1 1 clk1 0
-------------------------------------------------------

Debug
Get the “constant_value” attribute of the source of the clock to confirm it is constant.

tv_shell > get_attribute [get_attribute [get_clocks CLK1] source] constant_value

0

Trace the constant of the application point to determine the origin of the constant.

tv_shell > trace_constants -to [get_attribute [get_clocks CLK1] source]

OBJECT: clk1 : Case Analysis - constant logic 0
Source : file: design_data/CLK_INC_CONST.sdc line: 10

In the case of “CLKL1” Timevision reports the constant is from a “Case Analysis” in the constraints file.

Realistically, this rule should never be waived. However, a waiver example is below.

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Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC018 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC018 -obj1 CLK1 -obj2 clk1 -obj3 0 -author "hollis" -date "07/11/14" -reason "None"

3.5.19 Rule CLK-INC019

- source point of a generated clock is a constant

Description:
This rule identifies all “create_generated_clock” where the source is constant either by
“set_case_analysis”, or a constant is propagated to the application point.

Design in figure 3.5.19 below shows timing points reported under rule CLK-INC019.
Figure 3.5.19

_
set_case_analysis 0 [get_pins B1/I] D Q

clk1 B1 Q
create_clock -name CLK1
[get_ports clk1] create_generated_clock -source [get_pins B1/I]
[get_pins B1/Z]

In the above design, the create_clock is defined on port clk1 but a set_case_analysis is also defined on
the port.
Therefore, “check_constraints” will report these ports under rule CLK-INC019.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

--------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC019 Fatal 1 0 Sdc.Clock/CLK-INC019.rpt source point of a generated clock is a constant

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Sdc.Clock/CLK-INC019.rpt :
# Rule: CLK-INC019
# Severity: Fatal
# ==============================
#
# Design : top
# CLK-INC019
# source point of a generated clock is a constant
#

A# Clock Clock ID Source Constant

---------------------------------------------------
A0 gclk1 2 B1/I 0
----------------------------------------------------
Debug
Get the “constant_value” attribute of the source of the generated clock to confirm it is constant.

tv_shell > get_attribute [get_attribute [get_clocks gclk1] source] constant_value

0

Trace the constant of the application point to determine the origin of the constant.

tv_shell > trace_constants -to [get_attribute [get_clocks gclk1] source]

OBJECT: B1/I : Case Analysis - constant logic 0
Source : file: design_data/CLK_INC_CONST.sdc line: 14

In the case of “gclk1” Timevision reports the constant is from a “Case Analysis” in the constraints file.

Realistically, this rule should never be waived. However, a waiver example is below.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC019 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC019 -obj1 gclk1 -obj2 B1/I -obj3 0 -author "hollis" -date "07/11/14" -reason "None"

3.5.20 Rule CLK-INC020

- clock propagation overlaps with user-applied case analysis

Description:
This rule identifies all “create_clocks” and “create_generated_clock” whose
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 TimeVision Constraints User Guide
propagation overlap with “set_case_analysis”.

Design in figure 3.5.20 below shows timing points reported under rule CLK-INC020.
Figure 3.5.20

_
set_case_analysis 0 [get_pins B1/I] D Q

clk1 B1 Q
create_clock -name CLK1 [get_ports clk1]

In the above design, the create_clock is defined on port clk1 and a set_case_analysis is defined on the
pin B1/I and the propagation to the clock pin of the flop overlaps.
Therefore, “check_constraints” will report these ports under rule CLK-INC020.

Reports:

Sdc.Qor_Fails.rpt:

Category Rule Sev'ty #'Vios #'Waived Report Description

--------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC020 Warning 1 0 Sdc.Clock/CLK-INC020.rpt clock propagation overlaps with user-applied case analysis

Sdc.Clock/CLK-INC020.rpt :
# Rule: CLK-INC020
# Severity: Warning
# ==============================
#
# Design : top
# CLK-INC020
# clock propagation overlaps with user-applied case analysis
#

A# Clock Clock ID Point Constant

---------------------------------------
A0 CLK1 0 B/I 0
---------------------------------------

Debug
Trace the path from the clock source to see if it is disabled.

tv_shell > trace_path -from [get_ports clk1]

Point Type Flags

-------------------------------------------
(Unconstrained Startpoint)
clk1 (port) cs
B1/A BUF_X1 d

Pin B1/A is disabled so the clock propagation stops. Trace the constant to determine its source.

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tv_shell > trace_constant -to [get_pins B1/A]

OBJECT: B1/A : Case Analysis - constant logic 0

Source : file: tests/check_cons_CLK-INC020_test1.tcl line: 25

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC020 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC020 -obj1 CLK1 -obj2 B1/I -obj3 0 -author "hollis" -date "07/11/14" -reason "None"

3.5.21 Rule CLK-INC021

- generated_clock lists -source and application point at same location

Description:
This rule identifies all “create_generated_clock” where the source point and the application
point are the same.

Design in figure 3.5.21 below shows timing points reported under rule CLK-INC021.
Figure 3.5.21

_
D Q

clk1 B1 Q
create_clock -name CLK1 [get_ports clk1]
create_generated_clock -source [get_pins B1/Z] [get_pins B1/Z]

In the above design, the create_generated_clock is defined on pin B1/Z and it list B1/Z as the source
point.
Therefore, “check_constraints” will report these ports under rule CLK-INC021.

Reports:

Sdc.Qor_Fails.rpt:

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Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-INC021 Error 1 0 Sdc.Clock/CLK-INC021.rpt generated_clock lists -source and application point at same
location.

Sdc.Clock/CLK-INC021.rpt :
# Rule: CLK-INC021
# Severity: Error
# ==============================
#
# Design : top
# CLK-INC021
# generated_clock lists -source and application point at same location.
#
A# Clock Clock ID Source/App Point
----------------------------------------
A0 gclk1 2 B1/Z
----------------------------------------

Debug
Get the printable attribute of the generated clock to see if the application point and source points are
the same.

tv_shell > get_attribute [get_ports gclk1] printable

create_generated_clock (tests/check_cons_CLK-INC021_test1.tcl:25:2) -name gclk1 -add \
-source [get_pins b/Z] -divide_by 2 [get_pins b/Z]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-INC021 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set set_waiver -rule CLK-INC021 -obj1 gclk1 -obj2 B1/Z -author "hollis" -date "07/11/14" -reason "None"

3.6 Clock wave rules

3.6.1 Rule CLK-WAV001

- div-1 or combinational clock on a sequential Q pin

Description:
This rule identifies all “create_generated_clock” defined on “Q” pins or sequential cells output
pins and is “-divide_by 1” or “combinational”.

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Design in figure 3.6.1 below shows timing points reported under rule CLK-WAV001

Figure 3.6.1

_ _
D Q D Q
FF1
clk1 Q Q
create_clock -name CLK1 [get_ports clk1]

create_generated_clock -source [get_ports clk1] -divide_by 1 [get_pins FF1/Q]

In the above designs, FF1/Q has a generated clock with “-divide_by 1”, which is not possible.
Therefore, “check_constraints” will report these ports under rule CLK-WAV001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV001 Error 1 0 Sdc.Clock/CLK-WAV001.rpt div-1 or combinational clock on a sequential Q pin

Sdc.Clock/CLK-WAV001.rpt :
# Rule: CLK-WAV001
# Severity: Error
# ==============================
#
# Design : top
# CLK-WAV001
# div-1 or combinational clock on a sequential Q pin
#

A# Clock Clock ID Type App Point

------------------------------------------------------------
A0 gclk 1 -divide_by 1 FF1/Q
-----------------------------------------------------------

Debug
Get the “printable” attribute of the generated clock to see how it is defined.

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (tests/check_cons_CLK-WAV001_test1.tcl:25:1) -name gclk \
-source [get_ports clk1] -divide_by 1 [get_pins FF1/Q]

Note the generated clock is defined on the “Q” pin of a flop as “divide_by 1”.

Waivers
Any reported violation can be waived using the “set_waiver” command.

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Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-WAV001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-WAV001 -obj1 gclk -obj2 FF1/Q -obj3 {-divide_by\ 1} -author "hollis" -date "07/10/14" -reason "None"

3.6.2 Rule CLK-WAV002

- div-1 or combinational clock on a combinational gate when no clock reaches pin

Description:
This rule identifies all “divide_by 1” or “combinational” “create_generated_clock” defined on
combinational logic cells pins but no clock reaches the pin.

Design in figure 3.6.2 below shows timing points reported under rule CLK-WAV002

Figure 3.6.2
create_clock -name CLK1
[get_ports clk1] _
D Q
clk1 FF1
M1 Q
clk2
create_generated_clock -source [get_ports clk1]
create_clock -name CLK2
-divide_by 1 [get_pins M1/Z]
[get_ports clk2]
set_case_analysis 1
[get_pins M1/SEL]

In the above designs, M1/Z has a generated clock with “-divide_by 1”, however no clock reaches the
pin because the mux select pin selects “I1” but the source is port “clk1”.
Therefore, “check_constraints” will report these ports under rule CLK-WAV002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV002 Error 1 0 Sdc.Clock/CLK-WAV002.rpt div-1 or combinational clock on a combinational gate when
no clock reaches pin
Sdc.Clock/CLK-WAV002.rpt :
# Rule: CLK-WAV002
# Severity: Error

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# ==============================
#
# Design : top
# CLK-WAV002
# div-1 or combinational clock on a combinational gate when no clock reaches pin
#

A# Clock Clock ID Type App Point

-----------------------------------------------
A0 gclk 1 -divide_by 1 M1/Z
-----------------------------------------------

Debug
Get the “prop_clocks” attribute of the generated clock application point to see if any clocks propagate
to the pin.

tv_shell > get_attribute [get_pins M1/Z] prop_clocks

{ CLK2 }

Only one clock propagates to the pin, “CLK2”. The generated clock is defined with port “clk1” as the
source. Check the name of the clock defined on port “clk1”.

tv_shell > get_attribute [get_ports clk1] clocks

{ CLK1 }

It was confirmed previously that only “CLK2” propagate to the generated clock application point so we
must determine why the master clock is not propagating. Check the select pin of the mux to see if it
has a constant value.

tv_shell > get_attribute [get_pins M1/SEL] constant_value

1

The mux select pin has a constant value of “1” indicating the “I1” pin is selected. Now trace the path to
see of port “clk1” is connected to the “I1” pin of the mux.

tv_shell > trace_path -from [get_ports clk1] -to [get_pins M1/I1]

No path is returned so the master clock of the mux pin where the master clock of the generated clock is
connected is not selected to propagate through the mux

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-WAV002 –id A0 –reason “None”
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 TimeVision Constraints User Guide
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-WAV002 -obj1 gclk -obj2 M1/Z -obj3 {-divide_by\ 1} -author "hollis" -date "07/10/14" -reason "None"

3.6.3 Rule CLK-WAV003

- div-N clock on combinational gate when master clock reaches the application point directly.

Description:
This rule identifies all “create_generated_clock” defined on combinational cells with a divide
by “N” where “N>1”, however, the master clock reaches the application point.

Design in figure 3.6.3 below shows timing points reported under rule CLK-WAV003

Figure 3.6.3
create_clock -name CLK1
[get_ports clk1] _
D Q
clk1 FF1
M1 Q
clk2
create_generated_clock -source [get_ports clk1]
create_clock -name CLK2
-divide_by 3 [get_pins M1/Z]
[get_ports clk2]

In the above designs, M1/Z has a generated clock with “-divide_by 3” defined, however the master
clock reaches the pin directly.
Therefore, “check_constraints” will report these ports under rule CLK-WAV003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV003 Error 1 0 Sdc.Clock/CLK-WAV003.rpt div-N clock on combinational gate when master clock reaches
the application point directly.

Sdc.Clock/CLK-WAV003.rpt :
# Rule: CLK-WAV003
# Severity: Error
# ==============================
#
# Design : top
# CLK-WAV003
# div-N clock on combinational gate when master clock reaches the application point directly.
#

A# Clock Clock ID Type App Point

-----------------------------------------------
A0 gclk 2 -divide_by 3 M1/Z
-----------------------------------------------

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 TimeVision Constraints User Guide
Debug
Get the “prop_clocks” attribute of the generated clock application point to see if the master clock
propagates to the pin.

tv_shell > get_attribute [get_pins M1/Z] prop_clocks

{ CLK1 CLK2 }

Indeed, one of the clocks propagating to the pin is the master clock of generated clock “gclk”. The
generated clock is defined with port “clk1” as the source. Check the name of the clock defined on port
“clk1”.

tv_shell > get_attribute [get_ports clk1] clocks

{ CLK1 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-WAV003 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-WAV003 -obj1 gclk -obj2 M1/Z -obj3 {-divide_by\ 3} -author "hollis" -date "07/10/14" -reason "None"

3.6.4 Rule CLK-WAV004

- div-N clock, N>2, on ICG when downstream contains both negative & positive elements.

Description:
This rule identifies all “create_generated_clock” defined on ICG cells with a divide by “N”
where “N>2”, and downstream consist of both positive and negative unate elements.

Design in figure 3.6.4 below shows timing points reported under rule CLK-WAV004

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 TimeVision Constraints User Guide
Figure 3.6.4

_
D Q
FF1
clk1 CK Q CLK Q
ICG1
create_clock -name CLK1 [get_ports clk1]
create_generated_clock -source [get_ports clk1] \
_
D Q
-divide_by 3 [get_pins ICG1/Q]
FF2
CLKN Q

In the above designs, ICG1/Q has a generated clock with “-divide_by 3” defined, the down stream cells
have both positive and negative unateness.
Therefore, “check_constraints” will report these ports under rule CLK-WAV004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV004 Error 2 0 Sdc.Clock/CLK-WAV004.rpt div-N clock, N>2, on ICG when downstream contains both
negative & positive
elements.

Sdc.Clock/CLK-WAV004.rpt :
# Rule: CLK-WAV004
# Severity: Error
# ==============================
#
# Design : top
# CLK-WAV004
# div-N clock, N>2, on ICG when downstream contains both negative & positive elements.
#

A# Clock Clock ID Type App Point

-------------------------------------------------------
A0 gclk 2 -divide_by 3 ICG1/Q
-------------------------------------------------------

Debug
It is necessary to find the leaf clock pins which create the positive and negative scenario. Source the
utilities script from the install directory:

tv_shell > source $install_path/scriptWare/ae_CLK_WAV004.tcl

Now execute the proc to return the clocks, the leaf clock pins, and the unateness.

tv_shell > ae_CLK_WAV004_debug

+-----------+-----------+
| CLOCK | gclk |
+-----------+-----------+
| UNATE | COUNT |
+-----------+-----------+
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 TimeVision Constraints User Guide
| POSITIVE | 1 |
+-----------+-----------+
| NEGATIVE | 1 |
+-----------+-----------+
********
POSITIVE
********
CLOCK --> gclk
FF1/CLK
********
NEGATIVE
********
CLOCK --> gclk
FF2/CLKN

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-WAV004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-WAV004 -obj1 gclk -obj2 ICG1/Q -obj3 {-divide_by\ 3} -author "hollis" -date "07/10/14" -reason "None"

3.6.5 Rule CLK-WAV005

- div-N clock, N>1, on Integrated clock gating latch.

Description:
This rule identifies all “create_generated_clock” defined on ICG cells with a divide by “N”
where “N>1”.

Design in figure 3.6.5 below shows timing points reported under rule CLK-WAV005

Figure 3.6.5

_
D Q
FF1
CLK-WAV005
clk1 CK
ICG1
Q B1 CLK Q
create_clock -name CLK1 [get_ports clk1]
create_generated_clock -source [get_ports clk1] \
-divide_by 2 [get_pins ICG1/Q]

In the above designs, ICG1/Q has a generated clock with “-divide_by 2” defined, the down stream cells
have both positive and negative unateness.
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 TimeVision Constraints User Guide
Therefore, “check_constraints” will report these ports under rule CLK-WAV005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV005 Error 1 0 Sdc.Clock/CLK-WAV005.rpt div-N clock, N>1, on Integrated clock gating latch.

Sdc.Clock/CLK-WAV005.rpt :
# Rule: CLK-WAV005
# Severity: Error
# ==============================
#
# Design : top
# CLK-WAV005
# div-N clock, N>2, on ICG elements.
#

A# Clock Clock ID Type App Point

-------------------------------------------------------
A0 gclk 2 -divide_by 2 ICG1/Q
-------------------------------------------------------

Debug
It is necessary to find the leaf clock pins which create the positive and negative scenario. Source the
utilities script from the install directory:

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (tests/check_cons_CLK-WAV005_test1.tcl:34:2) -name gclk -master CLK1 \
-source [get_ports clk1] -divide_by 2 [get_pins ICG1/Q]

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-WAV005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-WAV005 -obj1 gclk -obj2 ICG1/Q -author "hollis" -date "07/10/14" -reason "None"

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3.7 Incomplete generated clock rules

3.7.1 Rule CLK-IGC001

- Incomplete generated clock w.r.t. fastest incident clock

Description:
This rule identifies pins, where a correct but an incomplete set of “create_generated_clock”
definitions exist. Multiple master clocks reach these “create_generated_clock” points, but the
“create_generated_clock” is only defined w.r.t. a partial set of master clocks reaching these
points and the fastest clock does not have a generated clock defined.

Design in figure 3.7.1 below shows timing points reported under rule CLK-IGC001

Figure 3.7.1
create_clock -name CLK1 -period 2.7 [get_ports clk1]
_
D Q
clk1 FF1
M Q
clk2

create_clock -name CLK2 -period 5.25 [get_ports clk2]

create_generated_clock -name gclk -master CLK2

-source [get_ports clk2] [get_pins M/Z]

In the above designs, M/Z has only one generated clock defined, however, multiple master clocks reach
the generated clock application point, and the generated clock that is defined is not with respect to the
fastest master clock.

Therefore, “check_constraints” will report these ports under rule CLK-IGC001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-IGC001 Fatal 1 0 Sdc.Clock/CLK-IGC001.rpt Incomplete generated clock w.r.t. fastest incident clock

Sdc.Clock/CLK-IGC001.rpt :
# Rule: CLK-IGC001
# Severity: Fatal
# ==============================
#
# Design : top
# CLK-IGC001
# Incomplete generated clock w.r.t. fastest incident clock
#

A# App Point Clock

-----------------------
A0 M/Z CLK1
-----------------------
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 TimeVision Constraints User Guide
Debug
1) Get the “clocks” attribute of pin“FF1/CP” to determine all clocks propagated to the clock pin.

tv_shell > get_attribute [get_pins FF1/CP] clocks

{"CLK1","CLK2"}

2) Two clocks are propagated to the clock pin of the register. Now get the “clocks” attribute of
pin“FF1/Q” to determine all clocks on the pin.

tv_shell > get_attribute [get_pins FF1/Q] clocks

{"gclk"}

3) Only one master clock has a generated clock defined, so another generated clock need to be defined
relative to the other master clock. Now get the periods of the master clocks to see if the fastest one
has a generated clock.

tv_shell > get_attribute [get_clockss CLK1] period

{"2.7"}

tv_shell > get_attribute [get_clockss CLK2] period

{"5.25"}

4) The generated clock is defined relative to master clock CLK2, which is not the fastest master clock.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-IGC001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-IGC001 -obj1 M/Z -obj2 CLK1 -author "hollis" -date "07/10/14" -reason "None"

3.7.2 Rule CLK-IGC002

- Incomplete generated clock w.r.t. non-critical incident clock

Description:
This rule identifies pins, where a correct but an incomplete set of “create_generated_clock”
definitions exist. Multiple master clocks reach these “create_generated_clock” points, but the
“create_generated_clock” is only defined w.r.t. a partial set of master clocks reaching these
points, however, the fastest clock has a generated clock defined.

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 TimeVision Constraints User Guide
Design in figure 3.7.2 below shows timing points reported under rule CLK-IGC002

Figure 3.7.2

create_clock -name CLK1 -period 2.7 [get_ports clk1]

_
D Q
clk1 FF1
M Q
clk2

create_clock -name CLK2 -period 5.25 [get_ports clk2]

create_generated_clock -name gclk -master CLK1

-source [get_ports clk1] [get_pins M/Z]

In the above designs, M/Z has only one generated clock defined, however, multiple master clocks reach
the generated clock application point, but the generated clock that is defined is with respect to the
fastest master clock.
Therefore, “check_constraints” will report these ports under rule CLK-IGC002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-WAV002 Error 1 0 Sdc.Clock/CLK-WAV002.rpt div-1 or combinational clock on a combinational gate when no
clock reaches pin

Sdc.Clock/CLK-IGC002.rpt :
# Rule: CLK-IGC002
# Severity: Warning
# ==============================
#
# Design : top
# CLK-IGC002
# Incomplete generated clock w.r.t. non-critical incident clock
#
A# App Point Clock
-----------------------
A0 M/Z CLK2
-----------------------

Debug
1) Get the “clocks” attribute of pin“FF1/CP” to determine all clocks propagated to the clock pin.

tv_shell > get_attribute [get_pins FF1/CP] clocks

{"CLK1","CLK2"}

2) Two clocks are propagated to the clock pin of the register. Now get the “clocks” attribute of
pin“FF1/Q” to determine all clocks on the pin.

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 TimeVision Constraints User Guide
tv_shell > get_attribute [get_pins FF1/Q] clocks
{"gclk"}

3) Only one master clock has a generated clock defined, so another generated clock need to be defined
relative to the other master clock. Now get the periods of the master clocks to see if the fastest one
has a generated clock.

tv_shell > get_attribute [get_clockss CLK1] period

{"2.7"}

tv_shell > get_attribute [get_clockss CLK2] period

{"5.25"}

4) The generated clock is defined relative to master clock CLK1, which is the fastest master clock.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-IGC002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-IGC002 -obj1 M/Z -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"

3.8 Reconvergent clock rules

3.8.1 Rule CLK-RCN001

- Reconvergent clock path

Description:
This rule works in conjunction with the settings “Build/IntentionalCells”, which can be a regular
expression list of design intended cell names considered synthesized, and design intentional. Any
“Build/IntentionalCells” defined and violated reconvergence, will be reported under rule CLK-RCN001.
Any cells not listed in “Build/IntentionalCells”, and violates reconvergence will be reported in rule CLK-
RCN002. If “Build/IntentionalCells” is not set then all cells are considered intentional and reported
under rule CLK-RCN001.

Example usage of “Build/IntentionalCells”:

settings Build/IntentionalCells M.* }
Explaination of usage: Any cell matching the name “M.* and violates reconvergence will be reported
under rule CLK-RCN001, any cell not matching the name “M.*” and violates reconvergence will be
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 TimeVision Constraints User Guide
reported under rule CLK-RCN002.

Design in figure 3.8.1 below shows timing points reported under rule CLK- RCN001

Figure 3.8.1

settings Build/IntentionalCells {M.*} – mark every synthesized cells

with partial instance name “M” as design intentional

_
D Q

M1 Q
clk1 MB1 MB2

create_clock -name CLK1 [get_ports clk1]

In the above designs, MB1, MB2, M1, all match the partial name “M.*” and thus M1 would violate
reconvergence rule CLK-RCN001.

Therefore, “check_constraints” will report these ports under rule CLK-RCN001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-RCN002 Error 1 0 Sdc.Clock/CLK-RCN002.rpt Reconvergent clock path through synthesized logic

Sdc.Clock/CLK-RCN001.rpt :
# Rule: CLK-RCN001
# Severity: Warning
# ==============================
#
# Design : top
# CLK-RCN001
# Reconvergent clock path
#
A# Clock Reconvergent Point
--------------------------------
A0 CLK1 M1/Z
--------------------------------

Debug
1) Trace the path from the source of the clock which has the Reconvergence to the reported
reconvergent pin, with the option “max_path” set to at least 2.

tv_shell > trace_path -from [get_clocks CLK1] -to [get_pins M1/Z] -max_path 2
Point Type Flags
-------------------------------
clk1 (port) cs
M1/I0 CKMUX2D0 ~
M1/Z CKMUX2D0 ~

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Point Type Flags

-------------------------------
clk1 (port) cs
MB1/I BUFFD1 ~
MB1/Z BUFFD1 ~
MB2/I BUFFD1 ~
MB2/Z BUFFD1 ~
M1/I1 CKMUX2D0 ~
M1/Z CKMUX2D0 ~

2) In this case the paths converge at the output of a mux, to resolve this violation a “set_case_analysis”
should be applied to the select pin of the mux.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-RCN001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-RCN001 -obj1 M1/Z -author "hollis" -date "07/10/14" -reason "None"

3.8.2 Rule CLK-RCN002

- Reconvergent clock path through synthesized logic

Description:
This rule works in conjunction with the variable “design_intentional_cell_names”, which can be a
regular expression list of design intended cell names. Any “design_intentional_cell_names” defined
and violated reconvergence, will be reported under rule CLK-RCN001. Any cells not listed in
“design_intentional_cell_names”, and violates reconvergence will be reported in rule CLK-RCN002.

Example usage of “design_intentional_cell_names”:

set design_intentional_cell_names { .*BF.* }
Explaination of usage: Any cell matching the name “.*BF.*” and violates reconvergence will be
reported under rule CLK-RCN001, any cell not matching the name “.*BF.*” will be reported under rule
CLK-RCN002.

Design in figure 3.8.2 below shows timing points reported under rule CLK- RCN002

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 TimeVision Constraints User Guide Figure 3.8.2
set design_intentional_cell_names { .*BF.* } – mark every
synthesized cells with partial instance name “BF” as design
intentional
_
D Q

M1 Q BF1

clk1 BUF1 BUF2

create_clock -name CLK1 [get_ports clk1]

In the above designs, BUF1, BUF2, and M1 does not match the partial name “BF.*” and thus M1 would
violate reconvergence rule CLK-RCN002.

Therefore, “check_constraints” will report these ports under rule CLK-RCN002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-RCN002 Error 1 0 Sdc.Clock/CLK-RCN002.rpt Reconvergent clock path through synthesized logic

Sdc.Clock/CLK-RCN002.rpt :
# Rule: CLK-RCN002
# Severity: Error
# ==============================
#
# Design : top
# CLK-RCN002
# Reconvergent clock path through synthesized logic
#

A# Clock Reconvergent Point

--------------------------------
A0 CLK1 M1/Z
--------------------------------

Debug
1) Trace the path from the source of the clock which has the Reconvergence to the reported
reconvergent pin, with the option “max_path” set to at least 2.

tv_shell > trace_path -from [get_clocks CLK1] -to [get_pins M1/Z] -max_path 2
Point Type Flags
-------------------------------
clk1 (port) cs
M1/I0 CKMUX2D0 ~
M1/Z CKMUX2D0 ~

Point Type Flags

-------------------------------
clk1 (port) cs
BUF1/I BUFFD1 ~
BUF1/Z BUFFD1 ~
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BUF2/I BUFFD1 ~
BUF2/Z BUFFD1 ~
M1/I1 CKMUX2D0 ~
M1/Z CKMUX2D0 ~

2) In this case the paths converge at the output of a mux, to resolve this violation a “set_case_analysis”
should be applied to the select pin of the mux.

debug_rule –rule CLK-RCN002 –id A0

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-RCN002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-RCN002 -obj1 M1/Z -author "hollis" -date "07/10/14" -reason "None"

3.8.3 Rule CLK-PCN001

- Phase-reconvergent clock path

Description:
This rule works in conjunction with the settings “Build/IntentionalCells”, which can be a regular
expression list of design intended cell names considered synthesized, and design intentional. Any
“Build/IntentionalCells” defined and violated phase-reconvergence, will be reported under rule CLK-
PCN001. Any cells not listed in “Build/IntentionalCells”, and violates phase-reconvergence will be
reported in rule CLK-PCN002. If “Build/IntentionalCells” is not set then all cells are considered
intentional and reported under rule CLK-PCN001.

Example usage of “Build/IntentionalCells”:

settings Build/IntentionalCells M.* }
Explaination of usage: Any cell matching the name “M.* and violates phase-reconvergence will be
reported under rule CLK-PCN001, any cell not matching the name “M.*” and violates phase-
reconvergence will be reported under rule CLK-PCN002.

Design in figure 3.8.3 below shows timing points reported under rule CLK- PCN001

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 TimeVision Constraints User Guide
Figure 3.8.3
settings Build/IntentionalCells {M.*} – mark every synthesized cells
with partial instance name “M” as design intentional
_
D Q

M2 Q
clk1 MB1 MB2

create_clock -name CLK1 [get_ports clk1]

In the above designs, MB1, MB2, M1, all match the partial name “M.*” and thus M1 would violate
phase-reconvergence rule CLK-PCN001.

Therefore, “check_constraints” will report these ports under rule CLK-PCN001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-PCN001 Error 1 0 Sdc.Clock/CLK-PCN001.rpt Phase-reconvergent clock path

Sdc.Clock/CLK-PCN001.rpt :
# Rule: CLK-PCN001
# Severity: Error
# ==============================
#
# Design : top
# CLK-PCN001
# Phase-reconvergent clock path
#

A# Clock Reconvergent Point

--------------------------------
A0 CLK1 M2/Z
--------------------------------

Debug
1) Trace the path from the source of the clock which has the Phase Reconvergence to the reported
reconvergent pin, with the option “max_path” set to at least 2 and “-clock_phase” set to the clock in
violation.

tv_shell > trace_path -from [get_clocks CLK1] -to [get_pins M2/Z] -max_path 2 -clock_phase CLK1

Point Type Flags Phase

-------------------------------------------
clk1 (port) cs P
M2/I0 CKMUX2D0 ~ P
M2/Z CKMUX2D0 ~ N P

Point Type Flags Phase

----------------------------------------
clk1 (port) cs P
MB1/I BUFFD1 ~ P
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MB1/Z BUFFD1 ~ P
MB2/I INVD1 ~ P
MB2/Z INVD1 ~ N
M2/I1 CKMUX2D0 ~ N
M2/Z CKMUX2D0 ~ N P

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-PCN001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-PCN001 -obj1 M2/Z -author "hollis" -date "07/10/14" -reason "None"

3.8.4 Rule CLK-PCN002

- Phase-reconvergent clock path through synthesized logic

Description:
This rule works in conjunction with the variable “design_intentional_cell_names”, which can be a
regular expression list of design intended cell names. Any “design_intentional_cell_names” defined
and violated phase-reconvergence, will be reported under rule CLK-PCN001. Any cells not listed in
“design_intentional_cell_names”, and violates phase-reconvergence will be reported in rule
CLK-PCN002.

Example usage of “design_intentional_cell_names”:

set design_intentional_cell_names { .*BF.* }
Explaination of usage: Any cell matching the name “.*BF.*” and violates phase-reconvergence will be
reported under rule CLK-PCN001, any cell not matching the name “.*BF.*” will be reported under rule
CLK-PCN002.

Design in figure 3.8.4 below shows timing points reported under rule CLK- PCN002

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 TimeVision Constraints User Guide
Figure 3.8.4
set design_intentional_cell_names { .*BF.* } – mark every
synthesized cells with partial instance name “BF” as design
intentional
_
D Q

M2
Q BF2

clk1 BUF1 INV2

create_clock -name CLK1 [get_ports clk1]

In the above designs, BUF1, INV2, and M2 does not match the partial name “BF.*” and thus M2 would
violate phase-reconvergence rule CLK-PCN002.

Therefore, “check_constraints” will report these ports under rule CLK-PCN002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-PCN002 Error 1 0 Sdc.Clock/CLK-PCN002.rpt Phase-reconvergent clock path through synthesized logic

Sdc.Clock/CLK-PCN002.rpt :
# Rule: CLK-PCN002
# Severity: Error
# ==============================
#
# Design : top
# CLK-PCN002
# Phase-reconvergent clock path through synthesized logic
#
A# Clock Reconvergent Point
--------------------------------
A0 CLK1 M2/Z
--------------------------------

Debug
1) Trace the path from the source of the clock which has the Phase Reconvergence to the reported
reconvergent pin, with the option “max_path” set to at least 2 and “-clock_phase” set to the clock in
violation.

tv_shell > trace_path -from [get_clocks CLK1] -to [get_pins M2/Z] -max_path 2 -clock_phase CLK1

Point Type Flags Phase

-------------------------------------------
clk1 (port) cs P
M2/I0 CKMUX2D0 ~ P
M2/Z CKMUX2D0 ~ N P

Point Type Flags Phase

----------------------------------------
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 TimeVision Constraints User Guide
clk1 (port) cs P
MB1/I BUFFD1 ~ P
MB1/Z BUFFD1 ~ P
INV2/I INVD1 ~ P
INV2/Z INVD1 ~ N
M2/I1 CKMUX2D0 ~ N
M2/Z CKMUX2D0 ~ N P

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-PCN002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-PCN002 -obj1 M2/Z -author "hollis" -date "07/10/14" -reason "None"

3.9 Blocked clock rules

3.9.1 Rule CLK-BLK001

- create_clock blocks clock propagation

Description:
This rule identifies “create_clock” which blocks the propagation of other clocks beyond its
application point.

Design in figure 3.9.1 below shows timing points reported under rule CLK- BLK001

Figure 3.9.1

_
create_clock -name clka [get_pins B1/I] D Q

clk1 B1 Q
create_clock -name CLK1 [get_ports clk1]
create_clock -name clkb [get_pins B1/Z]

In the above designs, the create_clock defined on port clk1 is blocked by the create_clock defined at
the input of the buffer at “B1/I” and the create_clock defined on the buffer input “B1/I” is blocked but
the create_clock defined on the output of the buffer at “B1/Z”.

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 TimeVision Constraints User Guide
Therefore, “check_constraints” will report these ports under rule CLK-BLK001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-BLK001 Error 2 0 Sdc.Clock/CLK-BLK001.rpt create_clock blocks clock propagation

Sdc.Clock/CLK-BLK001.rpt :
# Rule: CLK-BLK001
# Severity: Error
# ==============================
#
# Design : top
# CLK-BLK001
# create_clock blocks clock propagation
#

A# Clock Clock ID Blocked Clock Blocked Clock ID App Point

------------------------------------------------------------------
A0 clka 2 CLK1 0 B1/I
A1 clkb 1 clka 2 B1/Z
------------------------------------------------------------------

Debug
1) Get the “printable” attribute of the blocking clock “clka” to confirm it is a “create_clock”.

tv_shell > get_attribute [get_clocks clka] printable

create_clock (design_data/CLK-BLK.sdc:2:2) -name clka -period 3.3 [get_pins B1/I]

2) Clock “clka” is a “create_clock”. Now trace the path from the blocked clock “CLK1” to the blocking
clock “clka” to confirm the blocking path.
tv_shell > trace_path -from [get_clocks CLK1] -to [get_clocks clka]

Point Type Flags

------------------------------
clk1 (port) cs
B1/I BUFFD1 cs ~

3) Clock “clka” is a “create_clock” defined on pin “B1/Z” blocking all other clock propagation from that
point forward.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

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Example:
set_waiver -rule CLK-BLK001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-BLK001 -obj1 clka -obj2 CLK1 -obj3 B1/A -author "hollis" -date "07/10/14" -reason "None"

3.9.2 Rule CLK-BLK002

- create_generated_clock blocks clock propagation

Description:
This rule identifies “create_generated_clock” which blocks the propagation of other clocks
beyond its application point.

Design in figure 3.9.2 below shows timing points reported under rule CLK- BLK002
Figure 3.9.2

create_generated_clock -source [get_ports clk1]

[get_pins M1/Z]

create_clock -name CLK1 [get_ports clk1]

_
D Q
clk1 FF1
M1 Q
_
clk2
D Q
create_clock -name CLK2 [get_ports clk2] FF1
B1 Q

create_generated_clock -source [get_ports clk2]

[get_pins B1/Z]

In the above designs, the create_generated_clock defined on ports M1/Z blocks clock CLK2 so the
generated clock defined on pin B1/Z does not have a path to its master.

Therefore, “check_constraints” will report these ports under rule CLK-BLK002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-BLK002 Warning 1 0 Sdc.Clock/CLK-BLK002.rpt create_generated_clock blocks clock propagation

Sdc.Clock/CLK-BLK002.rpt :
# Rule: CLK-BLK002
# Severity: Warning
# ==============================
#
# Design : top
# CLK-BLK002
# create_generated_clock blocks clock propagation
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#

A# Generated Clock Clock ID Blocked Clock Blocked Clock ID App Point

----------------------------------------------------------------------------
A0 gclk 2 CLK2 1 M1/Z
----------------------------------------------------------------------------

Debug
1) Get the “printable” attribute of the blocking clock “gclk” to confirm it is a “create_generated_clock”.

tv_shell > get_attribute [get_clocks gclk] printable

create_generated_clock (design_data/CLK-BLK.sdc:11:2) -name gclk -source [get_ports clk1] \
-divide_by 1 [get_pins M1/Z]

2) Clock “gclk” is a “create_generated_clock”. Now trace the path from the blocked clock “CLKL2” to
the blocking clock “gclk” to confirm the blocking path.

tv_shell > trace_path -from [get_clocks CLK2] -to [get_clocks gclk]

Point Type Flags

----------------------------------
clk1 (port) cs
M1/I1 CKMUX2D0 ~
M1/Z CKMUX2D0 cs~

3) Clock “gclk” is a “create_generated_clock” defined on pin “M1/Z” blocking all other clock
propagation from that point forward.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-BLK002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-BLK002 -obj1 gclk -obj2 CLK2 -obj3 M1/Z -author "hollis" -date "07/10/14" -reason "None"

3.10 Clock object rule

3.10.1 Rule CLK-OBJ001

- clock network gate is not of allowable type

Description:
This rule identifies any celltypes in the clock path that does not match the intended clock cells specified
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in variable “design_intentional_clock_library_cells” or “Build/IntentionalClockLibraryCells”

Design in figure 3.10.1 below shows timing points reported under rule CLK-OBJ001

Figure 3.10.1

settings Build/IntentionalClockLibraryCells
"BUF_X8" – marks clock cell “BUF_X8” as the
only allowably clock cell in the clock path
_
D Q

clk1 B1 B2 Q
create_clock -name CLK1 [get_ports clk1]
Is cell type BUF_X8 Is cell type BUF_X32

In the above designs, the second buffer is of celltype “BUF_X32” and therefore does not match the
intended celltype variable.

Therefore, “check_constraints” will report these ports under rule CLK-OBJ001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-OBJ001 Warning 1 0 Sdc.Clock/CLK-OBJ001.rpt clock network gate is not of allowable type.

Sdc.Clock/CLK-OBJ001.rpt :
# Rule: CLK-OBJ001
# Severity: Warning
# ==============================
#
# Design : top
# CLK-OBJ001
# Clock network contains cells not in the 'design_intentional_clock_network_cells'
# set of regular expressions for allowable library cells in the network.
#

A# Clock Clock ID Clock Network Node Lib Cell

--------------------------------------------------------------------
A0 CLK1 0 B2 BUF_X32
--------------------------------------------------------------------

Debug
Check the value of the variable “design_intentional_clock_library_cells”.

tv_shell > puts $design_intentional_clock_library_cells

BUF_X8

The user has specified that only celltype BUF_X8 are allowed in the clock network, so any other celltype
will be reported as violation.

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Trace the clock path to see if the cell is in the clock network.

tv_shell > trace_path -from [get_clocks CLK1]

Point Type Flags

--------------------------------------------
(Unconstrained Startpoint)
CLK1 (port) cs
B1/I BUF_X8 ~
B1/Z BUF_X8 ~
B2/I BUF_X32 ~
B2/Z BUF_X32 ~
FF1/CK DFF_X1 ~

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-OBJ001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-OBJ001 -obj1 CLK1 -obj2 B2 -obj3 BUF_X32 -author "hollis" -date "07/10/14" -reason "None"

3.10.2 Rule CLK-OBJ002

- clock is defined on hierarchical (logical) pin

Description:
This rule identifies identifies create_clocks or create_generated_clocks which are defined on
hierarchical (logical) pins.

Design in figure 3.10.2 below shows timing points reported under rule CLK-OBJ001

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 TimeVision Constraints User Guide
Figure 3.10.2
blk

b1 _
din
D Q
bf1
clk b0 Q dou t

create_clock -name HCLK -period 1.0 [ get_pins u_blk/hclk ]

In the above designs, HCLK is defined on hierarchical pin u_blk/hclk.

Therefore, “check_constraints” will report these ports under rule CLK-OBJ002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-OBJ002 Warning 1 0 Sdc.Clock/CLK-OBJ002.rpt clock is defined on hierarchical (logical) pin.

Sdc.Clock/CLK-OBJ002.rpt :
# Rule: CLK-OBJ002
# Severity: Warning
# ==============================
#
# Design : top
# CLK-OBJ002
# clock is defined on hierarchical (logical) pin.
#

A# Clock Clock ID Hierarchical Pin

-------------------------------------------------
A0 HCLK 0 u_blk/hclk
------------------------------------------------

Debug
Check the attribute “app_clocks” on the hierarchical pin to confirm a clock is applied.

tv_shell > get_attribute [get_pins u_blk/hclk] app_clocks

{ HCLK }

“HCLK” is returnes as the clock defined on the hierarchical pin.

Waivers
Any reported violation can be waived using the “set_waiver” command.

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Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-OBJ002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-OBJ002 -obj1 HCLK -obj2 u_blk/hclk -author "hollis" -date "05/06/15" -reason "None"

3.11 Clock data rules

3.11.1 Rule CLK-DATA01

- First gating pin of data network

Description:
This rule identifies “pins” at which a clock network becomes a data network.
Design in figure 3.11.1 below shows pins reported under rule CLK-DATA01. The purpose of identifying
these pins is to manage CTS implementation, and disable all clock gating checks at these pins. Basically,
beyond at these pins and beyond, it is not a clock network any longer, and can be traded as such. If a
designer instantiates such logic in the RTL or netlist intentionally, using certain .lib cells or instance
names, these intentional .lib cell names or instance names can be specified using variables, for
example:

set design_intentional_library_cell_names { .*CKAND.* }

set design_intentional_cell_names { .*CLK.*}

If either of these variables is defined, all clock network to data network cells/pins which match these
variables are considered as “intentional”, and are reported by rule CLK-DATA01. All other clock network
to data network cells/pins not matching these variables are considered as “synthesized”
(unintentional), and reported by rule CLK-DATA02.

If neither of these variables is defined, for RTL designs, Timevision can auto determine which cells are
synthesized (CLK-DATA02), and which cells are not (CLK-DATA01). However, for gate/netlist designs, all
clock network to data network cells/pins variables are considered “intentional” by default, and
reported by rule CLK-DATA01.

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Figure 3.11.1
module top ff3 ## SDC:
din2 create_clock -name sclk -period 3.0 \
A1
{sclk}
A2 `
U128
sreg0 create_clock -name LV_clk -period 8.0 \
ff4
{LV_clk}

din3

LV_reg0
`

ckmux ff1 Output of the A2 pins of

sclk
0 ckbuf these gates are “data”
LV_clk A1 networks (driving no leaf
1 A2
` clock pins). The input to
U_ckand1 A2 pins of these gates are
csel ff2 “clock” network (driving
leaf clock pins). Hence, A2
pins of these gates are
din1 identified by rule
CLK-DATA01

In the above design, U128/A2 and U_ckand1/A2 are pins at which a clock network becomes a data
network, since all fanout endpoints from these two pins are non-clock endpoints. Therefore, these two
pins are reported by rule CLK-DATA-01.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-DATA01 Warning 4 0 Sdc.Clock/CLK-DATA01.rpt First gating pin of data network

Sdc.Clock/CLK-DATA01.rpt :
# Rule: CLK-DATA01
# Severity: Warning
# ==============================
#
# Design : top
# CLK-DATA01
# First gating pin of data network
# Severity: Warning
# ==============================
#
# Violations

A# Clock Data Network Gater

---------------------------------
A0 LV_clk U_ckand1/A2
A1 LV_clk U128/A2
A2 sclk U_ckand1/A2
A3 sclk U128/A2
---------------------------------

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Debug
1) Find all “data” endpoints from this pin – some pins should be returned:
tv_shell [6] > all_fanout -from U_ckand1/A2 -end -filter "is_data_pin == 1"
{ ff1/D ff2/D }

2) Find all “clock” endpoints from this pin – nothing should be returned:
tv_shell [7] > all_fanout -from U_ckand1/A2 -end -filter "is_clock_pin == 1"

tv_shell [8] >

Waivers
Any reported violation can be waived using the “set_waiver” command.
Example:
set_waiver -rule CLK-DATA01 –id {A0 A1} –reason “Bist clock, don’t care”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-DATA01 -obj1 LV_clk -obj2 U_ckand1/A2 -author "atul" -date "08/04/14" -
reason "Bist clock, don't care"

set_waiver -rule CLK-DATA01 -obj1 LV_clk -obj2 U128/A2 -author "atul" -date "08/04/14" -
reason "Bist clock, do't care"

3.11.2 Rule CLK-DATA02

- First gating pin of data network is synthesized

Description:
This rule identifies synthesized “pins” at which a clock network becomes a data network.
Design in figure 3.11.2 below shows pins reported under rule CLK-DATA02. The purpose of identifying
these pins is to manage CTS implementation, and disable all clock gating checks at these pins. Basically,
beyond at these pins and beyond, it is not a clock network any longer, and can be traded as such. If a
designer instantiates such logic in the RTL or netlist intentionally, using certain .lib cells or instance
names, these intentional .lib cell names or instance names can be specified using variables, for
example:

set design_intentional_library_cell_names { .*CKAND.* }

set design_intentional_cell_names { .*CLK.*}

If either of these variables is defined, all clock network to data network cells/pins which match these
variables are considered as “intentional”, and are reported by rule CLK-DATA01. All other clock network
to data network cells/pins not matching these variables are considered as “synthesized”
(unintentional), and reported by rule CLK-DATA02.

If neither of these variables is defined, for RTL designs, Timevision can auto determine which cells are
synthesized (CLK-DATA02), and which cells are intentional (CLK-DATA01). However, for gate/netlist
designs, all clock network to data network cells/pins variables are considered “intentional”, and
reported by rule CLK-DATA01.

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Figure 3.11.2
## Design setup:
set design_intentional_cell_names { .*ck.* }
module top ff3
## SDC:
din2 create_clock -name sclk -period 3.0{sclk}
A1
A2 ` create_clock -name LV_clk -period 8.0 {LV_clk}
U128
sreg0
ff4
Output of this gate is a “data” network –
driving no leaf clock pins. The input to this
din3 gate is a “clock” network. Moreover, this cell is
not specified in either of these variables:
LV_reg0 set design_intentional_cell_names
` set design_intentional_library_cell_names

ckmux ff1 Hence, it is reported by rule CLK-DATA02

sclk
0 ckbuf
A1
LV_clk
1 A2
` set design_intentional_cell_names {*.ck*.}
U_ckand1
csel ff2 Therefore, U_ckand1 is considered as intentional,
and *NOT* reported by rule CLK-DATA02

din1

In the above design, U128/A2 and U_ckand1/A2 are pins at which a clock network becomes a
data network, since all fanout endpoints from these two pins are non-clock endpoints.
However, “U_ckand1/A2” is specified as an intentional cell using command:

set design_intentional_cell_names { .*ck.* }

Therefore, only “U128/A2” is considered synthesizable, and reported as rule CLK-DATA02.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-DATA02 Error 2 0 Sdc.Clock/CLK-DATA02.rpt First gating pin of data network is synthesized

Sdc.Clock/CLK-DATA02.rpt :
# Rule: CLK-DATA02
# Severity: Warning
# =============================================
# Design : top
# CLK-DATA02
# First gating pin of data network is synthesized
# Severity: Error
# =============================================
#
# Violations
A# Clock Data Network Gater
---------------------------------
A0 LV_clk U128/A2
A1 sclk U128/A2
---------------------------------
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Debug
1) Find all “data” endpoints from this pin – some pins should be returned:
tv_shell [6] > all_fanout -from U128/A2 -end -filter "is_data_pin == 1"
{ ff3/D ff4/D }

2) Find all “clock” endpoints from this pin – nothing should be returned:
tv_shell [7] > all_fanout -from U_ckand1/A2 -end -filter "is_clock_pin == 1"

tv_shell [8] >

Waivers
Any reported violation can be waived using the “set_waiver” command.
Example:
set_waiver -rule CLK-DATA02 –id {A0} –reason “Bist clock, don’t care”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-DATA02 -obj1 LV_clk -obj2 U128/A2 -author "atul" -date "08/04/14" -
reason "Bist clock, don't care"

3.11.3 Rule CLK-DATA03

- Clock drives data pins

Description:
This rule identifies all clocks sources which drive data pins. The following are excluded:
1. Data pins of clock divider flop driven by generated clock source points.
2. Output ports driven by generated clock source points.
## SDC
create_clock -name sclk -period 3.0 {sclk}
create_clock -name LV_clk -period 8.0 {LV_clk}
create_clock –name clkin –period 4.5 {clkin}

create_generated_clock –name sclk_div2 –divide_by 2 \

–source [get_port {sclk}] [get_pins {ck_div_reg/Q}]

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Figure 3.11.3

module top
clkin clkout

din2 ff3

ckinv
Clock “clkin” drives output
port “clkout”. Not reported
by CLK-DATA03
ck_div_reg
`

ckmux ff1
sclk
0 ckbuf Clock “sclk_div2” feedbacks
LV_clk to its own divider flop D pin
1 Not reported by CLK-DATA03
U_ckand1
csel ff2

din1

Clocks “sclk” and “LV_clk” drive leaf data

pins of flops. Hence. these clocks are
reported by CLK-DATA03

In the above design, clocks “sclk” and “LV_clk” drive data pins, and therefore and reported as
rule CLK-DATA03. Note that:

1. clock “clkin” drives output port “clkout”, and therefore not reported under CLK-DATA03.

2. generated clock “sclk_div2” drives data pin of the clock divider flop, which is also not
reported under CLK-DATA03.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-DATA03 Warning 2 0 Sdc.Clock/CLK-DATA03.rpt Clock drives data pins

Sdc.Clock/CLK-DATA03.rpt :
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 TimeVision Constraints User Guide
# Rule: CLK-DATA03
# Severity: Warning
# =============================================
# Design : top
# CLK-DATA03
# Clock drives data pins
# Severity: Warning
# =============================================
# Violations
A# Clock
----------------
A0 LV_clk
A1 sclk
----------------

Debug
1) Find where the reported clock is defined:
tv_shell [6] > get_attr [get_clocks sclk] sources
{ sclk }

2) Find all “data” endpoints from this clock definition point:

tv_shell [7] > all_fanout -from sclk -end -filter "is_data_pin == 1"
{ ff1/D ff2/D }

Waivers
Any reported violation can be waived using the “set_waiver” command.
Example:
set_waiver -rule CLK-DATA03 –id {A0} –reason “Bist clock, don’t care”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-DATA03 -obj1 LV_clk -obj2 LV_clk -author "atul" -date "08/04/14" -reason
"Bist clock, don't care"

3.12 Clock merging point rules

3.12.1 Rule CLK-MRG01

- Clock merging point

Description:
This rule identifies clock merge points where two or more clocks converge and the convergent point
drives a leaf clock pin or an output port.

Design in figure 3.12.1.1 below shows points reported under rule CLK-MRG01, and an example of a
point not reported under rule CLK-MRG01.

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Figure 3.12.1.1
Clock Merge
clk1
Point

create_clock -name CLK1 M1 _

D Q
[get_ports clk1]
clk2 M2 FF1
create_clock -name CLK2 M3 Q
[get_ports clk2]

clk3

create_clock -name CLK3 _

[get_ports clk3]
D Q
FF2
clk4

create_clock -name CLK4

Q
[get_ports clk4]

Figure 3.12.1.2
Clock Merge
Point

OUT1
clk1 A1
OR1
A0 A1
A2
create_clock -name CLK1 OR2
A0 A1 _
[get_ports clk1]
A2
OR3
A2
A0 D Q
clk2
FF1
create_clock -name CLK2
[get_ports clk2] Q
clk3

create_clock -name CLK3

[get_ports clk3]
clk4

create_clock -name CLK4

[get_ports clk4]

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Figure 3.12.1.3
Not a Clock
clk1
Merge Point

create_clock -name CLK1 M1

[get_ports clk1]
clk2 M2
_
create_clock -name CLK2 M3 D Q
[get_ports clk2]
FF1
clk3
Q
create_clock -name CLK3
[get_ports clk3]
clk4

create_clock -name CLK4

[get_ports clk4]

In the above designs, Figures 3.12.1.1 and 3.12.1.2 shows clock merge points at the output of mux
“M3” and the output of “OR3” because “M3” drive a leaf clock pin and “OR3” drive an output port
“OUT1”. However, Figure 3.12.1.3 shows an example of a point that is not considered to be a clock
merge point because neither mux drives a leaf clock pin nor an output port.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MRG01 Info 2 0 Sdc.Clock/CLK-MRG01.rpt clock merging point

Sdc.Clock/CLK-MRG01.rpt :
# Rule: CLK-MRG001
# Severity: Info
# ==============================
#
# Design : top
# CLK-MRG01
# Clock merging point
# Severity: Info
#
# ==============================
#
# Violations
#

A# MergePoint Clock Clock

-------------------------------
A0 M3/Z
A1 OR3/Z
-------------------------------
Debug
1) Get attribute “clocks” to confirm multiple clocks indeed converge at the merge point.

tv_shell > get_object_name [get_attribute [get_pins M3/Z] clocks]

CLK1 CLK2 CLK3 CLK4

tv_shell > get_object_name [get_attribute [get_pins OR3/Z] clocks]

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CLK1 CLK2 CLK3 CLK4

2) Confirm that each merge point drives a leaf clock pin or a port.

tv_shell > get_object_name [all_fanout -from M3/ZN -end \

-filter "is_clock_pin || is_port"]
FF1/CK

tv_shell > get_object_name [all_fanout -from OR3/ZN -end \

-filter "is_clock_pin || is_port"]
OUT1

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-MRG01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-MRG01 -obj1 M3/Z -author "hollis" -date "07/10/14" -reason "None"

3.12.2 Rule CLK-MRG02

- Clock merging point is synthesized

Description:
This rule identifies clock merge points where two or more clocks converge and the convergent point
drives a leaf clock pin or an output port, and is not a design intentional cell.

Design in figure 3.12.2.1 below shows points reported under rule CLK-MRG02 because it does not
match the criteria listed in “set_design_intentional_cell_names” variable.

Design in figure 3.12.2.2 below shows points reported under rule CLK-MRG01 because it does match
the criteria listed in “set_design_intentional_cell_names” variable.

Design in figure 3.12.2.3 below shows points not reported under rule CLK-MRG01 nor CLK-MRG02 even
though it matches the criteria listed in “set_design_intentional_cell_names” variable. However, it does
not drive a leaf clock pin nor an output port.

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Figure 3.12.2.1

Synthesized Clock Merge Point Reported In Rule CLK-MRG02

OUT1
clk1 A1
OR1
A0 A1
A2
create_clock -name CLK1 OR2
A0 A1 _
[get_ports clk1]
A2
OR3
A2
A0 D Q
clk2
FF1
create_clock -name CLK2
[get_ports clk2] Q
clk3

create_clock -name CLK3

[get_ports clk3]
clk4

create_clock -name CLK4

[get_ports clk4]

Figure 3.12.2.2

set_design_intentional_cell_names { .*M.* } Clock Merge Point Reported

clk1
in Rule CLK-MRG01

create_clock -name CLK1 M1 _

D Q
[get_ports clk1]
clk2 M2 FF1
create_clock -name CLK2 M3 Q
[get_ports clk2]

clk3

create_clock -name CLK3 _

[get_ports clk3]
D Q
FF2
clk4

create_clock -name CLK4

Q
[get_ports clk4]

Figure 3.12.2.3 Not a Clock

clk1
Merge Point

create_clock -name CLK1 M1

[get_ports clk1]
clk2 M2
_
create_clock -name CLK2 M3 D Q
[get_ports clk2]
FF1
clk3
Q
create_clock -name CLK3
[get_ports clk3]
clk4

create_clock -name CLK4

[get_ports clk4]
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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-MRG02 Error 1 0 Sdc.Clock/CLK-MRG02.rpt clock merging point is synthesized

Sdc.Clock/CLK-MRG02.rpt :
# Rule: CLK-MRG002
# Severity: Error
# ==============================
#
# Design : top
# CLK-MRG02
# Clock merging point is synthesized
# Severity: Error
#
# ==============================
#
# Violations
#

A# MergePoint Clock Clock

-------------------------------
A0 OR3/Z
-------------------------------

Debug
1) Get attribute “clocks” to confirm multiple clocks indeed converge at the merge point.

tv_shell > get_object_name [get_attribute [get_pins OR3/Z] clocks]

CLK1 CLK2 CLK3 CLK4

2) Confirm that each merge point drives a leaf clock pin or a port.
tv_shell > get_object_name [all_fanout -from OR3/ZN -end \
-filter "is_clock_pin || is_port"]
OUT1

3) Confirm the cell does not match the “design_intentional_cell_names” variable criteria.
tv_shell > puts $design_intentional_cell_names

.*M.*

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

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Example:
set_waiver -rule CLK-MRG02 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-MRG02 -obj1 OR3/Z -author "hollis" -date "07/10/14" -reason "None"

3.13 Incorrect clock groups and interclock false path rule with paths

3.13.1 Rule CGWP-INC001/ICFP-INC001

- Incorrect set_clock_groups, sync. clocks/Incorrect interclock false path, synchronous

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and have logic paths between them in the unique-to-unique domain.

Design in figure 3.13.1 below shows timing points reported under rule CGWP-INC001/ICFP-INC001
Synchronous – with logic paths
Figure 3.13.1
PLL 0

CLKA
CLKA

÷2
CLKA_div2

CLKA_div2

set_clock_group -group CLKA -group CLKA_div2

set_false_path -from CLKA -to CLKA_div2
In the above designs, CLKA_div2 is a divided clock of CLKA and the green arrow indicates there are
paths between the clock domains, and there is either a set_clock_group or set_false_path between
them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC001/ICFP-INC001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC001 Fatal 1 0 Sdc.Interclock/ICFP-INC001.rpt Incorrect interclock false path, synchronous
CGWP-INC001 Fatal 1 0 Sdc.Interclock/CGWP-INC001.rpt Incorrect set_clock_groups , sync. clocks

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Sdc.Clock/ICFP-INC001.rpt :
# Rule: ICFP-INC001
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC001
# Incorrect interclock false path, synchronous
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

------------------------------------------------------------
A0 CLKA 7 CLKA_div2 9
------------------------------------------------------------

Sdc.Clock/CGWP-INC001.rpt :
# Rule: CGWP-INC001
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC001
# Incorrect set_clock_groups , sync. clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

-----------------------------------------------------------
A0 CLKA 1 CLKA_div2 3
----------------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKA_div2}

sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKA_div2}

#####################################################################
## RELATIONSHIP TYPE: sync
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Generated Clock " CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

Note that in this portion of the report above clock CLKA_div2 is a generated clock of CLKA.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.
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tv_shell > get_constraints -clock {CLKA CLKA_div2} -type set_clock_group
{ set_clock_group5 set_clock_group6 }
4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 5] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:12:5) -asynchronous \
-group [get_clocks { CLKA }] -group [get_clocks { CLKA_div2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC001 –id A0 –reason “None”
set_waiver -rule CGWP-INC001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC001 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC001 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.13.2 Rule CGWP-INC002/ICFP-INC002

- Incorrect set_clock_groups , sync. + le clocks (paths from/to common domain)/ Incorrect
interclock false path, synchronous logically-exclusive, unique<->common

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and have logic paths in the common domain, and paths in the unique-to-common and
common-to-unique domains.
Design in figure 3.13.2 below shows timing points reported under rule CGWP-INC002/ICFP-INC002

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Figure 3.13.2

Logically Exclusive – tocommon synchronous

PLL 0

CLKA

÷2
CLKA_div2

1 0

CLKA + CLKA_div2 CLKA_div2

CLKA
COMMON UNIQUE
UNIQUE

set_clock_group -group CLKA -group CLKA_div2

set_false_path -from CLKA -to CLKA_div2

In the above designs, CLKA_div2 is a divided clock of CLKA and the green arrows indicates there are
paths between the unique-common, common-unique, and within common, and there is either a
set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC002/ICFP-INC002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC002 Fatal 1 0 Sdc.Interclock/ICFP-INC002.rpt Incorrect interclock false path, synchronous
logically-exclusive, unique<->common
CGWP-INC001 Fatal 1 0 Sdc.Interclock/CGWP-INC002.rpt Incorrect set_clock_groups , sync. + le clocks
(paths from/to common domain)
Sdc.Clock/ICFP-INC002.rpt :
# Rule: ICFP-INC002
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC002
# Incorrect interclock false path, synchronous logically-exclusive, unique<->common
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKA_div2 5
--------------------------------------------------

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Sdc.Clock/CGWP-INC002.rpt :
# Rule: CGWP-INC002
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC002
# Incorrect set_clock_groups , sync. + le clocks (paths from/to common domain)
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKA_div2 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKA_div2}

logically_exclusive:tocommon:sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKA_div2}

#####################################################################
## RELATIONSHIP TYPE: sync , logically_exclusive
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Generated Clock " CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
PLL0/clk_out PLL
buf0/A BUF_X1
buf0/Z BUF_X1
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKA_div2" path to Converge Point:

f4/Q DFF_X1
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA_div2 is a generated clock of CLKA and they are
logically exclusive in that they both are inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.
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tv_shell > get_constraints -clock {CLKA CLKA_div2} -type set_clock_group
{ set_clock_group6 set_clock_group9 }
4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 6] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:17:6) -logically_exclusive \
-group [get_clocks { CLKA }] -group [get_clocks { CLKA_div2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC002 –id A0 –reason “None”
set_waiver -rule CGWP-INC002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC002 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC002 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.13.3 Rule CGWP-INC003/ICFP-INC003

- Incorrect set_clock_groups , sync. + le clocks (paths in cross domain)/ Incorrect interclock false
path, synchronous logically-exclusive, unique<->unique

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and have logic paths in the common domain, and paths in the cross (unique-to-unique)
domain.
Design in figure 3.13.3 below shows timing points reported under rule CGWP-INC003/ICFP-INC003

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Figure 3.13.3
Logically Exclusive – cross synchronous

PLL 0

CLKA

÷2
CLKA_div2

1 0

CLKA + CLKA_div2 CLKA_div2

CLKA
COMMON UNIQUE
UNIQUE

set_clock_group -group CLKA -group CLKA_div2

set_false_path -from CLKA -to CLKA_div2

In the above designs, CLKA_div2 is a divided clock of CLKA and the green arrows indicates there are
paths between the unique-unique and within common, and there is either a set_clock_group or
set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC003/ICFP-INC003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC003 Fatal 1 0 Sdc.Interclock/ICFP-INC003.rpt Incorrect interclock false path, synchronous
logically-exclusive, unique<->unique
CGWP-INC003 Fatal 2 0 Sdc.Interclock/CGWP-INC003.rpt Incorrect set_clock_groups , sync. + le clocks
(paths in cross domain)

Sdc.Clock/ICFP-INC003.rpt :
# Rule: ICFP-INC003
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC003
# Incorrect interclock false path, synchronous logically-exclusive, unique<->unique
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKA_div2 5
--------------------------------------------------
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Sdc.Clock/CGWP-INC003.rpt :
# Rule: CGWP-INC003
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC003
# Incorrect set_clock_groups , sync. + le clocks (paths in cross domain)
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKA_div2 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKA_div2}

logically_exclusive:cross:sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKA_div2}

#####################################################################
## RELATIONSHIP TYPE: sync , logically_exclusive
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Generated Clock " CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
PLL0/clk_out PLL
buf0/A BUF_X1
buf0/Z BUF_X1
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKA_div2" path to Converge Point:

f4/Q DFF_X1
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA_div2 is a generated clock of CLKA and they are
logically exclusive in that they both are inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

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tv_shell > get_constraints -clock {CLKA CLKA_div2} -type set_clock_group
{ set_clock_group4 set_clock_group5 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 4] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:13:5) -logically_exclusive \
-group [get_clocks { CLKA }] -group [get_clocks { CLKA_div2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC003 –id A0 –reason “None”
set_waiver -rule CGWP-INC003 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC003 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC003 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.13.4 Rule CGWP-INC004/ICFP-INC004

- Incorrect set_clock_groups , sync. + le clocks (paths in from/to common + cross domain)/
Incorrect interclock false path, synchronous logically-exclusive, unique<->unique/common

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and have logic paths in the common domain, cross (unique-to-unique) domain, and in the
common-to-unique/unique-to-common domains.

Design in figure 3.13.4 below shows timing points reported under rule CGWP-INC004/ICFP-INC004

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Figure 3.13.4
Logically Exclusive – combo synchronous

PLL 0

CLKA

÷2
CLKA_div2

1 0

CLKA + CLKA_div2 CLKA_div2

CLKA COMMON UNIQUE
UNIQUE

set_clock_group -group CLKA -group CLKA_div2

set_false_path -from CLKA -to CLKA_div2

In the above designs, CLKA_div2 is a divided clock of CLKA and the green arrows indicates there are
paths between the unique-unique, unique-common, common-unique, nad within common, and there
is either a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC004/ICFP-INC004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC004 Fatal 1 0 Sdc.Interclock/ICFP-INC004.rpt Incorrect interclock false path, synchronous
logically-exclusive, unique<->unique/common
CGWP-INC004 Fatal 1 0 Sdc.Interclock/CGWP-INC004.rpt Incorrect set_clock_groups , sync. + le clocks
(paths in from/to common + cross domain)

Sdc.Clock/ICFP-INC004.rpt :
# Rule: ICFP-INC004
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC004
# Incorrect interclock false path, synchronous logically-exclusive, unique<->unique/common
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKA_div2 5
--------------------------------------------------
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Sdc.Clock/CGWP-INC004.rpt :
# Rule: CGWP-INC004
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC004
# Incorrect set_clock_groups , sync. + le clocks (paths in from/to common + cross domain)
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKA_div2 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKA_div2}

logically_exclusive:combo:sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKA_div2}

#####################################################################
## RELATIONSHIP TYPE: sync , logically_exclusive
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Generated Clock " CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
PLL0/clk_out PLL
buf0/A BUF_X1
buf0/Z BUF_X1
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKA_div2" path to Converge Point:

f4/Q DFF_X1
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA_div2 is a generated clock of CLKA and they are
logically exclusive in that they both are inputs to the same mux.

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 TimeVision Constraints User Guide
3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock {CLKA CLKA_div2} -type set_clock_group

{ set_clock_group9 set_clock_group15 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 15] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:33:55) -logically_exclusive \
-group [get_clocks { CLKA }] -group [get_clocks { CLKA_div2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC004 –id A0 –reason “None”
set_waiver -rule CGWP-INC004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC004 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC004 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.13.5 Rule CGWP-INC005/ICFP-INC005

- Incorrect set_clock_groups , sync. + le through inheritance clocks/Incorrect interclock false
path, synchronous LE inheritance.

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and inherits logical exclusivity from the parent clocks.

Design in figure 3.13.5 below shows timing points reported under rule CGWP-INC005/ICFP-INC005

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 TimeVision Constraints User Guide

Figure 3.13.5

Logically Exclusive Synchronous - Inheritance

_
D Q
CLKA
PLL 0 0
CLKA_div2 (master_clock “CLKA”) CLKA_div2
Q CLKA_slow_div2 (master_clock “CLKA_slow”) CLKA_slow_div2
1
÷2

CLKA_slow
CLKA_slow
UNIQUE
set_clock_group -group CLKA_slow -group CLKA_div2

In the above designs, CLKA_slow is a divided clock of CLKA, and they have a logically exclusive
relationship. Both parent clocks have child clocks defined and their child clocks inherit logical
exclusivity. The green arrows indicates there are paths between them , and there is either a
set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC005/ICFP-INC005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC005 Fatal 1 0 Sdc.Interclock/ICFP-INC005.rpt Incorrect interclock false path, synchronous LE
inheritance
CGWP-INC005 Fatal 1 0 Sdc.Interclock/CGWP-INC005.rpt Incorrect set_clock_groups , sync. + le through
inheritance clocks

Sdc.Clock/ICFP-INC005.rpt :
# Rule: ICFP-INC005
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC005
# Incorrect interclock false path, synchronous LE inheritance
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA_div2 5 CLKA_slow_div2 6
--------------------------------------------------

Sdc.Clock/CGWP-INC005.rpt :
# Rule: CGWP-INC005
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC005
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 TimeVision Constraints User Guide
# Incorrect set_clock_groups , sync. + le through inheritance clocks
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA_div2 1 CLKA_slow_div2 2
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA_div2 CLKA_slow_div2}

logically_exclusive:inherit:sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA_div2 CLKA_slow_div2}

#####################################################################
## RELATIONSHIP TYPE: sync , logically_exclusive_inherit
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Generated Clock "CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

Generated Clock "CLKA_slow_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f0/Q" (Generated Clock: CLKA_slow)
Defined at "f1/Q" (Generated Clock: CLKA_slow_div2)

2. logically_exclusive_inherit clock sources:

*Clock Paths to logically_exclusive inherit point 1 at: f1/Q (DFF_X1)

"CLKA_div2" path to logically_exclusive inherit point:

PLL0/out_clk PLL (clock: CLKA)
m0/A MUX2_X1
m0/Z MUX2_X1
f1/CK DFF_X1
f1/Q DFF_X1 (generated clock: CLKA_div2, w.r.t. master clock CLKA)

"CLKA_slow_div2" path to logically_exclusive inherit point:

f0/Q DFF_X1 (clock: CLKA_slow)
m0/B MUX2_X1
m0/Z MUX2_X1
f1/CK DFF_X1
f1/Q DFF_X1 (generated clock: CLKA_slow_div2, w.r.t. master clock CLKA_slow)

Note that in this portion of the report above CLKA_div2 and CLKA_slow are generated clock of CLKA,
and CLKA_slow_div2 is a generated clock of CLKA_slow. CLKA and CLKA_slow are logically exclusive in
that they both are inputs to the same mux and CLKA_div2 and CLKA_slow_div2 inherits logically
exclusiveness.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.
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 TimeVision Constraints User Guide

tv_shell > get_constraints -clock {CLKA_div2 CLKA_slow_div2} -type set_clock_group

{ set_clock_group20 set_clock_group25 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 20] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:37:20) -logically_exclusive \
-group [get_clocks { CLKA_div2 }] -group [get_clocks { CLKA_slow_div2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC005 –id A0 –reason “None”
set_waiver -rule CGWP-INC005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC005 -obj1 CLKA_div2 -obj2 CLKA_slow_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC005 -obj1 CLKA_div2 -obj2 CLKA_slow_div2 -author "hollis" -date "07/10/14" -reason "None"

3.13.6 Rule CGWP-INC006/ICFP-INC006

- Incorrect set_clock_groups , sync. + le through partial inheritance clocks/Incorrect interclock
false path, synchronous partial-LE inheritance.

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are
synchronous and partially inherits logical exclusivity from the parent clocks due to the fact that not all
parent clocks have a child clock.

Design in figure 3.13.6 below shows timing points reported under rule CGWP-INC006/ICFP-INC006

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 TimeVision Constraints User Guide Figure 3.13.6
Logically Exclusive Synchronous – Partial Inheritance
_
D Q
CLKA
PLL 0 0
CLKA_div2 (master_clock “CLKA”) CLKA_div2
Q UNIQUE
1
÷2

CLKA_slow
CLKA_slow
UNIQUE
set_clock_group -group CLKA_slow -group CLKA_div2

In the above designs, CLKA_slow is a divided clock of CLKA, and they have a logically exclusive
relationship. Only one parent clock, CLKA, has a child clock which partially inherit logical exclusivity.
The green arrows indicates there are paths between them , and there is either a set_clock_group or
set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC006/ICFP-INC006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC006 Fatal 1 0 Sdc.Interclock/ICFP-INC006.rpt Incorrect interclock false path, synchronous partial-LE
inheritance
CGWP-INC006 Fatal 1 0 Sdc.Interclock/CGWP-INC006.rpt Incorrect set_clock_groups , sync. + le through partial
inheritance clocks

Sdc.Clock/ICFP-INC006.rpt :
# Rule: ICFP-INC006
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC006
# Incorrect interclock false path, synchronous partial-LE inheritance
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA_div2 4 CLKA_slow 5
--------------------------------------------------

Sdc.Clock/CGWP-INC006.rpt :
# Rule: CGWP-INC006
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC006
# Incorrect set_clock_groups , sync. + le through partial inheritance clocks
#

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 TimeVision Constraints User Guide
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA_div2 1 CLKA_slow 2
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA_div2 CLKA_slow}

logically_exclusive:inherit_partial:sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA_div2 CLKA_slow}

#####################################################################
## RELATIONSHIP TYPE: sync , logically_exclusive_inherit
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Generated Clock "CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

Generated Clock "CLKA_slow" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f0/Q" (Generated Clock: CLKA_slow)

2. logically_exclusive_inherit clock sources:

*Clock Paths to logically_exclusive inherit point 1 at: f1/Q (DFF_X1)

"CLKA_div2" path to logically_exclusive inherit point:

PLL0/out_clk PLL (clock: CLKA)
m0/A MUX2_X1
m0/Z MUX2_X1
f1/CK DFF_X1
f1/Q DFF_X1 (generated clock: CLKA_div2, w.r.t. master clock CLKA)

"CLKA_slow" path to logically_exclusive inherit point:

PLL0/out_clk PLL (clock: CLKA)
m0/B MUX2_X1
m0/Z MUX2_X1
f1/CK DFF_X1
f1/Q DFF_X1 (generated clock: CLKA_slow, w.r.t. master clock CLKA)

Note that in this portion of the report above CLKA_div2 and CLKA_slow are generated clock of CLKA.
CLKA and CLKA_slow are logically exclusive in that they both are inputs to the same mux and CLKA_div2
inherits partial logically exclusiveness.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock {CLKA_div2 CLKA_slow} -type set_clock_group

{ set_clock_group21 }

4) Get the printable attribute of the clock group to see where it is defined.
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 TimeVision Constraints User Guide

tv_shell > get_attribute [get_constraints -id 21] printable

set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:11:21) -logically_exclusive \
-group [get_clocks { CLKA_div2 }] -group [get_clocks { CLKA_slow }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC006 –id A0 –reason “None”
set_waiver -rule CGWP-INC006 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC006 -obj1 CLKA_div2 -obj2 CLKA_slow -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC006 -obj1 CLKA_div2 -obj2 CLKA_slow -author "hollis" -date "07/10/14" -reason "None"

3.13.7 Rule CGWP-INC007/ICFP-INC007

- Incorrect set_clock_groups , source sync clocks/Incorrect interclock false path,
source-synchronous.

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs that are source
synchronous.

Design in figure 3.13.7 below shows timing points reported under rule CGWP-INC007/ICFP-INC007
Figure 3.13.7

Source Synchronous clocks (CLK1_div2 & CLK1_div2_out)

Generated Clock :
Generated Clock : CLK1_div2_out
CLK1 CLK1_div2
PLL 0 ÷2
_
D Q

Q
set_output_delay -clock CLK1_div2_out

set_clock_group -group CLK1_div2 -group CLK1_div2_out

set_false_path -from CLK1_div2 -to CLK1_div2_out

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 TimeVision Constraints User Guide
In the above designs, CLK1_div2 is a divided clock of CLK1, and CLK1_div2_out is a generated clock with
CLK1_div2 as its master, defined on the output port. CLK1_div2 also clocks a register which drives an
output port. The output port is constrained by the generated clock on the output port and there is
either a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC007/ICFP-INC007.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC007 Fatal 1 0 Sdc.Interclock/ICFP-INC007.rpt Incorrect interclock false path, source-synchronous
CGWP-INC007 Fatal 1 0 Sdc.Interclock/CGWP-INC007.rpt Incorrect set_clock_groups , source sync clocks

Sdc.Clock/ICFP-INC007.rpt :
# Rule: ICFP-INC007
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC007
# Incorrect interclock false path, source-synchronous
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

----------------------------------------------------
A0 CLK1_div2 5 CLK1_div2_out 6
----------------------------------------------------

Sdc.Clock/CGWP-INC007.rpt :
# Rule: CGWP-INC007
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC007
# Incorrect set_clock_groups , source sync clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

----------------------------------------------------
A0 CLK1_div2 1 CLK1_div2_out 2
----------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLK1_div2 CLK1_div2_out}

source-sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks { CLK1_div2 CLK1_div2_out}

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 TimeVision Constraints User Guide
#####################################################################
## RELATIONSHIP TYPE: source_sync
#####################################################################

1. source_sync clock source (Sync. Root Clock "CLK1" is defined on object "PLL0/clk_out"):

Generated Clock "CLK1_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLK1)
Defined at "FF1/Q" (Generated Clock: CLK1_div2)

Generated Clock "CLK1_div2_out" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLK1)
Defined at "FF1/Q" (Generated Clock: CLK1_div2)
Defined at "clk_out" (Generated Clock: CLK1_div2_out)

*source_sync Clock Path 1 from master clock to generated clock defined at: clk_out
FF1/Q SDFCNQD1 (master clock: CLK1_div2)
clk_out oport (generated clock: CLK1_div2_out, w.r.t. master clock CLK1_div2)

Note that in this portion of the report above CLK1_div2 is a generated clock of CLK1. CLK1_div2_out is
a generated clock on output port “clk_out”. Output data port “out1” constrained with respect to
generated clock “CLK1_div2_out” forms a source-sync relationship.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLK1_div2 CLK1_div2_out } -type set_clock_group

{ set_clock_group11 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 11] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:19:11) -asynchronous \
-group [get_clocks { CLKA_div2 }] -group [get_clocks { CLKA_div2_out }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC007 –id A0 –reason “None”
set_waiver -rule CGWP-INC007 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC007 -obj1 CLK1_div2 -obj2 CLK1_div2_out -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC007 -obj1 CLK1_div2 -obj2 CLK1_div2_out -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.13.8 Rule CGWP-INC008/ICFP-INC008
- Incorrect set_clock_groups , when user defined allow_path is specified/Incorrect interclock
false path, asynchronous -allow_paths clock group.

Description:
This rule identifies “set_clock_group/set_false_path” between clock pairs where the user
specified “async_allow” relationship via the command “define_clock_relation -async_allow -clock”, and
there is either a set_clock_group or set_false_path between them.

Design in figure 3.13.8 below shows timing points reported under rule CGWP-INC008/ICFP-INC008

Figure 3.13.8

Asynchronous – with user specified “allow_path”

PLL1 PLL2

CLKA CLKB

CLKA CLKB

define_clock_relation -async_allow -clock {CLKA CLKB}

set_clock_group -group CLKA -group CLKB
set_false_path -from CLKA -to CLKB

In the above designs, CLKA and CLKB are asynchronous, however, the user has defined the clock pair
relationship as async_allow and there is either a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC008/ICFP-INC008.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC008 Fatal 1 0 Sdc.Interclock/ICFP-INC008.rpt Incorrect interclock false path, asynchronous
-allow_paths clock group
CGWP-INC008 Fatal 1 0 Sdc.Interclock/CGWP-INC008.rpt Incorrect set_clock_groups , when user defined
allow_path is specified

Sdc.Clock/ICFP-INC008.rpt :
# Rule: ICFP-INC008
# Severity: Fatal

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 TimeVision Constraints User Guide
# ==============================
#
# Design : top
# ICFP-INC008
# Incorrect interclock false path, asynchronous -allow_paths clock group
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 2 CLKB 3
--------------------------------------------------

Sdc.Clock/CGWP-INC008.rpt :
# Rule: CGWP-INC008
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC008
# Incorrect set_clock_groups , when user defined allow_path is specified
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute
tv_shell > get_clock_relation -clock {CLKA CLKB}
async_allow

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks { CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous_allow
#####################################################################

1. asynchronous_allow clock source (Sync. Root Clock "CLKA" is defined on object

"PLL1/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Create Clock "CLKB " Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

{ set_clock_group39 }

4) Get the printable attribute of the clock group to see where it is defined.

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 TimeVision Constraints User Guide
tv_shell > get_attribute [get_constraints -id 39] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:44:39) -asynchronous \
-group [get_clocks { CLKA }] -group [get_clocks { CLKB }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC008 –id A0 –reason “None”
set_waiver -rule CGWP-INC008 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC008 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC008 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.13.9 Rule CGWP-INC009/ICFP-INC009

- Incorrect set_clock_groups , between same clocks/ Incorrect same-clock false path

Description:
This rule identifies incorrect “set_clock_group” defined on the same clock domain.

Design in figure 3.13.9 below shows timing points reported under rule CGWP-INC009/ICFP-INC009

Figure 3.13.9

set_clock_group – “same clock”

PLL 0

CLKA

CLKA

set_clock_group -group CLKA -group CLKA

In the above designs, CLKA is defined in two different groups and there is either a set_clock_group or
set_false_path between them.

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 TimeVision Constraints User Guide
Therefore, “check_constraints” will report these clocks under rule CGWP-INC009/ICFP-INC009.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-INC009 Fatal 1 0 Sdc.Interclock/ICFP-INC009.rpt Incorrect same-clock false path
CGWP-INC009 Fatal 1 0 Sdc.Interclock/CGWP-INC009.rpt Incorrect set_clock_groups , between same clocks

Sdc.Clock/ICFP-INC009.rpt :
# Rule: ICFP-INC009
# Severity: Fatal
# ==============================
#
# Design : top
# ICFP-INC009
# Incorrect same-clock false path
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 1 CLKA 1
--------------------------------------------------

Sdc.Clock/CGWP-INC009.rpt :
# Rule: CGWP-INC009
# Severity: Fatal
# ==============================
#
# Design : top
# CGWP-INC009
# Incorrect set_clock_groups , between same clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKA 0
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute
tv_shell > get_clock_relation -clock {CLKA CLKA}
self

2) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKA } -type set_clock_group

{ set_clock_group16 }

3) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 16] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:29:16) -asynchronous \

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-group [get_clocks { CLKA }] -group [get_clocks { CLKA }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-INC009 –id A0 –reason “None”
set_waiver -rule CGWP-INC009 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC009 -obj1 CLKA -obj2 CLKA -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC009 -obj1 CLKA -obj2 CLKA -author "hollis" -date "07/10/14" -reason "None"

3.13.10 Rule CGWP-INC010

- Incorrect set_clock_groups , SDC has incorrect set_clock_group -asynchronous -allow_paths

Description:
This rule identifies clock pairs which are asynchronous and have registered logic paths between them
and a user specified “set_clock_group –async -allow_path” is defined between them.

Design in figure 3.13.10 below shows timing points reported under rule CGWP-INC010

Figure 3.13.10

Asynchronous – with SDC specified “allow_path”

PLL1 PLL2

CLKA CLKB

CLKA CLKB

set_clock_group -async -allow_path -group CLKA -group CLKB

In the above designs, CLKA and CLKB are asynchronous with path between then and there is a
set_clock_group -async -allow_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC010.

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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock CGWP-INC010 Error 1 0 Sdc.Interclock/CGWP-INC010.rpt Incorrect set_clock_groups , SDC has incorrect
set_clock_group -asynchronous -allow_paths
Sdc.Clock/CGWP-INC010.rpt :
# Rule: CGWP-INC010
# Severity: Error
# ==============================
#
# Design : top
# CGWP-INC010
# Incorrect set_clock_groups , SDC has incorrect set_clock_group -asynchronous -allow_paths
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute
tv_shell > get_clock_relation -clock {CLKA CLKB}
async

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks { CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "PLL1/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Create Clock "CLKB " Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

{ set_clock_group2 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 2] printable
set_clock_group (./tests/check_cons_CGWP.tcl:3:2) -asynchronous -allow_paths \
-group [get_clocks { CLKA }] -group [get_clocks { CLKB }]

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Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGWP-INC010 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC010 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC010 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.13.11 Rule CGWP-INC011

- Type Incorrect set_clock_groups (Crosstalk / SI impact only) between clocks with timing paths

Description:
The logic type of a clock pair is determined by the relationship. If the relationship inferred by timevision
or defined by the user is in conflict with the relationship specified in the set_clock_group command
then the rule is violated. The timing paths between the clock pair are still false path in Static Timing
Analysis, however, Crosstalk/SI analysis is impacted.

Table of Violation:
Clock Pair Relation Clock Group Relation Violate (yes/no)
physically_exclusive asynchronous yes
physically_exclusive logically_exclusive yes
logically_exclusive asynchronous yes
logically_exclusive physically_exclusive yes
asynchronous physically_exclusive yes
asynchronous logically_exclusive yes
physically_exclusive physically_exclusive no
logically_exclusive logically_exclusive no
asynchronous asynchronous no

Design in figure 3.13.11 below shows one example of timing points reported under rule CGWP-INC011

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 TimeVision Constraints User Guide Figure 3.13.11

Async – incorrectly specified as LE

PLL1 PLL2

CLKA CLKB

CLKA CLKB

set_clock_group -logically_exclusive -group CLKA -group CLKB

In the above designs, CLKA and CLKB are asynchronous with path between them however the clock
group is incorrectly specified as logically_exclusive.

Therefore, “check_constraints” will report these clocks under rule CGWP-INC011.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock CGWP-INC011 Error 1 0 Sdc.Interclock/CGWP-INC011.rpt Type Incorrect set_clock_groups (Crosstalk / SI impact
only) between clocks with timing paths

Sdc.Clock/CGWP-INC011.rpt :
# Rule: CGWP-INC011
# Severity: Error
# ==============================
#
# Design : top
# CGWP-INC011
# Type Incorrect set_clock_groups (Crosstalk / SI impact only) between clocks with timing paths
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute
tv_shell > get_clock_relation -clock {CLKA CLKB}
async

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks { CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous
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#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "PLL1/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Create Clock "CLKB " Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

{ set_clock_group7 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 7] printable
set_clock_group (./tests/check_cons_CGWP.tcl:9:7) -logically_exclusive \
-group [get_clocks { CLKA }] -group [get_clocks { CLKB }]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGWP-INC011 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CGWP-INC011 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14 Missing clock groups and interclock false path rule

3.14.1 Rule CGWP-MIS001/ICFP-MIS001

- Missing physically-exclusive set_clock_group between clocks/Missing interclock false path,
physically exclusive.

Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are
“-physically_exclusive”, i.e. multiple clocks are defined on the same port or pin and cannot
physically exist at the same time.

Design in figure 3.14.1 below shows timing points reported under rule CGWP-MIS001/ICFP-MIS001

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 TimeVision Constraints User Guide
Figure 3.14.1

Missing Physically Exclusive

_
D Q

CLKA
CLKB
clk B1 Q
The following should exist:
set_clock_group -group CLKA -group CLKB
or
set_false_path -from CLKA -to CLKB

In the above designs, CLKA and CLKB are physically exclusive, defined on the same port and there is
neither a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS001/ICFP-MIS001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS001 Error 1 0 Sdc.Interclock/ICFP-MIS001.rpt Missing interclock false path, physically exclusive
CGWP-MIS001 Error 1 0 Sdc.Interclock/CGWP-MIS001.rpt Missing physically-exclusive set_clock_group between
clocks

Sdc.Clock/ICFP-MIS001.rpt :
# Rule: ICFP-MIS001
# Severity: Error
# ==============================
#
# Design : top
# ICFP-MIS001
# Missing interclock false path, physically exclusive
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Sdc.Clock/CGWP-MIS001.rpt :
# Rule: CGWP-MIS001
# Severity: Error
# ==============================
#
# Design : top
# CGWP-MIS001
# Missing physically-exclusive set_clock_group between clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

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tv_shell > get_clock_relation -clock {CLKA CLKB}
physically_exclusive

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks { CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: physically_exclusive
#####################################################################

1. physically_exclusive clock source (Sync. Root Clock "CLKA" is defined on object "clk"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "clk" (Clock: CLKA)

Create Clock "CLKB " Source (Starting from "root" master clock onwards):
Defined at "clk" (Clock: CLKB)

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

Note that no clock group was returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS001 –id A0 –reason “None”
set_waiver -rule CGWP-MIS001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-MIS001 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS001 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14.2 Rule CGWP-MIS002/ICFP-MIS002

- Missing logically-exclusive set_clock_group between clocks/Missing interclock false path,
logically exclusive

Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are
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 TimeVision Constraints User Guide
“-logically_exclusive”, i.e. all paths between the clock pair are in the common domain.

Design in figure 12.1.1 below shows timing points reported under rule CGWP-MIS002/ICFP-MIS002

Figure 3.14.2

Missing Logically Exclusive – domain Missing Logically Exclusive – pure

CLKA CLKB CLKA CLKB

1 0 1 0

CLKA + CLKB CLKB CLKA + CLKB

CLKA
COMMON UNIQUE COMMON
UNIQUE

The following should exist:

set_clock_group -logically_exclusive -group CLKA -group CLKB
or
set_false_path -from CLKA -to CLKB

In the above designs, CLKA and CLKB are physically exclusive, defined on the same port and there is
neither a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS002/ICFP-MIS002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS001 Error 1 0 Sdc.Interclock/ICFP-MIS001.rpt Missing interclock false path, physically exclusive
CGWP-MIS001 Error 1 0 Sdc.Interclock/CGWP-MIS001.rpt Missing physically-exclusive set_clock_group between
clocks

Sdc.Clock/ICFP-MIS002.rpt :
# Rule: ICFP-MIS002
# Severity: Error
# ==============================
#
# Design : top
# ICFP-MIS002
# Missing interclock false path, logically exclusive
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

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Sdc.Clock/CGWP-MIS002.rpt :
# Rule: CGWP-MIS002
# Severity: Error
# ==============================
#
# Design : top
# CGWP-MIS002
# Missing logically-exclusive set_clock_group between clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

logically_exclusive:domain

2) To see how the clocks are logically run command “justify_inter_clock”. Only portions of this report is
used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous, logically_exclusive
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "CLKA"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "CLKA" (Clock: CLKA)

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "CLKB" (Clock: CLKB)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
CLKA (port)
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKB" path to Converge Point:

CLKB (port)
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA and CLKB are logically exclusive in that they both are
inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

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Note that no clock group was returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS002 –id A0 –reason “None”
set_waiver -rule CGWP-MIS002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-MIS002 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS002 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14.3 Rule CGWP-MIS003/ICFP-MIS003

- Missing asynchronous (non-harmonic) set_clock_group between clocks/Missing interclock
false path, asynchronous non-harmonic

Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are “-async” and
their periods are non-harmonic. The clock pair can also have paths between them per the topologies in
the diagram below.

Design in figure 3.14.3 below shows timing points reported under rule CGWP-MIS003/ICFP-MIS003

Figure 3.14.3

Missing Async – Non-Harmonic

PLL1 PLL2
275MHz 333MHz
CLKA CLKB

CLKA CLKB

The following should exist:

set_clock_group -async -group CLKA -group CLKB
or
set_false_path -from CLKA -to CLKB

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In the above designs, CLKA and CLKB are async, non-harmonic, and there is neither a set_clock_group
or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS003/ICFP-MIS003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS003 Error 1 0 Sdc.Interclock/ICFP-MIS003.rpt Missing interclock false path, asynchronous
non-harmonic
CGWP-MIS003 Error 1 0 Sdc.Interclock/CGWP-MIS003.rpt Missing asynchronous (non-harmonic) set_clock_group
between clocks

Sdc.Clock/ICFP-MIS003.rpt :
# Rule: ICFP-MIS003
# Severity: Error
# ==============================
#
# Design : top
# ICFP-MIS003
# Missing interclock false path, asynchronous non-harmonic
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Sdc.Clock/CGWP-MIS003.rpt :
# Rule: CGWP-MIS003
# Severity: Error
# ==============================
#
# Design : top
# CGWP-MIS003
# Missing asynchronous (non-harmonic) set_clock_group between clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

logically_exclusive:combo

2) To see how the clocks are logically run command “justify_inter_clock”. Only portions of this report is
used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

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#####################################################################
## RELATIONSHIP TYPE: asynchronous, logically_exclusive
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "CLKA"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "CLKA" (Clock: CLKA)

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "CLKB" (Clock: CLKB)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
CLKA (port)
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKB" path to Converge Point:

CLKB (port)
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA and CLKB are logically exclusive in that they both are
inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

Note that no clock group was returned.

4) Get period of each clock.

tv_shell > get_attribute [get_clocks CLKA] period
3.636363
tv_shell > get_attribute [get_clocks CLKB] period
3.003
Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS003 –id A0 –reason “None”
set_waiver -rule CGWP-MIS003 –id A0 –reason “None”
write_waiver top.waivers.tcl

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top.waivers.tcl
set_waiver -rule ICFP-MIS003 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS003 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14.4 Rule CGWP-MIS004/ICFP-MIS004

- Missing asynchronous (harmonic) set_clock_group between clocks/Missing interclock false
path, asynchronous harmonic
Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are “-async” and
their periods are harmonic.

Design in figure 3.14.4 below shows timing points reported under rule CGWP-MIS004/ICFP-MIS004

Figure 3.14.4

Missing Async – Harmonic

PLL1 PLL2
250MHz 500MHz
CLKA CLKB

CLKA CLKB

The following should exist:

set_clock_group -async -group CLKA -group CLKB
or
set_false_path -from CLKA -to CLKB

In the above designs, CLKA and CLKB are async, harmonic, and there is neither a set_clock_group or
set_false_path between them.
Therefore, “check_constraints” will report these clocks under rule CGWP-MIS004/ICFP-MIS004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS004 Warning 1 0 Sdc.Interclock/ICFP-MIS004.rpt Missing interclock false path, asynchronous harmonic
CGWP-MIS004 Warning 1 0 Sdc.Interclock/CGWP-MIS004.rpt Missing asynchronous (harmonic) set_clock_group
between clocks

Sdc.Clock/ICFP-MIS004.rpt :
# Rule: ICFP-MIS004
# Severity: Warning
# ==============================
#
# Design : top
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# ICFP-MIS004
# Missing interclock false path, asynchronous harmonic
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Sdc.Clock/CGWP-MIS004.rpt :
# Rule: CGWP-MIS004
# Severity: Warning
# ==============================
#
# Design : top
# CGWP-MIS004
# Missing asynchronous (harmonic) set_clock_group between clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

logically_exclusive:combo

2) To see how the clocks are logically run command “justify_inter_clock”. Only portions of this report is
used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous, logically_exclusive
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "CLKA"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "CLKA" (Clock: CLKA)

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "CLKB" (Clock: CLKB)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
CLKA (port)
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKB" path to Converge Point:

CLKB (port)
m1/B MUX2_X1
m1/Z MUX2_X1

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Note that in this portion of the report above CLKA and CLKB are logically exclusive in that they both are
inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

Note that no clock group was returned.

4) Get period of each clock.

tv_shell > get_attribute [get_clocks CLKA] period
4.00
tv_shell > get_attribute [get_clocks CLKB] period
2.00

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS004 –id A0 –reason “None”
set_waiver -rule CGWP-MIS004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-MIS004 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS004 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14.5 Rule CGWP-MIS005/ICFP-MIS005

- Missing asynchronous (same-period) set_clock_group between clocks/Missing interclock false
path, asynchronous same-period

Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are “-async” and
their periods are identical.

Design in figure 3.14.5 below shows timing points reported under rule CGWP-MIS005/ICFP-MIS005

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 TimeVision Constraints User Guide
Figure 3.14.5
Missing Async – Same Period

PLL1 PLL2
500MHz 500MHz
CLKA CLKB

CLKA CLKB

The following should exist:

set_clock_group -async -group CLKA -group CLKB
or
set_false_path -from CLKA -to CLKB

In the above designs, CLKA and CLKB are async, same period, and there is neither a set_clock_group or
set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS005/ICFP-MIS005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS005 Warning 1 0 Sdc.Interclock/ICFP-MIS005.rpt Missing interclock false path, asynchronous
same-period
CGWP-MIS005 Warning 1 0 Sdc.Interclock/CGWP-MIS005.rpt Missing asynchronous (same-period)
set_clock_group between clocks

Sdc.Clock/ICFP-MIS005.rpt :
# Rule: ICFP-MIS005
# Severity: Warning
# ==============================
#
# Design : top
# ICFP-MIS005
# Missing interclock false path, asynchronous same-period
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------
Sdc.Clock/CGWP-MIS005.rpt :
# Rule: CGWP-MIS005
# Severity: Warning
# ==============================
#
# Design : top
# CGWP-MIS005
# Missing asynchronous (same-period) set_clock_group between clocks
#

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 TimeVision Constraints User Guide
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

logically_exclusive:combo

2) To see how the clocks are logically run command “justify_inter_clock”. Only portions of this report is
used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: asynchronous, logically_exclusive
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "CLKA"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "CLKA" (Clock: CLKA)

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "CLKB" (Clock: CLKB)

2. logically_exclusive clock sources:

*Clock Convergence Path Set 1 at: m1/Z (MUX2_X1)

Clock "CLKA" path to Converge Point:
CLKA (port)
m1/A MUX2_X1
m1/Z MUX2_X1

Clock "CLKB" path to Converge Point:

CLKB (port)
m1/B MUX2_X1
m1/Z MUX2_X1

Note that in this portion of the report above CLKA and CLKB are logically exclusive in that they both are
inputs to the same mux.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB } -type set_clock_group

Note that no clock group was returned.

4) Get period of each clock.

tv_shell > get_attribute [get_clocks CLKA] period
2.00
tv_shell > get_attribute [get_clocks CLKB] period
2.00

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 TimeVision Constraints User Guide
Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS005 –id A0 –reason “None”
set_waiver -rule CGWP-MIS005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-MIS005 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS005 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.14.6 Rule CGWP-MIS006/ICFP-MIS006

- Missing physically-exclusive(inherit) set_clock_group between clocks/Missing interclock false
path, physically exclusive:inherit

Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are
“-physically_exclusive:inherit”, i.e. multiple primary clocks are defined on the same port
or pin and generated clocks are defined with the primary clocks as masters, thus the generated clocks
relationships inherits physical exclusivity from the primary master clocks.

Design in figure 3.14.6 below shows timing points reported under rule CGWP-MIS006/ICFP-MIS006.

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 TimeVision Constraints User Guide
Figure 3.14.6

Missing Physically Exclusive - Inheritance

_
D Q
CLKA CLKA_div2 CLKA_div2
CLKB clk B1 Q CLKB_div2 CLKB_div2

CLKA
CLKB

The following should exist:

set_clock_group -physically_exclusive -group CLKA -group CLKB
set_clock_group -physically_exclusive -group CLKA -group CLKB_div2
set_clock_group -physically_exclusive -group CLKB -group CLKA_div2
set_clock_group -physically_exclusive -group CLKA_div2 -group CLKB_div2
or
set_false_path -from CLKA -to CLKB
set_false_path -from CLKA -to CLKB_div2
set_false_path -from CLKB -to CLKA_div2
set_false_path -from CLKA_div2 -to CLKB_div2

In the above designs, CLKA and CLKB are physically exclusive and each has a child clock and with paths
between the child clocks and the parent clocks. The child clocks inherits physical exclusivity from the
parent clocks, and there is neither a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS006/ICFP-MIS006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS006 Error 2 0 Sdc.Interclock/ICFP-MIS006.rpt Missing interclock false path, physically exclusive:inherit
CGWP-MIS006 Error 2 0 Sdc.Interclock/CGWP-MIS006.rpt Missing physically-exclusive(inherit) set_clock_group
between clocks

Sdc.Clock/ICFP-MIS006.rpt :
# Rule: ICFP-MIS006
# Severity: Error
# ==============================
#
# Design : top
# ICFP-MIS006
# Missing interclock false path, physically exclusive:inherit
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA 0 CLKB_div2 3
A1 CLKB 1 CLKA_div2 2
--------------------------------------------------

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Sdc.Clock/CGWP-MIS006.rpt :
# Rule: CGWP-MIS006
# Severity: Error
# ==============================
#
# Design : top
# CGWP-MIS006
# Missing physically-exclusive(inherit) set_clock_group between clocks
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB_div2 3
A1 CLKB 1 CLKA_div2 2
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB_div2}

physically_exclusive:inherit

2) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA CLKB_div2 } -type set_clock_group

Note that no clock group was returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS006 –id A0 –reason “None”
set_waiver -rule CGWP-MIS006 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-MIS006 -obj1 CLKA -obj2 CLKB_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-MIS006 -obj1 CLKB -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.14.7 Rule CGWP-MIS007/ICFP-MIS007

- Missing physically-exclusive(branch) set_clock_group between clocks/Missing interclock false
path, physically exclusive:branch

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 TimeVision Constraints User Guide
Description:
This rule identifies missing “set_clock_group/set_false_path” between clock pairs that are
“-physically_exclusive:branch”, i.e. logically exclusive primary clocks branch to different
paths and physically exclusive generated clocks are defined relative to each primary master, thus the
generated clocks relationships are physical exclusivity branch.

Design in figure 3.14.7 below shows timing points reported under rule CGWP-MIS007/ICFP-MIS007

Figure 3.14.7

Missing Physically Exclusive - Branch

_
CLKA
D Q D Q
_

PLL 0 0
CLKA_div2_0
CLKB Q Q
CLKB_div2_0
PLL 1 1

Logic

_ _
D Q D Q
CLKA_div2_1
Q Q
CLKB_div2_1

The following should exist:

set_clock_group -physically_exclusive -group CLKA_div2_1 -group CLKB_div2_0
set_clock_group -physically_exclusive -group CLKA_div2_0 -group CLKB_div2_1
or
set_false_path -from CLKA_div2_1 -to CLKB_div2_0
set_false_path -from CLKA_div2_0 -to CLKB_div2_1

Therefore, “check_constraints” will report these clocks under rule CGWP-MIS007/ICFP-MIS007.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-MIS007 Error 4 0 Sdc.Interclock/ICFP-MIS007.rpt Missing interclock false path, physically exclusive:branch
CGWP-MIS007 Error 2 0 Sdc.Interclock/CGWP-MIS007.rpt Missing physically-exclusive(branch) set_clock_group
between clocks

Sdc.Clock/ICFP-MIS007.rpt :
# Rule: ICFP-MIS007
# Severity: Error
# ==============================
#
# Design : top
# ICFP-MIS007
# Missing interclock false path, physically exclusive:branch
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 TimeVision Constraints User Guide
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA_div2_1 2 CLKB_div2_0 5
A1 CLKB_div2_0 3 CLKA_div2_1 4
A2 CLKA_div2_0 4 CLKB_div2_1 3
A3 CLKB_div2_1 5 CLKA_div2_0 2
--------------------------------------------------

Sdc.Clock/CGWP-MIS006.rpt :
# Rule: CGWP-MIS007
# Severity: Error
# ==============================
#
# Design : top
# CGWP-MIS007
# Missing physically-exclusive(branch) set_clock_group between clocks
#
A# Clock1 Clock1 ID Clock2 Clock2 ID Info
--------------------------------------------------
A0 CLKA_div2_1 2 CLKB_div2_0 5
A1 CLKA_div2_0 4 CLKB_div2_1 3
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA_div2_1 CLKB_div2_0}

physically_exclusive:inherit

2) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock { CLKA_div2_1 CLKB_div2_0 } -type set_clock_group

Note that no clock group was returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-MIS007 –id A0 –reason “None”
set_waiver -rule CGWP-MIS007 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CGWP-MIS007 -obj1 CLKA_div2_1 -obj2 CLKB_div2_0 -author "hollis" -date "07/14/14" -reason "None"
set_waiver -rule CGWP-MIS007 -obj1 CLKA_div2_0 -obj2 CLKB_div2_1 -author "hollis" -date "07/14/14" -reason "None"
set_waiver -rule ICFP-MIS007 -obj1 CLKA_div2_1 -obj2 CLKB_div2_0 -author "hollis" -date "07/14/14" -reason "None"
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 TimeVision Constraints User Guide
set_waiver -rule ICFP-MIS007 -obj1 CLKB_div2_0 -obj2 CLKA_div2_1 -author "hollis" -date "07/14/14" -reason "None"
set_waiver -rule ICFP-MIS007 -obj1 CLKA_div2_0 -obj2 CLKB_div2_1 -author "hollis" -date "07/14/14" -reason "None"
set_waiver -rule ICFP-MIS007 -obj1 CLKB_div2_1 -obj2 CLKA_div2_0 -author "hollis" -date "07/14/14" -reason "None"

3.15 Incorrect clock groups and interclock false path rule with no paths

3.15.1 Rule CGNP-INC001/ICFP-IRR001

- Incorrect set_clock_groups between clocks with NO timing paths/Irrelevant interclock false
path, no clock-to-clock path

Description:
This rule identifies incorrect “set_clock_group” between clock pairs that are synchronous but have NO
logic paths between them.

Design in figure 3.15.1 below shows timing points reported under rule CGNP-INC001/ICFP-IRR001

Figure 3.15.1

Synchronous – with no logic paths

PLL 0

CLKA
CLKA

÷2
CLKA_div2

CLKA_div2

set_clock_group -group CLKA -group CLKA_div2

set_false_path -from CLKA -to CLKA_div2

In the above designs, CLKA_div2 is a divided clock of CLKA and there are no paths between the clock
domains, and there is either a set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGNP-INC001/ICFP-IRR001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Interclock ICFP-IRR001 Warning 1 0 Sdc.Interclock/ICFP-IRR001.rpt Irrelevant interclock false path, no clock-to-clock path
CGNP-INC001 Warning 1 0 Sdc.Interclock/CGNP-INC001.rpt Incorrect set_clock_groups between clocks with NO
timing paths
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 TimeVision Constraints User Guide
Sdc.Clock/ICFP-IRR001.rpt :
# Rule: ICFP-IRR001
# Severity: Warning
# ==============================
#
# Design : top
# ICFP-IRR001
# Irrelevant interclock false path, no clock-to-clock path
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 7 CLKA_div2 9
--------------------------------------------------

Sdc.Clock/CGNP-INC001.rpt :
# Rule: CGNP-INC001
# Severity: Warning
# ==============================
#
# Design : top
# CGNP-INC001
# Incorrect set_clock_groups between clocks with NO timing paths
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 1 CLKA_div2 3
--------------------------------------------------
Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKA_div2}

sync

2) To see how the clocks are synchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKA_div2}

#####################################################################
## RELATIONSHIP TYPE: sync
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL0/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)

Generated Clock " CLKA_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL0/clk_out" (Clock: CLKA)
Defined at "f1/Q" (Generated Clock: CLKA_div2)

Note that in this portion of the report above CLKA_div2 is a generated clock of CLKA.

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

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 TimeVision Constraints User Guide
tv_shell > get_constraints -clock {CLKA CLKA_div2} -type set_clock_group
{ set_clock_group5 set_clock_group6 }

4) Get the printable attribute of the clock group to see where it is defined.
tv_shell > get_attribute [get_constraints -id 5] printable
set_clock_group (./tests/check_cons_CGWP_ICFP.tcl:8:5) -asynchronous \
-group [get_clocks { CLKA }] -group [get_clocks { CLKA_div2 }]

5) Now report the paths between the clock pair.

tv_shell > report_path -constraint [get_constraints -id 5] -start_end

No path returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule ICFP-IRR001 –id A0 –reason “None”
set_waiver -rule CGNP-INC001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule ICFP-INC001 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule CGWP-INC001 -obj1 CLKA -obj2 CLKA_div2 -author "hollis" -date "07/10/14" -reason "None"

3.16 Missing clock groups rule with no paths

3.16.1 Rule CGNP-MIS001

- Missing set_clock_groups between clocks with NO timing paths

Description:
This rule identifies missing “set_clock_group” between clock pairs that are “-async” or
“-physically_exclusive” and have NO paths between them, regardless of their period
relationship.

Design in figure 3.16.1 below shows timing points reported under rule CGNP-MIS001

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 TimeVision Constraints User Guide

Figure 3.16.1

Missing Async – Non-Harmonic – No Path

PLL1 PLL2
275MHz 333MHz
CLKA CLKB

CLKA CLKB

The following should exist:

set_clock_group -async -group CLKA -group CLKB

In the above designs, CLKA and CLKB are async but have no paths between. However, it is good design
practice to define a clock group between the clock pair for Crosstalk/SI reasons, and there is either a
set_clock_group or set_false_path between them.

Therefore, “check_constraints” will report these clocks under rule CGNP-MIS001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
Sdc.Interclock CGNP-MIS001 Warning 1 0 Sdc.Interclock/CGNP-MIS001.rpt Missing set_clock_groups between clocks with NO
timing paths

Sdc.Clock/CGNP-MIS001.rpt :
# Rule: CGNP-MIS001
# Severity: Warning
# ==============================
#
# Design : top
# CGNP-MIS001
# Missing set_clock_groups between clocks with NO timing paths
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

async

2) To see how the clocks are asynchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

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 TimeVision Constraints User Guide
#####################################################################
## RELATIONSHIP TYPE: asynchronous
#####################################################################

1. asynchronous clock sources:

Clock "CLKA" Source:

Defined at "PLL1/clk_out" (Clock: CLKA)

Clock "CLKB" Source:

Defined at "PLL2/clk_out" (Clock: CLKB)

3) Now get the clock group(s) defined between the clock pair. Note that there can be multiple clock
groups involving the clock pair.

tv_shell > get_constraints -clock {CLKA CLKB} -type set_clock_group

Note no clock group is returned

4) Now report the paths between the clock pair.

tv_shell > report_path -from [get_clocks CLKA] -to [get_clocks CLKB] -start_end

No path returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGNP-MIS001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CGNP-MIS001 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.17 User inferred clock groups honored from SDC rules

3.17.1 Rule CGIN-INF001

- User-Inferred synchronous group between primary clocks, non-harmonic

Description:
This rule identifies user defined, synchronous “set_clock_group” relationships between primary clock
pairs and is in conflict with TimeVision inferred relationship for the clock pair. The user issued the
command: “infer_clock_relations -honor_sdc_clock_groups”, which overrides TimeVision inferred clock
relationships.

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 TimeVision Constraints User Guide
Design in figure 3.17.1 below shows timing points reported under rule CGIN-INF001
Figure 3.17.1

Asynchronous
infer_clock_relations -honor_sdc_clock_groups

PLL1 PLL2

CLKA CLKB

CLKA CLKB

set_clock_group -async -group { CLKA CLKB }

In the above designs, CLKA and CLKB are async but the clock group has them in the same group
implying synchronous relationship, however, this is in conflict with Timevision inferred clock
relationship of asynchronous between the clock pair.

Therefore, “check_constraints” will report these clocks under rule CGIN-INF001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
Sdc.Interclock CGIN-INF001 Info 1 0 Sdc.Interclock/CGIN-INF001.rpt User-Inferred synchronous group between primary
clocks, non-harmonic

Sdc.Interclock/CGIN-INF001.rpt :
# Rule: CGIN-INF001
# Severity: Info
# ==============================
#
# Design : top
# CGIN-INF001
# User-Inferred synchronous group between primary clocks, non-harmonic
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB 1
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB}

sync

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 TimeVision Constraints User Guide
2) To see how the clocks are asynchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB}

#####################################################################
## RELATIONSHIP TYPE: sync
#####################################################################

1. sync clock source (Sync. Root Clock "CLKA" is defined on object "PLL1/cout"):

Clock "PLL1/cout" Source:

Defined at "PLL1/cout" (Clock: CLKA)

Clock "PLL2/cout" Source:

Defined at "PLL2/cout" (Clock: CLKB)

Note that the clock pair is reported as “sync” however, they are defined on different ports which
means the clock pair is definitely asynchronous.

3) Now get the clock pair attribute “is_user_relation”.

tv_shell > get_attribute [get_clock_pair -from CLKA -to CLKB] is_user_relation

1

Note the attribute is true meaning the user specified the clock pair relationship.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGIN-INF001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CGIN-INF001 -obj1 CLKA -obj2 CLKB -author "hollis" -date "07/10/14" -reason "None"

3.17.2 Rule CGIN-INF002

- User-Inferred synchronous group between primary/generated clocks, overriding asynchronous

Description:
This rule identifies user defined, synchronous “set_clock_group” relationships between clock pairs
where a generated clock is involved, and is in conflict with TimeVision inferred relationship for the
clock pair. The user issued the command: “infer_clock_relations -honor_sdc_clock_groups”, which
overrides TimeVision inferred clock relationships.
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 TimeVision Constraints User Guide
Design in figure 3.17.2 below shows timing points reported under rule CGIN-INF002

Figure 3.17.2

Asynchronous
infer_clock_relations -honor_sdc_clock_groups

PLL1 PLL2

CLKA CLKB

÷2

CLKA CLKB_div2

set_clock_group -asyc -group { CLKA CLKB_div2 }

In the above designs, CLKA and CLKB_div2 are async but the clock group has them in the same group
implying synchronous relationship, however, this is in conflict with Timevision inferred clock
relationship of asynchronous between the clock pair.

Therefore, “check_constraints” will report these clocks under rule CGIN-INF002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
Sdc.Interclock CGIN-INF002 Info 1 0 Sdc.Interclock/CGIN-INF002.rpt User-Inferred synchronous group between
primary/generated clocks, overriding asynchronous

Sdc.Interclock/CGIN-INF002.rpt :
# Rule: CGIN-INF002
# Severity: Info
# ==============================
#
# Design : top
# CGIN-INF002
# User-Inferred synchronous group between primary/generated clocks, overriding asynchronous
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKA 0 CLKB_div2 3
--------------------------------------------------

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Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKA CLKB_div2}

sync

2) To see how the clocks are asynchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKA CLKB_div2}

#####################################################################
## RELATIONSHIP TYPE: sync
#####################################################################

1. async clock source (Sync. Root Clock "CLKA" is defined on object "PLL1/clk_out"):

Create Clock "CLKA" Source (Starting from "root" master clock onwards):
Defined at "PLL1/clk_out" (Clock: CLKA)

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)

Generated Clock " CLKB_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)
Defined at "f1/Q" (Generated Clock: CLKB_div2)

Note that the clock pair is reported as “sync” however, the generated clock is defined with “CLKB” as its
master and “CLKB” is defined on different ports which means the clock pair is definitely asynchronous.

3) Now get the clock pair attribute “is_user_relation”.

tv_shell > get_attribute [get_clock_pair -from CLKA -to CLKB_div2] is_user_relation

1

Note the attribute is true meaning the user specified the clock pair relationship.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGIN-INF002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CGIN-INF002 -obj1 CLKA -obj2 CLKB_div2 -author "hollis" -date "07/10/14" -reason "None"

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3.17.3 Rule CGIN-INF003
- User-Inferred asynchronous group between primary/generated clocks, overriding synchronous

Description:
This rule identifies user defined, asynchronous “set_clock_group” relationships between clock pairs
and is in conflict with TimeVision inferred relationship for the clock pair. The user issued the
command: “infer_clock_relations -honor_sdc_clock_groups”, which overrides TimeVision inferred clock
relationships.

Design in figure 3.17.3 below shows timing points reported under rule CGIN-INF003
Figure 3.17.3

Synchronous
infer_clock_relations -honor_sdc_clock_groups

PLL2

CLKB

÷2

CLKB_div2

set_clock_group -async -group { CLKB } -group { CLKB_div2 }

In the above designs, CLKB and CLKB_div2 are synchronous but the clock group has them in different
groups implying asynchronous relationship, however, this is in conflict with Timevision inferred clock
relationship of synchronous between the clock pair.

Therefore, “check_constraints” will report these clocks under rule CGIN-INF003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
Sdc.Interclock CGIN-INF003 Info 1 0 Sdc.Interclock/CGIN-INF003.rpt User-Inferred asynchronous group between
primary/generated clocks, overriding synchronous

Sdc.Interclock/CGIN-INF003.rpt :
# Rule: CGIN-INF003
# Severity: Info
# ==============================
#
# Design : top
# CGIN-INF003
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# User-Inferred synchronous group between primary/generated clocks, overriding asynchronous
#

A# Clock1 Clock1 ID Clock2 Clock2 ID Info

--------------------------------------------------
A0 CLKB 2 CLKB_div2 3
--------------------------------------------------

Debug
1) Get the clock pair relationship attribute

tv_shell > get_clock_relation -clock {CLKB CLKB_div2}

async

2) To see how the clocks are asynchronous run command “justify_inter_clock”. Only portions of this
report is used in this document.

tv_shell > justify_inter_clock -clocks {CLKB CLKB_div2}

#####################################################################
## RELATIONSHIP TYPE: async
#####################################################################

1. async clock source (Sync. Root Clock "CLKB" is defined on object "PLL2/clk_out"):

Create Clock " CLKB" Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)

Generated Clock " CLKB_div2" Source (Starting from "root" master clock onwards):
Defined at "PLL2/clk_out" (Clock: CLKB)
Defined at "f1/Q" (Generated Clock: CLKB_div2)

Note that the clock pair is reported as “async” however, the generated clock is defined with “CLKB” as
its master and “CLKB” which means the clock pair is definitely synchronous.

3) Now get the clock pair attribute “is_user_relation”.

tv_shell > get_attribute [get_clock_pair -from CLKB -to CLKB_div2] is_user_relation

1

Note the attribute is true meaning the user specified the clock pair relationship.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CGIN-INF003 –id A0 –reason “None”
write_waiver top.waivers.tcl
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top.waivers.tcl
set_waiver -rule CGIN-INF003 -obj1 CLKB -obj2 CLKB_div2 -author "hollis" -date "07/10/14" -reason "None"

3.18 Mode rules

3.18.1 Rule MODE-CNF-01

- Conflicting propagated case values

Description:
This rule identifies points where a propagated case value and an applied case value are in conflict.

Design in figure 3.18.1 below shows timing points reported under rule MODE-CNF-01.

Figure 3.18.1

Conflicting propagated case value

A
U1 Z A
B U2 Z
B

( set_case_analysis 1 [get_pins U1/B] ) ( set_case_analysis 0 [get_pins U2/Z] )

In the above designs, a case value of “1” is set on pin U1/B which propagates and conflicts with the
value of “0” is set on pin U2/Z.

Therefore, “check_constraints” will report these clocks under rule MODE-CNF-01.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Mode MODE-CNF-01 Error 1 0 Sdc.Mode/MODE-CNF-01.rpt Conflicting propagated case values

Sdc.Mode/MODE-CNF-01.rpt :
# Rule: MODE-CNF-01
# Severity: Error
# ==============================
#
# Design : top
# MODE-CNF-01
# Conflicting propagated case values
#

A# Case Analysis Point Conflicting Cases

-------------------------------------------------------
A0 set_case_analysis3 U2/Z {set_case_analysis2 }
-------------------------------------------------------

Debug
1) First, trace the constant to pin U2/Z.

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tv_shell > trace_constant -to U2/Z

OBJECT: U2/Z : Case Analysis - constant logic 0

Source : file: tests/check_cons_MODE_test1.tcl line: 29

Note that the pin has a case value set directly on it. Now to find the conflicting constant.

2) Get all the input pins of cell U2 and check the constant values.
tv_shell > get_pins U2/*
{ U2/A U2/B U2/Z }

tv_shell > get_attribute [get_pins U2/A] constant_value

1

tv_shell > get_attribute [get_pins U2/A] constant_value

x

Pin U2/A1 has constant value “1” and pin U2/A has constant value “x”, meaning it is not constant.

3) Now trace the constant to U2/A.

tv_shell > trace_constants -to U2/A1 -fullpath

OBJECT: U2/A : Propagated Case Analysis - constant logic 1

Source : file: tests/check_cons_MODE_test1.tcl line: 28

Path #0
----------------
U1/B OR2_X1 def: 1 (file: tests/check_cons_MODE_test1.tcl line: 28)
U1/Z OR2_X1 prop:1
U2/A OR2_X1 prop:1

Note that pin U1/B has constant value “1” from a constraint file that propagates to U2/Z because U2 is
an OR gate, thus a value “1” propagates from U2/A to the U2/Z pin.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule MODE-CNF-01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule MODE-CNF-01 -obj1 U2/Z -obj2 set_case_analysis3 -author "hollis" -date "07/10/14" -reason "None"
3.18.2 Rule MODE-CNF-02
- Conflicting set_case_analysis

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Description:
This rule identifies points where a propagated case value and an applied case value are in conflict.

Design in figure 3.18.2 below shows timing points reported under rule MODE-CNF-0

Figure 3.18.2

Conflicting case value applied to same point

A
or0 Z
B

( set_case_analysis 0 [get_pins or0/Z] )

( set_case_analysis 1 [get_pins or0/Z] )

In the above designs, conflicticting case values are applied to the same pin.

Therefore, “check_constraints” will report these clocks under rule MODE-CNF-02.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Mode MODE-CNF-02 Error 1 0 Sdc.Mode/MODE-CNF-02.rpt Conflicting set_case_analysis

Sdc.Mode/MODE-CNF-02.rpt :
# Rule: MODE-CNF-02
# Severity: Error
# ==============================
#
# Design : top
# MODE-CNF-02
# Conflicting set_case_analysis
#

A# App Point Cases Conflicting Cases

-----------------------------------------------------------
A0 or1/B {set_case_analysis5 } set_case_analysis4
-----------------------------------------------------------

Debug
1) Since this rule implies conflicting case values are applied directly to the pin, get the constraints
attribute to get the set_case_analysis constraints applied to the pin.
tv_shell [16] > get_attribute [get_pins or1/B] constraints
{ set_case_analysis4 set_case_analysis5 }

Two set_case_analysis are returned.

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2) Get printable attribute of each case analysis.
tv_shell > get_attribute [get_constraints -id 4] printable
set_case_analysis (tests/check_cons_MODE_test1.tcl:32:4) 0 [get_pins or1/B]
tv_shell > get_attribute [get_constraints -id 5] printable
set_case_analysis (tests/check_cons_MODE_test1.tcl:33:5) 1 [get_pins or1/B]
Indeed, conflicting values are applied directly to the pin.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule MODE-CNF-02 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule MODE-CNF-02 -obj1 or1/B -obj2 set_case_analysis4 -author "hollis" -date "07/10/14" -reason "None"

3.18.3 Rule MODE-OVL-01

- Overlapping propagated/set case values

Description:
This rule identifies points where overlapping case values are propagated and applied to the same point.

Design in figure 3.18.3 below shows timing points reported under rule MODE-OVL-01

Figure 3.18.3

Overlapping propagated/set case value

A
a3 ZN A
B Z
B

( set_case_analysis 0 [get_pins or0/A] )

( set_case_analysis 0 [get_pins a3/A] )

In the above designs, overlappinging case values are reported on pin or0/A1.
Therefore, “check_constraints” will report these clocks under rule MODE-OVL-01.

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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Mode MODE-OVL-01 Warning 1 0 Sdc.Mode/MODE-OVL-01.rpt Overlapping propagated/set case values

Sdc.Mode/MODE-OVL-01.rpt :
# Rule: MODE-OVL-01
# Severity: Warning
# ==============================
#
# Design : top
# MODE-OVL-01
# Overlapping propagated/set case values
#

A# Case Analysis Point Overlapping Cases

--------------------------------------------------------------------------
A0 set_case_analysis3 or0/A {set_case_analysis2 }
--------------------------------------------------------------------------

Debug
1) First, trace the constant to pin or0/A.
tv_shell > trace_constant -to or0/A

OBJECT: or0/A : Case Analysis - constant logic 0

Source : file: tests/check_cons_MODE_test1.tcl line: 17

Note that the pin has a case value set directly on it. Now to find the overlapping constant.

2) Trace the path to pin or0/A.

tv_shell > trace_path -to or0/A

Point Type Flags

-------------------------------------------
a3/Z AND2_X1 d
or0/A OR2_X1 d

3) Note the “d” in the Flags column indicating disabled. Pin a3/Z is also disabled, so trace the constant
to that pin.
tv_shell > trace_constants -to a3/AZ -fullpath

OBJECT: a3/Z : Propagated Case Analysis - constant logic 0

Source : file: OVL001.tcl line: 28

Path #0
----------------
a3/A AND2_X1 def: 0 (file: OVL001.tcl line: 28)
a3/Z AND2_X1 prop:0

Note that pin a3/A has constant value “0” from a constraint file that propagates to a3/Z . Since a3/Z
connects directly to or0/A, the constants overlap.

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Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule MODE-OVL-01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule MODE-OVL-01 -obj1 or0/A -obj2 set_case_analysis3 -author "hollis" -date "07/10/14" -reason "None"

3.18.4 Rule MODE-TBL-01

- No Case setting applied to pin involved with multiple clock selection.

Description:
This rule identifies potential mode select points where clocks or scan selects merge, but no case
analysis is set.

Design in figure 3.18.4 below shows timing points reported under rule MODE-TBL-01

Figure 3.18.4

Potentially missing case analysis on mode pin

CLK1
0

CLK2 1

SEL

Missing mode value

In the above designs, there is no case value on the “SEL” where two clocks propagate through the mux.

Therefore, “check_constraints” will report these clocks under rule MODE-TBL-01.

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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Mode MODE-TBL-01 Warning 1 0 Sdc.Mode/MODE-TBL-01.rpt No Case setting applied to pin involved with multiple clock
selection.

Sdc.Mode/MODE-TBL-01.rpt :
# Rule: MODE-TBL-01
# Severity: Warning
# ==============================
#
# Design : top
# MODE-TBL-01
# No Case setting applied to pin involved with multiple clock selection.
#

A# Mode Point
-----------------
A0 SEL
-----------------

Debug
1) First, get the constant_value attribute of the mux select pin to confirm it is not constant.

tv_shell > get_attribute [get_pins M1/S] constant_value

x

Pin M1/S has constant value “x”, meaning it is not constant.

2) Get the clocks attribute of each MUX input pin to confirm a clock propagates each pin.

tv_shell > get_attribute [get_pins M1/I0] clocks

{ CLK1 }
tv_shell > get_attribute [get_pins M1/I1] clocks
{ CLK2 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule MODE-TBL-01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule MODE-TBL-01 -obj1 SEL -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.18.5 Rule MODE-TBL-02
- No Case setting applied to pin involved with single clock selection.

Description:
This rule identifies potential mode select points where a single clock propagates, but no case analysis is
set.

Design in figure 3.18.5 below shows timing points reported under rule MODE-TBL-02

Figure 3.18.5

Potentially missing case analysis on mode pin

where a single clock is selected

CLK1
0

SEL

Missing mode value

In the above designs, there is no case value on the “SEL” where a single clock propagate through the
mux.

Therefore, “check_constraints” will report these clocks under rule MODE-TBL-02.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Mode MODE-TBL-02 Info 1 0 Sdc.Mode/MODE-TBL-02.rpt No Case setting applied to pin involved with single clock
selection.

Sdc.Mode/MODE-TBL-02.rpt :
# Rule: MODE-TBL-01
# Severity: Warning
# ==============================
#
# Design : top
# MODE-TBL-02
# No Case setting applied to pin involved with single clock selection.
#

A# Mode Point
-----------------
A0 SEL
-----------------

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Debug
1) First, get the constant_value attribute of the mux select pin to confirm it is not constant.

tv_shell > get_attribute [get_pins M1/S] constant_value

x

Pin M1/S has constant value “x”, meaning it is not constant.

2) Get the clocks attribute of each MUX input pin to confirm a clock propagates each pin.

tv_shell > get_attribute [get_pins M1/I0] clocks

{ CLK1 }
tv_shell > get_attribute [get_pins M1/I1] clocks
No clocks are returned for pin M1/I1.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule MODE-TBL-02 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule MODE-TBL-02 -obj1 SEL -author "hollis" -date "07/10/14" -reason "None"

3.19 Coverage rules

3.19.1 Rule UNC-001

- Floating or Undriven register clock pins

Description:
This rule identifies register clock pins that are floating or undriven.

Design in figure 3.19.1 below shows timing points reported under rule UNC-001.

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Figure 3.19.1
Floating or Undriven register clock pins
(the mux has no driver so the clock pin is floating )

0 D Q B
CLK

In the above designs, both mux pins are floating so there no driver that propagates to the register clock
pin.

Therefore, “check_constraints” will report these clocks under rule UNC-001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Coverage UNC-001 Error 1 0 Sdc.Coverage/UNC-001.rpt Floating or Undriven register clock pins

Sdc.Coverage/UNC-001.rpt :
# Rule: UNC-001
# Severity: Error
# ==============================
#
# Design : top
# UNC-001
# Floating or Undriven register clock pins
#

A# Clock Pin
----------------
A0 f1/CLK
----------------

Debug
1) Get all fanin to the register clock pin.

tv_shell > all_fanin -to f1/CLK -start

{ M1/I0 M1/I1 }

2) Now get the fanin to each mux pin.

tv_shell > all_fanin -to M1/I0 -start

{ M1/I0 }
tv_shell > all_fanin -to M1/I1 -start
{ M1/I1 }

Each mux input fanin is undriven because only the pin itself was returned.

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Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule UNC-001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule UNC-001 -obj1 f1/CK -author "hollis" -date "07/10/14" -reason "None"

3.19.2 Rule UNC-002

- Un-Clocked register clock pins

Description:
This rule identifies register clock pins that are driven but unclocked.

Design in figure 3.19.2 below shows timing points reported under rule UNC-002.

Figure 3.19.2

Unclocked register pin

(no clock defined on buffer input)

D Q B
CLK

In the above designs, the buffer input is properly connected to a port, however, the port does not have
a clock defined so the register clock pin is driven but never gets a clock.

Therefore, “check_constraints” will report these clocks under rule UNC-002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Coverage UNC-002 Error 1 0 Sdc.Coverage/UNC-002.rpt Un-Clocked register clock pins

Sdc.Coverage/UNC-002.rpt :
# Rule: UNC-002
# Severity: Error
# ==============================

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 TimeVision Constraints User Guide
#
# Design : top
# UNC-002
# Un-Clocked register clock pins
#

A# Clock Pin
----------------
A0 f2/CLK
----------------

Debug
1) Get all fanin to the register clock pin.

tv_shell > all_fanin -to f2/CLK -start

{ clk1 }

2) This is a primary input. Now get the clocks attribute to see if a clock is defined on the port.

tv_shell > get_attribute [get_ports clk1] clocks

Nothing is returned, no clocks are defined on the port so the register is driven but unclocked.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule UNC-002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule UNC-002 -obj1 f2/CLK -author "hollis" -date "07/10/14" -reason "None"

3.19.3 Rule UNC-003

- set_case_analysis or propagated-constant register clock pins

Description:
This rule identifies register clock pins that are driven by a constant.

Design in figure 3.19.3 below shows timing points reported under rule UNC-003.

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 TimeVision Constraints User Guide

Figure 3.19.3

Constant propagates to register clock pins

D Q
A b3 Z CLK

set_case_analysis 0 [get_pins b3/A]

In the above designs, the input of the buffer is set to “0” so the output propagates a constant “0” to
the register clock pin.

Therefore, “check_constraints” will report these clocks under rule UNC-003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Coverage UNC-003 Error 1 0 Sdc.Coverage/UNC-003.rpt set_case_analysis or propagated-constant register clock pins

Sdc.Coverage/UNC-003.rpt :
# Rule: UNC-003
# Severity: Error
# ==============================
#
# Design : top
# UNC-003
# set_case_analysis or propagated-constant register clock pins
#

A# Clock Pin
----------------
A0 f3/CK
----------------
Debug
1) Get all fanin to the register clock pin.

tv_shell > all_fanin -to f3/CLK -start

{ b3/A }

2) Now get the constant_value attribute to see if the pin is a constant.

tv_shell > get_attribute [get_pins b3/A] constant_value

0

3) The pin is a constant “0”. Now get the constraints attribute of pin b3/A to see if the constant is
applied to the pin.

tv_shell > get_attribute [get_pins b3/A] constraints

{ set_case_analysis5 }

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 TimeVision Constraints User Guide
Pin b3/A has a case analysis applied directly, which is the source of the constant propagating to the
register clock pin.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule UNC-003 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule UNC-003 -obj1 f3/CLK -author "hollis" -date "07/10/14" -reason "None"

3.19.4 Rule UNC-004

- Un-Clocked Macro Clock pin

Description:
This rule identifies unclocked macro clock pins.

Design in figure 3.19.4 below shows timing points reported under rule UNC-004

Figure 3.19.4

Unclocked Macro clock pin

Unclocked Macro clock pin

mmac
CK

In the above designs, one input of the AND gate iset to “0” so the output propagates a constant “0” to
the register clock pin.

Therefore, “check_constraints” will report these clocks under rule UNC-004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Coverage UNC-004 Error 1 0 Sdc.Coverage/UNC-004.rpt Un-Clocked Macro Clock pin

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Sdc.Coverage/UNC-004.rpt :
# Rule: UNC-004
# Severity: Error
# ==============================
#
# Design : top
# UNC-004
# Un-Clocked Macro Clock pin
#
A# Clock Pin
----------------
A0 mmac/CK
----------------

Debug
1) Get all fanin to the macro clock pin.

tv_shell > all_fanin -to mmac/CK -start

{ MCLK }

2) Now get the clocks attribute of the port to see if a clock is defined on it.

tv_shell > get_attribute [get_ports MCLK] clocks

Nothing is returned so there is no clock defined on the port.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule UNC-004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule UNC-004 -obj1 mmac/CK -author "hollis" -date "07/10/14" -reason "None"

3.19.5 Rule UNC-005

- constant register clock pins due to tie-offs

Description:
This rule identifies register clock pins that are tied-off to “1” or “0”.

Design in figure 3.19.5 below shows timing points reported under rule UNC-005

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 TimeVision Constraints User Guide
Figure 3.19.5

Tied-off register pin UNC-005

A
_
D Q B
FF1
Q

In the above designs, the clock input of the register is tied to “0”.

Therefore, “check_constraints” will report these clocks under rule UNC-005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------
Sdc.Coverage UNC-005 Warning 1 0 Sdc.Coverage/UNC-005.rpt constant register clock pins due to tie-offs

Sdc.Coverage/UNC-005.rpt :
# Rule: UNC-004
# Severity: Error
# ==============================
#
# Design : top
# UNC-005
# constant register clock pins due to tie-offs
#
A# Clock Pin
----------------
A0 FF1/CK
----------------

Debug
1) Trace the constant to the register clock pin.

tv_shell > trace_constant -to FF1/CK

OBJECT: FF1/CK : Tied - constant logic 0

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule UNC-005 –id A0 –reason “None”

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write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule UNC-005 -obj1 FF1/CK -author "hollis" -date "07/10/14" -reason "None"

3.20 LOOP rules

3.20.1 Rule LOOP-01

- Datapath loop not broken by SDC

Description:
This rule identifies datapth combinational loops in the design where no SDC constraint exist to break
the loop.

Design in figure 3.20.1 below shows timing points reported under rule LOOP-01.

Figure 3.20.1

LOOP-01
_
D Q
FF1
clk1 B1 Q A
A1 Z I1 B2
create_clock -name CLK1 B
[get_ports clk1]

In the above design, a datapath loop exist to A1/B.

Therefore, “check_constraints” will report these clocks under rule LOOP-01.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.Netlist LOOP-01 Warning 1 0 Sdc.Netlist/LOOP-01.rpt Datapath loop not broken by SDC

Sdc.Netlist/LOOP-01.rpt :
# Rule: LOOP-01
# Severity: Warning
# ==============================
#
# Design : top
# LOOP-01
# Datapath loop not broken by SDC
#

A# Clock Pin
---------------------------
A0 A1
---------------------------

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Debug
1) Trace path from “A1/Z” to “A1/B”.

tv_shell > trace_path -from A1/Z -to A1/B

Point Type Flags
-------------------------------------------
A1/Z AND2_X1
I1/A INV_X1
I1/ZN INV_X1
A1/B AND2_X1

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule LOOP-01 -obj1 A1 -obj2 B -obj3 Z -author "hollis" \
-date "12/04/14" -reason "None"

write_waiver top.waivers.tcl

3.20.2 Rule LOOP-02

- Clock loop not broken by SDC

Description:
This rule identifies clock path combinational loops in the design where no SDC constraint exist to break
the loop.

Design in figure 3.20.2 below shows timing points reported under rule LOOP-01.

Figure 3.20.2

_ LOOP-02
D Q

clk1 B1 A
A1 Z B2 A
B A2 Z B3
create_clock -name CLK1 B
[get_ports clk1]

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In the above design, a clock path combinational loop exist to A1/B.

Therefore, “check_constraints” will report these clocks under rule LOOP-02.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.Netlist LOOP-02 Warning 1 0 Sdc.Netlist/LOOP-02.rpt Clock loop not broken by SDC

Sdc.Netlist/LOOP-02.rpt :
# Rule: LOOP-02
# Severity: Warning
# ==============================
#
# Design : top
# LOOP-02
# Clock loop not broken by SDC
#

A# Clock Pin
---------------------------
A0 A1
---------------------------

Debug
1) Trace path from “A1/Z” to “A1/B”.

tv_shell > trace_path -from A1/Z -to A1/B

Point Type Flags
-------------------------------------------
A1/Z AND2_X1
B2/A BUF_X1
B2/Z BUF_X1
A2/A AND2_X1
A2/Z AND2_X1
B3/A BUF_X1
B3/Z BUF_X1
A1/B AND2_X1

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule LOOP-02 -obj1 A1 -obj2 B -obj3 Z -author "hollis" \
-date "12/04/14" -reason "None"

write_waiver top.waivers.tcl
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3.21 Incorrect IO rules

3.21.1 Rule IOC-INC001/IOC-INC004

- Incorrect & Effectively Unconstrained Input/Output Data port

Description:
This rule identifies IO ports which are constrained to the wrong clock and there is a false path set
between the constraining clock and the register clock, effectively making the IO port unconstrained.

Design in figure 3.21.1 below shows timing points reported under rule IOC-INC001/IOC-INC004.

Figure 3.21.1

Incorrect clock, also effectively unconstrained

(CLK1, CLK2 are async, and false path exist)
_
D1 D Q
set_input_delay 1.0 -clock [get_clocks CLK2] [get_ports D1] FF1
clk1 Q T1

create_clock -name CLK1 [get_ports clk1] set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports T1]
set_clock_group -group CLK1 -group CLK2

In the above designs, the input and output ports are constrained to a different clock than the one
which clocks data into the register. The clocks are async and have a clock group between them, which
makes the ports effectively unconstrained.

Therefore, “check_constraints” will report these clocks under rule IOC-INC001/IOC-INC004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-INC001 Fatal 1 0 Sdc.IO/IOC-INC001.rpt Incorrect & Effectively Unconstrained Input Data port
IOC-INC004 Fatal 1 0 Sdc.IO/IOC-INC004.rpt Incorrect & Effectively Unconstrained Output Data port

Sdc.IO/IOC-INC001.rpt :
# Rule: IOC-INC001
# Severity: Fatal
# ==============================
# Design : top
# IOC-INC001
# Incorrect & Effectively Unconstrained Input Data port
#

A# Port Current Clock

---------------------------
A0 D1 CLK2
---------------------------

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Sdc.IO/IOC-INC004.rpt :
# Rule: IOC-INC004
# Severity: Fatal
# ==============================
#
# Design : top
# IOC-INC004
# Incorrect & Effectively Unconstrained Output Data port
#

A# Port Current Clock

---------------------------
A0 T1 CLK2
---------------------------

Debug
1) Use the “justify_io_cons” command to get the violations details.

tv_shell > justify_io_cons -port [get_ports D1]

## Input Port "D1" :

*Constrained using "set_input_delay" w.r.t. :

clock:CLK2 Period:11.0

*Driving Data Endpoints:

-> FF1/D
clocked by:CLK1 Period:10.0

2) Now check for false path between the clock pair.

tv_shell > get_constraints -clock {CLK2 CLK1}
{ CLK1 CLK2 set_input_delay7 set_clock_group9 }

3) Get the printable attribute of the clock group.

tv_shell > get_attribute [get_constraints -id 9] printable
set_clock_group (tests/check_constraints_IOC_IOC.tcl:24:9) -asynchronous \
-group [get_clocks { CLK1 }] -group [get_clocks { CLK2 }]

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-INC001 –id A0 –reason “None”
set_waiver -rule IOC-INC004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-INC001 -obj1 D1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule IOC-INC004 -obj1 T1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"

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 TimeVision Constraints User Guide
3.21.2 Rule IOC-INC002/IOC-INC005
- Incorrectly Constrained (Non-Harmonic) Input/Output Data port

Description:
This rule identifies IO ports which are constrained to the wrong clock and the constraining clock and
the register clock are non-harmonic.

Design in figure 3.21.2 below shows timing points reported under rule IOC-INC002/IOC-INC005.
Figure 3.21.2
Incorrect non-harmonic clock, no false path
(CLK1, CLK2 are async, non-harmonic)
CLK1 period = 1.5ns ; CLK2 period = 2.7ns
_
D1 D Q
set_input_delay 1.0 -clock [get_clocks CLK2] [get_ports D1] FF1
clk1 Q T1

create_clock -name CLK1 [get_ports clk1] set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports T1]

In the above designs, the input and output ports are constrained to a different clock than the one
which clocks data into the register. The clocks are async, non-harmonic and there is no false path
between them.

Therefore, “check_constraints” will report these clocks under rule IOC-INC002/IOC-INC005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-INC002 Warning 1 0 Sdc.IO/IOC-INC002.rpt Incorrectly Constrained (Non-Harmonic) Input Data port
IOC-INC005 Warning 1 0 Sdc.IO/IOC-INC005.rpt Incorrectly Constrained (Non-Harmonic) Output Data port

Sdc.IO/IOC-INC002.rpt :
# Rule: IOC-INC002
# Severity: Warning
# ==============================
#
# Design : top
# IOC-INC002
# Incorrectly Constrained (Non-Harmonic) Input Data port
#

A# Port Current Clock

---------------------------
A0 D1 CLK2
---------------------------

Sdc.IO/IOC-INC005.rpt :
# Rule: IOC-INC005
# Severity: Warning
# ==============================
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 TimeVision Constraints User Guide
#
# Design : top
# IOC-INC005
# Incorrectly Constrained (Non-Harmonic) Output Data port
#

A# Port Current Clock

---------------------------
A0 T1 CLK2
---------------------------

Debug
1) Use the “justify_io_cons” command to get the violations details.

tv_shell > justify_io_cons -port [get_ports D1]

## Input Port "D1" :

*Constrained using "set_input_delay" w.r.t. :

clock:CLK2 Period:2.7

*Driving Data Endpoints:

-> FF1/D
clocked by:CLK1 Period:1.5

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-INC002 –id A0 –reason “None”
set_waiver -rule IOC-INC005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-INC002 -obj1 D1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule IOC-INC005 -obj1 T1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"

3.21.3 Rule IOC-INC003/IOC-INC006

- Incorrectly Constrained (Harmonic) Input/Output Data port

Description:
This rule identifies IO ports which are constrained to the wrong clock and the constraining clock and
the register clock are harmonic.

Design in figure 3.21.3 below shows timing points reported under rule IOC-INC003/IOC-INC006.

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Figure 3.21.3

Incorrect non-harmonic clock, no false path

(CLK1, CLK2 are async, harmonic)
CLK1 period = 1.5ns ; CLK2 period = 3.0ns
_
D1 D Q
set_input_delay 1.0 -clock [get_clocks CLK2] [get_ports D1] FF1
clk1 Q T1

create_clock -name CLK1 [get_ports clk1] set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports T1]

In the above designs, the input and output ports are constrained to a different clock than the one
which clocks data into the register. The clocks are async, harmonic and there is no false path between
them.

Therefore, “check_constraints” will report these clocks under rule IOC-INC003/IOC-INC006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-INC003 Warning 1 0 Sdc.IO/IOC-INC003.rpt Incorrectly Constrained (Harmonic) Input Data port
IOC-INC006 Warning 1 0 Sdc.IO/IOC-INC006.rpt Incorrectly Constrained (Harmonic) Output Data port

Sdc.IO/IOC-INC003.rpt :
# Rule: IOC-INC003
# Severity: Warning
# ==============================
#
# Design : top
# IOC-INC003
# Incorrectly Constrained (Harmonic) Input Data port
#

A# Port Current Clock

---------------------------
A0 D1 CLK2
---------------------------

Sdc.IO/IOC-INC006.rpt :
# Rule: IOC-INC006
# Severity: Warning
# ==============================
#
# Design : top
# IOC-INC006
# Incorrectly Constrained (Harmonic) Output Data port
#

A# Port Current Clock

---------------------------
A0 T1 CLK2
---------------------------

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 TimeVision Constraints User Guide
Debug
Use the “justify_io_cons” command to get the violations details.

tv_shell > justify_io_cons -port [get_ports D1]

## Input Port "D1" :

*Constrained using "set_input_delay" w.r.t. :

clock:CLK2 Period:3.0

*Driving Data Endpoints:

-> FF1/D
clocked by:CLK1 Period:1.5

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-INC003 –id A0 –reason “None”
set_waiver -rule IOC-INC006 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-INC003 -obj1 D1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule IOC-INC006 -obj1 T1 -obj2 CLK2 -author "hollis" -date "07/10/14" -reason "None"

3.22 Missing IO rules

3.22.1 Rule IOC-MIS001/IOC-MIS002

- Unconstrained Input/Output Data port
Description:
This rule identifies IO ports which are constrained to the wrong clock and there is a false path set
between the constraining clock and the register clock, effectively making the IO port unconstrained.

Design in figure 3.22.1 below shows timing points reported under rule IOC-MIS001/IOC-MIS002.

Figure 3.22.1
Unconstrained Input and Output ports

_
D1 D Q
No constraint FF1
clk1 Q T1

create_clock -name CLK1 [get_ports clk1] No constraint

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 TimeVision Constraints User Guide
In the above designs, the input and output ports are unconstrained.

Therefore, “check_constraints” will report these clocks under rule IOC-MIS001/IOC-MIS002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-MIS001 Warning 1 0 Sdc.IO/IOC-MIS001.rpt Unconstrained Input Data port
IOC-MIS002 Warning 1 0 Sdc.IO/IOC-MIS002.rpt Unconstrained Output Data port

Sdc.IO/IOC-MIS001.rpt :
# Rule: IOC-MIS001
# Severity: Warning
# ==============================
#
# Design : top
# IOC-MIS001
# Unconstrained Input Data port
#

A# Port
-------------
A0 D1
-------------

Sdc.IO/IOC-MIS002.rpt :
# Rule: IOC-MIS002
# Severity: Warning
# ==============================
#
# Design : top
# IOC-INC002
# Unconstrained Output Data port
#

A# Port
-------------
A0 T1
-------------

Debug
Get the constraints attribute of the port to see if it is constrained.

tv_shell > get_attribute [get_ports D1] constraints

Nothing is returned, the port is unconstrained.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

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After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-MIS001 –id A0 –reason “None”
set_waiver -rule IOC-MIS002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-MIS001 -obj1 D1 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule IOC-MIS002 -obj1 T1 -author "hollis" -date "07/10/14" -reason "None"

3.23 Under constrained IO rules

3.23.1 Rule IOC-UND001/IOC-UND002

- Underconstrained Input/Output Data port

Description:
This rule identifies IO ports which are not constrained relative to all clocks clocking the associated
registers.

Design in figure 3.23.1 below shows timing points reported under rule IOC-UND001/IOC-UND002.

Figure 3.23.1

Underconstrained input and output ports,

(not constrained with respect to every clock)
_
D1 D Q
set_input_delay 1.0 -clock [get_clocks CLK2] [get_ports D1] FF1
clk1 Q T1

create_clock -name CLK1 [get_ports clk1] set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports T1]
create_clock -name CLK2 [get_ports clk1] -add

In the above designs, the input and output ports are underconstrained because they are not
constrained with respect to every clock which reaches the register.

Therefore, “check_constraints” will report these clocks under rule IOC-UND001/IOC-UND002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-UND001 Warning 1 0 Sdc.IO/IOC-UND001.rpt UnderConstrained Input Data port
IOC-UND002 Warning 1 0 Sdc.IO/IOC-UND002.rpt UnderConstrained Output Data port

Sdc.IO/IOC-UND001.rpt :
# Rule: IOC-UND001
# Severity: Warning
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# ==============================
#
# Design : top
# IOC-UND001
# UnderConstrained Input Data port
#

A# Port Expected Clock

----------------------------
A0 D1 CLK1
----------------------------

Sdc.IO/IOC-UND002.rpt :
# Rule: IOC-UND002
# Severity: Warning
# ==============================
#
# Design : top
# IOC-UND002
# UnderConstrained Output Data port
#
A# Port Expected Clock
----------------------------
A0 T1 CLK1
----------------------------

Debug
Use the “justify_io_cons” command to get the violations details.
tv_shell > justify_io_cons -port [get_ports D1]

## Input Port "D1" :

*Constrained using "set_input_delay" w.r.t. :

clock:CLK1 Period:20.0

*Driving Data Endpoints:

-> FF1/D
clocked by:CLK1 Period:10.0
clocked by:CLK2 Period:5.0

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-UND001 –id A0 –reason “None”
set_waiver -rule IOC-UND002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-UND001 -obj1 D1 -obj2 CLK1 -author "hollis" -date "07/10/14" -reason "None"
set_waiver -rule IOC-UND002 -obj1 T1 -obj2 CLK1 -author "hollis" -date "07/10/14" -reason "None"
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3.24 Source Sync IO rules

3.24.1 Rule IOC-SSI001

- Source-Sync Output Data port not constrained to source-sync clock

Description:
This rule identifies IO ports which are not constrained as a source-sync interface. When a clock is
connected to an output port, a generated clock should be defined at the output port with the
connected clock defined as its master clock. When a register is clocked by the master clock and drives
an output port, the output port should be constrained to the generated clock defined on the clock
output port, creating a source-sync interface.

Design in figure 3.24.1 below shows timing points reported under rule IOC-SSI001.

Figure 3.24.1

Source Synchronous output port not constrained to source-sync clock

Generated Clock :
Generated Clock : CLK1_div2_out
CLK1 CLK1_div2
PLL 0 ÷2
_
D Q set_output_delay 1.0 -clock
[get_clocks CLK1_div2] [get_ports out]
FF1
Q out

In the above designs, the source-sync output port is not constrained with respect to the source-sync
clock CLK1_div2_out..

Therefore, “check_constraints” will report these clocks under rule IOC-SSI001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-SSI001 Warning 1 0 Sdc.IO/IOC-SSI001.rpt Source-Sync Output Data port not constrained to source-sync clock
Sdc.IO/IOC-SSI001.rpt :
# Rule: IOC-SSI001
# Severity: Warning
# ==============================
#
# Design : top
# IOC-SSI001
# Source-Sync Output Data port not constrained to source-sync clock
#

A# Port Expected Clock

----------------------------
A0 out CLK1_div2_out
----------------------------

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Debug
Use the “justify_io_cons” command to get the violations details.

tv_shell > justify_io_cons -port [get_ports out]

## Output Port "out" :

*Constrained using "set_output_delay" w.r.t. :

clock:CLK1_div2 Period:8.4

*Driven by Startpoints:
<- FF1/CK
clocked by:CLK1_div2 Period:8.4

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-SSI001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-SSI001 -obj1 out -obj2 CLK1_div2_out -author "hollis" -date "07/10/14" -reason "None"

3.25 Feedthru IO rules

3.25.1 Rule IOC-FTP001

- Unconstrained feedthrough pair

Description:
This rule identifies unconstrained IO port pairs which are combinational feed throughs.

Design in figure 3.25.1 below shows timing points reported under rule IOC-FTP001.

Figure 3.25.1

Feedthru IO pair completely unconstrained

in out
Combo Logic

In the above designs, shows a feedthru pair that is completely unconstrained.

Therefore, “check_constraints” will report these clocks under rule IOC-FTP001.

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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Severity Status Object_1 Object_2
----------------------------------------------------------
Sdc.IO IOC-FTP001 Warning FAIL in out

Sdc.IO/IOC-FTP001.rpt :
# Rule: IOC-FTP001
# Severity: Warning
# ==============================
#
# Design : top
# IOC-FTP001
# Unconstrained feedthrough pair.
#
A# Input Port Output Port
------------------------------
A0 in out
------------------------------

Debug

Trace the feedthrough path to see if it is constrained

tv_shell > trace_path -from [get_ports in] -to [get_ports out]

Point Type Flags

-------------------------------------------
(Unconstrained Endpoint)
in1 (port)
b1/A BUF_X1
b1/Z BUF_X1
out1 (port)
(Unconstrained Endpoint)

Note that both input and output ports are unconstrained

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-FTP001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-FTP001 -obj1 in -obj2 out -author "hollis" -date "07/10/14" -reason "None"

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3.25.2 Rule IOC-FTP002
- IO constraint conflict on feedthrough pair - input/output delay and max delays

Description:
This rule identifies IO port pairs which are feed throughs which have set_input_delay constraint on the
input port, set_output_delay on the output port, and a set_max_delay from the input port to the
output port, creating a constraint conflict.

Design in figure 3.25.2 below shows timing points reported under rule IOC-FTP002.

Figure 3.25.2

Feedthru IO pair with conflicting constraints

set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports out]

set_input_delay 1.0 -clock [get_clocks CLK2] [get_ports in]

in out
Combo Logic

set_max_delay 1.0 -from [get_ports in] -to [get_ports out]

In the above designs, shows a feedthru pair that conflicting constraints. The ports are constrained with
set_input_delay/set_output_delay and set_max_delay.

Therefore, “check_constraints” will report these clocks under rule IOC-FTP002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-FTP002 Warning 1 0 Sdc.IO/IOC-FTP002.rpt IO constraint conflict on feedthrough pair - input/output delay & max
delays

Sdc.IO/IOC-FTP002.rpt :
# Rule: IOC-FTP002
# Severity: Warning
# ==============================
#
# Design : top
# IOC-FTP002
# IO constraint conflict on feedthrough pair - input/output delay & max delays
#

A# Input Port Output Port

------------------------------
A0 in out
------------------------------

Debug
1) Get the constraints attribute for feedthrough pair.
tv_shell > get_attribute [get_ports in] constraints
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{ set_input_delay10 set_max_delay12 }
tv_shell > get_attribute [get_ports out] constraints
{ set_output_delay11 }

2) Get the printable attribute of the input port set_max_delay constraint.

tv_shell > get_attribute [get_constraints -id 12] printable

set_max_delay (tests/check_constraints_IOC-FTP_test1.tcl:35:12) 3.4 -from [get_ports in]

Waivers
Any reported violation can be waived using the “set_waiver” command.
Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-FTP002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-FTP002 -obj1 in -obj2 out -author "hollis" -date "07/10/14" -reason "None"

3.25.3 Rule IOC-FTP003

- Feedthrough pair constrained with non-harmonic clocks

Description:
This rule identifies IO port pairs which are feed throughs which have set_input_delay constraint on the
input port, set_output_delay on the output port, and the clock pair is non-harmonic.

Design in figure 3.25.3 below shows timing points reported under rule IOC-FTP003.

Figure 3.25.3

Feedthru IO pair constrained with

Async, Non-Harmonic clocks
CLK1 period = 1.5ns; CLK2 period = 2.7ns
set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports out]
set_input_delay 1.0 -clock [get_clocks CLK1] [get_ports in]

in out
Combo Logic

In the above designs, shows a feedthru pair that conflicting constraints. The ports are constrained with
set_input_delay/set_output_delay and set_max_delay.

Therefore, “check_constraints” will report these clocks under rule IOC-FTP003.

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Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-FTP003 Warning 1 0 Sdc.IO/IOC-FTP003.rpt Feedthrough pair constrained with non-harmonic clocks

Sdc.IO/IOC-FTP003.rpt :
# Rule: IOC-FTP003
# Severity: Warning
# ==============================
#
# Design : top
# IOC-FTP003
# Feedthrough pair constrained with non-harmonic clocks.
#

A# Input Port Output Port

------------------------------
A0 in out
------------------------------

Debug
1) Get the constraints attribute for feedthrough pair.

tv_shell > get_attribute [get_ports in] constraints

{ set_input_delay8}
tv_shell > get_attribute [get_ports out] constraints
{ set_output_delay9 }

2) Get the printable attribute of each port constraint.

tv_shell > get_attribute [get_constraints -id 8] printable
set_input_delay (tests/check_constraints_IOC-FTP_test1.tcl:29:8) \
-clock [get_clocks CLK1] 1.0 [get_ports in]

tv_shell > get_attribute [get_constraints -id 9] printable

set_input_delay (tests/check_constraints_IOC-FTP_test1.tcl:30:9) \
-clock [get_clocks CLK2] 1.0 [get_ports out]

3) Get the period attribute of each clock.

tv_shell > get_attribute [get_clocks CLK1] period
{ 1.5 }

tv_shell > get_attribute [get_clocks CLK2] period

{ 2.7 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

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Example:
set_waiver -rule IOC-FTP003 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-FTP003 -obj1 in -obj2 out -author "hollis" -date "07/10/14" -reason "None"

3.25.4 Rule IOC-FTP004

- Feedthrough pair effectively unconstrained

Description:
This rule identifies IO port pairs which are feed throughs which have set_input_delay constraint on the
input port, set_output_delay on the output port, and the clock pair are async and have a
set_clock_group between them, so the feedthrough pair is effectively undonstrained..

Design in figure 3.25.4 below shows timing points reported under rule IOC-FTP004.
Figure 3.25.4

Feedthru IO pair constrained with

Async, clocks and a set_clock_group exist
set_clock_group -async -group CLK1 -group CLK2
set_output_delay 1.0 -clock [get_clocks CLK2] [get_ports out]
set_input_delay 1.0 -clock [get_clocks CLK1] [get_ports in]

in out
Combo Logic

In the above designs, shows a feedthru pair constrained with set_input_delay/set_output_delay with
async clocks and a set_clock_group exist between the clock pair making the feedthrough pair
effectively unconstrained.

Therefore, “check_constraints” will report these clocks under rule IOC-FTP004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-FTP004 Warning 1 0 Sdc.IO/IOC-FTP004.rpt Feedthrough pair effectively unconstrained

Sdc.IO/IOC-FTP004.rpt :
# Rule: IOC-FTP004
# Severity: Warning
# ==============================
# Design : top
# IOC-FTP004
# Feedthrough pair effectively unconstrained.
#
A# Input Port Output Port
------------------------------
A0 in out
------------------------------

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Debug
1) Get the constraints attribute for feedthrough pair.

tv_shell > get_attribute [get_ports in] constraints

{ set_input_delay13 }
tv_shell > get_attribute [get_ports out] constraints
{ set_output_delay14 }

2) Get the printable attribute of each port constraint.

tv_shell > get_attribute [get_constraints -id 13] printable
set_input_delay (tests/check_constraints_IOC-FTP_test1.tcl:34:13) \
-clock [get_clocks CLK1] 1.0 [get_ports in]

tv_shell > get_attribute [get_constraints -id 9] printable

set_input_delay (tests/check_constraints_IOC-FTP_test1.tcl:35:14) \
-clock [get_clocks CLK2] 1.0 [get_ports out]

3) Get the period attribute of each clock.

tv_shell > get_attribute [get_clocks CLK1] period
{ 1.5 }

tv_shell > get_attribute [get_clocks CLK2] period

{ 2.7 }

3) Check if a set_clock_group exist between the clock pair.

tv_shell > get_constraints -clock {CLK1 CLK2} -type set_clock_group
{ set_clock_group5 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-FTP004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-FTP004 -obj1 in -obj2 out -author "hollis" -date "07/10/14" -reason "None"

3.25.5 Rule IOC-FTP005

- inconsistent set_min/set_max delays on feedthrough

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Description:
This rule identifies IO port pairs which are feed throughs and have set_min_delay constraint which is
greater than the set_max_delay.

Design in figure 3.25.5 below shows timing points reported under rule IOC-FTP005.

Figure 3.25.5

inconsistent set_min/set_max delays on feedthrough

in out
Combo Logic

set_max_delay 1.0 -from [get_ports in] -to [get_ports out]

set_min_delay 1.1 -from [get_ports in] -to [get_ports out]

In the above design, a feedthru pair constrained with set_min_delay/set_max_delay and the min delay
(1.1) is greater than the max delay (1.0).

Therefore, “check_constraints” will report these clocks under rule IOC-FTP005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-FTP005 Warning 1 0 Sdc.IO/IOC-FTP005.rpt Feedthrough pair with inconsistent set_min/set_max delay.

Sdc.IO/IOC-FTP005.rpt :
# Rule: IOC-FTP005
# Severity: Warning
# ==============================
#
# Design : top
# IOC-FTP005
# Feedthrough pair with inconsistent set_min/set_max delay
#

A# Input Port Output Port Max Delay Min Delay

-----------------------------------------------------------------------------------------
A0 in out set_max_delay0 set_min_delay1
------------------------------------------------------------------------------------------

Debug
1) Get the printable attribute of the set_min/set_max delay to confirm the inconsistency.

tv_shell > get_attribute [get_exceptions –id 0] printable

set_max_delay (tests/check_cons_IOC-FTP005_test1.tcl:19:0) 1.0 -from [get_ports in] \
-to [get_ports out]
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 TimeVision Constraints User Guide
tv_shell > get_attribute [get_exceptions –id 1] printable
set_min_delay (tests/check_cons_IOC-FTP005_test1.tcl:20:1) 1.1 -from [get_ports in] \
-to [get_ports out]
Note the min delay value (1.1) is greater than the max delay value (1.0).

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-FTP005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule IOC-FTP005 -obj1 in -obj2 out -obj3 MXD.Fxa16fb51c0eeTx28253ca75d67fV1.0 \
-obj4 MND.Fxa16fb51c0eeTx28253ca75d67fV1.1 -author "hollis" -date "05/07/15" -reason "None"

3.25.6 Rule IOC-FTP006

- Feedthrough pair with inconsistent input/output delay

Description:
This rule identifies IO port pairs which are feed throughs and have set_input_delay/set_output_delay
on the feedthrough pair constrained to the same clock or virtual clock which maps to the same real
clock and the combination of the delays greater than or equal to the period of the clock.

Design in figure 3.25.6 below shows timing points reported under rule IOC-FTP006.

Figure 3.25.6

inconsistent set_input/set_output delays on feedthrough pair

in out
Combo Logic

create_clock -name clk1_v -period 1.2

set_input_delay 1.0 -max -clock [ get_clocks clk1_v ] [ get_ports in ]
set_output_delay 0.3 -max -clock [ get_clocks clk1_v ] [ get_ports out ]

In the above design, a feedthru pair constrained with set_input_delay/set_output_delay to a virtual

clock of period “1.2”, however, the sum of the set_input_delay and set_output_delay is “1.3”, which is
greater than the clock period.

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 TimeVision Constraints User Guide
Therefore, “check_constraints” will report these clocks under rule IOC-FTP006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.IO IOC-FTP006 Warning 1 0 Sdc.IO/IOC-FTP006.rpt Feedthrough pair with inconsistent input/output delay.

Sdc.IO/IOC-FTP006.rpt :
# Rule: IOC-FTP006
# Severity: Warning
# ==============================
#
# Design : top
# IOC-FTP006
# Feedthrough pair with inconsistent input/output delay.
#

A# Input Port Output Port Input Delay Output Delay

------------------------------------------------------------------------------------------
A0 in out set_input_delay2 set_output_delay3
-----------------------------------------------------------------------------------------

Debug
1) Get the period attribute of the virtual clock the set_input/set_out delay are constrained.
tv_shell > get_attribute [get_clocks clk_v] period
{ 1.2 }

2) Get the printable attribute of the set_input/set_out delay to confirm the inconsistency.

tv_shell > get_attribute [get_exceptions –id 2] printable

set_input_delay (tests/check_cons_IOC-FTP006_test2.tcl:22:2) -max -clock [get_clocks clk_v] \
1.0 [get_ports in]

tv_shell > get_attribute [get_exceptions –id 3] printable

set_output_delay (tests/check_cons_IOC-FTP006_test2.tcl:23:3) -max -clock [get_clocks clk_v]\
0.3 [get_ports out]

Note the sum of the input delay value (1.0) and the output delay value (0.3) is greater than the
constraining clock period (1.2).

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule IOC-FTP006 –id A0 –reason “None”
write_waiver top.waivers.tcl

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top.waivers.tcl
set_waiver -rule IOC-FTP006 -obj1 in -obj2 out -obj3 set_input_delay2 -obj4 set_output_delay3 -author "hollis" -date "05/07/15" \
-reason "None"

3.26 Point-to-Point exception rules

3.26.1 Rule PPFP-001

- pnt-to-pnt set_false_path between sync_same_period clocks

Description:
This rule identifies point-to-point “set_false_path” between synchronous clocks with the same
clock period.

Design in figure 3.26.1 below shows timing points reported under rule PPFP-001.
Figure 3.26.1

Point-to-Point false path between sync_same_period clock

create_generated_clock -source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]
create_generated_clock -source [get_ports clk1] -divide_by 2 [get_pins FF3/Q]

_ _
D Q D Q
FF1 FF2
clk1 B1 Q Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q D
_
Q Logic
FF3 FF4
Q Q

set_false_path -from FF2/CK -to FF4/D

In the above designs, shows that generated clocks of the same source drive registers with a point-to-
point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-001 Warning 1 0 Sdc.Exception/PPFP-001.rpt pnt-to-pnt set_false_path between sync_same_period
clocks

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Sdc.Exception/PPFP-001.rpt :

# ==============================
#
# Design : top
# PPFP-001
# pnt-to-pnt set_false_path between sync_same_period clocks
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path5
----------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 5] printable

set_false_path (tests/check_cons_PPFP_test1.tcl:32:5) -from [get_pins FF2/CK] \
-to [get_pins FF4/D]

2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.

tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF4/D] data_clocks
{ gclk2 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:26:1) -name gclk1 \
-source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-001 -obj1 FP.Fxa3b7d435801354Tx28253c9ae1d9a -obj2 gclk1 -obj3 gclk2 -author "hollis" \
-date "07/30/14" -reason "None"

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3.26.2 Rule PPFP-002

- pnt-to-pnt set_false_path between sync_slow_to_fast_integral clocks

Description:
This rule identifies point-to-point “set_false_path” between synchronous clocks with clock periods that
are slow-to-fast integral.

Design in figure 3.26.2 below shows timing points reported under rule PPFP-002.

Figure 3.26.2

Point-to-Point false path between sync_slow_to_fast_integral clock

create_generated_clock -source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

_ _
D Q D Q
FF1 FF2
clk1 B1 Q Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q Logic
FF3
Q

set_false_path -from FF2/CK -to FF3/D

In the above designs, shows that a divided clocks drive one registers and the undivided clock drives the
other and there is a point-to-point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-002.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-002 Warning 1 0 Sdc.Exception/PPFP-002.rpt pnt-to-pnt set_false_path between
sync_slow_to_fast_integral clocks

Sdc.Exception/PPFP-002.rpt :
# ==============================
#
# Design : top
# PPFP-002
# pnt-to-pnt set_false_path between sync_slow_to_fast_integral clocks
# Severity: Warning
#
# ==============================
#
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 TimeVision Constraints User Guide
# Violations
#

A# Exception
----------------------
A0 set_false_path8
----------------------
Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 8] printable

set_false_path (tests/check_cons_PPFP_test1.tcl:37:8) -from [get_pins FF2/CK] \
-to [get_pins FF3/D]
2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.
tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF3/D] data_clocks
{ CLK1 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:27:5) -name gclk1 \
-source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

tv_shell > get_attribute [get_clocks CLK1] printable

create_clock (tests/check_cons_PPFP_test1.tcl:2:1) -name CLK1 -period 1.5 [get_ports clk1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-002 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-002 -obj1 FP.Fxa3b7d435f893feTx28253c9ae3c78 -obj2 gclk1 -obj3 CLK1 -author "hollis" -date "07/30/14" \
-reason "None"

3.26.3 Rule PPFP-003

- pnt-to-pnt set_false_path between sync_slow_to_fast_nonintegral clocks

Description:
This rule identifies point-to-point “set_false_path” between synchronous clocks with clock periods that
are slow-to-fast nonintegral.

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Design in figure 3.26.3 below shows timing points reported under rule PPFP-003.

Figure 3.26.3

Point-to-Point false path between sync_slow_to_fast_nonintegral clock

create_generated_clock -source [get_ports clk1] -divide_by 3 [get_pins FF1/Q]

_ _
D Q D Q
FF1 FF2
clk1 B1 Q Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q Logic
FF3
Q

set_false_path -from FF2/CK -to FF3/D

In the above designs, shows that a divide_by 3 clocks drive one registers and the undivided clock drives
the other and there is a point-to-point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-003.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-003 Warning 1 0 Sdc.Exception/PPFP-003.rpt pnt-to-pnt set_false_path between
sync_slow_to_fast_nonintegral clocks

Sdc.Exception/PPFP-003.rpt
# ==============================
#
# Design : top
# PPFP-003
# pnt-to-pnt set_false_path between sync_slow_to_fast_nonintegral clocks
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path9
----------------------

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Debug
1) Get the printable attribute of the false path.
tv_shell > get_attribute [get_constraints -id 9] printable
set_false_path (tests/check_cons_PPFP_test1.tcl:40:9) -from [get_pins FF2/CK] \
-to [get_pins FF3/D]

2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.

tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF3/D] data_clocks
{ CLK1 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:29:7) -name gclk1 \
-source [get_ports clk1] -divide_by 3 [get_pins FF1/Q]

tv_shell > get_attribute [get_clocks CLK1] printable

create_clock (tests/check_cons_PPFP_test1.tcl:2:1) -name CLK1 -period 1.5 [get_ports clk1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-003 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-003 -obj1 FP.Fxa3b7d435f4cd3eTx28253c9adef65 -obj2 gclk1 -obj3 CLK1 -author "hollis" -date "07/30/14" \
-reason "None"

3.26.4 Rule PPFP-004

- pnt-to-pnt set_false_path between sync_fast_to_slow_integral clocks

Description:
This rule identifies point-to-point “set_false_path” between synchronous clocks with clock periods that
are fast-to-slow integral.

Design in figure 3.26.4 below shows timing points reported under rule PPFP-004.

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Figure 3.26.4

Point-to-Point false path between sync_fast_to_slow_integral clock

create_generated_clock -source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

_ _
D Q D Q
FF1 FF2
clk1 B1 Q Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q Logic
FF3
Q

set_false_path -from FF3/CK -to FF2/D

In the above designs, shows that a divided clocks drive one registers and the undivided clock drives the
other and there is a point-to-point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-004.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-004 Warning 1 0 Sdc.Exception/PPFP-004.rpt pnt-to-pnt set_false_path between
sync_fast_to_slow_integral clocks

Sdc.Exception/PPFP-004.rpt :
# ==============================
#
# Design : top
# PPFP-004
# pnt-to-pnt set_false_path between sync_fast_to_slow_integral clocks
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path7
----------------------

Debug
1) Get the printable attribute of the false path.
tv_shell > get_attribute [get_constraints -id 7] printable
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set_false_path (tests/check_cons_PPFP_test1.tcl:29:7) -from [get_pins FF3/CK] \
-to [get_pins FF2/D]

2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.

tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF3/D] data_clocks
{ CLK1 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:22:5) -name gclk1 \
-source [get_ports clk1] -divide_by 2 [get_pins FF1/Q]

tv_shell > get_attribute [get_clocks CLK1] printable

create_clock (tests/check_cons_PPFP_test1.tcl:2:1) -name CLK1 -period 1.5 [get_ports clk1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-004 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-004 -obj1 FP.Fxa3b7d411f4fe3eTx282373c9adef65 -obj2 gclk1 -obj3 CLK1 -author "hollis" -date "07/30/14" \
-reason "None"

3.26.5 Rule PPFP-005

- pnt-to-pnt set_false_path between sync_fast_to_slow_nonintegral clocks

Description:
This rule identifies point-to-point “set_false_path” between synchronous clocks with clock periods that
are fast-to-slow nonintegral.

Design in figure 3.26.5 below shows timing points reported under rule PPFP-005.

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Figure 3.26.5

Point-to-Point false path between sync_fast_to_slow_nonintegral clock

create_generated_clock -source [get_ports clk1] -divide_by 3 [get_pins FF1/Q]

_ _
D Q D Q
FF1 FF2
clk1 B1 Q Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q Logic
FF3
Q

set_false_path -from FF3/CK -to FF2/D

In the above designs, shows that a divide_by 3 clocks drive one registers and the undivided clock drives
the other and there is a point-to-point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-005.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-005 Warning 1 0 Sdc.Exception/PPFP-005.rpt pnt-to-pnt set_false_path between
sync_fast_to_slow_nonintegral clocks

Sdc.Exception/PPFP-005.rpt :
# ==============================
#
# Design : top
# PPFP-005
# pnt-to-pnt set_false_path between sync_fast_to_slow_nonintegral clocks
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception
-----------------------
A0 set_false_path10
-----------------------

Debug
1) Get the printable attribute of the false path.
tv_shell > get_attribute [get_constraints -id 10] printable
set_false_path (tests/check_cons_PPFP_test1.tcl:35:10) -from [get_pins FF3/CK] \
-to [get_pins FF2/D]

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2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.
tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF3/D] data_clocks
{ CLK1 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:27:9) -name gclk1 \
-source [get_ports clk1] -divide_by 3 [get_pins FF1/Q]

tv_shell > get_attribute [get_clocks CLK1] printable

create_clock (tests/check_cons_PPFP_test1.tcl:2:1) -name CLK1 -period 1.5 [get_ports clk1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-005 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-004 -obj1 FP.Fxa3b8d411f4fa6eTx288933c9adef65 -obj2 gclk1 -obj3 CLK1 -author "hollis" -date "07/30/14" \
-reason "None"

3.26.6 Rule PPFP-006

- pnt-to-pnt set_false_path between source_sync clocks

Description:
This rule identifies point-to-point “set_false_path” between clocks that are source synchronous.

Design in figure 3.26.6 below shows timing points reported under rule PPFP-006.

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Figure 3.26.6

Point-to-Point false path between source-sync clocks

create_generated_clock -source [get_ports clk1] -divide_by 1 [get_pins B2/Z]

_
D Q
FF2
clk1 B1 B2 Q
create_clock -name CLK1 [get_ports clk1]

D
_
Q Logic
FF3
Q

set_false_path -from FF3/CK -to FF2/D

In the above designs, shows that a divide_by 1 clocks drive one registers and the undivided clock drives
the other and there is a point-to-point false path betwee them.

Therefore, “check_constraints” will report these clocks under rule PPFP-006.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception PPFP-006 Warning 1 0 Sdc.Exception/PPFP-006.rpt pnt-to-pnt set_false_path between source_sync clocks

Sdc.Exception/PPFP-006.rpt :
# ==============================
# Design : top
# PPFP-006
# pnt-to-pnt set_false_path between source_sync clocks
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
-----------------------
A0 set_false_path11
------------------------

Debug
1) Get the printable attribute of the false path.
tv_shell > get_attribute [get_constraints -id 11] printable
set_false_path (tests/check_cons_PPFP_test1.tcl:35:12) -from [get_pins FF3/CK] \
-to [get_pins FF2/D]

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2) Get the clocks and data_clocks attribute of the startpoint/endpoint registers.
tv_shell > get_attribute [get_pins FF2/CK] clocks
{ gclk1 }
tv_shell > get_attribute [get_pins FF3/D] data_clocks
{ CLK1 }

3) Get the printable attribute of each clock.

tv_shell > get_attribute [get_clocks gclk1] printable
create_generated_clock (tests/check_cons_PPFP_test1.tcl:29:13) -name gclk1 \
-source [get_ports clk1] -divide_by 1 [get_pins B2/Z]

tv_shell > get_attribute [get_clocks CLK1] printable

create_clock (tests/check_cons_PPFP_test1.tcl:2:1) -name CLK1 -period 1.5 [get_ports clk1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule PPFP-006 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule PPFP-004 -obj1 FP.Fxa3b83e11f4fa6eTx287733c9adaf65 -obj2 gclk1 -obj3 CLK1 -author "hollis" -date "07/30/14" \
-reason "None"

3.27 SDC Exception rules

3.27.1 Rule SDC-FP-01/SDC-MCP-01

- Clock-Clock Exception -setup not covered by -hold

Description:
This rule identifies clock-to-clock exceptions where the option “-setup” is specified but there is no
matching “-hold” constraint.

Example:
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
set_multicycle_path 2 -setup -from [get_clocks clk1] -to [get_clocks clk2]

In the above example, no matching -hold is specified.

Therefore, “check_constraints” will report these clocks under rule SDC-FP-01/SDC-MCP-01.

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Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-01 Error 1 0 Sdc.Exception/SDC-FP-01.rpt Clock-Clock False path -setup not covered by -hold

Sdc.Exception/SDC-FP-01.rpt :
# ==============================
#
# Design : top
# SDC-FP-01
# Clock-Clock False path -setup not covered by -hold
# Severity: Error
#
# ==============================
#
# Violations
#
A# Exception
----------------------
A0 set_false_path3
----------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP_test1.tcl:28:3) -setup -from [get_clocks clk1] \
-to [get_clocks clk2]

2) Check the dominant_setup and dominant_hold attribute of the clock pair to confirm no hold
constraint exist.
tv_shell > get_attribute [get_clock_pair -from clk1 -to clk2] dominant_setup
{ set_false_path3 }
tv_shell > get_attribute [get_clock_pair -from clk1 -to clk2] dominant_hold

Nothing is returned, the clock pair does not have a matching setup/hold constraint.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-FP-01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-01 -obj1 FP.Fx28253cae40652Tx28253cae40653 -author "hollis" -date "07/30/14" -reason "None"
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3.27.2 Rule SDC-FP-02/SDC-MCP-02
- Clock-Clock Exception -hold not covered by -setup

Description:
This rule identifies clock-to-clock exceptions where the option “-hold” is specified but there is no
matching “-setup” constraint.

Example:
set_false_path -hold -from [get_clocks clk1] -to [get_clocks clk2]
set_multicycle_path 2 -hold -from [get_clocks clk2] -to [get_clocks clk3]

In the above example, no matching -setup is specified.

Therefore, “check_constraints” will report these clocks under rule SDC-FP-02/SDC-MCP-02.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-02 Error 1 0 Sdc.Exception/SDC-FP-02.rpt Clock-Clock False path -hold not covered by -setup

Sdc.Exception/SDC-FP-02.rpt :
# ==============================
#
# Design : top
# SDC-FP-02
# Clock-Clock False path -hold not covered by -setup
# Severity: Error
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path4
----------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 4] printable

set_false_path (tests/check_cons_SDC-FP_test1.tcl:31:4) -hold -from [get_clocks clk2] \
-to [get_clocks clk3]

2) Check the dominant_setup and dominant_hold attribute of the clock pair to confirm no hold
constraint exist.
tv_shell > get_attribute [get_clock_pair -from clk1 -to clk2] dominant_setup

tv_shell > get_attribute [get_clock_pair -from clk1 -to clk2] dominant_hold

{ set_false_path4 }

Nothing is returned for setup, the clock pair does not have a matching setup/hold constraint.
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Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-FP-02 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-02 -obj1 FP.Fx28253cae40653Tx28253cae40654 -author "hollis" -date "07/30/14" -reason "None"

3.27.3 Rule SDC-FP-03/SDC-MCP-03

- Pt-to-Pt exception -setup not covered by -hold

Description:
This rule identifies point-to-point exceptions where the option “-setup” is specified but there is no
matching constraint with option “-hold”.

Example:
set_false_path -setup -from [get_pins f5/CK] -to [get_pins f6/D]
set_multicycle_path 2 -setup -from [get_pins f5/CK] -to [get_pins f6/D]

In the above example, no matching -hold is specified.

Therefore, “check_constraints” will report these clocks under rule SDC-FP-03/SDC-MCP-03.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception Sdc. SDC-FP-03 Error 1 0 Sdc.Exception/SDC-FP-03.rpt Pt-to-Pt False path -setup not covered by -hold

Sdc.Exception/SDC-FP-03.rpt :
# ==============================
#
# Design : top
# SDC-FP-03
# Pt-to-Pt False path -setup not covered by -hold
# Severity: Error
#
# ==============================
#
# Violations
#

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A# Exception
----------------------
A0 set_false_path5
----------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 5] printable

set_false_path (tests/check_cons_SDC-FP_test1.tcl:34:5) -setup -from [get_pins f5/CK] \
-to [get_pins f6/D]

2) Get all false paths on the startpoint/endpoint pair.

tv_shell > get_exceptions -from [get_pins f5/CK] -to [get_pins f6/D]
{ set_false_path5 }

Only one exception returned, the one that violates the rule.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-FP-03 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-03 -obj1 FP.Fxa3b7d435801354Tx28253c9ae3c78 -author "hollis" -date "07/30/14" -reason "None"

3.27.4 Rule SDC-FP-04/SDC-MCP-04

- Pt-to-Pt exception -hold not covered by -setup

Description:
This rule identifies point-to-point exceptions where the option “-hold” is specified but there is no
matching constraint with option “-setup”.
Example:
set_false_path -hold -from [get_pins f7/CK] -to [get_pins f8/D]
set_multicycle_path 2 -hold -from [get_pins f7/CK] -to [get_pins f8/D]

In the above example, no matching -setup is specified.

Therefore, “check_constraints” will report these clocks under rule SDC-FP-04/SDC-MCP-04.

Reports: (Only false path will be used as an example)

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Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-04 Error 1 0 Sdc.Exception/SDC-FP-04.rpt Pt-to-Pt False path -hold not covered by -setup

Sdc.Exception/SDC-FP-04.rpt :
# ==============================
#
# Design : top
# SDC-FP-04
# Pt-to-Pt False path -hold not covered by -setup
# Severity: Error
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path6
----------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 6] printable

set_false_path (tests/check_cons_SDC-FP_test1.tcl:37:6) -hold -from [get_pins f7/CK] \
-to [get_pins f8/D]

2) Get all false paths on the startpoint/endpoint pair.

tv_shell > get_exceptions -from [get_pins f7/CK] -to [get_pins f8/D]
{ set_false_path6 }

Only one exception returned, the one that violates the rule.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-FP-04 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-04 -obj1 FP.Fxa3b7d435f893feTx28253c9aedb94 -author "hollis" -date "07/30/14" -reason "None"

3.27.5 Rule SDC-FP-05

- False path covers no paths
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 TimeVision Constraints User Guide

Description:
This rule identifies point-to-point “set_false_path” which covers no paths.

Example:
set_false_path -from [get_pins f9/CK] -to [get_pins f10/D]

In the above example, no paths are covered by the specified exceptions.

Therefore, “check_constraints” will report these clocks under rule SDC-FP-05.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-05 Warning 1 0 Sdc.Exception/SDC-FP-05.rpt False path covers no paths

Sdc.Exception/SDC-FP-05.rpt :
# ==============================
#
# Design : top
# SDC-FP-05
# False path covers no paths
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
----------------------
A0 set_false_path7
---------------------- -

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 7] printable

set_false_path (tests/check_cons_SDC-FP_test1.tcl:40:7) -from [get_pins f9/CK] \
-to [get_pins f10/D]

2) Trace the path of the startpoint/endpoint pair.

tv_shell > trace_path -from [get_pins f9/CK] -to [get_pins f10/D]

No path returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

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After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-FP-05 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-05 -obj1 FP.Fxa3b7d435b3203bTxa3b7d435903b3a -author "hollis" -date "07/30/14" -reason "None"

3.27.6 Rule SDC-MCP-05

- Multicycle path covers multiple clocks without -start or –end specified

Description:
This rule identifies “set_multicycle_path” where the the startpoints and endpoints are clocked by
asynchronous clocks and no “-start” or “-end” is specify.

Example:
set_multicycle_path 2 -setup -from [get_clocks clk1] -to [get_clocks clk2]

In the above example, the set_multicycle_path is specified between asynchronous clock pairs.

Therefore, “check_constraints” will report these clocks under rule SDC-MCP-05.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-MCP-05 Error 4 0 Sdc.Exception/SDC-MCP-05.rpt Multicycle path covers multiple clocks without -start or
-end specified

Sdc.Exception/SDC-MCP-05.rpt :
# ==============================
#
# Design : top
# SDC-MCP-05
# Multicycle path covers multiple clocks without -start or -end specified
# Severity: Error
#
# ==============================
#
# Violations
#
A# Exception
---------------------------
A0 set_multicycle_path3
A1 set_multicycle_path4
A2 set_multicycle_path5
A3 set_multicycle_path6
---------------------------
Debug
1) Get the printable attribute of the multicycle path.

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tv_shell > get_attribute [get_constraints -id 3] printable
set_multicycle_path (tests/check_cons_SDC-MCP_test1.tcl:28:3) 2 -setup \
-from [get_clocks clk1] -to [get_clocks clk2]

2) Get periods of the clock pair.

tv_shell > get_attribute [get_clocks clk1] period
{ 1.5 }
tv_shell > get_attribute [get_clocks clk2] period
{ 1.7 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-MCP-05 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-MCP-05 -obj1 MCP.Fx28253cae40652Tx28253cae40653V2 -author "hollis" -date "07/31/14" -reason "None"

3.27.7 Rule SDC-MCP-06

- Multicycle path covers no paths

Description:
This rule identifies point-to-point “set_multicycle_path” which covers no paths.

Example:
set_multicycle_path 2 -from [get_pins f9/CK] -to [get_pins f10/D]

In the above example, no paths are covered by set_multicycle_path specified.

Therefore, “check_constraints” will report these clocks under rule SDC-MCP-06.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-MCP-06 Warning 1 0 Sdc.Exception/SDC-MCP-06.rpt Multicycle path covers no paths

Sdc.Exception/SDC-MCP-06.rpt :
# ==============================
#
# Design : top
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 TimeVision Constraints User Guide
# SDC-MCP-06
# Multicycle path covers no paths
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception
---------------------------
A0 set_multicycle_path7
---------------------------

Debug
1) Get the printable attribute of the multicycle path.

tv_shell > get_attribute [get_constraints -id 7] printable

set_multicycle_path (tests/check_cons_SDC-MCP_test1.tcl:40:7) 2 -from [get_pins f9/CK] \
-to [get_pins f10/D]

2) Trace the path of the startpoint/endpoint pair.

tv_shell > trace_path -from [get_pins f9/CK] -to [get_pins f10/D]

No path returned.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDC-MCP-06 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-MCP-06 -obj1 MCP.Fxa3b7d435b3203bTxa3b7d435903b3aV2 -author "hollis" -date "07/31/14" -reason "None"

3.28 Exceptions Object rules

3.28.1 Rule SDC-FP-O-01/SDC-MCP-O-01/SDC-MD-O-01/SDC-GP-O-01

- Startpoint of exception is not a timing startpoint

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Description:
This rule identifies exceptions where the startpoint is defined on an object that is not a timing
startpoint. Example objects that are not timing startpoints are hierarchical pins or combinational cell
pins.
Design in figure 3.28.1 below shows timing points reported.

Figure 3.28.1

Startpoint of exception is not a timing startpoint

_
D Q

clk1 B1 Q

set_false_path -from [get_pins B1/A]

set_multicycle_path 2 -from [get_pins B1/A]
set_max_delay 2.1 -from [get_pins B1/A]
group_path -from [get_pins B1/A]

In the above designs, the exceptions are applied to the input of the buffer, which is not a timing start
point.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-01 Warning 1 0 Sdc.Exception/SDC-FP-O-01.rpt Startpoint of set_false_path is not a timing startpoint

Sdc.Exception/SDC-FP-O--01.rpt :
# ==============================
# Design : top
# SDC-FP-O-01
# Startpoint of set_false_path is not a timing startpoint
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception Point
-----------------------------
A0 set_false_path3 B1/A
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:22:3) -from [get_pins B1/A]

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2) Get the ref_name attribute of the cell.
tv_shell > get_attribute [get_cells B1] ref_name
{ BUFF_X1 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-01 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-01 -obj1 FP.Fxa3b7dbd5a05caf -obj2 B1/A -author "hollis" -date "07/31/14" -reason "None"

3.28.2 Rule SDC-FP-O-02/SDC-MCP-O-02/SDC-MD-O-02/SDC-GP-O-02

- Endpoint of exception is not a timing startpoint

Description:
This rule identifies exceptions where the endpoint is defined on an object that is not a timing endpoint.
Example objects that are not timing endpoints are hierarchical pins or combinational cell pins.

Design in figure 3.28.2 below shows timing points reported.

Figure 3.28.2

Endpoint of exception is not a timing endpoint

_
D
_
Q D Q
FF1
clk1 Q B1 Q

set_false_path -to [get_pins B1/A]

set_multicycle_path 2 -to [get_pins B1/A]
set_max_delay 2.1 -to [get_pins B1/A]
group_path -to [get_pins B1/A]

In the above designs, the exceptions are applied to the input of the buffer, which is not a timing end
point.

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Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-02 Warning 1 0 Sdc.Exception/SDC-FP-O-02.rpt Endpoint of set_false_path is not a timing endpoint
Sdc.Exception/SDC-FP-O--02.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-02
# Endpoint of set_false_path is not a timing endpoint
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Point
-----------------------------
A0 set_false_path3 B1/A
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:22:3) -to [get_pins B1/A]

2) Get the ref_name attribute of the cell.

tv_shell > get_attribute [get_cells B1] ref_name
{ BUFF_X1 }

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-02 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-02 -obj1 FP.Txa3b7dbd5a45372 -obj2 B1/A -author "hollis" -date "07/31/14" -reason "None"

3.28.3 Rule SDC-FP-O-03/SDC-MCP-O-03/SDC-MD-O-03/SDC-GP-O-03

- Endpoint of exception is a synthesized timing endpoint

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Description:
This rule identifies exceptions where the specified endpoint is synthesized clock-gating cell and not a
timing endpoint.

Design in figure 3.28.3 below shows timing points reported.

Figure 3.28.3

Endpoint of exception is a synthesized timing endpoint

set design_intentional_library_cell_names OR_X1

_
D Q _
D Q
FF0
FF1
clk1 B1 Q A1

A2
A0 Q

_
D Q _
D Q
FF2
FF3
Q A1

A2
OR1
A0 Q

set_false_path -to [get_pins {A0/A1 OR1/A1}]

set_multicycle_path 2 -to [get_pins {A0/A1OR1/A1}]
set_max_delay 2.1 -to [get_pins {A0/A1 OR1/A1}]
group_path -to [get_pins {A0/A1 OR1/A1}]
In the above designs, the exceptions are applied to the “A1” input of both the “OR” gate and the “AND”
gate, which are clock-gating cells. The “OR” gate is specified as a design intentional cell listed in the
variable “design_intentional_library_cellnames” and thus would not violate the rule, however, the
“AND” gate violates.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-03 Warning 1 0 Sdc.Exception/SDC-FP-O-03.rpt Endpoint of set_false_path is a synthesized timing
endpoint

Sdc.Exception/SDC-FP-O--03.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-03
# Endpoint of set_false_path is a synthesized timing endpoint
# Severity: Warning
#
# ==============================
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#
# Violations
#
A# Exception Point
-----------------------------
A0 set_false_path2 A0/A1
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 2] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:25:2) -to [get_pins A0/A1]

2) Get the ref_name attribute of the cell.

tv_shell > get_attribute [get_cells A0] ref_name
{ AND2_X1 }

3) Get the is_synthesized attribute of the cell.

tv_shell > get_attribute [get_cells A0] is_synthesized
1

4) Get the is_clock_used_as_data attribute of the pin which is in the clock network to confirm it is used
as data also.
tv_shell > get_attribute [get_pins A0/A2] is_clock_used_as_data

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-03 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-03 -obj1 FP.Txa3b7dbd5a82315 -obj2 A0/A1 -author "hollis" -date "07/31/14" -reason "None"

3.28.4 Rule SDC-FP-O-04/SDC-MCP-O-04/SDC-MD-O-04/SDC-GP-O-04

- Thru-point of exception is a synthesized point

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Description:
This rule identifies exception where the specified thru-point is not listed in the design intended variable
and is a synthesized combinational logic pin.

Design in figure 3.28.4 below shows timing points reported.

Figure 3.28.4

Throughpoint of exception is a synthesized timing point

settings Build/IntentionalCells .*u_DT.*
Note the AND gate instance name is A4 so it will violate
_
D Q
FF7
clk1 Q

_
D Q A1
A4
A2
FF8
clk2 Q
set_false_path -through [get_pins A4/A1]
set_multicycle_path 2 -through [get_pins A4/A1]
set_max_delay 2.1 -through [get_pins A4/A1]
group_path -through [get_pins A4/A1]

In the above designs, the exceptions are applied to the A1 input of the AND gate. The settings
Build/IntentionalCells is set to “.*u_DT.*” however, the AND gate instance name is “A4” which is not in
the intentional cells list.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-04 Warning 1 0 Sdc.Exception/SDC-FP-O-04.rpt Thru-point of set_false_path is a synthesized point

Sdc.Exception/SDC-FP-O--04.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-04
# Thru-point of set_false_path is a synthesized point
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Point
-----------------------------
A0 set_false_path3 A4/A1
-----------------------------
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Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:25:3) -through [get_pins A4/A1]

2) Get the ref_name attribute of the cell.

tv_shell > get_attribute [get_cells A4] ref_name
{ AND2_X1 }

3) Get the settings Build/IntentionalCells value to confirm the AND gate instance name does not
match.
tv_shell > settings Build/IntentionalCells

Group Variable Value

------------------------------------------------------
Build Build/IntentionalCells .*u_DT.*
(design_intentional_cell_names)

Note that the AND gate “A4” does not match the settings value.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-04 –id A0 –reason “None”
write_waiver top.waivers.tcl
top.waivers.tcl
set_waiver -rule SDC-FP-O-04 -obj1 FP.Xxa3b7dbd5adb2d8 -obj2 A4/A1 -author "hollis" -date "07/31/14" -reason "None"

3.28.5 Rule SDC-FP-O-05/SDC-MCP-O-05/SDC-MD-O-05/SDC-GP-O-05

- Thru-point of exception is a hierarchical pin.

Description:
This rule identifies exceptions where the thru-point is defined on a hierarchical pin.

Design in figure 3.28.5 below shows timing points reported.

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 TimeVision Constraints User Guide Figure 3.28.5

Through point of exception is a hierarchical pin

_
D Q
FF1
HCLK
clk1 B1 B2 Q

set_false_path -through [get_pins U1/HCLK]

set_multicycle_path 2 -through [get_pins U1/HCLK]
set_max_delay 2.1 -through [get_pins U1/HCLK]
group_path -through [get_pins U1/HCLK]

In the above designs, the exceptions are applied to hierarchical pin U1/HCLK.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-05 Warning 1 0 Sdc.Exception/SDC-FP-O-05.rpt Thru-point of set_false_path is a hierarchical pin.

Sdc.Exception/SDC-FP-O--05.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-05
# Thru-point of set_false_path is a hierarchical pin.
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Exception Point
-----------------------------
A0 set_false_path3 U1/HCLK
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:25:3) -through [get_pins U1/HCLK]

2) Get the is_hierarchical attribute of the pin.

tv_shell > get_attribute [get_cells U1/HCLK] is_hierarchical
1

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2) Trace the path through the hierarchical pin.
tv_shell > trace_path -from [get_ports clk1] -through U1/HCLK -nets -hier
Point Type Flags
-------------------------------------------
(Unconstrained Startpoint)
clk1 (port) cs
clk1 (net) ~
B1/A BUF_X1 ~
B1/Z BUF_X1 ~
HCLK h
HCLK (net) ~
FF1/CK DFF_X1 ~

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-05 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-05 -obj1 FP.Xxd842623698ed1c9a -obj2 U1/HCLK -author "hollis" -date "07/31/14" -reason "None"

3.28.6 Rule SDC-FP-O-06/SDC-MCP-O-06

- Startpoint of exception covers no paths.

Description:
This rule identifies exceptions where the startpoint has no path to the specified endpoint.

Design in figure 3.28.6 below shows timing points reported.

Figure 3.28.6 Startpoint of exception covers no paths

No path from FF2
_ _
d1 D Q D Q
FF1 FR1
clk2 Q Q

_
d2 D Q
FF2
Q
set_false_path -from [get_pins FF*/CK] -to [get_pins FR*/D]
set_multicycle_path 2-from [get_pins FF*/CK] -to [get_pins FR*/D]
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In the above designs, the exceptions are applied to startpoint FF2/CK, but it has not path to an
endpoint.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-06 Warning 1 0 Sdc.Exception/SDC-FP-O-05.rpt Startpoint of set_false_path covers no paths.

Sdc.Exception/SDC-FP-O-06.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-06
# rpt Startpoint of set_false_path covers no paths
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Point
-----------------------------
A0 set_false_path3 FF2/CK
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:28:3) -from [get_pins FF*/CK] \
-to [get_pins FR*/D]

2) Trace the path from FF2/CK.

tv_shell > trace_path -from [get_pins FF2/CK]
In this case no path is returned, however, it is possible that other paths could exist from FF2/CK but
none would match the false path -to objects.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-06 –id A0 –reason “None”
write_waiver top.waivers.tcl

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top.waivers.tcl
set_waiver -rule SDC-FP-O-06 -obj1 FP.Fx3a0fbb4d85ba3a6fTx1caf09e8b10e0293 -obj2 FF2/CK -author "hollis" -date "07/31/14"\
-reason "None"

3.28.7 Rule SDC-FP-O-07/SDC-MCP-O-07

- Endpoint of exception covers no paths.

Description:
This rule identifies exceptions where the endpoint has no path from the specified startpoint.

Design in figure 3.28.7 below shows timing points reported.

Figure 3.28.7
Endpoint of exception covers no paths
No path to FR2

_ _
d1 D Q D Q
FF1 FR1
clk2 Q Q

_
D Q
FR2
Q

set_false_path -from [get_pins FF*/CK] -to [get_pins FR*/D]

set_multicycle_path 2-from [get_pins FF*/CK] -to [get_pins FR*/D]

In the above designs, the exceptions are applied to endpoint FR2/D, but it has not path from the
specified startpoint.
Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-07 Warning 1 0 Sdc.Exception/SDC-FP-O-07.rpt Endpoint of set_false_path covers no paths.

Sdc.Exception/SDC-FP-O-07.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-07
# rpt Endpoint of set_false_path covers no paths
# Severity: Warning
#
# ==============================
#
# Violations
#

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A# Exception Point
-----------------------------
A0 set_false_path3 FR2/D
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:30:3) -from [get_pins FF*/CK] \
-to [get_pins FR*/D]

2) Trace the path to FR2/D.

tv_shell > trace_path -to [get_pins FR2/D]

In this case no path is returned, however, it is possible that other paths could exist from FR2/D but
none would match the false path -to objects.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-07 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-07 -obj1 FP.Fxbcefbccbe696b337Tx1b679a404e4b51a0 -obj2 FR2/D -author "hollis" -date "07/31/14"\
-reason "None"
3.28.8 Rule SDC-FP-O-08/SDC-MCP-O-08
- More that 25% of startpoints in exception covers no paths.

Description:
This rule identifies exceptions where the startpoints have no path to at least 25% of the specified
endpoints.

Design in figure 3.28.8 below shows timing points reported.

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 TimeVision Constraints User Guide
Figure 3.28.8
set_false_path -from [get_pins FF*/CK] -to [get_pins FR*/D]
set_multicycle_path 2-from [get_pins FF*/CK] -to [get_pins FR*/D]

Greater than 25% of startpoint of exception covers no paths

No path from FF2, FF3,FF4
_ _
d1 D Q D Q
FF1 FR1
clk2 Q Q

_
d2 D Q
FF2
Q

_
d3 D Q
FF3
Q

_
d4 D Q
FF4
Q
set_false_path -from [get_pins FF*/CK] -to [get_pins FR*/D]
set_multicycle_path 2-from [get_pins FF*/CK] -to [get_pins FR*/D]

In the above designs, the exceptions are applied to startpoint where 3 of the 4 startpoint registers have
not path to the specified endpoints.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-08 Warning 1 0 Sdc.Exception/SDC-FP-O-08.rpt More that 25% of startpoints in exception covers no
paths..

Sdc.Exception/SDC-FP-O-08.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-08
# rpt More that 25% of startpoints in exception covers no paths.
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Percent
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-----------------------------
A0 set_false_path3 75%
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:20:3) -from [get_pins FF*/CK] \
-to [get_pins FR*/D]

2) Get the from_objects attribute of the exception.

tv_shell > get_attribute [get_exception -id 3] from_objects
{ FF4/CK FF1/CK FF2/CK FF3/CK }

2) Get the to_objects attribute of the exception.

tv_shell > get_attribute [get_exception -id 3] to_objects
{ FR1/D }

In this case there are 4 startpoint registers but only 1 endpoint register.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-08 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-08 -obj1 FP.Fxb72fb92c2352b298Tx536aa9ac6396a765 -obj2 75% -author "hollis" -date "07/31/14"\
-reason "None"

3.28.9 Rule SDC-FP-O-09/SDC-MCP-O-09

- More that 25% of endpoints in exception covers no paths.
Description:
This rule identifies exceptions where the endpoints have no path to at least 25% of the specified
startpoints.

Design in figure 3.28.9 below shows timing points reported.

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Figure 3.28.9
Greater than 25% of endpoint of exception covers no paths
No path to FR2, FR3,FR4
_ _
d1 D Q D Q
FF1 FR1
clk2 Q Q

_
D Q
FR2
Q

_
D Q
FR3
Q

_
D Q
FR4
Q

set_false_path -from [get_pins FF*/CK] -to [get_pins FR*/D]

set_multicycle_path 2-from [get_pins FF*/CK] -to [get_pins FR*/D]

In the above designs, the exceptions are applied to endpoint where 3 of the 4 endpoint registers have
not path to the specified startpoints.

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-09 Warning 1 0 Sdc.Exception/SDC-FP-O-09.rpt More that 25% of endpoints in exception covers no
paths.
Sdc.Exception/SDC-FP-O-09.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-09
# rpt More that 25% of endpoints in exception covers no paths.
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Percent
-----------------------------
A0 set_false_path3 75%
-----------------------------

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Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:20:3) -from [get_pins FF*/CK] \
-to [get_pins FR*/D]

2) Get the from_objects attribute of the exception.

tv_shell > get_attribute [get_exception -id 3] from_objects
{ FF1/CK }

2) Get the to_objects attribute of the exception.

tv_shell > get_attribute [get_exception -id 3] to_objects
{ FR3/D FR2/D FR4/D FR1/D }

In this case there is 1 startpoint registers but 4 endpoint register.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule SDF-FP-O-09 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-09 -obj1 FP.Fx536aa9abad006e15Tx3d64ef925baa1cb -obj2 75% -author "hollis" -date "07/31/14"\
-reason "None"

3.28.11 Rule SDC-FP-O-11/SDC-MCP-O-11

- Exception -through sequential element..

Description:
This rule identifies exceptions as through a sequential element.

Design in figure 3.28.11 below shows timing points reported.

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Figure 3.28.11

Exception -through sequential element

_ _
D Q D Q
FF1 FF2
clk1 Q Q

set_false_path -through [get_cells FF1]

set_multicycle_path 2 -through [get_cells FF1]

Reports: (Only false path will be used as an example)

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-FP-O-11 Warning 1 0 Sdc.Exception/SDC-FP-O-11.rpt set_false_path -through sequential element.

Sdc.Exception/SDC-FP-O-11.rpt :
# ==============================
#
# Design : top
# SDC-FP-O-11
# rpt set_false_path -through sequential element.
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Exception Point
-----------------------------
A0 set_false_path3 FF1
-----------------------------

Debug
1) Get the printable attribute of the false path.

tv_shell > get_attribute [get_constraints -id 3] printable

set_false_path (tests/check_cons_SDC-FP-O_test1.tcl:20:3) -through [get_cells FF1]

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

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Example:
set_waiver -rule SDF-FP-O-11 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule SDC-FP-O-11 -obj1 FP.Xxa16fb57b1db -obj2 FF1 -author "hollis" -date "07/31/14" -reason "None"

3.29 SDC Lint rules

3.29.1 Rule SDC-LNTC-01

- Unknown command in SDC

Description:
This rule identifies any SDC command unknown to Timevision and requires the constraints to be loaded
with “read_sdc” command. Sourcing Tcl constraints with “source” command will not trigger this rule to
violate even though the command is unknown by Timevision. Instead, an error message is emitted to
the shell and the log file.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_input_noise -above -low -width 1.70 -height 0.58 [het_pins u_blk/b2/A]

Note the SDC command “set_input_noise” is unknown to Timevision. When the content of the SDC file
is loaded with the command “read_sdc” this rule will violate.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Exception SDC-LNTC-01 Warning 1 0 Sdc.Lint/SDC-LNTC-01.rpt Unknown command in SDC

Sdc.Lint/SDC-LNTC--01.rpt :
# ==============================
# Design : top
# Date : Thu Jun 04 01:17:11 PM PDT 2015
#
# SDC-LNTC-01
# Unknown command in SDC
# Severity: Warning
# ==============================
#
# Violations
#

A# Command
-------------------------
A0 set_unknown_check1
-------------------------

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Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTC-01 –id A0

#********************************************************
#
# Rule: SDC-LNTC-01
# Severity: Warning
# Unknown command in SDC
# ==============================
Violation A0

List of constraints/node:
set_unknown_check1 (constraint)

set_unknown_check1 (Design: top, Scenario: default):

set_unknown_check (tests/check_cons_SDC-LNTC-01_test1.sdc:5:1) set_input_noise

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.2 Rule SDC-LNTC-02

- User-disallowed command in SDC

Description:
This rule identifies any SDC command which the user has specified as “not_allowed”. The user specifies
the “not_allowed” commands by setting the variable “user_sdc_control”.

Example command:
set user_sdc_control [dic create "create_generated_clock" [dict create "not_allowed" "1" ]]

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name div2_clk -divide_by 2 -add -master [get_clocks clk2] \
-source [get_ports clk2] [get_pins f1/Q]]

Note the SDC command “create_generated_clock” will be flagged as “not_allowed”. When the content
of the SDC file is loaded with the command “read_sdc” this rule will violate.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTC-02 Warning 1 0 Sdc.Lint/SDC-LNTC-02.rpt User-disallowed command in SDC

Sdc.Lint/SDC-LNTC--02.rpt :

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# ==============================
#
# Design : top
# Date : Tue Sep 08 07:38:53 PM PDT 2015
# SDC-LNTC-02
# User-disallowed command in SDC
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Options
------------------------
A0 div2_clk
------------------------

Debug

1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTC-02 –id A0

#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTC-02 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTC-02
# Severity: Warning
# User-disallowed command in SDC
# ==============================
Violation A0

List of constraints/node:
div2_clk (generated clock)

div2_clk (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTC-02_test1.sdc:6:0) -name div2_clk -
add -source [get_ports clk2] -divide_by 2 -master [get_clocks clk2] \
[get_pins f1/Q]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.3 Rule SDC-LNTC-03

- TCL error in SDC command parsing

3.29.4 Rule SDC-LNTC-04

- Ambiguous command in SDC

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3.29.5 Rule SDC-LNTO-01
- Unknown option to command

Description:
This rule identifies any SDC command where an unknown option is used in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_multicycle_path -fast [get_clocks clk2]

Note the SDC command option “-fast” is an unknown option for “set_multicycle_path”. When the
content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-01 Warning 1 0 Sdc.Lint/SDC-LNTO-01.rpt Unknown option to command

Sdc.Lint/SDC-LNTO--01.rpt :
# ==============================
# Design : top
# Date : Thu Jun 04 02:40:43 PM PDT 2015
#
# SDC-LNTO-01
# Unknown option to command
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Option
-----------------------------------
A0 set_multicycle_path0 fast
-----------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-01 –id A0

#********************************************************
#
# Rule: SDC-LNTO-01
# Severity: Warning
# Unknown option to command
# ==============================
Violation A0

List of constraints/node:
set_multicycle_path0 (constraint)

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set_multicycle_path0 (Design: top, Scenario: default):

fail/set_multicycle_path (tetst/check_cons_SDC-LNTO-01_test1.tcl:24:2) -1

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.6 Rule SDC-LNTO-02

- User-disallowed option to command

Description:
This rule identifies any SDC command option which the user has specified as “not_allowed”. The user
specifies the “not_allowed” options by setting the variable “user_sdc_control”.

Example command:
set user_sdc_control [dict create "create_clock" [dict create "waveform" "not_allowed"] \
"set_clock_groups" [dict create "physically_exclusive" "not_allowed"]]
Sample SDC content:

create_clock -name clk1 -period 3.9 -waveform {0.0 3.45} [get_ports clk1]
create_clock -name clk2 -period 6.9 [get_ports clk2]
create_clock -name clk3 -period 1.9 [get_ports clk3]
set_clock_groups -physically_exclusive -group {clk2} -group {clk3}

Note the SDC command options “-waveform” and “-physically_exclusive” will be flagged as
“not_allowed”. When the content of the SDC file is loaded with the command “read_sdc” this rule will
violate.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
---------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-02 Warning 2 0 Sdc.Lint/SDC-LNTO-02.rpt User-disallowed option to command

Sdc.Lint/SDC-LNTO--02.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTO-02
# User-disallowed option to command
# Severity: Warning
#
# ==============================
#
# Violations
#

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A# Command Option
---------------------------------------------
A0 clk1 waveform
A1 set_clock_group1 physically_exclusive
---------------------------------------------

Debug

1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-02

#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTO-02 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTO-02
# Severity: Warning
# User-disallowed option to command
# ==============================
Violation A0

List of constraints/node:
clk1 (clock)

clk1 (Design: top, Scenario: default):

fail/create_clock (<interactive>:0:0) -name clk1 -period 3.9 -waveform { 0.0 3.45 } \
[get_ports clk1]

# ==============================
Violation A1

List of constraints/node:
set_clock_group1 (constraint)

set_clock_group1 (Design: top, Scenario: default):

fail/set_clock_group (<interactive>:0:1) -physically_exclusive \
-group [get_clocks {clk2 }] \
-group [get_clocks {clk3 }]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.7 Rule SDC-LNTO-03

- Missing required option

Description:
This rule identifies any SDC command where a required option is missing in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

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create_clock -name clk2 -period 6.9 [get_ports clk2]
set_multicycle_path –max [get_clocks clk2]

Note the SDC command option “-from/-to/-through” are missing for “set_multicycle_path”. When the
content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-03 Warning 1 0 Sdc.Lint/SDC-LNTO-03.rpt Missing required option

Sdc.Lint/SDC-LNTO--03.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 03:52:30 PM PDT 2015
#
# SDC-LNTO-03
# Missing required option
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Option
-----------------------------------
A0 set_multicycle_path0 <NULL>
-----------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-03 –id A0

#********************************************************
#
# Rule: SDC-LNTO-03
# Severity: Warning
# Missing required option
# ==============================
Violation A0

List of constraints/node:
set_multicycle_path0 (constraint)

set_multicycle_path0 (Design: top, Scenario: default):

fail/set_multicycle_path (tests/check_cons_SDC-LNTO-03_test1.tcl:24:2) -1

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.8 Rule SDC-LNTO-04

- Overlapping mutially-exclusive options
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 TimeVision Constraints User Guide

Description:
This rule identifies any SDC command where mutually exclusive options are used in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_clock_groups -logically_exclusive -async -group {clk1} -group {clk2}

Note the SDC command option “-logically_exclusive and async” are mutually exclusive and cannot be
used in the same “set_clock_groups” command. When the content of the SDC file is loaded this rule
will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-04 Error 1 0 Sdc.Lint/SDC-LNTO-04.rpt Overlapping mutially-exclusive options

Sdc.Lint/SDC-LNTO--04.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 04:11:06 PM PDT 2015
#
# SDC-LNTO-04
# Overlapping mutially-exclusive options
# Severity: Error
#
# ==============================
#
# Violations
#

A# Command Option1 Option2

----------------------------------------------------------
A0 set_clock_group0 asynchronous logically_exclusive
----------------------------------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-04 –id A0

#********************************************************
#
# Rule: SDC-LNTO-04
# Severity: Error
# Overlapping mutially-exclusive options
# ==============================
Violation A0

List of constraints/node:
set_clock_group0 (constraint)

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set_clock_group0 (Design: top, Scenario: default):
fail/set_clock_group (tests/check_cons_SDC-LNTO-04_test1.tcl:24:2) -logically_exclusive \
-asynchronous \
-group [get_clocks {clk1 }] \
-group [get_clocks {clk2 }]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.9 Rule SDC-LNTO-05

- Multiple usage of same option

Description:
This rule identifies any SDC command where an options is used multiple times in an SDC command.
Some examples of exceptions to this rule are:
set_clock_group -group -group
set_false_path -through -through

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_clock_groups - async -async -group {clk1} -group {clk2}

Note the SDC command option “-async” is used two times in the same “set_clock_groups” command.
When the content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-05 Warning 1 0 Sdc.Lint/SDC-LNTO-05.rpt Multiple usage of same option

Sdc.Lint/SDC-LNTO-05.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 04:36:14 PM PDT 2015
#
# SDC-LNTO-05
# Multiple usage of same option
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Command Option
-------------------------------------
A0 set_clock_group2 asynchronous
-------------------------------------
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Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-05 –id A0

#********************************************************
#
# Rule: SDC-LNTO-05
# Severity: Warning
# Multiple usage of same option
# ==============================
Violation A0

List of constraints/node:
set_clock_group2 (constraint)

set_clock_group2 (Design: top, Scenario: default):

set_clock_group (tests/check_cons_SDC-LNTO-05_test1.tcl:24:2) -asynchronous \
-group [get_clocks {clk1 }] \
-group [get_clocks {clk2 }]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.10 Rule SDC-LNTO-06

- Option requires another option when used

Description:
This rule identifies any SDC command where an options is used and another option is required in an
SDC command.

Examples of constraint options which can violate this rule are:

create_generated_clock -name -master -source –divide_by ( missing -add)

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_clock -name clk3 -period 6.9 [get_ports clk3]

Note : for generated clocks to violate this rule the following must be set:
settings Clock/StrickGeneratedClockCheck true

create_generated_clock -name clk3_g1 -add -source [get_ports clk3] -comb -div 1 [get_pins c2/Z]
create_generated_clock -name clk3_g2 -master_clock [get_clocks clk3] -source [get_ports clk3] \
-comb -div 1 [get_pins c2/Z]

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Note in the first generated clock command option “-master_clock” is missing and in the second
generated clock command “-add” is missing. In “create_generated_clock” command “-master_clock”
and “-add” must be together. When the content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-06 Error 2 0 Sdc.Lint/SDC-LNTO-06.rpt Option requires another option when used

Sdc.Lint/SDC-LNTO-06.rpt :
# ==============================
#
# Design : top
#
# SDC-LNTO-06
# Option requires another option when used
# Severity: Error
#
# ==============================
#
# Violations
#

A# Command Option1 Option2

------------------------------------------
A0 clk3_g1 add master_clock
A1 clk3_g2 master_clock add
------------------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-06

#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTO-06 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTO-06
# Severity: Error
# Option requires another option when used
# ==============================
Violation A0

List of constraints/node:
clk3_g1 (generated clock)

clk3_g1 (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTO-06_test1.sdc:11:1) -name clk3_g1 -
add -combinational -source [get_ports clk3] -divide_by 1 \
[get_pins c2/Z]

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# ==============================
Violation A1

List of constraints/node:
clk3_g2 (generated clock)

clk3_g2 (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTO-06_test1.sdc:12:2) -name clk3_g2 -
combinational -source [get_ports clk3] -divide_by 1 -master [get_clocks clk3] \
[get_pins c2/Z]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.11 Rule SDC-LNTO-07

- Ambiguous option used

Description:
This rule identifies any SDC command where an options is specified however, the abbreviated option
matches other option in the SDC command.

Examples of constraint options which can violate this rule are:

set_max_delay -ri (“ri” matches rise, rise_from, rise_through, rise_to)

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]

set_max_delay 1.1 -ri -from [get_pins b0/A]

Note in “set_max_delay” command option “-ri” is ambiguous because it matches implies other options
starting with “ri”. When the content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTO-07 Error 1 0 Sdc.Lint/SDC-LNTO-07.rpt Ambiguous option used

Sdc.Lint/SDC-LNTO-07.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTO-07
# Ambiguous option used
# Severity: Error
#
# ==============================
#
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 TimeVision Constraints User Guide
# Violations
#

A# Command Option
-----------------------------
A0 set_max_delay0 ri
-----------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTO-07

#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTO-07 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTO-07
# Severity: Error
# Ambiguous option used
# ==============================
Violation A0

List of constraints/node:
set_max_delay0 (constraint)

set_max_delay0 (Design: top, Scenario: default):

fail/set_max_delay (tests/check_cons_SDC-LNTO-07_test1.sdc:10:0) 1.1 -rise_to

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.12 Rule SDC-LNTV-01

- Missing required value

Description:
This rule identifies any SDC command where a required value is missing in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_multicycle_path -to [get_clocks clk2]

Note the SDC command “set_multicycle_path” is missing the number of cycles. When the content of
the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
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-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTV-01 Warning 1 0 Sdc.Lint/SDC-LNTV-01.rpt Missing required value

Sdc.Lint/SDC-LNTV--01.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 04:54:16 PM PDT 2015
#
# SDC-LNTV-01
# Missing required value
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Value
---------------------------------------
A0 set_multicycle_path0 multiplier
---------------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTV-01 –id A0

#********************************************************
#
# Rule: SDC-LNTV-01
# Severity: Warning
# Missing required value
# ==============================
Violation A0

List of constraints/node:
set_multicycle_path0 (constraint)

set_multicycle_path0 (Design: top, Scenario: default):

fail/set_multicycle_path (tests/check_cons_SDC-LNTV-01_test1.tcl:24:2) 0 \
-to [get_clocks clk2]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.13 Rule SDC-LNTV-02

- Invalid value provided

Description:
This rule identifies any SDC command where an invalid value is used in an SDC command.

Sample SDC content:

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create_clock -name clk1 -period 3.9 [get_ports clk1]
create_clock -name clk2 -period 6.9 [get_ports clk2]
set_multicycle_path 2.5 -to [get_clocks clk2]
Note the SDC command “set_multicycle_path” the value “2.5” is an invalid value for the number of
cycles because the value must be an integer. When the content of the SDC file is loaded this rule will
violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTV-02 Warning 1 0 Sdc.Lint/SDC-LNTV-02.rpt Invalid value provided.

Sdc.Lint/SDC-LNTV--02.rpt :
==============================
#
# Design : top
# Date : Thu Jun 04 05:03:00 PM PDT 2015
#
# SDC-LNTV-02
# Invalid value provided.
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Value
---------------------------------------
A0 set_multicycle_path0 multiplier
---------------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTV-02 –id A0

#********************************************************
#
# Rule: SDC-LNTV-02
# Severity: Warning
# Invalid value provided.
# ==============================
Violation A0

List of constraints/node:
set_multicycle_path0 (constraint)

set_multicycle_path0 (Design: top, Scenario: default):

fail/set_multicycle_path (tests/check_cons_SDC-LNTV-02_test1.tcl:22:2) -1 \
-to [get_clocks clk2]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

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3.29.14 Rule SDC-LNTV-03
- Value out of range

Description:
This rule identifies any SDC command where a specified value is beyond the limits required of that
value in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name clk2_mult3 -multiply_by 3 -duty_cycle 400 \
-source [get_ports clk2] [get_pins u_blk/f2/CK]

Note the SDC command “create_generated_clock” the “-duty_cycle” value “400” is out og range
because the value cannot be more than 100. When the content of the SDC file is loaded this rule will
violate.
Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTV-03 Error 1 0 Sdc.Lint/SDC-LNTV-03.rpt Value out of range..

Sdc.Lint/SDC-LNTV--03.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 05:13:26 PM PDT 2015
#
# SDC-LNTV-03
# Value out of range.
# Severity: Error
#
# ==============================
#
# Violations
#

A# Command Value
-----------------------------
A0 clk2_mult3 duty_cycle
-----------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTV-03 –id A0

#********************************************************
#
# Rule: SDC-LNTV-03
# Severity: Error
# Value out of range.
# ==============================

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Violation A0

List of constraints/node:
clk2_mult3 (generated clock)

clk2_mult3 (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTV-03_test2.tcl:25:3) -name clk2_mult3
-source [get_ports clk2] -multiply_by 3 \
[get_pins u_blk/f2/CK]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.15 Rule SDC-LNTV-04

- Value list empty or incorrect value count.

Description:
This rule identifies any SDC command where a specified list is empty or incorrect in an SDC command.
This rule specifically looks for list in “{}”.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name clk2_div2 -edges { 1 2 3 4 } -source [get_ports clk2] [get_pins f1/Q]

Note the SDC command “create_generated_clock” the “-edges” incorrectly has four edges in the list
when three are required. When the content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTV-04 Error 1 0 Sdc.Lint/SDC-LNTV-04.rpt Value list empty or incorrect value count.

Sdc.Lint/SDC-LNTV--04.rpt :
# ==============================
#
# Design : top
# Date : Thu Jun 04 05:27:00 PM PDT 2015
#
# SDC-LNTV-04
# Value list empty or incorrect value count.
# Severity: Error
#
# ==============================
#
# Violations
#

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 TimeVision Constraints User Guide
A# Command Value
-----------------------
A0 clk2_div2 edges
-----------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTV-04 –id A0

#********************************************************
#
# Rule: SDC-LNTV-04
# Severity: Error
# Value list empty or incorrect value count.
# ==============================
Violation A0

List of constraints/node:
clk2_div2 (generated clock)

clk2_div2 (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTV-04_test1.tcl:24:2) -name clk2_div2 \
-source [get_ports clk2] -edges { 1 2 3 4 } [get_pins f1/Q]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.16 Rule SDC-LNTR-01

- Object cannot be found (single).

Description:
This rule identifies any SDC command where a single specified object cannot be found.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name clk2_div2 -divide_by 2 -source [get_ports clk2] -master [get_clocks clk2]
[get_pins f1/Q]

set_max_delay 1.0 -from [get_pins {f1/Q f1/q}]

Note the SDC command “set_max_delay” object “f1/q” cannot be found in the database. When the
content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTR-01 Warning 1 0 Sdc.Lint/SDC-LNTR-01.rpt Object cannot be found (single).

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Sdc.Lint/SDC-LNTR--01.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTR-01
# Object cannot be found (single).
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Option Object

-------------------------------------
A0 set_max_delay3 from f1/q
-------------------------------------

Debug

1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTR-01 –id A0
#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTR-01 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTR-01
# Severity: Warning
# Object cannot be found (single).
# ==============================
Violation A0

List of constraints/node:
set_max_delay3 (constraint)

set_max_delay3 (Design: top, Scenario: default):

set_max_delay (<interactive>:0:3) 1.0 -from [get_pins f1/Q]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.17 Rule SDC-LNTR-02

- Object cannot be found (wildcard).

Description:
This rule identifies any SDC command where multiple object cannot be found specified with a wildcard
“*”.

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Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name clk2_div2 -divide_by 2 -source [get_ports clk2] -master [get_clocks clk2]
[get_pins f1/Q]

set_multicycle_path 2 -from [get_clocks {clk* gclk*}]

Note the SDC command “set_multicycle_path” object “gclk*” cannot be found in the database. When
the content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTR-02 Warning 1 0 Sdc.Lint/SDC-LNTR-02.rpt Object cannot be found (wildcard).

Sdc.Lint/SDC-LNTR--02.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTR-02
# Object cannot be found (wildcard).
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Command Option Object

-------------------------------------------
A0 set_multicycle_path3 from gclk*
-------------------------------------------

Debug

1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTR-02 –id A0
#********************************************************
#* *
#* debug_rule *
#* -rule {SDC-LNTR-02 } *
#* *
#* Design : top *
#* *
#********************************************************
#
# Rule: SDC-LNTR-02
# Severity: Warning
# Object cannot be found (wildcard).
# ==============================

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 TimeVision Constraints User Guide
Violation A0

List of constraints/node:
set_multicycle_path3 (constraint)

set_multicycle_path3 (Design: top, Scenario: default):

set_multicycle_path (<interactive>:0:3) 2 -from [get_clocks {{clk* gclk*}}]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.18 Rule SDC-LNTR-03

- Object is not found, and is part of blackbox or stub.

3.29.19 Rule SDC-LNTR-04

- Incorrect object value type.

Description:
This rule identifies any SDC command where a specified object type is incorrect in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_false_path -from [get_nets *]

Note the SDC command “set_false_path” is incorrectly being set on object type “nets”. When the
content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTR-04 Error 1 0 Sdc.Lint/SDC-LNTR-04.rpt Incorrect object value type.

Sdc.Lint/SDC-LNTR--04.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTR-04
# Incorrect object value type
# Severity: Error
#
# ==============================
#
# Violations
#

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 TimeVision Constraints User Guide
A# Command Option Specification
------------------------------------------------------------------------
A0 set_false_path0 from from expect clock, cell, pin or port : *
------------------------------------------------------------------------

Debug

1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTR-04 –id A0
#********************************************************
#
# Rule: SDC-LNTR-04
# Severity: Error
# Incorrect object value type
# ==============================
Violation A0

List of constraints/node:
set_false_path0 (constraint)

set_false_path0 (Design: top, Scenario: default):

fail/set_false_path (tests/check_cons_SDC-LNTR-04_test1.tcl:22:2) -from [get_nets *]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.20 Rule SDC-LNTR-05

- Empty collection argument.

Description:
This rule identifies any SDC command where a specified object argument is empty in an SDC
command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_clock -name clk2 -period 6.9 [get_ports { }]

Note the SDC command “create_clock” has “[get_ports {}]”, where the port object is empty. When the
content of the SDC file is loaded this rule will violate.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTR-05 Error 1 0 Sdc.Lint/SDC-LNTR-05.rpt Empty objects argument.

Sdc.Lint/SDC-LNTR--5.rpt :

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 TimeVision Constraints User Guide

# ==============================
#
# Design : top
#
# SDC-LNTR-05
# Empty collection argument
# Severity: Error
#
# ==============================
#
# Violations
#
A# Command Option Specification
----------------------------------------------
A0 clk2 objects objects are empty :
----------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.21 Rule SDC-LNTR-06

- Incorrect number of objects.

Description:
This rule identifies any SDC command where a specified object argument has an incorrect number of
objects than required in an SDC command.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
create_generated_clock -name clk2_div2 -divide_by 2 -source [get_ports clk*] \
-master [get_clocks clk2] [get_pins f1/Q]

Note the SDC command “create_generated_clock” has “-source [get_ports clk*]”. From the constraints
above the generated clock would have two sources, ports “clk1 and clk2”, which is incorrect. When the
content of the SDC file is loaded this rule will violate.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-LNTR-06 Error 1 0 Sdc.Lint/SDC-LNTR-06.rpt Incorrect number of objects.

Sdc.Lint/SDC-LNTR--06.rpt :

# ==============================
#
# Design : top
#
# SDC-LNTR-06
# Incorrect number of objects
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 TimeVision Constraints User Guide
# Severity: Error
#
# ==============================
#
# Violations
#

A# Command Option Specification

-----------------------------------------------------------------
A0 clk2_div2 source source expects single point only : clk*
-----------------------------------------------------------------

Debug
1) Use debug_rule command.

tv_shell> debug_rule –rule SDC-LNTR-06 –id A0

#********************************************************
#
# Rule: SDC-LNTR-06
# Severity: Error
# Incorrect number of objects
# ==============================
Violation A0

List of constraints/node:
clk2_div2 (generated clock)

clk2_div2 (Design: top, Scenario: default):

fail/create_generated_clock (tests/check_cons_SDC-LNTR-06_test1.tcl:20:1) -name clk2_div2
-source [get_ports clk*] -divide_by 2 [get_pins f1/Q]

# ==============================

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.22 Rule CLK-SNK001

- clock has no sink

Description:
This rule identifies identifies create_clocks or create_generated_clocks which are not connected to a
legimitate sink. Legitimate sinks are:
1) Clock pin of registers
2) Clock pin of macros
3) Clock pin of ICG
4) The source of another clock application point
5) A port

Design in figure 3.10.3 below shows timing points reported under rule CLK-OBJ001

Figure 3.10.3a

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 TimeVision Constraints User Guide
clk

create_clock -name CLK -period 1.0 [ get_ports clk ]

Figure 3.10.3b

tclk tb0

create_clock -name TCLK -period 1.0 [ get_ports tclk ]

Figure 3.10.3c

rclk tb1 tb2

create_generated_clock -name RCLK_DIV1 \

-source [get_ports rclk] -master [ get_clocks RCLK ] \
create_clock -name RCLK -period 1.0 [ get_ports rclk ] -divide_by 1 [ get_pins tb2/Z ]

In the above designs, Figure 3.10.3a violates because it a floating port with a clock applied, Figure
3.10.3b violates because the clock source does not drive any clock pins or a port, and in Figure 3.10.3c
the generated clock violates because it does drive any clock pins or a port.

Therefore, “check_constraints” will report these ports under rule CLK-SNK001.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Clock CLK-SNK001 Warning 1 0 Sdc.Clock/CLK-SNK001.rpt clock has no sink.

Sdc.Clock/CLK-SNK001.rpt :
# Rule: CLK-SNK001
# Severity: Warning
# ==============================
#
# Design : top
# CLK-SNK001
# clock has no sink
#

A# Clock Clock ID
----------------------------
A0 TCLK 0
----------------------------

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Debug
To confirm the clock has no sinks, check the fanout from the clock application point to “all clock pins”
or “ports”.

tv_shell > all_fanout –from [get_attribute [get_clocks TCLK] source] –endpoints_only \

–filter “is_clock_pin == true || is_port == true”

Nothing is returned confirming the clock has no legitimate sinks.

Waivers
Any reported violation can be waived using the “set_waiver” command.

Usage:
set_waiver –rule <rule_name> -id <annotation ID of the violation>

After all waivers are specified for all rules and ID’s, a complete waivers Tcl command file must be
written out before exiting “tv_shell”. This waivers Tcl file is sourced in future timevision runs.

Example:
set_waiver -rule CLK-SNK001 –id A0 –reason “None”
write_waiver top.waivers.tcl

top.waivers.tcl
set_waiver -rule CLK-SNK001 -obj1 TCLK -author "hollis" -date "05/06/15" -reason "None"

3.29.23 Rule CLK-LAT01

- port/pin with latency for clock that is not part of clock tree

Description:
This rule identifies identifies pins or ports where set_clock_latency is defined, however, the pin or port
is not in the clock tree of the specified clock. For example, datapath pins are usually not part of the
clock tree, or, a specifying pin is in a clock tree different from the clock specified in the
set_clock_latency command.

Design in figure 3.29.20 below shows a pins reported under rule CLK-LAT01

Figure 3.29.20

set_clock_latency -clock [get_clocks clk1] 0.3 [get_pins f1/D]

_
din D Q
f1
clk1 b1 Q

In the above design, Figure 3.29.20 violates because a set_clock_latency is defined for the “D” pin of a
register, which is not in the clock tree.
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 TimeVision Constraints User Guide

Therefore, “check_constraints” will report these ports under rule CLK-LAT01.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-LAT01 Warning 1 0 Sdc.Lint/CLK-LAT01.rpt port/pin with latency for clock that is not part of clock tree.

Sdc.Clock/CLK-LAT01.rpt :
# ==============================
#
# Design : top
#
# CLK-LAT01
# port/pin with latency for clock that is not part of clock tree
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Latency Point
--------------------------------
A0 set_clock_latency2 f1/D
--------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.24 Rule CLK-LAT02

- source latency for generated clock less than master clock source latency

Description:
This rule identifies identifies generated clocks which has a source latency less than the source latency
of its master clock.

Design in figure 3.29.21 below shows a pins reported under rule CLK-LAT02

Figure 3.29.21
create_generated_clock -name clk2_div2 -divide_by 2 -source [get_ports clk2] -master [get_clocks clk2] [get_pins f1/Q]
set_clock_latency 0.3 -source [get_clocks clk2_div2]

_ _
D
_
din D Q D Q Q
f1 f2 f3
clk2 b1 Q Q Q

create_clock -name clk2 -period 1.5 [get_ports clk2]

set_clock_latency 1.3 -source [get_clocks clk2]

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In the above design, Figure 3.29.21 violates because a source latency of 0.3 for generated clock
“clk2_div2” is less than source latency of “1.3” for its master “clk2”.

Therefore, “check_constraints” will report these ports under rule CLK-LAT02.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-LAT02 Warning 1 0 Sdc.Lint/CLK-LAT02.rpt source latency for generated clock less than master clock source
latency

Sdc.Clock/CLK-LAT02.rpt :
# ==============================
#
# Design : top
#
# CLK-LAT02
# source latency for generated clock less than master clock source latency
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Max/Late Latency Master Clock Min/Early Latency Generated Clock

----------------------------------------------------------------------------
A0 set_clock_latency4 clk2 set_clock_latency5 clk2_div2
----------------------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.25 Rule CLK-LAT03

- inconsistent latency specified (min > max | early > late)

Description:
This rule identifies identifies set_clock_latency where “-min” is greater than “-max” or “-early” is
greater than “-late”, which is inconsistent.

Design in figure 3.29.22 below shows a pins reported under rule CLK-LAT03

Figure 3.29.23

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 TimeVision Constraints User Guide

_
din D Q
f1
clk2 b1 Q

create_clock -name clk2 -period 1.5 [get_ports clk2]

set_clock_latency -max 0.3 [get_clocks clk2]
set_clock_latency -min 1.3 [get_clocks clk2]

In the above design, Figure 3.29.22 violates because the “-max” latency of 0.3 is less than “-min”
latency of “1.3” for clock “clk2”.

Therefore, “check_constraints” will report these ports under rule CLK-LAT03.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-LAT03 Warning 1 0 Sdc.Lint/CLK-LAT03.rpt inconsistent latency specified (min > max | early > late)

Sdc.Clock/CLK-LAT03.rpt :
# ==============================
#
# Design : top
#
# CLK-LAT03
# inconsistent latency specified (min > max | early > late)
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Max Latency Min LatencyClock

---------------------------------------------
A0 set_clock_latency2 set_clock_latency3
---------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.26 Rule CLK-LAT04

- negative latency value

Description:
This rule identifies identifies set_clock_latency where the value is negative.

Design in figure 3.29.23 below shows a pins reported under rule CLK-LAT04
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 TimeVision Constraints User Guide

Figure 3.29.23

_
din D Q
f1
clk2 b1 Q

create_clock -name clk2 -period 1.5 [get_ports clk2]

set_clock_latency -1.3 [get_clocks clk2]

In the above design, Figure 3.29.23 violates because the latency of “-1.3” for clock “clk2”.

Therefore, “check_constraints” will report these ports under rule CLK-LAT04.

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-LAT04 Warning 2 0 Sdc.Lint/CLK-LAT04.rpt negative latency value

Sdc.Clock/CLK-LAT04.rpt :
# ==============================
#
# Design : top
#
# CLK-LAT04
# negative latency value
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Latency Value Clock

------------------------------------------------------
A0 set_clock_latency2 -1.3 clk2
------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.27 Rule CLK-UNC01

- uncertainty set for object not a clock.

Description:
This rule identifies set_clock_uncertainty commands set on any object other than a clock.

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Sample SDC content:

create_clock -name clk2 -period 6.9 [get_ports clk2]

set_clock_uncertainty 0.1 [get_ports clk2]

Note the SDC command “set_clock_uncertainty” is set on port “clk2”. Even though there is a clock
“clk2” this willviolate because the object type is port.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-UNC01 Warning 1 0 Sdc.Lint/CLK-UNC01.rpt uncertainty set for object not a clock.

Sdc.Lint/SDC-UNC01.rpt :

# ==============================
#
# Design : top
#
# CLK-UNC01
# uncertainty set for object not a clock
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Uncertainty Object
-------------------------------------
A0 set_clock_uncertainty2 clk2
-------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.28 Rule CLK-UNC02

- uncertainty greater than available clock time.

Description:
This rule identifies set_clock_uncertainty where the uncertainty time is greater than the available clock
time.

Sample SDC content:

create_clock -name clk2 -period 6.9 [get_ports clk2]

set_clock_uncertainty 7.1 [get_clocks clk2]

Note the SDC command “set_clock_uncertainty” is set to 7.1 for clock “clk2” while the clock period is
6.9.
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Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-UNC02 Warning 1 0 Sdc.Lint/CLK-UNC02.rpt uncertainty greater than available clock time

Sdc.Lint/SDC-UNC02.rpt :

# ==============================
#
# Design : top
#
# CLK-UNC02
# uncertainty greater than available clock time
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Uncertainty From Clock To Clock

------------------------------------------------------------------
A0 set_clock_uncertainty2 clk2 clk2
------------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.29 Rule CLK-UNC03

- incomplete uncertainty specified.

Description:
This rule identifies set_clock_uncertainty where certain options are used which require other options
or a matching set_clock_uncertainty of the opposite timing type.
For example “set_clock_unceratinty -setup” might require “set_clock_uncertainty -hold”, otherwise it
might be incomplete.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_clock_uncertainty 0.2 -rise -from [get_clocks clk2]

Note the SDC command “set_clock_uncertainty –rise -from” causes timevision to violate this rule
because “-fall, -setup, and –hold” are also expected.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------

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Sdc.Lint CLK-UNC03 Warning 1 0 Sdc.Lint/CLK-UNC03.rpt incomplete uncertainty specified

Sdc.Lint/SDC-UNC03.rpt :

# ==============================
#
# Design : top
#
# CLK-UNC03
# incomplete uncertainty specified
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Uncertainty Relationship
-----------------------------------------------
A0 clk2 missing -fall -setup -hold
-----------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.30 Rule CLK-UNC04

- negative uncertainty value.

Description:
This rule identifies set_clock_uncertainty where the uncertainty time is a negative value.

Sample SDC content:

create_clock -name clk2 -period 6.9 [get_ports clk2]

set_clock_uncertainty -0.5 [get_clocks clk2]

Note the SDC command “set_clock_uncertainty” is set to “-0.5” for clock “clk2”.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-UNC04 Warning 1 0 Sdc.Lint/CLK-UNC04.rpt negative uncertainty value

Sdc.Lint/SDC-UNC04.rpt :

# ==============================
#
# Design : top
#
# CLK-UNC04
# negative uncertainty value
# Severity: Warning
#

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# ==============================
#
# Violations
#

A# Uncertainty Value From Clock To Clock

---------------------------------------------------------------------------
A0 set_clock_uncertainty2 -0.5 clk2 clk2
---------------------------------------------------------------------------
Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.31 Rule CLK-OVR01

- clock is overridden by another clock with same name.

Description:
This rule identifies create_clock or create_generated_clock constraints which are overridden by
another clock applied at the same point with the same name, independent of “-add”.

Sample SDC content:

create_clock -name clk1 -period 6.9 [get_ports clk1]

create_clock -name clk1 -period 7.9 [get_ports clk1]

Note the SDC command the second create_clock overrides the first at application point port “clk1”.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-OVR01 Warning 1 0 Sdc.Lint/CLK-OVR01.rpt clock is overridden by another clock with same name

Sdc.Lint/CLK-OVR01.rpt :

# ==============================
#
# Design : top
#
# CLK-OVR01
# clock is overridden by another clock with same name
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Overriding clock Overridden Clock

-----------------------------------------
A0 clk1 clk1
-----------------------------------------
Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.
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3.29.32 Rule CLK-OVR02

- clock is overriden because another clock defined at same point without -add

Description:
This rule identifies create_clock or create_generated_clock constraints which are overridden by
another clock applied at the same point with different name and “-add” was not used so the clock
defined first is completely overridded by the last clock applied.

Sample SDC content:

create_clock -name clk1 -period 6.9 [get_ports clk1]

create_clock -name pclk -period 7.9 [get_ports clk1]

Note the SDC command the second create_clock “pclk” overrides the first clock “clk1”at application
point.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-OVR02 Warning 1 0 Sdc.Lint/CLK-OVR02.rpt clock is overriden because another clock defined at
same point without -add

Sdc.Lint/CLK-OVR02.rpt :

# ==============================
#
# Design : top
#
# CLK-OVR02
# clock is overriden because another clock defined at same point without -add
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Overriding clock Overridden Clock Apply Point

------------------------------------------------------
A0 clk1 pclk clk1
------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.33 Rule CLK-VRT01

- virtual mapped clock does not have same period as real

Description:
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 TimeVision Constraints User Guide
This rule identifies any virtual clock mapped to a real clock and the virtual clock period does not match
the real clock period.

Sample SDC content:

create_clock -name clk1 -period 6.9 [get_ports clk1]

create_clock -name clk1_v -period 7.9

Note the SDC command the virtual clock “clk1_v” has a period of 7.9 but the real clock has a period of
6.9.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-VRT01 Warning 1 0 Sdc.Lint/CLK-VRT01.rpt virtual mapped clock does not have same period as real

Sdc.Lint/CLK-VRT01.rpt :

# ==============================
#
# Design : top
#
# CLK-VRT01
# virtual mapped clock does not have same period as real
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Real Clock Virtual Clock

--------------------------------
A0 clk1 clk1_v
--------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.34 Rule CLK-VRT02

- virtual clock has no corresponding real clock

Description:
This rule identifies any virtual clock mapped to a real clock and the virtual clock period does not match
the real clock period.

Sample SDC content:

create_clock -name clk1 -period 6.9 [get_ports clk1]

create_clock -name dummy_clk1_v -period 0.0
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 TimeVision Constraints User Guide

Note the SDC command the virtual clock “dummy_clk1_v” has a period of 0.0 but the real clock has a
period of 6.9 so the virtual clock will not map to a real clock.

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-VRT02 Warning 1 0 Sdc.Lint/CLK-VRT02.rpt virtual clock has no corresponding real clock

Sdc.Lint/CLK-VRT02.rpt :

# ==============================
#
# Design : top
#
# CLK-VRT02
# virtual clock has no corresponding real clock
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Virtual Clock
--------------------
A0 dummy_clk1_v
--------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.35 Rule CLK-TRN01

- inconsistent set_clock_transition options (min > max)

Description:
This rule identifies set_clock_transition where “-min” value is greater than “-max” value.

Sample SDC content:

create_clock -name clk1 -period 6.9 [get_ports clk1]

set_clock_transition -min 0.3 [get_clocks clk1 ]
set_clock_transition -max 0.1 [get_clocks clk1]

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-TRN01 Warning 1 0 Sdc.Lint/CLK-TRN01.rpt inconsistent set_clock_transition options (min > max)

Sdc.Lint/CLK-TRN01.rpt :

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 TimeVision Constraints User Guide
# ==============================
#
# Design : top
#
# CLK-TRN01
# inconsistent set_clock_transition options (min > max)
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Max Transition Min Transition

------------------------------------------------------------------
A0 set_clock_transition3 set_clock_transition2
------------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.36 Rule CLK-TRN02

- incomplete set_clock_transition values (-rise without -fall or -min without -max)

Description:
This rule identifies incomplete set_clock_transition where “-min” exist but no “-max”, or “-rise” exist
but no “-fall”.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_clock_transition -rise 0.3 [get_clocks {clk1 clk2}]

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-TRN02 Warning 2 0 Sdc.Lint/CLK-TRN02.rpt incomplete set_clock_transition values
(-rise without -fall or -min without -max)

Sdc.Lint/CLK-TRN02.rpt :

# ==============================
#
# Design : top
#
# CLK-TRN02
# incomplete set_clock_transition values (-rise without -fall or -min without -max)
# Severity: Warning
#
# ==============================
#
# Violations
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#

A# Transition Type
---------------------------------
A0 clk1 missing -fall
A1 clk2 missing -fall
---------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.37 Rule CLK-TRN03

- negative set_clock_transition

Description:
This rule identifies set_clock_transition with negative transition value.

Sample SDC content:

create_clock -name clk1 -period 3.9 [get_ports clk1]

create_clock -name clk2 -period 6.9 [get_ports clk2]
set_clock_transition -0.5 [get_clocks clk1]
set_clock_transition 0.5 [get_clocks clk2]

Reports:
Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint CLK-TRN03 Warning 1 0 Sdc.Lint/CLK-TRN03.rpt negative set_clock_transtiion

Sdc.Lint/CLK-TRN03.rpt :

# ==============================
#
# Design : top
#
# CLK-TRN03
# negative set_clock_transtiion
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Transition Value Clock

------------------------------------------
A0 set_clock_transition0 -0.5 clk1
------------------------------------------
Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

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 TimeVision Constraints User Guide
3.29.38 Rule IO-LD-01
- undefined set_load on constrained output without set_dont_touch/network specified

Description:
This rule identifies constrained outputs which are missing a “set_load” constraint.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports dout1]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports io1]

3.29.39 Rule IO-LD-02

- incomplete load options (no -min with -max for example)

Description:
This rule identifies constrained outputs which has a “set_load -min” constraint but missing “set_load –
max” constraint.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports dout1]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports io1]
set_load 0.1 -min [get_ports dout1]
set_load 0.1 -max [get_ports io1]

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint IO-LD-02 Warning 2 0 Sdc.Lint/IO-LD-02.rpt incomplete load options (no -min with -max for example)

Sdc.Lint/IO-LD-02.rpt :

# ==============================
#
# Design : top
#
# IO-LD-02
# incomplete load options (no -min with -max for example)
# Severity: Warning
#
# ==============================
#
# Violations
#

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 TimeVision Constraints User Guide
A# Node Rise Constraint Fall Constraint Max Constraint Min Constraint
------------------------------------------------------------------------------
A0 dout1 set_load3 set_load3 missing -max set_load3
A1 io1 set_load4 set_load4 set_load4 missing -min
------------------------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.40 Rule IO-LD-03

- inconsistent load values (min>max)

Description:
This rule identifies constrained outputs which has a “set_load -min” constraint greater than “set_load –
max” constraint.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports dout1]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports io1]
set_load 0.2 -min [get_ports dout1]
set_load 0.1 -max [get_ports dout1]
set_load 0.2 -min [get_ports io1]
set_load 0.1 -max [get_ports io1]

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint IO-LD-03 Warning 2 0 Sdc.Lint/IO-LD-03.rpt inconsistent load values (min>max)

Sdc.Lint/IO-LD-03.rpt :

# ==============================
#
# Design : top
#
# IO-LD-03
# inconsistent load values (min>max)
# Severity: Warning
#
# ==============================
#
# Violations
#
A# Max Load Min Load Node
----------------------------------
A0 set_load6 set_load5 io1
A1 set_load4 set_load3 dout1
----------------------------------

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Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.41 Rule IO-LD-04

- load outside char range for driver

Description:
This rule identifies constrained outputs which has a “set_load” constraint greater outside the
characterized parameters in the liberty model.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports dout1]

set_output_delay 1.0 -clock [get_clocks clk] [get_ports io1]
set_load 500.0 [get_ports dout1]
set_load 500.0 [get_ports io1]

3.29.42 Rule SDC-MD-01

- incomplete set_max_delay

Description:
This rule identifies a “set_max_delay -rise” constraint but missing “set_max_delay -fall”, or a
“set_max_delay -fall” but missing “set_max_delay -rise”.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_max_delay -rise 0.2 -from [get_pins f1/Q]

set_max_delay -fall 0.2 -from [get_pins f2/Q]

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-MD-01 Warning 2 0 Sdc.Lint/SDC-MD-01.rpt incomplete set_max_delay

Sdc.Lint/SDC-MD-01.rpt :

# ==============================
#
# Design : top
#
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# SDC-MD-01
# incomplete set_max_delay
# Severity: Warning
#
# ==============================
#
# Violations
#

A# Max Delay Rise Fall Object Clock

----------------------------------------------------------------------
A0 set_max_delay1 specified -rise missing -fall f1/Q
A1 set_max_delay2 missing -rise specified -fall f2/Q
----------------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

3.29.43 Rule SDC-ND-01

- incomplete set_min_delay

Description:
This rule identifies a “set_min_delay -rise” constraint but missing “set_min_delay -fall”, or a
“set_min_delay -fall” but missing “set_min_delay -rise”.

Sample SDC content:

create_clock -name clk -period 1.0 [get_ports clk]

set_min_delay -rise 0.2 -from [get_pins f1/Q]

set_min_delay -fall 0.2 -from [get_pins f2/Q]

Reports:

Sdc.Qor_Fails.rpt:
Category Rule Sev'ty #'Vios #'Waived Report Description
-----------------------------------------------------------------------------------------------------------------------------------------------------
Sdc.Lint SDC-ND-01 Warning 2 0 Sdc.Lint/SDC-ND-01.rpt incomplete set_min_delay

Sdc.Lint/SDC-ND-01.rpt :

# ==============================
#
# Design : top
#
# SDC-ND-01
# incomplete set_min_delay
# Severity: Warning
#
# ==============================
#
# Violations
#

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A# Min Delay Rise Fall Object

---------------------------------------------------------------
A0 set_min_delay1 specified -rise missing -fall f1/Q
A1 set_min_delay2 missing -rise specified -fall f2/Q
---------------------------------------------------------------

Waivers
SDC Lint rule violations cannot be waived. The user must fix the violation.

January 2015 284 Ausdia, Inc © 2015