590 Chapter 7 Sequential Logic Design Principles ee | KEEP YOUR FEEDBACK TO | YOURSELF Only rarely does a logic designer encounter a situation where a feedback sequential circuit must be analyzed or designed. The most commonly used feedback sequential circuits are the flip-flops and latches that are used as the building blocks in larger sequential circuits. Their internal design and operating specifications are supplied by an IC manufacturer. Even an ASIC designer typically does not design gate-level flip-flop or latch. circuits, since these elements are supplied in a “library” of commonly used functions in the particular ASIC technology. Still, you may be curious about how off-the-shelf flip-flops and latches “do their thing”; this section shows you how to analyze such circuits. fiundamental-mode *7.9 Feedback Sequential-Circuit Analy The simple bistable and the various latches and flip-flops that we studied earlier in this chapter are all feedback sequential circuits. Each has one or more feed- back loops that, ignoring their behavior during state transitions, store a 0 or a 1 at all times. The feedback loops are memory elements, and the circuits’ behavior depends on both the current inputs and the values stored in the loops. *7.9.1 Basic Analysis Feedback sequential circuits are the most common example of fundamental- mode circuits. In such circuits, inputs are not normally allowed to change simultaneously, The analysis procedure assumes that inputs change one at a time, allowing enough time between successive changes for the circuit to settle into a stable internal state. This differs from clocked circuits, in which multiple inputs can change at almost arbitrary times without affecting the state, and all input values are sampled and state changes occur with respect to a clock signal. Like clocked synchronous state machines, feedback sequential circuits ‘may be structured as Mealy or Moore circuits, as shown in Figure 7-65. A circuit with n feedback loops has n binary state variables and 2" states. To analyze a feedback sequential circuit, we must break the feedback loops in Figure 7-65 so that the next value stored in each loop can be predicted as a function of the circuit inputs and the current value stored in all loops. Figure 7-66 shows how to do this for the NAND circuit for a D latch, which has only one feedback loop. We conceptually break the loop by inserting a fictional butfer in the loop as shown. The output of the buffer, named Y, is the single state variable for this example. Let us assume that the propagation delay of the fictional buffer is 10 ns (but any nonzero number will do) and that all of the other circuit components have “This section and all of its subsections are optional.7.9 Feedback Sequential-Circuit Analysis 591 Mealy machine only inputs ==>] Next-State Beatie Output Logie Logie outputs (| ¥ G feedback loops zero delay. If we know the circuit's current state (Y) and inputs (D and C), then we can predict the value Y will have in 10 ns. The next value of Y, denoted Y*, is acombinational function of the current state and inputs. Thus, reading the circuit diagram, we can write an excitation equation for Y* Ye = (C-D)+(C-D'+ YY C-D+C’-Y+D-Y Now the state of the feedback loop (and the circuit) can be written as a function of the current state and input, and enumerated by a transition table as shown in Figure 7-67. Each cell in the transition table shows the fictional-buffer output value that will occur 10 ns (or whatever delay you've assumed) after the corresponding state and input combination occurs. A transition table has one row for each possible combination of the state variables, so a circuit with n feedback loops has 2" rows in its transition table. The table has one column for each possible input combination, so a circuit with m inputs has 2” columns in its transition table. rT including itself, Figure 7-65 Feedback sequential circuit structure for Mealy and Moore machines. excitation equation transition table Figure 7-66 Feedback analysis, of a D latch. JUST ONE LOOP The way the circuit in Figure 7-66 is drawn, it may look like there are two feedback loops. However, once we make one break as shown, there are no more loops. That is, each signal can be written as a combinational function of the other signals, not592 Chapter7 total state internal state input state stable total stare unstable total state state table output equation Sequential Logic Design Principles 0 0 0 1 0 Figure 7-67 Transition table for the 1 1 1 10 Dlateh in Figure 7-66. = By definition, a fundamental-mode circuit such as a feedback sequential circuit does not have a clock to tell it when to sample its inputs. Instead, we can imagine that the circuit is evaluating its current state and input continuously (ot every 10 ns, if you prefer). As the result of each evaluation, it goes to a next state predicted by the transition table, Most of the time, the next state is the same as the current state: this is the essence of fundamental-mode operation. We make some definitions below that will help us study this behavior in more detail. Ina fundamental-mode circuit, a total state is a particular combination of internal state (the values stored in the feedback loops) and input state (the cur- rent value of the circuit inputs). A stable total state is a combination of internal state and input state such that the next internal state predicted by the transition table is the same as the current internal state. If the next internal state is different, then the combination is an unstable toral state. We have rewritten the transition table for the D latch in Figure 7-68 as a state table, giving the names SO and S1 to the states and drawing a circle around the stable total states. To complete the analysis of the circuit, we must also determine how the outputs behave as functions of the internal state and inputs. There are two outputs and hence two output equations: Q=C-D+C’-Y+D-Y QN = C-D'+Y’ Note that Q and QN are ourputs, not state variables. Even though the circuit has two outputs, which can theoretically take on four combinations, it has only one state variable Y, and hence only two states. The output values predicted by the Q and QN equations can be incorpor- ated in a combined state and output table that completely describes the operation of the circuit, as shown in Figure 7-69, Although Q and QN are normally com- plementary, it is possible for them to have the same value (1) momentarily, during the transition from $0 to S1 under the CD = 11 column of the table. We can now predict the behavior of the cireuit from the transition and output table. First of all, notice that we have written the column labels in our state tables in “Karnaugh map” order, so that only a single input bit changes between adjacent columns of the table. This layout helps our analysis because ‘we assume that only one input changes at a time and that the circuit always reaches a stable total state before another input changes. "7.9 Feedback Sequential-Circuit Analysis 593 cD s 00 OL ll 10 Figure 7-68 ss © 1 @ State table for the D latch in Figure 7-66, s @ © © showing stable total e slates, cD Ss 00 OL I 10 POCO ee ue Figure 7-69 s+ @10 @.0 G10 90,01 stateandoutputtable ge ey eon thereto Atany time, the circuit is in a particular internal state and a particular input is applied to it; we called this combination the total state of the circuit. Let us start at the stable total state “S0/00” (S = SO, C D = 00), as shown in Figure 7-70. Now suppose that we change D to 1. The total state moves to one cell to the right; we have a new stable total state, S0/01. The D input is different, but the internal state and output are the same as before. Next, let us change C to 1. The total state moves one cell to the right to 0/11, which is unstable. The next-state entry in this cell sends the circuit to internal state $1, so the total state moves down one cell, to S1/I1. Examining the next-state entry in the new cell, we find that we have reached a stable total state, We can trace the behavior of the circuit for any desired sequence of single input changes in this way. Now we can revisit the question of simultaneous input changes. Even though “almost simultaneous” input changes may occur in practice, we must assume that nothing happens simultaneously in order to analyze the behavior of sequential circuits. The impossibility of simultaneous events is supported by the varying delays of circuit components themselves, which depend on voltage, temperature, and fabrication parameters. What this tells us is that a set of 7 CD) Figure 7-70 soo m1 10 Analysis ofthe Dlatch “ for a few transitions. so Go gets @.o st @0 @uw 10 $0.01 S*,QQN594 Chapter 7 Sequential Logic Design Principles cut set minimal cut set co Ss 00 o1 Wl 10, so @ior_ | 1 6 @.o sin € ré Figure 7-71 TAnpelntcianges St G10) Gan 5 Baw 10 80.01 with the D latch. 35 QQN inputs that appear to us to change “simultaneously” may actually change in any of n! different orders from the point of view of the circuit operation, For example, consider the operation of the D latch as shown in Figure 7-71, Let us assume that it starts in stable total state $1/11. Now suppose that C and D are both “simultaneously” set to 0. In reality, the circuit behaves as if one or the other input went to 0 first. Suppose that C changes first. Then the sequence of two left-pointing arrows in the table tells us that the circuit goes to stable total state $1/00. However, if D changes first, then the other sequence of arrows tells us that the circuit goes to stable total state $0/00. So the final state of the circuit is unpredictable, a clue that the feedback loop may actually become metastable if we set C and D to 0 simultaneously. The time span over which this view of simultaneity is relevant is the setup- and hold-time window of the D latch. Simultaneous input changes don’t always cause unpredictable behavior, However, we must analyze the effects of all possible orderings of signal changes to determine this; if all orderings give the same result, then the circuit output is predictable. For example, consider the behavior of the D latch starting in total state $0/00 with C and D simultaneously changing from 0 to 1; italways ends up in total state 1/11. °7.9.2 Analyzing Circuits with Multiple Feedback Loops In circuits with multiple feedback loops, we must break all of the loops, creating one fictional buffer and state variable for each loop that we break. There are many possible ways, which mathematicians call cur sets, to break the loops in a given circuit, so how do we know which one is best? The answer is that any ‘minimal cut set—a cut set with a minimum number of cuts—is fine. Mathema- ticians can give you an algorithm for finding a minimal cut set, but as a digital designer working on small circuits, you can just eyeball the circuit to find one. Different cut sets for a circuit lead to different excitation equations, transi- tion tables, and state/output tables. However, the stable total states derived from one minimal cut set correspond one-to-one to the stable total states derived from any other minimal cut set for the same circuit. That is, state/output tables derived from different minimal cut sets display the same input/output behavior, with only the names and coding of the states changed.Figure 7-72 Simplified positive edge-triggered 7.9 Feedback Sequential-Circuit Analysis 595 es a ae YET te Y1-CLK+¥3-(Y1-+ CLK’ + ¥2-D) p(t CLKy | Y1-CLK + CLK'+¥2 =Y1+CLK’ +¥2-D (v3: (V1 + CLK'+ Y2-D))' = 8+ Y1"+¥2"- CLK + Y1"-CLK-D’ D flip-flop for analysis. po——_| ye ee at If you use more than the minimal number of cuts to analyze a feedback sequential circuit, the resulting state/output table will still describe the circuit correctly. However, it will use 2” times as many states as necessary, where m is the number of extra cuts. Formal state-minimization procedures can be used to reduce this larger table to the proper size, but it’s a much better idea to select a minimal cut set in the first place. A good example of a sequential circuit with multiple feedback loops is the commercial circuit design for a positive edge-triggered TTL D flip-flop that we showed in Figure 7-20. The circuit is redrawn in simplified form in Figure 7-72, assuming that the original circuit's PR_L and CLR_L inputs are never asserted, and also showing fictional butfers to break the three feedback loops. These three loops give rise to eight states, compared with the minimum of four states used by the two-loop design in Figure 7-19. We'll address this curious difference later. The following excitation and output equations can be derived from the logic diagram in Figure 7-72: vis Yas Ya Q aN Y2-D+Y1-CLK Y1+CLK’+Y2-D = Y1-CLK+Y1-Y3+Y3-CLK’+Y2-Y3-D Y1-CLK+Y1-Y3+Y3-CLK’+Y2-Y3-D Y3'+Y1’- Y2"- CLK +Y1’» CLK - D The corresponding transition table is shown in Figure 7-73, with the stable total states circled. Before going further, we must introduce the concept of “races.”596 race Chapter 7 Sequential Logic Design Principles aK Y1Y2Y3 00 o1 ob 10 00010010 000 001 O11 = oll 000 10 110 110000 ou 111 111000 100 010 010 i i Figure 7-73 101 oll oll lt i Transition table 110010 Lieu for the D flip-flop in Figure 7-72. ul ou (oD) ay @ NS a "7.9.3 Races Ina feedback sequential circuit, a race is said to occur when multiple internal variables change state as a result of a single input changing state. In the example of Figure 7-73, a race occurs in stable total state 011/00 when CLK is changed from 0 to 1. The table indicates that the next internal state is 000, a 2-variable change from O11. ‘As we've discussed previously, logic signals never really change “simulta- neously.” Thus, the internal state may make the change 011-000 as either 011-001-000 or 011-010-4000. Figure 7-74 indicates that the example circuit, starting in total state 011/00, should go to total state 000/10 when CLK changes from 0 to 1. However, it may temporarily visit total state 001/10 or 010/10 along the way. That's OK, because the next intemal state for both of these temporary states is 000; therefore, even in the temporary states, the excita- tion logic continues to drive the feedback loops toward the same stable total K Figure 7-74 CES Portion of the D flip-flop Yiy2Y3_ 00 OL un 10 transition table showing : a noneritical race 000 010 10 G0) God) ool oo o00_/ fo | 010 10110 \ 004 on Dn Pewo’ Yi Y2« Y3*7.9 Feedback Sequential-Circuit Analysis 597 CLK D YiY2y3 00 01 i 10 00001010 000 ool Ol. OLL 010 no 110 Or AR OCD ASTER 100010010, ol oll, Figure 7-75 se un A transition table Ww oO @y @y @ , containing a critical race. Yt% Yo" YS" state, 000/10. Since the final state does not depend on the order in which the state variables change, this is called a noncritical race. noneritical race ‘Now suppose that the next-state entry for total state 010/10 is changed to 110, as shown in Figure 7-75, and consider the case that we just analyzed. Starting in stable total state 011/00 and changing CLK to 1, the circuit may end up in internal state 000 or 111, depending on the order and speed of the internal variable changes. This is called a critical race. critical race WATCH OUT FOR = When you design a feedback-based sequential circuit, you must ensure that its CRITICAL RACES! transition table does not contain any critical races. Otherwise, the circuit may operate unpredictably, with the next state for racy transitions depending on factors like temperature, voltage, and the phase of the moon. “7.9.4 State Tables and Flow Tables Analysis of the real transition table, Figure 7-73, for our example D flip-flop circuit, shows that it does not have any critical races; in fact, it has no races, except the noncritical one we identified earlier. Once we've determined this fact, we no longer need to refer to state variables. Instead, we can name the state~ variable combinations and determine the output values for each state/input combination to obtain a state/output table such as Figure 7-76. The state table shows that for some single input changes, the circuit takes multiple “hops” to get to a new stable total state. For example, in state SO/I1, an input change to 01 sends the circuit first to state $2 and then to stable total state $6/01. A flow table eliminates multiple hops and shows only the ultimate desti- flow rable598 Chapter 7 Sequential Logic Design Principles CLKD Ss 00 ol in 10 $0 $2.01 $2.01 @).o1 @).01 $1 $3.10 $3.10 $0.01 $0.1 s2 @).01 $6.01 $6.01 So ,o1 3 @).10 S710 S7 ,10 So ,o1 84 $2.01 $2.01 87,11 $7.11 $5 $3.10 $3,10 S7 ,10 S7 ,10 Figure 7-76 se s2.o1 @é).o1 7.11 s7,11 State/output table for the D flip-flop in s7 3.10 @).1 @).10 @).10 Figure 7-72. SEV SSE eYS*SGION cs nation for each transition. The flow table also eliminates the rows for unused internal states—ones that are stable for no input combination—and eliminates the next-state entries for total states that cannot be reached from a stable total state as the result of a single input change. Using these rules, Figure 7-77 shows the flow table for our D flip-flop example, The flip-flop’s edge-triggered behavior can be observed in the series of state transitions shown in Figure 7-78, Let us assume that the flip-flop starts in internal state $0/10. That is, the flip-flop is storing a 0 (since Q = 0), CLK is 1, and Dis 0. Now suppose that D changes to 1; the flow table shows that we move one cell to the left, still a stable total state with the same output value. We can change D between 0 and 1 as much as we want, and just bounce back and Figure 7-77 CLKD Flow and output table tS et Pay for the D flip-flop in Figure 7-72. SO S201 $6 01 01 @0).o1 s2 @).o1 s6.o1 — $0.10 s3 @).10 s7,10 —,- 80,01 sé s2 01 @€),01 s7,11 —,- s7 $3.10 67,10 @),10 @),10 S*,QQN7.9 Feedback Sequential-Circuit Analysis cLKD s 0 Ol ul 10 sB GB).01 sé 01 @8).01 ou s3 @).10 87.10 —.- sB.01 Figure 7-79 So) Se eat Serr Ficcdioed toed 87 83,10 G7), 10 @).10 @),10 output table for a positive edge-triggered S*,Q0N D fip-tlop. forth between these two cells. However, once we change CLK to 0, we move to internal state S2 or $6, depending on whether D was 0 or 1 at the time; but still the output is unchanged. Once again, we can change D between 0 and 1 as much as we want, this time bouncing between $2 and S6 without changing the output. The moment of truth finally comes when CLK changes to 1. Depending on whether we are in $2 or $6, we go back to $0 (leaving Q at 0) or to S7 (setting Q to 1). Similar behavior involving $8 and $7 can be observed on a rising clock edge that causes Q to change from 1 to 0. In Figure 7-19 we showed a circuit for a positive edge-triggered D flip-flop with only two feedback loops and hence four states. The circuit that we just analyzed has three loops and eight states. Even after eliminating unused states, the flow table has five states. However, a formal state-minimization procedure can be used to show that states SO and $2 are “compatible,” so that they can be merged into a single state SB that handles the transitions for both original states, as shown in Figure 7-79. Thus, the job really could have been done by a four- state circuit, In fact, in Exercise 7.71 you'll show that the circuit in Figure 7-19 does the job specified by the reduced flow table. po GE Rs pir get ris] 2 Figure 7-78 s 00 1 u 10 Flow and output table showing the D flip-flop’s ae so se “br so a1 GS). ( edge-triggered behavior. = Os. Ol, $3 @ IN eY lo — sé \s2.01 Ser, o—.- s7 SAC Bw *.QQN 599600 Chapter 7 Sequential Logic Design Principles es Yee Po Y2 cK: Ee HE Ae Figure 7-80 Positive edge-triggered CMOS 0 flip-flop for analysis. .5 CMOS D Flip-Flop Analysis CMOS flip-flops typically use transmission gates in their feedback loops. For example, Figure 7-80 shows the circuit design of the “FD1Q” positive-edge- triggered D flip-flop in LSI Logic’s LCASOOK series of CMOS gate arrays. Such a flip-flop can be analyzed in the same way as a purely logic-gate-based design, once you recognize the feedback loops. Figure 7-80 has two feedback loops, each of which has a pair of transmission gates in a mux-like configuration con- trolled by CLK and CLK’, yielding the following loop equations: Yi* = CLK’. D’+CLK-Y1 Y2e = CLK-Y1’+CLK’- Y2 Except for the double inversion of the data as it goes from D to Y2* (once in the Y1# equation and again in the Y2* equation), these equations are very reminis- cent of the master/slave-latch structure of the D flip-flop in Figure 7-15. Completing the formal analysis of the circuit is left as an exercise (7.75). Note, however, that since there are just two feedback loops, the resulting state and flow tables will have the minimum of just four states. FEEDBACK CIRCUIT DESIGN The feedback sequential circuits that we've analyzed in this section exhibit quite reasonable behavior, since, after all, they are latch and flip-flop circuits that have been used for years. However, if we throw together a “random” collection of gates and feedback loops, we won't necessarily get “reasonable” sequential circuit behav- ior. In a few rare cases we may not get a sequential circuit at all (see Exercise 7.72), and in many cases the circuit may be unstable for some or all input combinations (see Exercise 7.87). Thus, the design of feedback sequential circuits continues to be something of a black art and is practiced only by a small fraction of digital designers, Still, the next section introduces basic concepts that help you do simple designs.7.10 Feedback Sequential-Circuit Design 601 te ue ro excitation logic a feedback loop *7.10 Feedback Sequential-Circuit Design It’s sometimes useful to design a small feedback sequential circuit, such as a specialized latch or a pulse catcher; this section will show you how. It’s even possible that you might go on to be an IC designer and be responsible for designing high-performance latches and flip-flops from scratch. This section will serve as an introduction to the basic concepts you'll need, but you'll still need considerably more study, experience, and finesse to do it right. *7.10.1 Latches Although the design of feedback sequential circuits is generally a hard problem, some circuits can be designed pretty easily. Any circuit with one feedback loop t a variation of an S-R or D latch. It has the general structure shown in Figure 7-81 and an excitation equation with the following format: Q* = (forcing term) + (holding term) Q For example, the excitation equations for S-R and D latches are Qe = S+R'-Q Q* = C-D+C'-Q Corresponding circuits are shown in Figure 7-82(a) and (b). Figure 7-81 General structure ofa latch. @) Figure 7-82 . > @ Latch circuits: (@) SR latch; a—f>o (b) unreliable 0 lateh; (0) hazard-free D latch. © Seer ” DSI Hr602 Chapter 7 Sequential Logic Design Principles Figure 7-83 Karnaugh maps for D-latch excitation functions: (a) original, containing a statio-1 hazard; (b) hazard eliminated hazard-free excitation logic —————_zva— PRODUCT-TERM EXPLOSION @ (o) Xrco ot d Gg ca D @ Q@=0-D+C-0 @ =0-D+0"-Q+0-0 In general, the excitation logic in a feedback sequential circuit must be hazard free; we'll demonstrate this fact by way of an example. Figure 7-83(a) is a Kamaugh map for the D-latch excitation circuit of Figure 7-82(b). The map exhibits a static-1 hazard when D and Q are | and C is changing. Unfortunately, the latch’s feedback loop may not hold its value if a hazard-induced glitch occurs, For example, consider what happens when D and Q are | and C changes from 1 to 0; the circuit should latch a 1. However, unless the inverter is very fast, the output of the top AND gate goes to 0 before the output of the bottom one goes to 1, the OR-gate output goes to 0, and the feedback loop stores a0. Hazards can be eliminated using the methods described in Section 4.4. In the D latch, we simply include the consensus term in the excitation equation: Q+ = C-D+C’-Q+D- Figure 7-82(c) shows the corresponding hazard-free, correct D-latch circuit. Now, suppose we need a specialized “D” latch with three data inputs, D1— D8, that stores a 1 only if D1-D3 = 010. We can convert this word description into an excitation equation that mimics the equation for a simple D latch: Q* = C-(D1’-D2-D3)+C’-Q Eliminating hazards, we get Q+ = C-D1’.D2-D3’+C’-Q+D1’-D2-D3"-Q The hazard-free excitation equation can be realized with discrete gates or in a PLD, as we'll show in Section 8.2.6. In some cases, the need to cover hazards can cause an explosion in the number of product terms in a two-level realization of the excitation logic. For example, suppose ‘we need a specialized latch with two control inputs, C1 and C2, and three data inputs as before. The latch is to be “open” only if both control inputs are 1, and is to store a 1 if any data input is 1. The minimal excitation equation is Qs = C1-C2- (D1 +D2+D3) + (C1 -C2)’-a = 01-C2-D1+C1-C2-D2+C1-C2-08+C1’-Q+C2’-a However, it takes six consensus terms to eliminate hazards (see Exercise 7.82).7.10 Feedback Sequential-Circuit Design *7.10.2 Designing Fundamental-Mode Flow Table To design feedback sequential circuits more complex than latches, we must first convert the word description into a flow table. Once we have a flow table, we can turn the crank (with some effort) to obtain a circuit, When we construct the flow table for a feedback sequential circuit, we give each state a meaning in the context of the problem, much as we did in the design of clocked state machines. However, it’s easier to get confused when construct- ing the flow table for a feedback sequential circuit, because not every total state is stable, Therefore, the recommended procedure is to construct a primitive flow table—one that has only one stable total state in each row. Since there is only one stable state per row, the output may be shown as a function of state only. In a primitive flow table, each state has a more precise “meaning” than it might otherwise have, and the table’s structure clearly displays the underlying fundamental-mode assumption: inputs change one at a time, with enough time between changes for the circuit to settle into a new stable state. A primitive flow table usually has extra states, but we can “tur the crank” later to minimize the number of states, once we have a flow table that we believe to be correct. We'll use the following problem, a “pulse-catching” circuit, to demon- strate flow-table design: Design a feedback sequential circuit with two inputs, P (pulse) and R (reset), and a single output Z that is normally 0. The output should be set to | whenever a 0-to-1 transition occurs on P, and should be reset to 0 whenever R is 1. Typical functional behavior is shown in Figure 7-84. Figure 7-85 is a primitive flow table for the pulse catcher, Let’s walk through how this table was developed. We assume that the pulse catcher is initially idle, with P and R both 0; this is the IDLE state, with Z = 0. In this state, if reset occurs (R = 1), we could prob- ably stay in the same state, but since this is supposed to be a primitive flow table, we create a new state, RES1, so as not to have two stable total states in the same row. On the other hand, if a pulse occurs (P = 1) in the IDLE state, we definitely Want to go to a different state, which we've named PLSt, since we've caught a pulse and we must set the output to 1. Input combination 11 is not considered in the IDLE state, because of the fundamental-mode assumption that only one input changes at a time; we assume the circuit always makes it to another stable state before input combination 11 can occur, Figure 7-84 Typical functional behavior of a pulse-catching circuit. 603 primitive flow table Fie seh ioed Hie Ven K ou gy usin mah Aoki Fe eee ae / SY sa RAT oe ee nie i LL604 Chapter7 Sequential Logic Design Principles Figure 7-85 Primitive flow table for pulse-catching circuit. PR Meaning Ss 00 o1 im 10 z Idle, waiting for pulse IDLE. += IDLE) RES = PLsi 0 Reset, no pulse RES1 IDLE RES2 - o Got pulse, outputon -- PLSt-—s PLS2-ss iC Reset, got pulse Res2 — RES1 PLSN 0 Pulse gone, outputon -PLS2_- PLS)_—RESI 0 PLSt 1 Got pulse, output off PLSN IDLE ee RES2 0 s* Next, we fill in the next-state entries for the newly created RES1 state. If reset goes away, we can go back to the IDLE state. If a pulse occurs, we must remain in a “reset” state, since, according to the timing diagram, a 0-to-1 transi- tion that occurs while R is 1 is ignored. Again, to keep the flow table in primitive form, we must create a new state for this case, RES2 Now that we have one stable total state in each column, we may be able to g0 to existing states for more transitions, instead of always defining new states. Sure enough, starting in stable total state PLS 1/10, for R = 1 we can go to RES2, which fits the requirement of producing a 0 output. On the other hand, where should we go for P = 0? IDLE is a stable total state in the 00 column, but it produces the wrong output value. In PLS1, we've gotten a pulse and haven’t seen a reset, so if the pulse goes away, we should go to a state that still has Z = Thus, we must create a new state PLS2 for this case. In RES2, we can safely go to RESt if the pulse goes away. However, we've got to be careful if reset goes away, as shown in the timing diagram. Since we've already passed the pulse’s 0-to-I transition, we can’t go to the PLS1 state, since that would give us a 1 output. Instead, we create a new state PLSN with a 0 output. Finally, we can complete the next-state entries for PLS2 and PLSN without creating any new states. Notice that, starting in PLS2, we bounce back and forth between PLS2 and PLS1 and maintain a continuous | output if we get a series of pulses without an intervening reset input. ‘7.10.3 Flow-Table Minimization As we mentioned earlier, a primitive flow table usually has more states than required. However, there exists a formal procedure, discussed in the References, for minimizing the number of states in a flow table. This procedure is often complicated by the existence of don’t-care entries in the flow table.7.10 Feedback Sequential-Circuit Design PR s 00 01 u 10 Zz IDLE RES PLS PLS IDLE RES Figure 7-86 Reduced flow tabl RES DLE IDLE forpulse-catehing circuit. S Fortunately, our example flow table is small and simple enough to minimize by inspection. States IDLE and RES1 produce the same output, and they have the same next-state entry for input combinations where they are both specified. Therefore, they are compatible and may be replaced by a single state (IDLE) in a reduced flow table. The same can be said for states PLS1 and PLS2 (replaced by PLS) and for RES2 and PLSN (replaced by RES). The resulting reduced flow table, which has only three states, is shown in Figure 7-86. *7.10.4 Race-Free State Assignment The next somewhat creative (read “difficult”) step in feedback sequential circuit design is to find a race-free assignment of coded states to the named states in the reduced flow table. Recall from Section 7.9.3 that a race occurs when multiple internal variables change state as a result of a single input change. A feedback- based sequential circuit must not contain any critical races: otherwise, the circuit may operate unpredictably. As we'll see, eliminating races often necessitates increasing the number of states in the circuit. A circuit's potential for having races in its transition table can be analyzed by means of a state adjacency diagram for its flow table. The adjacency diagram is a simplified state diagram that omits self-loops and does not show the direction of other transitions (A+B is drawn the same as B—+A) or the input combinations that cause them, Figure 7-87 is an example fundamental-mode flow table and Figure 7-88(a) is the corresponding adjacency diagram. za Figure 7-87 s 0 oF 10 Example flow table for - the state-assignment problem, ©QO©® state adjacency diagram 605606 adjacent states @ Chapter 7 Sequential Logic Design Principles ay 2 ® KX oo © of @—®) Figure 7-88 State-assignment example: (a) adjacency diagram; (b) a 2-cube; (0) one of eight possible race-free state assignments. ‘Two states are said to be adjacent if there is an arc between them in the state adjacency diagram. For race-free transitions, adjacent coded states must differ in only one bit. If two states A and B are adjacent, it doesn’t matter whether the original flow table had transitions from A to B, from B to A, or both. Any one of these transitions is a race if A and B differ in more than one variable. That's why we don’t need to show the direction of transitions in an adjacency diagram. ‘The problem of finding a race-free assignment of states to n state variables is equivalent to the problem of mapping the nodes and arcs of the adjacency diagram onto the nodes and arcs of an n-cube. In Figure 7-88, the problem is to ‘map the adjacency diagram (a) ways to do this (four rotations assignment shown in (c). Figure 7-89(a) is an adj onto a 2-cube (b). You can visually identify eight times two flips), one of which produces the state eney diagram for our pulse-catching circuit, based on the reduced flow table in Figure 7-86. Clearly, there’s no way to map this “triangle” of states onto a 2-cube. At this point, we can only go back and modify the original flow table. In particular, the flow table tells us the destina- tion state that we eventually must reach for each transition, but it doesn’t prevent us from going through other states on the way. As shown in Figure 7-90, we can create a new state RESA and make the transition from PLS to RES by going through RESA. The modified state table has the new adjacency diagram shown Figure 7-89 Adjacency diagrams for the pulse catcher: (a) using original flow table; (b) after adding a state; (c) showing one of eight possible race-tree state IDLE ) PLS assignments DE FES 00 10 © PLS FESR =)7.10 Feedback Sequential-Circuit Design 607 PR Ss 00. on u 10 Zz IDLE RES PLS PLS IDLE —-RESA 1 RESA — - RES = RES IDLE — IDLE. 0 S* in Figure 7-89(b), which has many race-free assignments possible, A transition table based on the assignment in (c) is shown in Figure 7-92. Note that the PLS—>RESA—RES transition will be slower than the other transitions in the original flow table because it requires two internal state changes, with two propagation delays through the feedback loops Even though we added a state in the previous example, we still got by with just two state variables. However, we may sometimes have to add one or more state variables to make a race-free assignment. Figure 7-91(a) shows the worst possible adjacency diagram for four states—every state is adjacent to every other state. Clearly, this adjacency diagram cannot be mapped onto a 2-cube. However, there is a race-free assignment of states to a 3-cube, shown in (b), where each state in the original flow table is represented by two equivalent states in the final state table. Both states in a pair, such as A1 and A2, are equivalent and produce the same output. Each state is adjacent to one of the states in every other pair, so a race-free transition may be selected for each next-state entry. Foss G)-@) @ LX] © CO @-@ ee 100 Figure 7-90 State table allowing a race-free assignment for the pulse-catching circuit Figure 7-91 A worst-case scenario: (a) four-state adjacency diagram; (b) assignment using pairs of equivalent states. HANDLING In the general case of a flow table with 2" rows, it can be shown that a race-free THE GENERAL assignment can be obtained using 2n— 1 state variables (see References). However, | ASSIGNMENT there aren’t many applications for fundamental-mode circuits with more than a few CASE states, so the general case is of little more than academic interest.608 Chapter 7 Sequential Logic Design Principles yiy2 oO ol 1 2Z o @M @M wow a o 0 @ » u @ Figure 7-92 W i — 10 — - Race-free transition table for the pulse- 0 o » @ 9 catching circu. Yin Ye" *7.10.5 Excitation Equations Once we have a race-free transition table for a circuit, we can just “turn the crank” to obtain excitation equations for the feedback loops. Figure 7-92 is the pulse catcher’s transition table. Its “don’t-care” next-state and output entries can be used in the corresponding Karnaugh maps to simplify the circuit's excitation and output logic. Since the excitation logic in a feedback sequential circuit must be hazard free, it might be necessary to add product terms to eliminate hazards. Detailed derivation of the excitation equations is left as an exercise (7.84), but the resulting circuit will be shown later, in Figure 7-94 on page 610. *7.10.6 Essential Hazards After all this effort, you'd think that we'd have a pulse catcher that works reli- ably all of the time. Unfortunately, we're not quite there yet. A fundamental- mode circuit must generally satisfy five requirements for proper operation: 1. Only one input signal may change at a time, with a minimum bound between successive input changes. There must be a maximum propagation delay through the excitation logic and feedback paths; this maximum must be less than the time between successive input changes. The state assignment (transition table) must be free of critical races. The excitation logic must be hazard free. The minimum propagation delay through the excitation logic and feedback paths must be greater than the maximum timing skew through the “input logic.” Without the first requirement, it would be impossible to satisfy the major premise of fundamental-mode operation—that the circuit has time to settle into a stable total state between successive input changes. The second requirement says that the excitation logic is fast enough to do just that. The third ensures that7.10 Feedback Sequential-Circuit Design Figure 7-93 Transition table forthe pulse-catching circuit, exhibiting an essential hazard. the proper state changes are made, even if the excitation circuits for different state variables have different delays. The fourth ensures that state variables that aren't supposed to change on a particular transition don’. The last requirement deals with subtle timing-dependent errors that can occur in fundamental-mode circuits, even ones that satisfy the first four requirements. An essential hazard is the possibility of a circuit's going to an erroneous next state as the result of a single input change; the error occurs if the input change is not seen by all of the excitation circuits before the resulting state~ variable transition(s) propagate back to the inputs of the excitation circuits. Ina world where “faster is better” is the usual rule, a designer may sometimes have to slow down excitation logic to mask these hazards. Essential hazards can be found in most but not all fundamental-mode circuits. There’s an easy rule for detecting them; in fact, this is the definition of “essential hazard” in some texts: + A fundamental-mode flow table contains an essential hazard for a stable total state S and an input variable X if, starting in state S, the stable total state reached after three successive transitions in X is different from the stable total state reached after one transition in X. ‘The pulse catcher’s transition table is repeated in Figure 7-93, this time showing arrows for the transitions that prove the existence of the essential hazard, starting in internal state 10 with P R= 10. The pulse catcher’s essential hazard can be seen in its realization, shown in Figure 7-94 on the next page. Suppose we built this circuit on a PCB or a chip, and we (or, more likely, our CAD system) inadvertently connected input signal P through a long, slow path. Let's assume that this delay is longer than the prop- agation delay of the AND-OR excitation logic. Now consider what can happen if P R = 10, the circuit is in internal state 10, and P changes from 1 to 0. According to the transition table in Figure 7-93, the circuit should go to internal state 00, and thats that. But let's look at the actual operation of the circuit, as traced in Figure 7-94: essential hazard 609610 Chapter? Sequential Logic Design Principles pte aut along, siow path iso 0 Y2 ost 191 Figure 7-94 Physical conditions in pulse-catching circuit for exhibiting an essential hazard. timing skew + (Changes shown with “->”) The first thing that happens after P changes is that Y1 changes from 1 to 0. Now the circuit is in internal state 00. + (Changes shown with “”) Y1_L changes from 0 to 1. The change in Y1_Lat AND gate A causes its output to go to 1, which in turn forces Y2 to 1. Whoops, now the circuit is in internal state 01. + (Changes shown with “=>”) The change in Y2 at AND gates B and C causes their outputs to go to 1, reinforcing the 1 output at Y2. All this time, we've been waiting for the 1-to-0 change in P to appear at point PD. + (Changes shown with “=") Finally, PD changes from | to 0, forcing the outputs of AND gates A and B to 0. However, AND gate C still has a 1 output, and the circuit remains in state 01—the wrong state. The only way to avoid this erroneous behavior in general is to ensure that changes in P arrive at the inputs of all the excitation circuits before any changes in state variables do. Thus, the inevitable difference in input arrival times, called timing skew, must be less than the propagation delay of the excitation circuits and feedback loops. This timing requirement can generally be satisfied only by careful design at the electrical circuit level. In the example circuit, it would appear that the hazard is easily masked, even by non-electrical engineers, since the designer need only ensure that a straight wire has shorter propagation delay than an AND-OR structure—easy in most technologies: Still, many feedback sequential circuits, such as the TTL edge-triggered D flip-flop in Figure 7-19, have essential hazards in which the input skew paths include inverters. In such cases, the input inverters must be guaranteed to be faster than the excitation logic; that’s not so trivial in either board-level or IC7.10 Feedback Sequential-Circuit Design 611 design, For example, if the excitation circuit in Figure 7-94 were physically built using AND-OR-INVERT gates, the delay from input changes to Y1_L could be very short indeed, as short as the delay through a single inverter. A fundamental-mode circuit must have at least three states to have an essential hazard, so latches don’t have them. On the other hand, all flip-flops (circuits that sample inputs on a clock edge) do. THESE HAZARDS | Essential hazards are called “essential” because they are inherent in the flow table for ARE, WELL, a particular sequential function and will appear in any circuit realization of that ESSENTIAL! function. They can be masked only by controlling the delays in the circuit. Compare with static hazards in combinational logic, where we could eliminate hazards by adding consensus terms to a logic expression. “7.10.7 Summary In summary, you use the following steps to design a feedback sequential circuit: Construct a primitive flow table from the circuit’s word description. primitive flow table Minimize the number of states in the flow table. state minimization Find a race-free assignment of coded states to named states, adding auxil- stare assignment iary states or splitting states as required. 4. Construct the transition table. transition table Construct excitation maps and find a hazard-free realization of the exeita- excitation maps tion equations and equations 6. Check for essential hazards. Modify the circuit if necessary to ensure that essential hazards minimum excitation and feedback delays are greater than maximum inverter or other input-logic delays 7. Draw the logic diagram, logic diagram Also note that some circuits routinely violate the basic fundamental-mode assumption that inputs change one at a time. For example, in a positive-edge- triggered D flip-flop, the D input may change at the same time that CLK changes from | to 0, and the flip-flop still operates properly. The same thing certainly cannot be said at the 0-to-1 transition of CLK. Such situations require analysis of the transition table and circuit on a case-by-case basis if proper operation in “special cases” is to be guaranteed. AFINAL Given the difficulty of designing fundamental-mode circuits that work properly, let QUESTION alone ones that are fast or compact, how did anyone ever come up with the 6-gate, 8-state, 74LS74 D flip-flop design in Figure 7-20? Don’t ask me, I don’t know!