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Vivado Verilog Tutorial

This tutorial provides a step-by-step guide for using the Vivado design environment to create a Verilog project, including adding source files and running simulations. It outlines the process of setting up a new project, implementing a Verilog module, and creating a testbench for behavioral simulation. The tutorial emphasizes the importance of verifying the design's functionality through simulation outputs.

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starlionjiang
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5 views

Vivado Verilog Tutorial

This tutorial provides a step-by-step guide for using the Vivado design environment to create a Verilog project, including adding source files and running simulations. It outlines the process of setting up a new project, implementing a Verilog module, and creating a testbench for behavioral simulation. The tutorial emphasizes the importance of verifying the design's functionality through simulation outputs.

Uploaded by

starlionjiang
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Vivado Verilog Tutorial

This tutorial will give a step-by-step walk through of the Vivado design environment.
This tutorial demonstrates how to create a Verilog project, add Verilog source files and
test the design via simulation.
Step 1: Creating a new project

1. In a terminal run the following commands to setup and launch Vivado:

> source /ad/eng/opt/xilinx/Vivado/2019.1/settings64.sh


> vivado

You should get the following result:


****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
start_gui

2. Click Create Project, and then click Next.


3. Give your new project a name and location to save, and click Next.
4. Choose RTL Project and select the “Do not specifiy sources at this time” check box.
Click Next.
5. Since all the labs for this course only use simulation, the FPGA selected does not
matter. You can skip the “Add sources” and “Add constraints” windows by clicking
‘Next’.
Click Next and Finish.
Step 2: Verilog gate-level implementation

We will implement the circuit shown below.

1. Create a Verilog module.

Select Project Manager in the Flow Navigator, click on Add Sources.


Select “Add or create design sources”, and click Next.

Click on “Create File”:


File type: Verilog
File name: tutorial (or any name you choose)
File location: <Local to Project>

Click OK, then Finish.

In the ‘Define Module’ Window specify A, B, and C as inputs, and D and E as outputs
and click OK.
Double click on the newly created file under the Design Sources folder:
This will open the file for editing. Now edit the file to contain the following:

2. Add a testbench.
Under Project Manager in the Flow Navigator, click on Add Sources.
Select ‘Add or create simulation sources’.
Select ‘Create Files’:
File type: Verilog
File name: tutorial_testbench (or any name you choose)
File location: <Local to Project>
Click OK, then Finish.
Click OK in the ‘Define Module’ Window.
4. Double click on the newly created file under the Simulation Sources folder in the
Sources tab:

This will open the file for editing. Now edit the file to contain the following:
Step 3: Behavioral Simulation

1. Select ‘Settings’ under the ‘Project Manager’ tasks of the ‘Flow Navigator’ pane. A
Project Settings form will appear showing the Simulation properties form.
2. Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click
OK.

3. Click on Run Simulation > Run Behavioral Simulation under the Flow Navigator pane.
The testbench and source files will be compiled and the XSim simulator will be run
(assuming no errors). You will see a simulator output similar to the one shown below.
Note that you may need to scroll and/or zoom out in order to see the full simulation.

Make sure that you understand how the waveform reflects the testbench, and that it
clearly shows that the provided design functions correctly. It is a good practice to test
the output for all the possible combinations of input (whenever possible).

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