Computer

Organization and
Design (COD)

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 Computer Organization and Design
U-1: Overview of Digital Seq. Cir. and Implementation (4 Hrs.)
U-2: Introduction to Computer Organization (8 Hrs.)
U-3: Instruction Set Architecture and Assembly Language Prog. (8 Hrs.)
U-4: Basics of Memory Organization and Pipelining (6 Hrs.)

Dr. Manoj Yadav, Assistant Professor

Department of ICT, PDEU Gandhinagar

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Details about lectures and contact
Office location: F-105,
Email: [email protected]
Office-time: 9am-5:30pm

Class timing and Venue:

§ ICT (4) – H4, H5, H6.
§ Lectures – 2 hrs/week,
§ Venue – E201 (Mon), E202 (Wed).
§ Timings: 1. Mon : 12:00 – 1:00pm; 2. Wed: 2:00-3:00pm

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Textbooks

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Course Objectives
and Outcomes

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 Course Objectives and Outcomes
COURSE OBJECTIVES:
• Understand the functional organization and integration of the
building blocks (Memory, Registers, ALU, Control, I/O, etc.) of
the micro-computer architecture
• Develop an Instruction Set Architecture
• Learn assembly language programming
COURSE OUTCOMES:
• Describe the building blocks of the micro-computer, such as: the ALU, registers,
control unit, memory and I/O unit.
• Identify the basics aspects of pipelining and memory organization.
• Organize the blocks of the micro-computer and create a basic functional architecture.
• Write simple programs in assembly language, utilizing the instruction set architecture.
• Apply the knowledge of digital logic, to implement some of the building blocks of the
micro-computer, especially, control unit, ALU, registers, PC, timing pulse generator.
• Design a processor or micro-computer, based on simple instruction set.

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 Course Outcome:

CO1: Remember the building CO2: Understand the working

blocks of Computer principle of ALU, and Control
organization. Unit.

CO3: Apply the instruction set CO4: Analyse the working and
to make assembly language performance of control unit and
program. memory systems.

CO5: Evaluate the performance

CO6: Design a processor or
of microprocessor
microcomputer based on
programming using assembly
simple instruction set.
language programs.

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Grading Policy

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 Grading Policy
Exam Divisions Marks (%)
Mid-semester 25
External exam Examination
End-semester 50
Examination
Attendance 5

Internal exam Quiz 10

Term-project/viva 10

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 Syllabus
Unit – 1 Topics References
Review of digital logic circuits: Tri-state based multiplexing for bus; 4.3: computer
systems
architecture, by
MM Mano
Sequential circuits (counters and registers) and Moore Finite State 6.1-4: digital
Machines (FSM): Various methods of implementation of FSM: design 5th ed by
implementation based on Decoders and OR gates, M. Morris
implementation based on two-level Multiplexers, Mano

https://slideplayer.com/slide/3254624/
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Block Diagram of Computer

Further reading:
https://www.eetimes.com/will-storage-class-memory-disrupt-memory-hierarchy/

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Inside a Computer System

o A Computer system is composed of several components. Some of the more common components are
the motherboard, processor, memory and hard drive.
o All components of a computer system are contained in the computer case.

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Computer System Bus
o The computer system bus is the method by which data is communicated between all the
internal pieces of a computer.
o It connects the processor to the RAM, to the hard drive, to the video processor, to the I/O
drives, and to all the other components of the computer.

o Types of buses:
i. Control bus – is
used to control
the functional
units
ii. Address bus – is
used to transfer
the address of the
data
iii. D a t a b u s – i s
used to transfer
data to and from
memory.

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 CPU Architecture and common Bus
Ø A typical digital computer has many registers, and paths must be provided to transfer
information from one register to another.
Ø The number of wires will be excessive if separate lines are used between each register and all
other registers in the system.
Ø A more efficient scheme for transferring information between registers in a multiple-register
configuration is a common bus system.
Ø A bus structure consists of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time.
Ø Control signals determine which register is selected by the bus during each register transfer.

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CPU Architecture and common Bus

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Bus Design

Bus may be designed using—

1. Mux
2. Tristate buffer

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Bus line using MUX

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Using MUX: 4 register with 4 bits each

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Using MUX: 4 register with 4 bits each

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If we have k registers each of n bits
Size of MUX: kX1

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Bus line using MUX

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Tri-state Bus Buffer

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Tri-state Bus Buffer

o Summary of tri-state bus buffer

o It only works when enable is ON.
o Buffer means output is same as input logic.

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Bus line using Decoder

o Realization of one-bit bus line using four tri-state buffers.

o Use of decoder ensures that only one tri-state buffer is active at one time.
o This is another way of constructing a 4*1 Mux since this circuit can replace the
MUX from previous case of circuit using MUX.

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 Bus Implementation Using tri-state
buffer

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 Sequential Circuits

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 Sequential Circuits
• Combinational Logic:
– Output depends only on current input
– Able to perform useful operations
(add/subtract/multiply/…)
– Has no memory

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 Sequential Circuits (cont.)
• Sequential Logic:
– Output depends not only on current input but
also on past input values, e.g., design a counter
– Need some type of memory to remember the
past input values

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 Sequential Circuits (cont.)
Circuits that we Information Storing
have learned Circuits
so far

Timed “States”
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 Sequential Logic: Concept
• Sequential Logic circuits remember past inputs
and past circuit state.
• Outputs from the system are
“fed back” as new inputs
– With gate delay and wire delay
• The storage elements are circuits that are
capable of storing binary information:
memory.

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 Synchronous vs. Asynchronous

There are two types of sequential circuits:

• Synchronous sequential circuit: circuit output
changes only at some discrete instants of time. This
type of circuits achieves synchronization by using a
timing signal called the common clock.
• Asynchronous sequential circuit: circuit output can
change at any time (clock-less).

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 Clock Signal

Clock generator: Periodic train of clock pulses

Different duty cycles

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 Synchronous Sequential Circuits:
Flip flops as state memory

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 Sequential Circuit Analysis
• Analysis: Consists of obtaining a suitable description that
demonstrates the time sequence of inputs, outputs, and
states.
• Logic diagram: Boolean gates, flip-flops (of any kind), and
appropriate interconnections.
• The logic diagram is derived from any of the following:
– State equations (Boolean Equations) (FF-Inputs, Outputs)
– State Table
– State Diagram

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 Flip-flops – Basically 4 types

S-R F/F J-K F/F

D F/F T F/F

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 Characteristic Table of flip flops
• Describes output for a given input of flip flop.
• Useful for analysis and for defining the operation of
f/f
J K Q(t+1) Comment
0 0 Q(t) No change
0 1 0 Reset J-K
1 0 1 Set
Flip
1 1 Q’(t) Compliment
Flop

S R Q(t+1) Comment
0 0 Q(t) No change R-S
0 1 0 Reset Flip
1 0 1 Set Flop
1 1 ? Unpredictable
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Manoj Yadav 1/28/2025 37
 Excitation Table
• This lists the required input for the given
transition of output state.

Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X J-K
1 0 X 1 Flip
1 1 X 0 Flop

Q(t) Q(t+1) S R
0 0 0 X R-S
0 1 1 X Flip
1 0 0 1 Flop
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Difference between Mealy Machine and Moore Machine.
Mealy Machine Moore Machine
Output depends both upon the Output depends only upon the
present state and the present input present state.

Generally, it has fewer states than Generally, it has more states than
Moore Machine. Mealy Machine.
The value of the output function is a The value of the output function is a
function of the transitions and the function of the current state and the
changes, when the input logic on the changes at the clock edges,
present state is done. whenever state changes occur.

Mealy machines react faster to inputs. In Moore machines, more logic is

They generally react in the same clock required to decode the outputs
cycle. resulting in more circuit delays. They
generally react one clock cycle later.

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 State equations

• Input: x(t)
x
• Output: y(t) D Q A

• State: (A(t), B(t)) C Q A

• What is the Output

Function?
D Q B

• What is the Next State CP C Q

Function?
y

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 Example (continued)
• Boolean equations
for the functions: x
D Q A
– A(t+1) = A(t)x(t) +
C Q A’
B(t)x(t) Next State

– B(t+1) = A’(t)x(t)
– y(t) = x’(t)(B(t) + A(t)) D Q B

– These may be reduced CP C Q'

using K-map
y

Output

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 State Table
• State table – a multiple variable table with the following
four sections:
– Present State – the values of the state variables for each allowed
state.
– Input – the input combinations allowed.
– Next-state – the value of the state at time (t+1) based on the
present state and the input.
– Output – the value of the output as a function of the present state
and (sometimes) the input.
• From the viewpoint of a truth table:
– the inputs are Clock and Input.. Output: Next State
• From the viewpoint of a Characteristic table:
– the inputs are Present State, Input and the output: Next State
• From the viewpoint of a Excitation table:
– the inputs are Present State, Next State and outputs: Inputs

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 Example : State Table
The state table can be filled in using the next state and
output equations:
– A(t+1) = A(t)x(t) + B(t)x(t)
– B(t+1) =A (t)x(t);
– y(t) =x (t)(A(t) + B(t))

Present state Next state Output

X=0 X=1 X=0 X=1
AB A(t+1)B(t+1) A(t+1)B(t+1) Y Y
00 00 01 0 0
01 00 11 1 0
10 00 10 1 0
11 00 10 1 0
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Manoj Yadav
 State Diagram
• The sequential circuit function can be represented in graphical
form as a state diagram with the following components:
– A circle with the state name in it for each state
– A directed arc from the Present State to the Next State for each state
transition
– A label on each directed arc with the Input values which causes the
state transition, and
– A label:
• On each circle with the output value produced, or
• On each directed arc with the output value produced.

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 Example: State Diagram
x=0/y=0 x=0/y=1 x=1/y=0
• Which type?
• Diagram gets A B
confusing for 0 0 x=0/y=11 0
large circuits x=1/y=0
• For small circuits, x=1/y=0
usually easier to x=0/y=1
understand than
the state table
0 1 1 1
• Pictorial view of state
x=1/y=0
transitions
• Used as initial design
specifications for a
sequential circuits.
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 State reduction
• Reducing the no. of f/f in circuit is known as state
reduction
• Cost # of states
• In switching theory various algorithms are
designed to reduce the # of states in design.
• m flip flops produce 2m states.
• State reduction may or may not produce
reduction in no of gates.
• Sometimes it may increase no. of gates.

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 Example

Input/output

Suppose input sequence is

0101010110100

At state a if applied i/p is 0 out will be 0 and system will go to next state a.
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 Obtain state table from state diagram

Two states are said to be equivalent if for each member

of the set of inputs they give exactly the same output and
send the circuit either to the same state or to an
equivalent state. One of them can be removed
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• Look for the two present states that go to the same
next state and have the same output for both input
combination.
• (similar rows except present state columns)
• Row for e and g are same hence equivalent states
one of them may be removed.

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 Modify the state table
• Remove last row and Replace state g by e at all
place.
• Look for new equivalency of states in a similar
fashion.
• States d and f become equivalent now
• Repeat the procedure till possible.

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 We can verify this by taking same sequence of input and we
observe that the same out comes—
State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output0 0 0 0 0 1 1 0 1 0 0

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 Reduced state diagram

•State reduction is possible only if input and out put relationship

is concerned.
•Output must be independent of number of states

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 State Assignment
• Size of combinational circuit associated with the
design may be reduced by using K-map or other
techniques.
• This may further be reduced by proper state
assignment.
• Assigning binary value to states is known as state
assignment.
• Minimization not applicable to circuit whose
external output are taken directly from f/f (circuit
viewed as external input output terminals).
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• Sequence of state is immaterial as long as
their input and output relationships are
maintained.
• Any binary number assignment is satisfactory
as long as states are unique.

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 State table with binary state
assignment1

The combinational circuit obtained depends upon

the binary state assignment
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chosen 57
 Optimal state assignment
• The most common criterion is that the chosen
assignment should result in a simple
combinational circuit.
• No state assignment procedure to guarantee
minimal-cost combinational circuit.

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 Q(t) Q(t+1) D
0 0 0 D Flip
0 1 1 Flop
1 0 0
1 1 1

Q(t) Q(t+1) T
0 0 0 T Flip
0 1 1 Flop
1 0 1
1 1 0

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 Design procedure of synchronous
Sequential Circuit

m f/f for upto 2m states

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 Example:
• Design a Mealy FSM
(sequential circuit)
that detects 3 (or
more) consecutive
1’s in the data stream.

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 Constructing state table
vDescription:
–  reset state(S0) : (initial state of machine)
– From S0 to S1 if input is 1, otherwise S0
– From state S1 to S2 if input is 1, otherwise S0
– From S2 to S3 if input is 1, otherwise S0
– From S3 to S3 if input is 1, otherwise S0

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 State diagram

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 State assignment

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 State table

Q’A=Ɛ (3, 5, 7); Q’B=Ɛ (1, 5, 7); y=Ɛ (5, 7)

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 Use D-FF for design and K-map

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 Circuit design

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 Moore FSM

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 Example:
• Design a Moore FSM
(sequential circuit)
that detects 3 (or
more) consecutive
1’s in the data stream.

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 Constructing state table
vDescription:
–  reset state(S0) : (initial state of machine)
– From S0 to S1 if input is 1, otherwise S0
– From state S1 to S2 if input is 1, otherwise S0
– From S2 to S3 if input is 1, otherwise S0
– From S3 to S3 if input is 1, otherwise S0

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Step1: Obtaining the State Diagram

•A very important step in the

design procedure.
•Requires experience!

•Example: Design a circuit that

detects a sequence of three
consecutive 1’s in a string of bits
coming through an input line (serial
bit stream)

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 Step2: Obtaining the State Table

•Assign binary codes for the states

•We choose 2 D-FF
•Next state specifies what should be
the input to each FF

•Example: Design a circuit that

detects a sequence of three
consecutive 1’s in a string of bits
coming through an input line (serial
bit stream)

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 Step3: Obtaining the State Equations

•Using K-Maps
•A(t + 1) = DA = ∑(3,5,7) = A x + B x
•B(t + 1) = DB = ∑(1,5,7) = A x + B’ x
•y = ∑(6,7) = A B

•Example: Design a circuit that

detects a sequence of three
consecutive 1’s in a string of bits
coming through an input line (serial
bit stream)

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 Step4: Draw Circuits

•Using K-Maps
•A(t + 1) = DA = ∑(3,5,7) = A x + B x
•B(t + 1) = DB = ∑(1,5,7) = A x + B’ x
•y = ∑(6,7) = A B

•Example: Design a circuit that

detects a sequence of three
consecutive 1’s in a string of bits
coming through an input line (serial
bit stream)

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 Timing Diagram (Verification)

• Question: Does it detect 111 ?

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 MUX/Decoder MUX/Decoder
FFs

FSM DESIGN
FSM
using
Design
MUX or
using MUX
Decoder

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Circuit design – We did in the last lecture

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 State table

Q’A=Ɛ (3, 5, 7); Q’B=Ɛ (1, 5, 7); y=Ɛ (5, 7)

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 Use D-FF for design and K-map

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Input DA implementation using MUX

0 I0 I1 I2 I3
1
X’ 0 2 4 6
2

3 X 1 3 5 7

4 0 X X X
5

I3=X
DA = X. (QA.QB + QA. QB’ + QA’. QB)
I2=X DA DA = X. (QA + QA’.QB)
I1=X
DA = X. (QA + QA’) . (QA + QB)
I0=0 DA = X. (QA + QB)

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QA QB
Input DB implementation using MUX

0 I0 I1 I2 I3
1
2
X’ 0 2 4 6

3 X 1 3 5 7
4
5
X 0 X X
6
7

I3=X
I2=X
DB DB = X. (QA.QB + QA. QB’ + QA’. QB’)
I1=0
DB = X. (QA.QB + QB’)
I0=X DB = X. (QA + QB’) . (QB + QB’)
DB = X. (QA + QB’)

QA QB
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 MUX – FF/Register – MUX
I3=X
I2=X DA QA
I1=X 0
I0=0 QA Y = X.QA

X
QA QB

I3=X
I2=X DB QB
I1=0
I0=X

QA QB
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 Decoder – FF/Register – Decoder
QA
QB DA QA
X
QA

X
Y = X.QA

QA
QB DB QB
X

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 MUX – FF/Register – Decoder
I3=X
I2=X DA QA
I1=X
I0=0 QA

X
Y = X.QA
QA QB

I3=X
I2=X DB QB
I1=0
I0=X

QA QB

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Other example: FSM Implementation using MUX

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Programmable Logic Array

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• Main difference between PLA, PAL and ROM is
their basic structure. In PLA, programmable
AND gate is followed by programmable OR
gate.
• In PAL, programmable AND gate is followed by
fixed OR gate.
• In ROM, fixed AND gate array is followed by
programmable OR gate array.

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Device AND Array OR Array Comment
PLA Programmable Programmable Complex but flexible
PAL Programmable Fixed Easier to use not flexible
ROM Fixed Fixed Only as memory

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 Example 2
• Problem: Design of A Sequence Recognizer
• Design a circuit that reads as inputs continuous bits, and
generates an output of ‘1’ if the sequence (1011) is
detected

X Y

Input 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1
Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0

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 Example 2 (cont.)

• Step1: State Diagram

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Sequence to be detected:1011 93
 Example 2 (cont.)

• Step 2: State Table

OR

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 Example 2 (cont.)

• Step 2: State Table Q: How many FF?

• state assignment log2(no. of states)

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 Example 2 (cont.)

• Step 2: State Table

• choose FF
• In this example, lets use JK–FF for
A and D-FF for B

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 Example 2 (cont.)

• Step 2: State Table D–FF excitation table

• complete state table
• use excitation tables for JK–FF and
D-FF
Next
State
output
JK–FF excitation table

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 Example 2 (cont.)

• Step 3: State Equations

• use k-map

• JA = BX’
• KA = BX + B’X’
• DB = X
• Y = ABX’

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 Example 2 (cont.)

• Step 4: Draw Circuit

•

• JA = BX’
• KA = BX + B’X’
• DB = X
• Y = ABX’

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 Example 3
Problem: Design of A 3-bit Counter
Design a circuit that counts in binary form as follows 000,
001, 010, … 111, 000, 001, …

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 Example 3 (cont.)

• Step1: State Diagram

- The outputs = the states

- Where is the input?
- What is the type of this
sequential circuit?

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 Example 3 (cont.)

• Step2: State Table

• No need for state assignment

here

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 Example 3 (cont.)

• Step2: State Table T–FF excitation table

• We choose T-FF

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 Example 3 (cont.)

• Step3: State Equations

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 Example 3 (cont.)

• Step4: Draw Circuit

• TA0 = 1
• TA1 = A0
• TA2 = A1A0

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 Example 4

• Problem: Design a traffic light controller for a 2-way

intersection. In each way, there is a sensor and a light
N

Traffic Action
EW only EW Signal green
NS Signal red
NS only NS Signal green
W E
EW Signal red
EW & NS Alternate
No traffic Previous state

S
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 Example 4 (cont.)

• Step1: State Diagram

11, 10

00, 01 00, 10
NS / 01 EW / 10

11, 01

INPUTS OUTPUTS
STATES
• Sensors X1, X0 • Light S1, S0
• NS: NS is green X0: car coming on NS S0 : NS is green
• EW: EW is green X1 : car coming on EW S1 : EW is green

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 Example 4 (cont.)
• Exercise: Complete the design using:
• D-FF
• JK-FF
• T-FF

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 Example 5
• Problem: Design Up/Down counter with Enable
• Design a sequential circuit with two JK flip-flops A
and B and two inputs X and E. If E = 0, the circuit
remains in the same state, regardless of the input
X. When E = 1 and X = 1, the circuit goes through
the state transitions from 00 to 01 to 10 to 11,
back to 00, and then repeats. When E = 1 and X =
0, the circuit goes through the state transitions
from 00 to 11 to 10 to 01, back to 00 and then
repeats.
•

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 Example 5 (cont.)
Present Inputs Next FF Inputs
State State
A B E X A B JA KA JB KB
00 10 00 0 0 0 0 0 0 0 X 0 X
01 01 0 0 0 1 0 0 0 X 0 X
00 01 0 0 1 0 1 1 1 X 1 X
11
0 0 1 1 0 1 0 X 1 X
0 1 0 0 0 1 0 X X 0
10 11 11 10 0 1 0 1 0 1 0 X X 0
0 1 1 0 0 0 0 X X 1
11 0 1 1 1 1 0 1 X X 1
11 10 1 0 0 0 1 0 X 0 0 X
00 00
01 01 1 0 0 1 1 0 X 0 0 X
10 1 0 1 0 0 1 X 1 1 X
1 0 1 1 1 1 X 0 1 X
1 1 0 0 1 1 X 0 X 0
1 1 0 1 1 1 X 0 X 0
1 1 1 0 1 0 X 0 X 1
1 1 1 1 0 0 X 1 X 1
1/28/2025 Manoj Yadav PJF - 110
 Example 5 (cont.)

E
EX 00 01 11 10 EX 00 01 11 10
AB AB X
00 0 0 0 1 00 x x x x
Y
01 0 0 1 0 01 x x x x
11 x x x x 11 0 0 1 0
JA A
10 x x x x 10 0 0 0 1
C
JA = BEX + B’EX’ KA = BEX + B’EX’ KA A’

EX 00 01 11 10 EX 00 01 11 10 JB B
AB AB
C
00 0 0 1 1 00 x x x x
KB B’
01 x x x x 01 0 0 1 1
11 x x x x 11 0 0 1 1 clock
10 0 0 1 1 10 x x x X

JB = E KB = E
1/28/2025 Manoj Yadav PJF - 111
 More Design Examples

1/28/2025 Manoj Yadav 112

 Summary
• To design a synchronous sequential circuit:
• Obtain a state diagram
• State reduction if necessary
• Obtain State Table
• State Assignment
• Choose type of flip-flops
• Use FF’s excitation table to complete the table
• Derive state equations
• Use K-Maps
• Obtain the FF input equations and the output equations
• Draw the circuit diagram

1/28/2025 Manoj Yadav 113

 0
State S0: zero 1s detected
State S1: one 1 detected
State S2: two 1s detected
State S3: three 1s detected

● Note that each state has 2 output arrows

● Two bits needed to encode state

1/28/2025 Manoj Yadav 114 / 17

● Sequence of inputs, outputs, and flip flop Present Next
State Input
states in state table State Output

● Present state indicates current value of A B x A B y

flip flops 0 0 0 0 0 0
● Next state indicates state after next rising 0 0 1 0 1 0
clock edge 0 1 0 0 0 0
0 1 1 1 0 0
● Output is current output value 1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

S0 = 00 S2 = 10
S1 = 01 S3 = 11

1/28/2025 Manoj Yadav 115 / 17

● Create K-map directly from state table (3 columns = 3 K-maps)
● Minimize K-maps to find SOP representations
● Separate circuit for each next state and output value

1/28/2025 Manoj Yadav PJF - 116

● Note location of state flip
flops
● Output value (y) is function
of state
● This is a Moore machine

1/28/2025 Manoj Yadav PJF - 117

 Detect 111 or 00 in input string
in Mealy machine

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1/28/2025 Manoj Yadav 119
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1/28/2025 Manoj Yadav 121
Example... There are 4 states
( 2 bit for each let A & B)
state assignment done.
1 input (let x)
No output (f/f states may
be taken as out put)
Step 1: formation of
diagram already given
Step 2: Obtain State
Table

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• State reduction  not possible (due to output
directly taken from f/f and no two rows of
state table are identical)
• state assignment not required
• No of flip flops for 4 states 2 f/f will be
required
• Type of f/f not mentioned in problem let us
take J-K f/f ( most versatile)

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• Obtain Circuit excitation table

1/28/2025 Manoj Yadav 124

 Expected digital circuit

1/28/2025 Manoj Yadav 125

• Simplify for each f/f input variable using K-
map.
Take A, B & x Take A, B &
as input and x as input
JA as output and KA as
output

Take A, B & Take A, B &

x as input x as input
and JB as and KB as
output output
1/28/2025 Manoj Yadav 126
 Boolean function for each variable...
• JA=Bx’ (J input of f/f A)
• KA=Bx (K input of f/f A)
• JB=x (J input of f/f B)
• KB=Ax+A’x’
• =A(X-NOR)x (K input of f/f B)

1/28/2025 Manoj Yadav 127

 Final circuit

1/28/2025 Manoj Yadav 128

 Practice

1/28/2025 Manoj Yadav 129

 State table

Present state Input x Input y Output S Output next

Q(t) state Q(t+1)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 State diagram

1/28/2025 Manoj Yadav 131

 Example2

1/28/2025 Manoj Yadav 132

 State Table
There is no external input nor output so present state is taken as
only input and next state as only output

Present state Present state Output next Output next

A(t) B(t) state Q(t+1) state Q(t+1)
0 0 0 1
0 1 1 0
1 0 0 0
1 1 0 0
Input to T-f/f A TA=A+B  next state toggles if TA is 1
A(t+1)=A’(A+B)+A(A+B)’=A’B=>(next state is A’ if (A+B ) is 1 otherwise
unchanged)

Input to T-f/f B TB=A’+B  next state toggles if TB is 1

B(t+1)=B’(A’+B)+B(A’+B)’=A’B’
1/28/2025 Manoj Yadav 133
 State diagram

11
00
• It is modulo 3
binary counter
• Counts as
0120
01
• If started from 11
10
resets
automatically to
1/28/2025 Manoj Yadav 00 134
 Practice problems

1/28/2025 Manoj Yadav 135

1/28/2025 Manoj Yadav 136
1/28/2025 Manoj Yadav 137
 Registers
• A register is a group of binary cells suitable for
holding information.
• Group of flip flops constitute register
• To perform loading (writing) and reading
additional circuit may be required.
• Contains information
• n f/f for n-bit information
• All f/f share the same clock pulse
1/28/2025 Manoj Yadav 138
 Counter
• It is register that goes through a
predetermined sequence of states upon
application of clock pulse.
• Special type of registers
• E.g. decade counter: 0 12….890

1/28/2025 Manoj Yadav 139

 Memory cells
• Collection of storage cells together with
associated circuits needed to transfer the
information in and out.
• RAM is Random Access Memory that
facilitates reading from and writing into
memory unit at any place.
• Read Write Memory (RWM) is more justified
word
• ROM facilitates only Reading (Read Only
Memory)
1/28/2025 Manoj Yadav 140
 Register

•4-bit register using D-f/fs

•No control on when the input is loaded into register
•(register content changes at next CP if data at input Ii
changes)

1/28/2025 Manoj Yadav 141

 Register with parallel load
•Two control signals added–
Load and Clear
•Clear  makes content
0000
•Load when this is enabled
(1) then S input of a SR f/f is
Ii and R input of f/f is I’i
•(effectively SR f/f works as D
f/f) with additional control–
load
•When Load input is
disabled(0) both S and R
inputs of SR f/f are 0 and no
change in the state of f/f.

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1/28/2025
Using D-f/f
Manoj Yadav 143
 Sequential circuit design

1/28/2025 Manoj Yadav 144

 K-map is used to reduce the above
functions A1(t+1), A2(t+1)and y.

1/28/2025 Manoj Yadav 145

 Shift registers
• Registers capable of shifting the content right
or left are known as shift registers.
• All f/f receive the same CP.

1/28/2025 Manoj Yadav 146

 Application

•Bit by bit manipulation can be done

•serial transfer is happening.
•Serial data transfer is done if no of channels is
restricted.
•In above block diagram content of reg A is
transferred serially to B. Due to feedback in reg A
1/28/2025 data is kept stored inManoj
regYadavA. 147
 Timing diagram—for 4-bit transfer

1/28/2025 Manoj Yadav 148

 Universal Shift Register
Data OUT (parallel)

S0
S1

MSB_in Universal LSB_in

CLK Shift
Register
Clear_b

S1 S0 Reg operation
Data IN (Parallel)
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
1/28/2025 Manoj Yadav 149
 Universal Shift Register

1/28/2025 Manoj Yadav 150

 Serial vs parallel processing
• Computer may operate in serial, parallel or
combination of both.
• In serial processing time required is more
while in parallel processing less time is
required.
• In serial processing less hardware is required.

1/28/2025 Manoj Yadav 151

Bidirectional shift with parallel load
• Circuit has following requirement
1. Hold the old content(00)
2. Shift right(01)
3. Shift left(10)
4. Parallel load(11)

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1/28/2025 Manoj Yadav 153
1/28/2025 Manoj Yadav 154
 Serial adder
• Mostly operations in digital computers are
done serially due to fast speed
• Serial operations are slower but require lesser
h/w
• E.g. Serial adders
• Let the two no. are in two registers A and B
• The sum is stored back in register A only.
• i.e. A A+B
1/28/2025 Manoj Yadav 155
•A Augend
•B Addend
•Clear=0;
•D f/f carry
•SO from A and B
corresponding bits to
be added
•Previous carry comes
from D f/f
•Right shift control
enables both reg and
carry
•As CP arrives o/p of
both reg and carry are
added and previous
sum from FA is stored
in reg A.
•....

1/28/2025 Manoj Yadav 156

 Example
• Design serial adder using sequential circuit
design method...

1/28/2025 Manoj Yadav 157

 Counters
• Two types
• 1. Ripple counters(asynchronous)
• 2. Synchronous counters
• In ripple counters the output of f/f works as
clock pulse for next f/f.
• In synchronous counters the CP input is given
to all f/f simultaneously

1/28/2025 Manoj Yadav 158

 Ripple counters
LSB MSB

Negative edge trigger

J=K=1 for J-K f/f
T =1 for T-f/f
1/28/2025 Manoj Yadav 159
 Working as up counter 0123....
1/28/2025 May work as down counter ifManoj
Q’ of f/f is considered.
Yadav 160
 BCD ripple counter
• Counts from 09 and back to 0.
• To represent each digit four f/f will be required.

State
diagram

Design procedure can not be followed b’coz of ripple nature.

No fixed rule to design.
1/28/2025 Manoj Yadav 161
 Timing diagram

Q1 is complemented on each negative transition

1/28/2025 of CP Manoj Yadav 162
 Q2 is complemented when Q8 is 0 and Q1 goes from 1 to 0.
1/28/2025Q2 is cleared if Q8 is 1. Manoj Yadav 163
 Q4 is complemented when Q2 from 1 to 0.
1/28/2025 Manoj Yadav 164
 Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to 0.
Q8 is cleared if either Q4 or Q2
1/28/2025 Manoj is 0.
Yadav 165
 Asynchronous BCD counter

The counter counts in normal fashion upto 1001.

i.e. Higher order f/f toggles when preceding f/f
become 10 (negative edge).
As soon as count value reach 1010

1/28/2025 Manoj Yadav 166

 3 decade BCD counter

1/28/2025 Manoj Yadav 167

• Design a Mod(20) counter.

1/28/2025 Manoj Yadav 168

 Synchronous counter
• CP input is applied to all f/f simultaneously
• A f/f is complemented or not; depends upon
the value of J and K.
• If J=K=0 output remains unchanged
• If J=K=1 output complements
• Normal procedure of sequential circuit design
may be followed.

1/28/2025 Manoj Yadav 169

 Synchronous binary up counter
• f/f on LSB is to be complemented on each
negative edge of CP  J=K=1.
• A f/f in any other position is complemented
with a pulse provided all the bits in the lower
order positions are 1.
• E.g. Present value=0011
• Next value=0100

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1/28/2025 Manoj Yadav 171
 4-bit binary up counter

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1/28/2025 Manoj Yadav 173
 Synchronous binary down counter
• f/f on LSB is to be complemented on each
negative edge of CP  J=K=1.
• A f/f in any other position is complemented
with a pulse provided all the bits in the lower
order positions are 0.
• E.g. Present value=1100
• Next value=1011
• Circuit will be same except output is taken
from Q’ rather than Q.
1/28/2025 Manoj Yadav 174
 Synchronous Binary up-down counter

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 4-bit synchronous binary down
counter

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 Up/down counter

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1/28/2025 Manoj Yadav 178
 Synchronous BCD Counter
• Can be designed using regular procedure of
sequential circuit design.
• Counts from 09 and back to 0.
• T-f/f is used for design.
• 4-f/f will be required to represent 9.
• State table may be formed considering present
state as input and next state and final count as
output.
• Thereafter excitation table may be formed

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