DMSCSE12

ANNAMALAI UNIVERSITY
DIRECTORATE OF DISTANCE EDUCATION

MSc COMPUTER SCIENCE

FIRST SEMESTER

COMPUTER ARCHITECTURE AND

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 Computer Architecture And Microprocessor

Table of Content

UNIT I
1.0 Introduction 1
1.1 Objective 1
1.2 Content 1
1.2.1 Number System 1
1.2.2 Representation of Negative Number 3
1.2.3 2’s Complement representation of numbers 6
1.2.4 Binary Coded Decimal (BCD) 7
1.2.5 Hexadecimal Number System 9
1.2.6 ASCII Code 12
1.2.7 Boolean Algebra 15
1.2.8 Flip – Flop 18
1.2.9 Register 18
1.2.10 Counters 19
1.2.11 Basic Logic gates 22
1.2.12 Logic circuits 25
1.2.13 TTL Circuit 29
1.2.14 Computer Languages 30
1.3 Revision Points 41
1.4 Intext Questions 41
1.5 Summary 41
1.6 Terminal Exercises 44
1.7 Supplementary Materials 45
1.8 Assignments 45
1.9 Suggested Reading 45
1.10 Learning Activities 45
1.11 Keywords 45

UNIT II
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Introduction 46
2.1 Objective 46
2.2 Content 46
2.2.1 Microprocessor architecture and its operations 46
2.2.2 Microprocessor-initiated operations and 47
8085/8080A bus organization
2.2.3 Memory 52
2.2.4 Memory map 54
2.2.5 Example of a microcomputer system 58
2.2.6 Interfacing devices 59
 2.2.7 The 8085 MPU 63
2.2.8 The 8085 Microprocessor 64
2.2.9 A detailed look at the 8085 MPU and its architecture 72
2.3 Revision Points 75
2.4 Intext Questions 75
2.5 Summary 76
2.6 Terminal Exercises 76
2.7 Supplementary Materials 77
2.8 Assignments 77
2.9 Suggested Reading 77
2.10 Learning Activities 77
2.11 Keywords 77

UNIT III
3.0 Introduction 78
3.1 Objective 78
3.2 Content 78
3.2.1 Organization of the 8085 78
3.2.2 Instruction Types 80
3.2.3 Data Transfer (COPY) Operations 80
3.2.4 Addressing Modes 82
3.2.5 Arithmetic Operations 89
3.2.6 Flag Concepts and Cautions 97
3.2.7 Logic Operations 97
3.2.8 Data Masking with Logic AND 99
3.2.9 Branch Operations 103
3.2.10 Looping, Counting 109
3.3 Revision Points 114
3.4 Intext Questions 115
3.5 Summary 115
3.6 Terminal Exercises 116
3.7 Supplementary Materials 116
3.8 Assignments 116
3.9 Suggested Reading 116

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3.10
3.11 UNIVERSITY
Learning Activities
Keywords
117
117

UNIT IV
4.0 Introduction 118
4.1 Objective 118
4.2 Content 118
4.2.1 Counter 118
4.2.2 Time delay 119
 4.2.3 Counter design with time delay 124
4.2.4 Stack 129
4.2.5 Subroutine 138
4.2.6 BCD to Binary Conversion 147
4.2.7 Binary to BCD Conversion 150
4.2.8 BCD to seven-segment led code conversion 152
4.2.9 Binary to ASCII and ASCII to Binary Code Conversion 155
4.2.10 Software Development System 159
4.3 Revision Points 163
4.4 Intext Questions 163
4.5 Summary 163
4.6 Terminal Exercises 164
4.7 Supplementary Materials 164
4.8 Assignments 164
4.9 Suggested Reading 165
4.10 Learning Activities 165
4.11 Keywords 165

UNIT V
5.0 Introduction 166
5.1 Objective 166
5.2 Content 166
5.2.1 The 8080A Interrupt 166
5.2.2 The 8085 Interrupts 170
5.2.3 Concepts in Serial I/O 175
5.2.4 Synchronous vs. Asynchronous Transmission 177
5.2.5 Programmable Interface Devices 179
5.2.6 The 8155/8156 Programmable I/O Ports and Timer 180
5.2.7 Interfacing the 8355/8755 Programmable I/O Ports 199
5.2.8 The 8279 Programmable Keyboard/Display Interface 199
5.2.9 Applications of Microprocessors 206
5.2.10 A Temperature Monitoring System 206
5.2.11 Closed Loop Process Control 240
5.3 Revision Points 245

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5.4
5.5 UNIVERSITY
Intext Questions
Summary
246
246
5.6 Terminal Exercises 246
5.7 Supplementary Materials 247
5.8 Assignments 247
5.9 Suggested Reading 247
5.10 Learning Activities 247
5.11 Keywords 247
 Computer Architecture and Microprocessor

UNIT – I
1.0 Introduction
A computer understands information composed of only zeros and ones.
Therefore, the computer in the form of 0s and 1s processes instructions and data. We are
familiar with the decimal number system in which digits are 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
The decimal number system is convenient for the programmer. The computer uses
binary digits for its operation. In the binary system there are only two digits 0 and 1.
The programmer feeds instructions and data in mnemonics and decimal digits. But for
the operation of the computer these are converted to binary bits. This chapter deals with
the conversion of binary numbers to decimal numbers and vice versa. It also deals with
hexadecimal and octal system. Computer circuitries are usually designed to process
hexadecimal or octal number.

1.1 Objective

This lesson provides the skill about number systems, computer languages. The
content of this lesson starts with number systems including decimal number system,
representation of negative numbers and hexadecimal numbers. It completely deals the
core concepts of Boolean algebra, registers, counters and logic circuits. Towards end of
this lesson student can understand the basic idea about the internals of the computer
system and the programming language fundamentals.

1.2 Content
1.2.1 Number System

Decimal Number System

We use decimal number system in everyday work. There are ten digits 0 to 9. The base
of the decimal number system is 10. The following example will explain the base and the
value of the each digit of a decimal number.
Example

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4598 = 4000 + 500 + 90 + 8
= 4 x 103 + 5 x 102 + 9 x 101 + 8 x 100
The value of each digit depends on its position in the number as described below:
The value of the 1st digit of the number from the right side
= 1st digit x 100
The value of the 2nd digit of the number from the right side
= 2nd digit x 101
The value of the 3rd digit of the number from the right side
= 3rd digit x 102
The value of the 4th digit of the number from the right side
= 4th digit x 103

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 Computer Architecture and Microprocessor

The value of the nth digit of the number from the right side
= nth digit x 10n-1 = nth digit x (base)n-1.
Binary Number System

In the binary number system there are only two digits 0 and 1. The binary digits are
called bits. The base of the binary number system is 2. In the decimal system there is no
difficulty in representing numbers up to 9. For ten there is no symbol or digit and hence
10 is written. Again, after 99 we have to write 100. Similarly, in binary system zero is
represented by 0 and one by 1. After this there is no digit for two. Therefore, two is
written as 10 and three as 11. Again for four we have to write 100. In this way we
proceed further. Thus we see that a binary number becomes very long and cumbersome.
The following example will illustrate the base and weight of each digit in a binary
number.
Example
1011 (binary number) = 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20
= 8 + 0 + 2 + 1 = 11 (decimal number)
The weight of each bit of a number depends on its position as described below :
The value of the 1st bit of the number from the right side = 1st bit x 20
The value of the 2nd bit of the number from the right side = 2nd bit x 21
The value of the 3rd bit of the number from the right side = 3rd bit x 22
The value of the 4th bit of the number from the right side = 4th bit x 23
The value of the nth bit of the number from the right side = nth bit x 2n-1 = nth bit x
(base)n-1
Thus we see that rules for decimal and binary numbers are exactly same. The value of a
digit in a number depends on the base and its relative position in the number.

Table 1.1. Decimal to Binary Conversion

____________________________________________________________
Decimal Number Binary Number
____________________________________________________________
0 0
1 1
2 10
3 11
4 100
5 101
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7
110
111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111

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16 10000
____________________________________________________________

1.2.2 Representation of Negative Number

The 2’s complement is used to represent the negative of a binary number. Before
understanding 2’s complement in the binary number system let us understand 9’s and
10’s complement in the decimal number system.

9’s complement.

To obtain the 9’s complement of a decimal number each digit of the number is subtracted
from 9. For example, the 9’s complement of 45 is (99-45) = 54.
The 9’s complement of 523 = (999 – 523) = 476.

10’s complement.

The 10’s complement of a decimal number = its 9’s complement + 1.

The 10’s complement of 45 = 54 + 1 = 55.
The 10’s complement of 523 = 476 + 1 = 477.
Now let us add the number and its 10’s complement and examine the sum.

Example 1
4 5 (decimal number)
+ 5 5 (its 10’s complement)
0 0
Carry =1

In this case the decimal number is of two digits. If we consider the sum of the number
and its 10’s complement only up to two digits, it is zero. In other words we are
neglecting the carry of the last stage.

Example 2
5 2 3 (decimal number)
+ 4 7 7 (its 10’s complement)
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________________________________________
0 0 0
Carry = 1

The decimal number 523 is of three digits. If we consider the sum of the number and its
10’s complement only up to three digits, it is zero. Thus we see that the 10’s complement
gives the negative value of the number
The 10’s complement of a decimal number = - decimal number.

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1’s Complement.

The 1’s complement in the binary number system is similar to the 9’s complement in the
decimal system. The 1’s complement of a binary number is obtained by subtracting each
bit of the number from 1. The 1’s complement of 01 is 10. The 1’s complement is 111 is
000. Thus we see that the 1’s complement of a binary number can be obtained by simply
changing each bit 1 to 0 and 0 to 1.

Example 1. Find 1’s complement of 100110.

The 1’s complement of 100110 = 011001.

Example 2 Find 1’s complement of 0000

The 1’s complement of 0000 = 1111.
Example 3 Find 1’s complement of 11111.
The 1’s complement of 11111 = 00000.

2’s Complement.

The 2’s complement in the binary number system is similar to the 10’s complement in the
decimal number system.
The 2’s complement of binary number = its 1’s complement + 1.

Example 1. Find 2’s complement of 10011.

The 2’s complement of 10011 = 01100 + 1
= 01101.
Example 2. Find 2’s complement of 111.
The 2’s complement of 111 = 000 + 1
= 001.
Example 3. Find 2’s complement of 0000.
The 2’s complement of 0000 = 1111 + 1
= 0000.

Now let us examine the sum when a binary number is added to its 2’s complement.

Example 1. Binary number = 1001

Its 1’s complement = 0110
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Its 2’s complement = 0110 + 1
= 0111.
Number + its 2’s complement = 1 0 0 1
+ 0 1 1 1
__________________
0 0 0 0
Carry

The last carry is lost if the processor is of 4 bits or sum is considered only 4 bits.

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For 8-bit processor the number and 2’s complement will be written in 8 bits as given
below:

Number = 00001001
1’s complement = 11110110
2’s complement = 11110110 + 1
= 11110111
Number = 00001001
+ 2’s complement = 11110111
__________________
00000000
carry
The last carry will be neglected, if the 8 bit sum is considered.

Example 2
+ 4 (decimal) = 00000100 (binary)
-4 = Its 2’s complement = 11111011 + 1
= 11111100
+4 = 00000100
-4 = 11111100
______________________
00000000

Example 3
Add + 5 and –7

7 = 00000111
-7 = 11111000 + 1
= 11111001
+5 = 00000101
-7 = 11111001
____________________________
-2 = 11111110

Check: 2 = 00000010
-2 = 11111101 + 1
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Thus we see that the 2’s complement of a binary number represents its negative.

Binary Subtraction Using 2’s Complement.

The addition of 2’s complement of a number is equivalent to the subtraction of the

number. Suppose, we want to subtract 0010 ( 2 decimal) from 0101 ( 5 decimal ). If the
2’s complement of 0010 (2 decimal) is added to 0101 (5 decimal) the sum will be 0011 (3
decimal). It is equal to 0101 (5 decimal) – 0010 (2 decimal) = 0011 (3 decimal).

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Ordinary binary subtraction:

0101 (5 decimal)
- 0010 (-2 decimal)
____________________
0011 (3 decimal)

Subtraction using 2’s complement:

1’s complement of 0010 (2 decimal) = 1101
2’s complement of 0010 = 1101 + 1 = 1110
0101 (5 decimal)
+ 1110 ( + 2’s complement of 2)
______________________________________
0011 (3 decimal)

The carry of the last stage is neglected.

1.2.3 2’s Complement representation of numbers

The 2’s complement of a binary number x, which has n bits, is given by (2n-x). Consider
the number +3 whose binary representation is 011. It has three bits. Hence the 2’s
complement of +3 is (23-3), which is 5. The binary representation of 5 is 101. Thus, 101
is the 2’s complement of 011.

In a computer, all numbers are represented in a uniform fashion using a fixed number of
bits. Thus, for an n-bit machine, the range of numbers it can handle is 0 to 2n-1. For
simplicity, consider a 4-bit machine. Sixteen numbers (0 to 15) can normally be
represented using these four bits. Now we devise a new scheme of representing negative
numbers as follows. We use the first seven combinations of bits for representing positive
numbers one to seven. We reserve seven of the remaining combinations for representing
negative numbers –1 to –7. Thus we have divided the total range into two parts, 0 and 8
being common to the two halves. Now we restrict ourselves to the use of numbers
having a maximum magnitude of seven. In this way we can represent both positive and
negative numbers as indicated in Fig. 1.1. With reference to the figure we see that the
code 1111, which normally represents 15, is assigned to –1. Similarly the binary
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equivalent of 14 is assigned to –2. Since 15 = 24-1, 14 = 24 – 2, etc., this is called the 2’s
complement representation of 1,2, etc. In general the 2’s complement representation (n-
1) bits represent the magnitude.

There is a simple procedure to obtain the 2’s complement of a binary number. We first
complement each bit of the number (i.e., replace ‘1’ by ‘0’ and ‘0’ by ‘1’). Now we add
a ‘1’ to the number. For example, consider the number 5 whose binary representation is
0101. Bit complementation yields 1010. Now adding a ‘1’ to this number gives 1011
which is the 2’s complement representation for –5.

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Yet another method of obtaining the 2’s complement of a binary number is to scan the
number from right to left and complement all bits appearing after the first appearance of a
‘1’. For example the 2’s complement of 0010 is 1110 and that of 0011 is 1101.

Fig. 1.1. Two’s complement representation of numbers

1.2.4 Binary Coded Decimal (BCD)

In BCD code a decimal digit is represented by four binary bits. For example, 5 is
represented by 0101. If there are two or more than two digits in a decimal number, each
decimal digit is represented by four binary bits. For example, 93 is represented by 1001
0011. The decimal number 2354 is represented by 0010 0011 0101 0100. Several BCD
codes are there such as standard BCD; 2, 4, 2, 1 BCD code; excess –3 BCD code etc. In
the standard BCD code the weights of the binary bits are 8, 4, 2, 1. These weights are
same as those in ordinary binary number. The standard BCD does not represent 1010 to
1111, i.e. 10 to 15 (decimal). 10 in BCD form is represented by 00010000 and 15 by
00010101. BCD codes are widely used with instruments and calculators. Table 1.2 gives
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the BCD representation of decimal numbers from 0 to 9. Table 1.3 shows the BCD
representation of two digit decimal numbers.

Gray Code.

The reflected binary or Gray Code is shown in Table 1.4. In this code only one bit
changes in the transition from one number to the next higher number. The Gray code is
used in shaft encoder which is to indicate the angular position of a shaft. The use of Gray
code reduces errors. Suppose that the present position of the shaft is indicated by Gray
code 0100 which is for 7. If the position changes to 8, the Gray code will be 1100. If the
new change in binary bit is not picked up by the detector the encoder will show the

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previous position i.e., 7. But in case of ordinary binary code 7 is represented by 0111 and
8 by 1000. Now suppose the detector picks up the least significant bits i.e., 000, but fails
to pick up the most significant bit 1, the output will be 0000 instead of 1000. So there is
a large error if a simple binary code is used for a shaft encoder.

Table 1.2 Decimal to Standard BCD Conversion

__________________________________________________________________
Decimal Number Standard BCD Number
__________________________________________________________________
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
__________________________________________________________________

Table 1.3. Decimal to Standard BCD Conversion

__________________________________________________________________
Decimal Number Standard BCD Number
__________________________________________________________________
10 00010000
11 00010001
12 00010010
13 00010011
14 00010100
15 00010101
30 00110000
45 01000101
64 01100100
73 01110011
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98 10011000
__________________________________________________________________

Table 1.4. Gray Code

__________________________________________________________________
Decimal Binary Code Gray Code
__________________________________________________________________

0 0000 0000
1 0001 0001

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2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
__________________________________________________________________

1.2.5 Hexadecimal Number System

The base of the hexadecimal number system is 16. The digits from 0 to 9 are same as
those of the decimal number system. In the hexadecimal system 10 is represented by A,
11 by B, 12 by C, 13 by D, 14 by E and 15 by F. The decimal number 16 is represented
by 10 in the hexadecimal system; 17 by 11; 18 by 12; 32 by 20; 33 by 21 and so on.

A hexadecimal digit is represented by four binary bits. For example, 6 is represented by

0110, B is represented by 1011 and F by 1111. If there are two or more than two digits in
a hexadecimal number, each hexadecimal digit is represented by four binary bits. For
example, 98 is represented by 1001 1005; 5C by 0101 1100; 3AFB by 0011 1010 1111
1011. The Hexadecimal system utilizes the full capacity of four binary bits. The BCD
system does not utilize the full capacity of four binary bits which represent a decimal
digit. In the hexadecimal system an 8-bit word can represent up to 11111111 or 255
(decimal) whereas in BCD only up to 10011001 or 99 (decimal). Thus the hardware cost
in the hexadecimal system is reduced. The BCD system has the advantage of simplicity
in getting the output in the decimal system.

Table 1.5 and Table 1.6 show decimal, hexadecimal and binary representations.
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Conversion of a Hexadecimal Number to Decimal Number.

The following examples illustrate the conversion of hexadecimal number to

decimal number.

Example 1. Convert the hexadecimal number 5B to its decimal equivalent.

B is the 1st digit from the right side; its weight is B x 160
5 is the 2nd digit from the right side; its weight is 5 x 161

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5B (hexadecimal) = 5 x 161 + B x 160

= 80 + B
= 80 + 11
= 91 (decimal)

Table 1.5
__________________________________________________________________
Decimal Number Hexadecimal Number Binary representation of
Hexadecimal number
__________________________________________________________________
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111
__________________________________________________________________

Table 1.6
__________________________________________________________________
Decimal Number Hexadecimal Number Binary representation of
Hexadecimal number
__________________________________________________________________
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42
92
UNIVERSITY 2A
5C
00101010
01011100
163 A3 10100011
168 A8 10101000
180 B4 10110100
185 B9 10111001
188 BC 10111100
191 BF 10111111
202 CA 11001010
205 CD 11001101
222 DE 11011110

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228 E4 11011111
236 EC 11101100
239 EF 11101111
248 F8 11111000
254 FE 11111110
255 FF 11111111
__________________________________________________________________

Example 2. Convert the hexadecimal number 5A9 to its decimal equivalent.

9 is the 1st digit from the right; its weight is 9 x 160

A is the 1st digit from the right; its weight is A x 161
5 is the 1st digit from the right; its weight is 5 x 162
5A9 (hex) = 5 x 162 + A x 161 + 9 x 160
= 5 x 256 + 10 x 16 + 9
= 1280 + 160 + 9
= 1449 (decimal).

Example 3. Convert the hexadecimal number 1A5D to its decimal equivalent.

1ASD (hex) = 1 x 163 + A x 162 + 5 x 161 + D x 160
= 4096 + 10 x 256 + 80 + 13 x 1
= 4096 + 2560 + 80 + 13
= 6749 (decimal).

Conversion of a Decimal Number to Hexadecimal Number.

For the conversion of a decimal number to a hexadecimal number, the technique of

division by 16 can be used. The following examples will illustrate the technique;

Example 1. Convert 35 (decimal) to its equivalent hexadecimal number.

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The hexadecimal number is 23.

Check: 23 (hex) = 2 x 161 + 3 x 160

= 32 + 3 = 35 (decimal)

Example 2. Convert the decimal number 10767 to a hexadecimal number.

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The hexadecimal number is 2A0F

Check: 2A0F (hex) = 2 x 163 + A x 162 + 0 x 161 + F x 160

= 2 x 4096 + 10 x 256 + 0 + 15
= 10767 (decimal)

Conversion of a Hexadecimal Number to Binary Number.

For the conversion of a hexadecimal number to binary number each digit of the given
hexadecimal number is converted to its 4-bit binary equivalent.

Example 1. Convert the hexadecimal number 5CB8 to its equivalent binary number

(5CB8)16 = (0101)(1100)(1011)(1000)
5 C B 8
= (0101110010111000)2

Example 2. Convert the hexadecimal number 4F2D to its binary equivalent.

(4F2D)16 = (0100)(1111)(0010)(1101)
4 F 2 D
= (0100111100101101)2

Codes for mnemonics and data are entered into a microprocessor kit in the form of
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hexadecimal for the convenience of the programmer. Internally they are converted to
binary equivalent as shown in Tables 1.5 and 1.6 for processing by the microprocessor.

1.2.6 ASCII Code

The ASCII stands for American Standard Code for Information Interchange. ASCII is
pronounced as “ask-ee”. The ASCII code is widely used in small computers, peripherals,
instruments and communication devices. It is a 7-bit code. Microcomputers having 8-bit
word length use 7 bits to represent the basic code. The 8th bit is used for parity or it may
be kept permanently 1 or 0. Table 1.7 shows ASCII codes.

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Table 1.7. ASCII Codes

_______________________________________________________
ASCII Code Character ASCII Code Character
_______________________________________________________
00 NUL 21 !
01 SOH 22 “
02 STX 23 #
03 ETX 24 $
04 EOT 25 %
05 ENQ 26 &
06 ACK 27 ‘
07 BEL 28 (
08 BS 29 )
09 HT 2A *
0A LF 2B +
0B VT 2C ,
0C FF 2D -
0D CR 2E .
0E S1 2F /
0F S0 30 0
10 DLE 31 1
11 DC1 (X-on) 32 2
12 DC2 (Tape) 33 3
13 DC3 (X-off) 34 4
14 DC4 35 5
15 NAK 36 6
16 SYN 37 7
17 ETB 38 8
18 CAN 39 9
19 EM 3A :
1A SUB 3B ;
1B ESC 3C <
1C FS 3D =
1D GS 3E >
1E RS 3F ?
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1F
20
US
SP
40
41
@
A

_______________________________________________________
ASCII Code Character ASCII Code Character
_______________________________________________________

42 B 63 c
43 C 64 d
44 D 65 e

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45 E 66 f
46 F 67 g
47 G 68 h
48 H 69 i
49 I 6A j
4A J 6B k
4B K 6C l
4C L 6D m
4D M 6E n
4E N 6F o
4F O 70 p
50 P 71 q
51 Q 72 r
52 R 73 s
53 S 74 t
54 T 75 u
55 U 76 v
56 V 77 w
57 W 78 x
58 X 79 y
59 Y 7A z
5A Z 7B {
5B [ 7C |
5C \ 7D }
5D ] 7E ~
5E ^() 7F DEL
5F -() (RUB OUT)
60 ‘
61 a
62 b

ASCII-8.

A new version of ASCII is ASCII-8. In ASCII seven bits represent the basic code. 7 bits
can represent up to 128 characters. ASCII-8 uses 8 bits represent the basic code of a
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character. 8 bits can represent up to 256 characters. Table 1.8 shows ASCII-8 codes.
ASCII-8 code is used in larger machines whereas ASCII in smaller machines.

Table 1.8 ASCII-8 Codes

__________________________________________________________________
Character ASCII-8 Code Character ASCII-8 Code
__________________________________________________________________
0 50 J AA
1 51 K AB
2 52 L AC

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3 53 M AD
4 54 N AE
5 55 O AF
6 56 P B0
7 57 Q B1
8 58 R B2
9 59 S B3
A A1 T B4
B A2 U B5
C A3 V B6
D A4 W B7
E A5 X B8
F A6 Y B9
G A7 Z BA
H A8
I A9
__________________________________________________________________

In ASCII-8 first 4 bits are called zone bits and remainder 4 bits are numeric bits. In
ASCII first 3 bits are zone bits and remainder 4 bits are numeric bits. In ASCII and
ASCII-8 numeric bits are identical but zone bits are different.

1.2.7 Boolean Algebra

Boolean algebra is the algebra of binary variables. Binary variables are also known as
Boolean variables. Boolean variables have only two values 0 and 1. The only logical
operations in Boolean algebra are OR, AND and NOT operations. The mathematical
symbol + and. stand for OR and AND operations respectively. The symbol – or ‘ is used
for NOT (INVERT or COMPLEMENT) operation.

There are two important means to express the relationship between input and output
variables of a digital system: truth table and Boolean expression. The aim of a designer
is to use minimum number of basic circuits to perform a digital operation. First of all he
writes Boolean expression for the system. This expression is minimized using Boolean
theorems. The map is also a minimization technique which is used in the design of
digital systems. The minimum number of circuits reduces the cost and increases the
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speed and reliability of the system.

Table 1.9 presents a list of important Boolean theorems. The first four laws are for OR
operation. These laws can easily be explained. The first law is
A+0=A
The binary variable A can have only two values, either 0 or 1. When 0 is put in the above
equation for A, the above equation becomes: 0 + 0 = 0;
This is true for OR operation.
Similarly, when 1 is put for A, we get
1 + 0 =1

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which is true for OR operation. Similarly, other OR laws can be explained putting 0 or 1
value for the binary variable A.

Table 1.9. Boolean Algebraic Theorems

________________________________________________________________________

1. A + 0 = A
2. A + 1 =1 OR Laws
3. A + A = A
4. A + A = 1
5. A.0 = 0
6. A.1 = A AND Laws
7. A.A =A
8. A . A=0

9. A = A
10. 1 = 0
11. 0 = 1 Laws of complementation
12. If A=0, then A =1
13. If A=1, then A = 0

14. A + B = B + A
15. A .B = B .A Commutative laws
16. (A + B) + C = A + (B + C) = A + B + C Associative Laws
17. (A.B).C = A.(B.C) = A.B.C
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18. A . (B+C) = A .B + A .C Distributive Laws
19. A + B.C = (A + B) . (A + C)
20. A + AB = A
21. A . (A + B) = A
22. A + AB = A + B
23. A . (A + B) = AB
24. AB + AB = A

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25. (A + B)(A + B) = A
26. AB + AC = (A + C) . (A + B)
27. (A + B) ( A + C) = AC + AB
28. AB + AC + BC = AB + AC
29. (A + B)(A + C)(B + C) = (A + B)(A + C)
30. (A + B +C + …) = A . B . C….
31. A.B.C… = A + B + C De Morgan’s Theorem
____________________________________________________________________________________

In Table 1.9, laws 5 to 8 are for AND operation. The fifth law is A.0 = 0. This law is
true for AND operation when A is put equal to either 0 to 1. Similarly, laws from 6 to 8
are true when the value of A is put either 0 or 1.

Laws of complementation from 9 to 13 are obvious and very simple.

The law 14 is for an OR gate : A + B = B + A. If the input signals of an OR gate are
transposed, the output remains same. Each of the binary variables A and B can have
either 0 or 1 value. Put all possible values for A and B in the law 14 and see that the
relation is true for OR law. The law 15 is for AND operation. If the input signals are
interchanged, the output remains same. This can also be explained by putting binary
values for A and B in the equation.

The law 16 is associated law for OR operation.

(A + B) + C = A + (B +C) = A + B + C

To explain this take two OR gates. A and B are used as input signals for the 1 st OR gate.
Now the output of the 1st gate and C are fed to the 2nd gate. You will see that the output
of the 2nd gate is equal to A + B + C. Again apply B and C to the 1st OR gate. The output
of the 1st gate and A are applied to the 2nd OR gate. The output of the 2nd gate will be
equal to A + B + C. This can also be explained by putting binary values of A, B and C in
the equation. For example, suppose A = 1, B =0 and C = 1.

Now the equation 16 becomes:

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(1 +0) + 1 = 1 + (0 +1)
Performing OR operation on binary numbers in brackets both sides, we get
1+1=1+1
or 1 = 1, which proves the law.
Also, A + B + C = 1 + 0 + 1 = 1.

The law 17 is for AND operation. This can also be explained as 16 has been explained.

Law 30 is DeMorgan’s Theorem. For a two input system the law is A + B = A.b. Now
forming the truth tables for A + B and A.B it can be shown that this law is true. This has
been proved while discussing NOR gate in section 2.15.5.

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Law 31 is also DeMorgan’s Theorem. For a two input system the law is A.B = A + B.
This can be proved forming truth tables for A.B and A + B for all possible binary values
of A and B. This has already been shown in Section 2.15.4 while discussion NAND gate.

Other laws of Table 1.9 can be proved using truth table or with the help of other Boolean
laws.

1.2.8 Flip – Flop

A digital computer needs devices which can store information. A flip – flop is a binary
storage device. It can store binary bit either 0 or 1. It has two stable states: HIGH and
LOW, i.e. 1 and 0. It has the property to remain in one state indefinitely until it is directed
by an input signal to switch over to the other state. It is also called bistable multivabrator.
It is a basic memory element. The basic flip – flops are S-R Flip – flop, J-K Flip – flop, D
Flip – flop, T Flip – flop. For Presetting and Clearing of a clocked flip – flop may be
required before applying inputs. For this purpose Preset (PR) and Clear (CLR) terminals
are provided. PR and CLR are not low at the same time. Preset and Clear are used to
initialize a circuit before normal clocked operation of the circuit starts.

1.2.9 Register

A flip-flop is the basic memory unit. It is a 1-bit memory element. A register is a set of
flip-flops to store a binary word. To store n-bit binary word a set of n flip-flops is used.
They are connected in parallel. All bits of an n-bit word are transferred to the register in
parallel. Unlike a latch, the contents of a register can be read at any time without altering
its value. Generally the registers are built using edge-triggered D flip-flops. 74273 is an
8-bit register. It consists of 8 positive-edge-triggered flip-flops with common clock and
clear lines. The registers of a microprocessor are within the microprocessor’s IC
package.

Shift Register

A shift register is a register, which is able to shift its content within itself without
changing the order of the bits. It may be designed to shift date either left or right. The

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data is shifted one bit at a time when a clock pulse is applied. The shift register is used
for temporary storage of data. The shift register is used for multiplication and division
where bit-shifting is required. The shift registers can be built using R-S, J-K or D flip-
flops. In a shift register the output of one flip-flop is connected to the input of the
following flip-flop. Shift registers are not suitable for storing large data as they are slow.
Depending on the modes of loading and reading data there are following 4 types of shift
registers:
(i) Serial-in, serial-out
(ii) Serial-in, parallel-out
(iii) Parallel-in, serial-out
(iv) Parallel-in, parallel-out

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1.2.10 Counters

The function of a digital counter is to count the number of electrical pulses. To count
certain events electrical pulses proportional to the number of events are generated for
counting. Digital counters consist of flip-flops. There are two types of digital counters
namely, asynchronous and synchronous. In an asynchronous counter all flip-flops are not
clocked simultaneously. On the other hand in a synchronous counter all flip-flops are
clocked simultaneously. Synchronous counters are faster than asynchronous counters
due to simultaneous clocking of flip-flops. If a counter consists of n flip-flops it may
count pulses up to 2n. A ripple counter is an asynchronous counter.

The pulses to be counted are applied to the CLK (clock) terminal of the 1st flip-flop of the
counter. The output Q of the 1st flip-flop is connected to the CLK terminal of the 2nd flip-
flop. Similarly, the output Q of the 2nd flip-flop is connected to the CLK terminal of the
3rd flip-flop. In this way the Q output of one flip-flop is connected to the CLK terminal
of the next flip-flop. If there are 4 flip-flops in a counter, the counter will count from
0000 to 1111 and it is called a 4-bit binary counter. There is CLR terminal to clear the
counter.

Up Counter.

An up counter counts upwards starting from zero. A four bit binary counter counts from
0000 to 1111.

Down Counter.

A down counter counts downward starting from the maximum value. For example, a
down counter containing 4 flip-flops starts counting from 1111 and goes to 0000. In a
down counter the Q output of the flip-flop of one stage is connected to the CLK terminal
of the flip-flop of the next stage. There is an arrangement for presetting that stores 1111
as initial value. When counting goes on each electrical pulse reduces this initial number
by 1.

Up-Down Counter.

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In an up-down counter a control circuit is added to make a counter either an up counter or
a down counter. An U/ D control terminal is provided in an up-down counter. If U/ D is
high the counter becomes an up counter. If U/ D is low the counter becomes a down
counter.

Controlled Counter.

A controlled counter counts electrical pulses only when it is asked to do so. There is a
terminal COUNT to control counting. When COUNT is high the counter counts
electrical pulses applied to it. When COUNT is low the counter does not make counting

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even though the pulses may remain applied to it. All flip-flops remain latched in this
situation.

Ring Counter.

A ring counter uses D flip-flops. The output Q of the last stage is fed back to the D input
of the 1st stage. CLK terminal of all flip-flops are connected to the clock pulses. All flip-
flops are clocked simultaneously. Fig 1.2 shows 4-bit ring counter. For initial setting,
when CLR first goes low and then becomes high, an initial word 0001 is set in a 4-bit
ring counter. Now each clock pulse shifts the content of the counter left by one bit.
MSK is shifted to LSB. A ring counter is used to control a sequence of operations. A
number of devices may be connected to Q0, Q1, Q2, … Qn outputs of a ring counter. The
outputs Q0, Q1, Q2, … Qn go high in a sequence. When CLR goes low Q0 becomes high
and it activates the device connected to it. Then CLR returns high. Now clock pulses
applied to CLK terminal activates devices connected to their Q outputs in a sequence.
The 1st clock pulse makes Q1 high, the 2nd clock pulse makes Q2 high and so on. At a
time only one output is high and others are low. In a digital computer a number of digital
circuits are to be activated in a right sequence at precisely right time to fetch and execute
instructions. A ring counter is quite suitable for this task.

Fig 1.2 Ring Counter.

Modulus of a Digital Counter.

The number of output states of a counter is called its modulus. A 4-bit binary counter has
distinct states numbered from 0000 to 1111. So its modulus is 16.
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Binary Counter.
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In a binary counter the output Q of the flip-flop of one stage is connected to the clock
terminal of the next stage. All flop-flop are connected to work as a T flip-flop. A T flip-
flop changes the state of its output on the receipt of a clock pulse. Suppose that a flip-
flop’s output is 0. Now a clock is applied. On the receipt of positive clock pulse the
output changes from 0 to 1. When clock pulse goes low there is no change. Again when
clock pulse becomes high the output changes from 1 to 0. Thus on the receipt of 2 clock
pulses the flip-flop gives one pulse at its output. Suppose, there are 3 flip-flops in a
counter. If 8 clock pulses are applied to its input terminal (which is the clock input

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terminal of the first flip-flop) the first flip-flop gives 4 pulses at its output terminal Q0.
As the Q0 is connected to the clock input terminal of the second flip-flop, the 2nd flip-flop
gives 2 pulses at its output terminal Q1. As Q1 is connected to the input terminal of the
3rd flip-flop, the 3rd flop-flop will give one pulse at its output terminal Q2. Thus the
counter can count from 000 to 111. So it is a 3-bit binary counter. Similarly, a counter
containing 4 flip-flops counts from 0000 to 1111 and it is a 4-bit binary counter. Fig.1.3
(a) shows a 4-bit binary counter. Fig. 1.3 (b) shows its timing diagram. Binary counter
can be built using J-K flip-flops. They are also available in ICs. 7493, 74161, 74163,
74191, 74193 etc. are 4-bit binary counters.

Fig 1.3 (a) 4 Bit Binary Counter (b) Timing Diagram

Decade Counter.

A decade counter counts from 0000 to 1001. Its outputs are in BCD. It is also called
Mod-10 counter, divide by 10 counter or BCD counter. The counter circuit is designed to
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generate a clear signal on the receipt of 10th clock pulse and the setting becomes 0000.
Thus for every 10 clock pulses it will give one pulse at its output terminal. Examples of
decade counters are: 7490, 74160, 74162, 74168, 74190, 74192, 74176 etc.

Presettable Counter.

In presettable counter the counting starts from a number greater than zero. This number
can be set before the counting starts. Suppose a presettable counter has 4 flip-flops. It
can count from 0000 to 1111. Now the counter is preset at 0100. When counting starts
the count will become 0101 on the receipt of 1st clock pulses. In this way it will count

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upto 1111 on the receipt of subsequent pulses. In a presettable counter the modulus
becomes variable. It has a programmable modulus.

Counters can be built using flip-flops in the laboratory but the use of counter IC will be
convenient. Table 1.10 shows counter Ics.

Table 1.10 Counter ICs.

________________________________________________________________________
IC No. Description
________________________________________________________________________
7490, 74290 Decade counters; divide by 2 and 5; Asynchronous
7492 Asynchronous counter, divide by 12 counter; divide by 2 and
divide by 6.
7493, 74293 4-bit Binary Counters; Asynchronous, divide by 2 and divide by 8.
74176, 74196 Presettable Decade/Bi-quinary Counter; Asynchronous.
74177, 74197 4-Bit Binary Counters; Presettable; Asynchronous.
74390 Dual Decade Counters; Bi-quinary or BCD; Asynchronous.
74393 Dual 4-Bit Binary Counters; Asynchronous.
74490 Dual Decade Counters; Asynchronous.
74160, 74162 Synchronous Decade UP Counters.
74161, 74163 Synchronous 4-Bit Binary UP Counters.
74168, 74190, 74192 Synchronous Decade UP/DOWN Counters.
74169, 74191, 74193 Synchronous 4-Bit Binary UP/DOWN Counter.
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1.2.11 Basic Logic Gates

The building blocks of the digital world are the transistor arrangements designed to
output a known result with the application of a signal. The transistors in this capacity act
as simple switches but it is the particular configuration, which will yield the desired
results. Since many of the devices used in digital electronics are prepackaged, we can
represent them by symbol and truth table. Some of these configurations are shown here.

And Gate
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The AND gate requires both inputs to be logic 1 for an output of logic 1

Fig 1.4 AND GATE

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Truth Table of And gate.

Q = A * B or Q = A . B

INPUT OUTPUT
A B Q
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
If any input is logic 1 then the output of an OR gate will be logic 1.

Fig 1.5 OR GATE

Truth Table for Or gate:

Q=A+B

INPUT OUTPUT
A B Q
0 0 0
0 1 1
1 0 1
1 1 1

INVERTER / Not Gate

Any input is inverted. Logic 1 in yields logic 0 out and vice versa.

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Fig 1.6 NOT GATE
Truth Table for Not gate:
Q=A
INPUT OUTPUT
A Q
0 1
1 0

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NAND Gate

It is a combination of AND gate and a NOT gate as shown in the fig 1.7 below.

Fig 1.7

The actual diagrammatic representation is as shown below.

Fig 1.8 NAND GATE

Truth Table for Nand gate:

Q= A.B

INPUT OUTPUT
A B Q
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate
It is a combination of OR gate and NOT gate as shown in the fig 1.9 below.

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Fig 1.9
The actual diagrammatic representation is as shown below.

Q=A+B

Fig 1.10

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Truth Table for Nor gate:

INPUT OUTPUT
A B Q
0 0 1
0 1 0
1 0 0
1 1 0

1.2.12 Logic Circuits

Fig. 1.11. Standard Symbols for logic gates.

The three logical operations AND, OR and NOT are said to be logically complete, as any
Boolean function may be realized using these three operations. The standard symbols
given in Fig. 1.11. are used to represent the Boolean operations AND, OR and NOT
respectively. Using these gates we can realize the expressions for sn and cn+1 given as
Eq. (LC1) and Eq. (LC2) as shown in Fig. 1.12. This circuit is called a full adder circuit.
If the three bits to be added are fed to the inputs an, bn and cn of the full adder, the sum sn
and carry cn+1, appear as output.

Eq (LC1) sn = an . bn . cn + an . bn . cn + an . bn . cn + an . bn . cn

Eq (LC2) cn+1 = an . bn . cn + an . bn . cn + an . bn . cn + an . bn . cn

Table 1.11 Truth table for a full adder

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an
0
bn
0
cn
0
sn
0
cn+1
0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Fig. 1.12. Gate realization of a full adder.

The truth table of Table 1.11 may also be realized using a memory. Suppose we
permanently store in a memory, which has 8 words, the values of sn and cn+1 of Table
1.11 as shown in Fig. 1.13. The information from the memory may be retrieved by
placing the bits corresponding to an, bn, cn in the MAR of the memory.

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Fig. 1.13. A ROM (read only memory) realization of a full adder.

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The contents of the specified location would appear in MDR and are the values of sn and
cn+1. Such a memory where a table may be stored permanently is known as a read only
memory (ROM).
If we want to add three bits, we place the three bits in the MAR of the ROM. The sum
bit and the carry bit appear in the MDR.
A Seven-segment Display
A seven-segment display is used extensively in calculators and in digital watches
Numbers 0 to 9 are displayed by selectively lighting a group of light emitting diodes
(LED) (Fig.1.14).

Fig. 1.14. A seven-segment display.

We will now design a logic circuit which will accept a 4 bit binary equivalent of a
decimal digit and give outputs to selectively light the LEDs. The output of the circuit
will be 7 bits, one bit corresponding to each segment to be lighted in the seven-segment
display. If the output bit is a 1 it will turn on the corresponding light in the display and if
it a 0 it will turn it off. Figure 1.15 is a block diagram of the logic circuit to be designed
for this purpose.

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Fig. 1.15. Logic circuit to be designed for a seven-segment display decoder.

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Truth table corresponding to this logic circuit is developed as follows:

Step 1: The 4 bit binary equivalent of the digits 0 through 9 are enumerated and
one row of the truth table is formed for each of these.

Step 2: For each row of the truth table the values of 7 output bits necessary to
light the segments of the display corresponding to the input digit are entered. For
example, to display the digit 0 the lights A, B, C, D, E and F of the seven-segment
display should light up. Thus the bits for A, B, C, D, E and F should be 1 and the bit
corresponding to G should be 0. Similarly to display as 1 the bits B and C of the output
should be 1 and A, D, E, F, G should be 0.

Step 3: The combinations of input bits 1010, 1011, 1100, 1101, 1110 and 1111
should not occur, as the input is expected to be a single digit. If these inputs occur by
mistake, an error indication should be displayed. We will use the letter E as an error
indication and display it by lighting up segments A, F, G, E and D.

The truth table developed is given as Table 1.12.

Table 1.12 Truth table to design seven-segment display

INPUTS OUTPUTS
X Y Z W A B C D E F G
L
E 0 0 0 0 0 1 1 1 1 1 1 0
G 1 0 0 0 1 0 1 1 0 0 0 0
A 2 0 0 1 0 1 1 0 1 1 0 1
L 3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
D 5 0 1 0 1 1 0 1 1 0 1 1
I 6 0 1 1 0 1 0 1 1 1 1 1
G 7 0 1 1 1 1 1 1 0 0 0 0
I 8 1 0 0 0 1 1 1 1 1 1 1

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1 0 0 1 1 1 1 1 0 1 1

1 0 1 0
E 1 0 1 1 1 0 0 1 1 1 1
R 1 1 0 0 1 0 0 1 1 1 1
R 1 1 0 1 1 0 0 1 1 1 1
O 1 1 1 0 1 0 0 1 1 1 1
R 1 1 1 1 1 0 0 1 1 1 1
1 0 0 1 1 1 1

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We can realize a logic circuit using AND, OR, NOT gates by writing Boolean
expressions for A, B, C, D, E, F, G in terms of X, Y, Z, W. For example, the expression
for B is

B = X . Y. Z. W + X . Y. Z . W + X . Y. Z. W + X . Y. Z . W +

X.Y.Z.W+X.Y.Z.W+X.Y.Z.W+X.Y.Z.W

Similar expressions may be obtained for A, C, D, E, F and G.

Another method of realizing the seven segment display is to store the outputs A, B, C, D,
E, F, G in a 16-bit word ROM. The 16 words of the ROM are the 16 rows of the truth
table (Table 1.12). The address bits are X, Y, Z, W and the contents are the
corresponding values of A, B, C, D, E, F, G in the truth table. For example, address 0111
corresponding to X = 0, Y = 1, Z = 1, W = 1 will store the bits A = 1, B = 1, C = 1, D = 0,
E = 0, F = 0 and G = 0. In order to display a digit its binary values X, Y, Z, W are fed to
the MAR of the ROM. The output of the ROM, which appears in a 7-bit MDR lights up
the display LEDs.

1.2.13 TTL Circuit

It stands for transistor - transistor logic. It is a saturated logic because transistors operate
between cut-off and saturation. It is the most widely used circuit line since early 1970s
because of its speed, good fan – in and fan – out and easy interface with other digital
circuitry. The unique feature of this circuit is that it uses multiple – emitter transistor at
the input which replaces the input diodes of the DLT (diode transistor logic). The
number of emitters is equal to the desired fan – in of the circuit. Since the multi – emitter
transistor is smaller in area than the diodes it replaces, the yield from a wafer is increased.
Moreover, smaller area results in a lower capacitance to the substrate, thereby reducing
circuit rise and fall times and hence increasing its speed. The family contains a very wide
selection of circuit modules ranging from simple gates and flip – flops in SSI circuit
series through various registers in computer in MSI circuit series to micro – processor bit
– slice chips in the LSI series.

The basic circuit of the TTL family is the NAND gate . However, at present, NOR, OR
and AND gate configurations have also been added to the series.
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TTL Sub – families
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TTL series has several sub families having different speed and power dissipation
characteristics as detailed below.

1. 74L00 series – the letter L standing for low power consumption. It has an
average power dissipation of 1 mW per gate but an average propagation delay of 33 ns.

2. 74H00 series – the letter H standing for highest speed. It has a propagation
delay 6 ns but an average power dissipation of 23 mW per gate.

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3. 74S00 – the letter S representing Schottky. It has the highest speed because its
average propagation delay is just 3 ns per gate. However, its average power dissipation is
23 mW per gate.

4. 74LS00—it is the most recent variant of TTL family. It is called low-power

Schottky TTL. It has an average propagation delay of 9.5 ns and an average power
dissipation of 2 mW.

1.2.14 Computer Languages

Computers recognize and operate in binary numbers. However, each computer has its
own binary words, meanings, and language, The words are formed by combining a
number of bits for a given machine. The word (or word length) is defined as the number
of bits the computer recognizes and processes at a time. The word length ranges from 4
bits for small, microprocessor based computers to 32 bits for large computers as IBM
370. Another term commonly used to express word length is byte. A Byte is defined as a
group of 8 bits. For example, a 16 bit microprocessor has a word length equal to 2 bytes.
The term nibble, which stands for a group of 4 bits, is found also in popular computer
magazine and books. A byte has two nibbles.

Each machine has its own set of instructions based on the design of its CPU or of its
microprocessor. To communicate with the computer, one must give instructions in binary
language (machine language) . Since it is difficult for most people to write programs in
sets of 0s and 1s, computer manufactures have devised English like words to represent
the binary instructions of a machine. Programmer’s can write programs, called assembly
language programs, using these words. Because an assembly language is specific to a
given machine, programs written in assembly language are not transferable from one
machine to another. To circumvent this limitation, such general purpose languages as
BASIC and FORTRAN have been devised, a program written in these languages can be
machine independent. These languages are called high-level languages.

MACHINE LANGUAGE

The number of bits in a word for a given machine is fixed, and words are formed through
various combinations of these bits. For example, a machine with a word length of 8 bits
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can have 256 (2^8) combinations of bits --- thus a language of 256 word. However, not
all of these words need be used in the machine. The microprocessor design engineer
selects combinations of bit patterns and gives a specific meaning to each combination by
using electronic logic circuits; this is called an instruction. Instructions are made up of
one word or several words. The set of instructions designed into the machine makes up its
machine language, a binary language, composed of 0s and 1s, that is specific to each
computer. The microprocessor determines the machine language and the operations of a
microcomputer.

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ASSEMBLY LANGUAGE

The first step in the evolution of programming languages was the development of what is
known as an assembly language. In an assembly language, mnemonics are used to
represent operation codes, and strings of characters to represent addresses. We give in
Table 1.15 a machine language program and the corresponding assembly language
program. It may be observed from this table that there is a one-to-one correspondence
between the assembly language program and the equivalent machine language program.
As an assembly language is designed mainly to replace each machine code with an
understandable mnemonic and each address with a simple alphanumeric string, it is
matched to a particular computer’s processor structure. It is thus machine dependent. It
is necessary for an assembly language programmer to know all details of a computer’s
logical structure in order to write a program. It thus suffers from many of the
disadvantages of machine language.

Table 1.15 An assembly program and a machine language equivalent

Assembly code Machine code

Operation Operand Operation Operand

address address

READ K A 200
READ L A 201
READ M A 202
READ N A 203
CLA K 1 200
ADD L 2 201
ADD M 2 202
ADD N 2 203
STO W 6 204
PRT W B 204
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HLT F

In order to execute an assembly language program on a computer, it should first be

translated to its equivalent machine language program. This is necessary because the
computer’s circuitry is designed to execute only the operation codes of the machine. The
mnemonic operation codes should be converted to absolute numeric operation codes.
The symbolic addresses of operands used in assembly language should also be converted
to absolute numeric addresses. The translator which does this is known as an assembler
(see Fig 1.13). The input to an assembler is the assembly language program and is

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known as the source program. Its output is the equivalent machine language program
and is known as the object program. The assembler is a system program which is
supplied by the computer manufacturer. It is writer by system programmers with great
care.

Fig. 1.13. Depicting an assembler

The main advantage of using an assembly language for programming is the efficiency of
the machine language program resulting from it. As all hardware features available in the
processor of the computer, such as registers, stacks, etc., are available to the assembly
language programmer, he has great flexibility in writing programs well-matched to the
computer.

The main disadvantages of an assembly language are:

(i) It is machine-dependent. Thus programs writer for one model of a
computer cannot be executed on another model. In other words it is not portable from
one machine to another.
(ii) An assembly language programmer must be an expert who knows all
about the logical
structure of the computer.
(iii) Writing assembly language programs is difficult and time-consuming.

The trend is thus to avoid using an assembly language. It is used only when efficiency is
of paramount importance or when there is a need to control input/output devices.

Efficiency is important, for instance, if a command to control an aircraft is to be given in

a specified time. In cost-sensitive applications for instance, when a microprocessor based
controller is used as a consumer item such as a washing machine, the program is stored in
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a Read Only Memory and the size of ROM determines the cost. The control program has
to be concise and Assembly Language ensures this.

Executing Assembly Language Program

Before a machine language program can be executed it must be stored in the memory of
the computer. The program itself may be stored in a floppy disk. This program is to be
read into memory by another program called loader which is already stored in the
memory. The loader, or initial program load (IPL) is automatically stored in the memory
by the hardware of the computer when the computer is switched on. In cheaper

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computers this program (in binary form) is loaded manually by the operator using
console switches.

The loader program should be kept small. Thus a procedure is used whereby the first few
instructions of the loader load the rest of the loader program. This is called bootstrap
loading.

In order to execute an assembly language program, we must first store the loader. The
loader than reads the assembler from a peripheral memory (such as a disk) and stores it in
the main memory. The assembler would be written in machine language and can thus
directly be stored in memory. The assembler now reads each instruction of the assembly
language, translates it into a machine language statement, and stores it in the main
memory. When the entire assembly language is translated and stored, control is passed to
the first instruction of the assembled user program. This program now starts execution.
The progression of storing various programs in main memory is illustrated in Fig. 1.14.
It may be observed from Fig. 1.14 that only part of the main memory is available to store
a user’s program. The available free memory for user programs is usually specified by
the manufacturer.

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Fig. 1.14. Illustrating memory allocation for loader and assembler

The assembler is a machine language program. Since machine language programs are
difficult to write, it would be preferable to keep them small. One method of doing it
would be to define an assembly language with minimal features and write an assembler

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for this language. A higher level assembly language may then be defined (for example
one which allows expressions for addresses). A program in this higher level assembly
language may be translated by a program written in the rudimentary assembly language
for which a translator already exists. This is a very powerful method and is called
bootstrap method. Figure 1.15 illustrates this.

Fig. 1.15 Illustrating bootstrap method of writing translators (Boxes 1 and 2 are
identical)

HIGHER LEVEL PROGRAMMING LANGUAGES

During the evolution of computers, till about 1955, computers were slow, and had a small
memory. Thus programming efficiency was very important and assembly language was
dominant. The use of computers was also limited to a small group of scientists. With
improvements in technology, computers were designed with larger memory capacity,
higher speed and improved reliability. The tremendous potential of computer
applications in diverse areas was foreseen. It was evident that this potential could be
realized only if a non-expert user could effectively use the computer to solve problems.
It was thus clear that a user should be concerned primarily with the development of
appropriate algorithms to solve problems of interest to him and not with the details of the
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internal logical structure of computer. Consequently a good notation to express
algorithms became an essential requirement. It would be ideal if an algorithm written in
a natural (spoken) language such as English were translated to machine language
automatically by the computer and executed. This is not possible because natural
languages are not precise or unambiguous. The interpretation of the meaning of a natural
language sentence depends on the context also. For example, the sentence “Give me a
ring” may mean either give me a ring to wear or a ring on the telephone depending on the
context. In fact the whole profession of lawyers would be redundant if sentences had
unique interpretation!

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Thus if algorithms are to be executed by computers, it is necessary to develop a simple,

concise, precise and unambiguous notation to express them. The notation should also
match the type of algorithm. For example, algorithms to solve science and engineering
problems would have complex arithmetic operations and would use mathematical
functions such as tan x, cos x, etc. Thus a notation to express such algorithms should
include complex arithmetic operations and mathematical functions. On the other hand,
algorithms for processing business data would have operations to be performed on
massive amounts of organized data known as files. Arithmetic to be performed would be
very simple. The notation in this case must facilitate describing files and procession files.
Such notations used to express algorithms are known as high level procedure
oriented programming languages.
In general, a high level language to express algorithms must have the following
features:
(i) Facility to describe the nature of the data to be processed. For example
specifications of integers, reals, complex numbers, characters, etc., are required
depending on the nature of the application area and the associated algorithm. Besides
individual data items, collection of similar types of data making up a composite, known
as a data structure, is very important in developing algorithms. Examples of data
structures are arrays, matrices, sets, and strings of characters. Each high level language
has the facility to describe some of these structures depending on the area of application
of the language. Rigid specification of variable type is one of the most important features
of high level procedure oriented programming languages.

(ii) Operators which are appropriate to the data items and data structures in the
language. For example, if we have a facility to represent complex numbers, then,
complex addition, subtraction, multiplication and division operations would be useful.

(iii) A set of characters using which symbols in the language are constructed. These
symbols have a precise meaning in the context of the language. For example, the symbol
** is used to represent the exponentiation operation in FORTRAN. Thus A**B would
mean raising A to the power B.

(iv) Control structures to sequence the operations to be performed are important. In

most algorithms one would find alternate set of statements to be performed on the basis
of testing a condition. Repetition of groups of statements is also necessary in many
algorithms. Thus a high level language should provide control structures appropriate to
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express algorithms. For example, a common control structure found in a high level
language is:

if A > B then X := Y + Z else X := P + Q;

which means “compare the numbers stored in A and B. If the number stored in A is
larger than that stored in B then add the number stored in Y to that stored in Z and place
it in X, otherwise add the number stored in P with that stored in Q and place it in X””.
A repetition structure, for example, is
I := 0;

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Repeat
I := I =1;
SUM := SUM + N;
N := N + 5;
Until (I = 10);

(v) A set of words each with a precise and unambiguous meaning and a role to play
in creating the program. For example the words READ, WRITE, DO have specific
meanings in the context of a programming language.

(vi) A set of syntax rules which precisely specify the combination of words and
operators permissible in the language. For example, a language may specify that A * B is
a legal combination in a language whereas A*/B may be illegal. The syntax rules are
rules of grammar valid for the language. These rules are derived systematically and their
number is kept small to enable users to memorize them.

(vii) A set of semantic rules which assign a single precise and unambiguous meaning to
each legal syntactic structure in the languages. For example, the statement: C = B/D
would have the meaning “Divide the number stored in B by the one stored in D and store
the result in C” in a particular high level language.

A syntactically correct statement is not necessarily semantically meaningful. In natural

language (English) for instance the sentences:

“Ram plays football”

“Football plays Ram”

are both syntactically correct. The second sentence, however, is semantically

meaningless. Similarly the statement C = B/D would be semantically incorrect if D
happens to be zero. In high level languages for computers, there should be no semantic
ambiguity. Each syntactically correct structure should have one and only one semantic
interpretation. This is in contrast with natural languages.

The syntax and semantic rules of the language, besides being concise and precise, should
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aid in understanding the program. An understandable program is self-documenting and
thus easily maintainable. One chooses words in the language which have meanings
similar to their meanings in English usage.

Besides this, the facility to intersperse the program with comments (which are not part of
the program) should be provided to aid program understanding.

High level languages are designed independent of the structure of a specific computer.
This facilitates executing a program written in such a language on different computers.
Associated with each high level language is an elaborate computer program which

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translates it into the machine language of the computer in which it is to be executed. The
translator program is normally written in the assembly language of that computer. Figure
1.16 explains various terms used in high level language translation. Figure 1.17
illustrates how machine independence is achieved by using different translators t translate
a high level language program to machine languages of different computers.

Fig. 1.16. Illustrating terminology used in High level language translation.

Fig. 1.17. Illustrating machine independence of High level language.

In Table 1.16 we illustrate a small program written in a high level language called BASIC
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and the equivalent machine language program of HYPCOM. Observe that one high level
language statement is translated into many machine language statements. This is one-to-
many translation. The terminology, high level language, arises due to this. An assembly
language is a low level language as its translation to machine language is one-to-one. It
is possible to translate a high level language to one at a lower level, but the reverse is not
always possible.

There are two approaches to writing language translators. One method is to take one
statement of a high level language at a time and translate it into a machine instruction
which is immediately executed. This is called an interpreter. Interpreters are easy to

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write and they do not require large memory space in the computer. The main
disadvantage of interpreters is that they require more time to execute on a computer.

The other approach to translation is to store the high level language program, scan it and
translate the whole program into an equivalent machine language program. Such a
translator is known as a compiler. A compiler is a complex program compared to an
interpreter. It takes more time to compile than to interpret. However, a compiles
machine language program runs much faster than an interpreted program.

Table 1.16. A basic program and its HYPCOM machine language equivalent

BASIC PROGRAM MACHINE LANGUAGE

10 READ K, L, M, N A 200
20 LET W = K + L + M + N A 201
A 202
A 203

30 PRINT W
40 END 1 200
2 201
2 202
2 203
6 204

B 204

The difference between an interpreter and a compiler may be understood with the help of
the following analogy. Suppose we want to translate a speech from Russian to English.
There are two approaches one can use. The translator can listen to a sentence in Russian
and immediately translate it to English. Alternatively, the translator can listen to the
whole passage Russian and then give the equivalent English passage. If the speaker
repeats the same or a similar sentence, then, in the first case, the equivalent English
sentence will also be repeated. In the second case, the translation will be more concise as
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the English equivalent of a whole passage will be given and there will be no repetitions.
A person who can translate a whole passage has to be a better translator and must
remember more information than one who translates sentence-by-sentence. An
interpreter is similar to sentence-by-sentence translation whereas a compiler is similar to
translation of the whole passage.

High level languages which have the power to express a general class of algorithms are
known as procedure oriented languages. These languages express in detail the procedure
used to solve a problem. Another class of high level languages is called problem oriented
languages. These languages are designed to solve a narrower class of problems. A user

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of such a language need not express in detail the procedure used to solve the problem.
Ready-made procedures are preprogrammed. The user merely presents the input data to
the program in a flexible “language”. For example, a problem oriented language called
STRESS (STRuctural Equation System Solver) accepts a description of a set of equations
to be solved in a simple format of the type:

NODE 5 IS AT X = 25.5, Y =20.7, Z = 10.5

BEAM BETWEEN NODES 5 AND 15
………………………………………
………………………………………

It then generates the equations to be solved, invokes built-in algebraic equation solution
program and solves the problem. The user need not specify how to solve the problem.
He merely has to state what problem is to be solved using the appropriate language.

Recent popular problem oriented languages are MATLAB and MATHEMATICA.

MATLAB is popular among scientists and engineers to solve a wide class of problems
modeled by differential equations, and matrices. MATHEMATICA is used to simplify
complex algebraic expressions, find expressions resulting from indefinite integration and
similar symbol manipulation problems.

COMPILING HIGH LEVEL LANGUAGE PROGRAM

In this section we will discuss briefly the steps in compiling a high level language
program to an executable machine language program. Broadly the compilation process
consists of two steps. The first step is the analysis of the source program and the second
is the synthesis of the object program in the machine language of the specified machine
(Fig. 1.18). The analysis step uses the precise description of the source programming
language. A source language is described using Lexical rules, Syntax rules and Semantic
rules.

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Fig. 1.18 Block diagram of a language processor

Lexical rules specify the valid syntactic elements or words of the language. Syntax rules
specify how the valid syntactic elements are combined to form statements of the
language. Semantic rules assign meaning to valid statements of the language.
Consider, for example, the following statement in a high level language.

Principal := principal * ( 1 + rate/100)

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The syntactic elements of the statement are:

Principal, := , *, ( , 1, +, rate, /, 100, and )

The syntactic elements principal and rate are called identifiers. The symbols :=, +, and /
are operators. The numbers 1 and 100 are integer constants and the symbols (,) and ; are
called delimiters. Each syntactic element is defined using the syntax rules of the
language. The syntax rules are given using a notation called Backus Naur form
abbreviated BNF in honor of Backus and Naur who invented this notation to describe
computer languages. Each syntactic unit is given a name and shown as <name>. For
example the syntactic unit digit is defined as:

<digit>  0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |

The arrow  represents “defined as” and the vertical bar | is used to represent “or”. The
above definition is thus read as: <digit> is defined as 0 or 1 or 2 or 3 or 4 or 5 or 6 or 7 or
8 or 9. We define letter as:

<letter>  a | b | c ….. x | y | z

In other words a <letter>is any one of the lower case English letters. These characters are
combined to form a syntactic unit called <identified> which is defined as:

<identifier> := <letter> | <identifier><letter>|<identifier><digit>

Observe that the above definition is defined in terms of itself. This is called a recursive
definition. Using this rule the following are valid identifiers:

p, pr, pr2, principal

as p is an <identifier> and pr is an <identifier> followed by a <letter> r which is also an

<identifier>. Following this argument pr followed by a <digit>, namely, 2 is also an
<identifier>. The reader can verify that principal is a valid identifier as it conforms to
these rules. On the other hand the following are not valid identifiers as they violate
syntax rules.
2p, 2 + p, p – 2, ? x, x; y
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Some other rules are:
<a.o.>  + | - | * | /

where <a.o.> is abbreviation for <arithmetic operator>

<delimiters>  ) | ( | ;
<assignment operators>  :=

Having defined the “words” of the language, we next define how “sentences” of the
language are formed using syntax rules. Some of the rules are given below:

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<arithmetic expression>  <identifier><a.o.><identifier> where <a.e.> is

abbreviation for arithmetic expression <a.e.> <(a.e.)>
<a.e.>  <a.e.> <a.o.> <a.e.>

An arithmetic statement is defined as:

<arithmetic statement>  <identifier> := <a.e.>. Using the above rule and the rules
given earlier defining <a.e.> it can be verified that

principal := principal * ( 1 + rate/100 )

is a syntactically correct arithmetic statement. Next we have to assign meanings to

syntactically correct units. In the above example the semantic interpretation of the
computation is:
Compute the value of the expression on the right hand side of := and replace the
value stored in the variable name principal by this value. The rules on how to compute
the arithmetic expression should also be specified as semantic rules. The steps used in the
process of translating a high level language source program to executable code are given
in Fig. 1.19. The first block is a lexical analyzer (or scanner). It reads successive lines of
a program and breaks them into individual lexical items, namely, identifier, operator,
delimiter etc., and attaches a type tag to each of these. Besides this it constructs a symbol
table for each identifier and finds the internal representation of each constant. The
symbol table is used later to allocate memory to each variable.

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Fig. 1.19 Steps in translation of high level language to machine language

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The second stage of translation is called syntax analysis or parsing. In this phase using
the results of lexical analysis identifies expressions, statements, declarations etc.. Syntax
analysis is aided by using techniques based on formal grammar of the programming
language.

In the semantic analysis phase the syntactic units recognized by the syntax analyzer are
processed. An intermediate representation of the final machine language code is
produced. This phase bridges the analysis and synthesis phases of translation (see Fig.
1.18).

The last phase of translation is code generation. A number of optimizations to reduce the
length of machine language program are carried out during this phase. The output of the
code generator is the machine language program of the specified computer. If a
subprogram library is used for if some subroutines are separately translated and compiled
a final linking and loading step is needed to produce the complete machine language
program ready for execution. If subroutines are separately compiled the addresses of the
resulting machine language instructions will not be their final address when all the
routines are place together In main memory. The linker’s jobs are to find the correct
locations of the final executable program. The loader will then place them in the memory
at their right addresses.

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1.3 Revision Points

Number System
A number system is a set of numbers, or number like objects, together with one or more
operations, such as addition or multiplication.

ASCII
The ASCII stands for American Standard Code for Information Interchange. The ASCII
code is widely used in small computers, peripherals, instruments and communication
devices. It is a 7-bit code.

Flip – Flop
A flip – flop is a binary storage device. It can store binary bit either 0 or 1. It has two
stable states: HIGH and LOW, i.e, 1 or 0.

1.4 Intext Questions

1. Why does a computer use binary numbers for its internal processing?
2. What is a hexadecimal number system? What are its advantages over BCD
system?
3. What is BCD system? Where is it used?
4. What is 1’s complement of a binary number?
5. What is 2’s complement of a binary number?
6. What do you understand by ASCII? Discuss their area of applications.
7. What are logic gates? Discuss AND and OR gates with their truth tables.
8. What are register?
9. What is a counter?
10. What are the functions of buffers?
11. What do you understand by the term machine language?

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12. What is an assembly language for a computer?
13. What is an assembler?
14. What is a high level language?

1.5 Summary
 A computer understands information composed of only zeros and ones.
 In the binary number system there are only two digits 0 and 1.
 The binary digits are called bits.

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 In BCD code a decimal digit is represented by four binary bits.

 The base of the hexadecimal number system is 16.
 George Boole a mathematician developed an algebra known as Boolean
algebra.
 The set of programs which provides the environment to write application
programs is known as the system software.
 A program written using the binary codes specified for the processor’s
operations and absolute binary memory addresses is known as the machine
language of the computer.
 An assembly language has a one-to-one correspondence with the machine
language of a computer and is thus machine is dependent.
 A program written in a high level language is converted to a machine
language program by a translator program.
 Translators are of two types: interpreter and compiler. An interpreter
translates a program, one statement at a time and immediately executes it. A
complier on the other hand translates the entire program into lower level
language and then executes it.
 Boolean expressions corresponding to truth tables may be implemented as
logic circuits using AND, OR and NOT gates.
 Syntax rules of a language are often described using a notation known BNF
notation.
 A hexadecimal digit is represented by four binary bits.
 The addition of 2’s complement of a number is equivalent to the subtraction
of the number.
 The base of the hexadecimal number system is 16.
 The 2’s complement is used to represent the negative of a binary number.
 A flip-flop is the basic memory unit.
 The function of a digital counter is to count the number of electrical pulses.
 Each machine has its own set of instructions based on the design of its CPU or
of its microprocessor.
 The microprocessor design engineer selects combinations of bit patterns and
gives a specific meaning to each combination by using electronic logic
circuits; this is called an instruction.
 The main advantage of using an assembly language for programming is the

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efficiency of the machine language program resulting from it.

1.6 Terminal Exercises

1. Find the 2’s complement of the following numbers: (i) 1101, (ii) 1100 (iii)
0100, (iv) 0110.
2. Find the 1’s complement of the following numbers: (i) 0101, (ii) 11011 (iii)
0000, (iv) 1111.

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3. Convert the following decimal numbers to equivalent binary numbers: (i)38,

(ii) 41, and (iii) 89.
4. Convert the following hexadecimal numbers to equivalent decimal numbers:
(i) 5D, (ii) 76, (iii)5A3
5. Convert the following decimal numbers to equivalent hexadecimal numbers:
(i) 129, (ii) 109, (iii) 76, (iv) 99.
6. Convert the following binary numbers to equivalent hexadecimal numbers: (i)
101010, (ii) 1101101, (iii) 1011000 (iv) 10010111.
1.7 Supplementary Materials

1. Ramesh S. Goankar ,“Microprocessor Architecture & Applications”, Third

Edition , Penram international Publishing (India),1997.
2. Mathur, “ Introduction to Microprocessors”, Third Edition, TMH.

1.8 Assignments

1. Discuss the advantages and applications of Number systems.

2. A Case Study: Computer Languages and its different types.

1.9 Suggested Reading/Reference Books/Set Books

1. “Introduction to Microprocessor, Software, Hardware programming “,

L.A.Levanthal.
2. “Fundamentals of Microprocessor”, B.Ram, Dhanapat Rai & Son’s

1.10 Learning Activities

1. Collect information on Number system.
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2. Collect research reports and information on computer languages.

1.11 Keywords

Binary Number System

Hexadecimal Number System
Binary Coded Decimal (BCD)
ASCII

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UNIT – II

2.0 Introduction
A microcomputer system consists primarily of four components – the
microprocessor, memory, input and output – as discusses in the previous chapter. The
microprocessor manipulates data, controls timing of various operations, and
communicates with such peripherals (devices) as memory and I/O. The internal logic
design of the microprocessor, called its architecture, determines how and what various
operations are performed by the microprocessor. The system bus provides path for data
flow.

2.1 Objective
This chapter expands on the bus concept and shows how data flow externally
among the components of the system. The chapter deals with the internal architecture
and various operations of the microprocessor in the context of the 8085/8080A. It also
expands on topics such as memory and I/O, and reviews interfacing devices such as
buffers, decoders, and latches, in a microcomputer system

2.2 Content
2.2.1 Microprocessor Architecture And Its Operations

The microprocessor is a programmable logic device, designed with registers, flip-

flops, and timing elements. The microprocessor has a set of instructions designed
internally, to manipulate data and communicate with peripherals. This process of data
manipulation and communication is determined by the logic design of the
microprocessor, call the architecture.

The microprocessor can be programmed to perform functions on given data by selecting

necessary instructions from its set. These instructions are given to the microprocessor by
writing them into its memory. Writing (or entering) instructions and data is done through
an input device such as a keyboard. The microprocessor reads or transfers each
instruction one at a time, matches it with its instruction set, and performs the data
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manipulation indicated by the instruction. The result can be stored in memory or sent to
such output devices as LEDs or a CRT terminal. In addition, the microprocessor can
respond to external signals. It can be interrupted, reset, or asked to wait to synchronize
with slower peripherals. All the various functions performed by the microprocessor can
be classified in three general categories:

1. Microprocessor-initiated operations
2. Internal data operations
3. Peripheral (or externally) initiated operations

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To perform these functions, the microprocessor requires a group of logic circuits and a
set of signals called control signals. However, early processors do not have the necessary
circuitry on one chip; the complete units are made up of more than one chip. Therefore,
the term Micro Processing Unit (MPU) is defined here as a group of devices that can
perform these functions with the necessary set of control signals. This terms is similar to
the term Central Processing Unit (CPU). However, later microprocessors include most of
the necessary circuitry to perform these operations on a single chip. Therefore, the terms
MPU and microprocessor often are used synonymously.

The microprocessor functions listed above are explained here in relation to the 8085 or
8080A MPU. The explanation does not include either the details of the MPUs or the
differences between the 8085 and 8080A microprocessors. The devices necessary to
make up the 8085 and 8080A MPUs will be discussed later.

2.2.2 Microprocessor-Initiated Operations and 8085/8080A Bus Organization

The MPU performs primarily four operations:

1. Memory Read: Read data from memory.

2. Memory Write: Writes data into memory.
3. I/O Read: Accepts data from input devices.
4. I/O Write: Sends data to output devices.

All these operations are part of the communication process between the MPU and
peripheral devices (including memory). To communicate with a peripheral (or a memory
location), the MPU needs to perform the following steps:

Step 1: Identify the peripheral or the memory location (with its address).
Step 2: Transfer data.
Step 3: Provide timing or synchronization signals.

The 8085/8080A MPU performs these functions using three sets of communication lines
called buses: the address bus, the data bus, and the control bus (Figure 2.1). In the figure
buses are shown as one group, called the system bus.

ADDRESS BUS
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The address bus is a group of sixteen lines generally identified as A0 to A15. The address
bus is unidirectional: bits flow in one direction – from the MPU to peripheral devices.
The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location (Step 1).

In a computer system, each peripheral or memory location is identified with a binary

number, called an address, and the address bus is used to carry a 16-bit address. This is
similar to the postal address of a house. The number of a house can be identified with
various number schemes. For example, the forty-fifth house in a lane can be identified

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with two-digit number 45, or with the four-digit number 0045. The two-digit numbering
scheme can identify ten thousand houses, from 0000 to 9999. Similarly, the number of
address lines of the MPU determines its capacity to identify different memory locations
(or peripherals). The 8085/8080A MPU with its sixteen address lines is capable of
addressing 216 = 65536 (generally known as 64K) memory locations. Generally 1K
memory is determined by rounding off 1024 to the nearest thousand; similarly, 65536 is
rounded off to 64000 as a multiple of 1K.

Most 8-bit microprocessors have sixteen address lines. This may explain why most
microcomputer systems have 64K memory – however, not every microcomputer system
has 64K memory. In fact, most single-board microcomputers have memory less than 2K,
even if the MPU is capable of addressing 64K memory. The number of address lines is
arbitrary; it is determined by the designer of a microprocessor based on such
considerations as availability of pins and intended applications of the processor. For
example, the MOS Technology MCS 6515 microprocessor has twelve address lines and
is capable of addressing 4K (212 = 4096) memory. Another example is the Motorola
68000, which has 23 address lines.

Fig 2.1 The 8085/8080A Bus Structure

DATA BUS
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The data bus is a group of eight lines used for data flow (Figure 2.1). These lines are
bidirectional – data flow in both directions between the MPU and peripheral devices.
The MPU uses the data bus to perform the second function: transferring data (Step 2).

The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =
256 numbers). The largest number that can appear on the data bus is 11111111 (25510).
The data bus influences the microprocessor architecture considerably. It determines the
word length and the register size of a microprocessor; thus the 8085/8080A
microprocessor is called an 8-bit microprocessor. Microprocessors such as the Inter

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8086, Zilog Z8000, and Motorola 68000 have sixteen data lines; thus they are known as
16-bit microprocessors.

CONTROL BUS
The control bus is comprised of various single lines that carry synchronization signals.
The MPU uses such lines to perform the third function: providing timing signals (Step 3).
The term bus, in relation to the control signals, is somewhat confusing. These are
individual lines that provide a pulse to indicate an MPU operation. The MPU generates
specific control signals for every operation (such as Memory Read or I/O Write) it
performs. These signals are used to identify a device type with which the MPU intends
to communicate.

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Fig 2.2 Memory Read Operation

To communicate with a memory – for example, to read an instruction from a memory

location – the MPU places the 16-bit address on the address bus (Figure 2.2). The
address on the bus is decoded by an external logic circuit, which will be explained later,
and the memory location is identified. The MPU sends a pulse called Memory Read as
the control signal. The pulse activates the memory chip, and the contents of the memory
location (8-bit data) are placed on the data bus and brought inside the microprocessor.

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What happens to the data byte brought into the MPU depends on the internal architecture
of the microprocessor, which we will describe in the next section.

Internal Data Operations and the 8085/8080A Registers

The internal architecture of the 8085/8080A microprocessor determines how and what
operations can be performed with the data. These operations are
1. Store 8-bit data.
2. Perform arithmetic and logic operations.
3. Test for conditions.
4. Sequence the execution of instructions.
5. Store data temporarily during execution in the defined R/W memory locations
called the stack.
To perform these operations, the microprocessor requires registers, arithmetic logic unit
(ALU) and control logic, and internal buses (paths for information flow). Figure 2.3 is a
simplified representation of the 8085/8080A internal architecture; it shows only those
registers which are programmable, meaning those register that can be used for data
manipulation by writing instructions. These registers are described in reference to the
five operations previously listed.

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Fig 2.3 The 8085 / 8080A Programmable Registers

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REGISTERS

The 8085/8080A has six general-purpose registers to perform the first operation listed
above; that is, to store 8-bit data during a program execution. These registers are
identified as B, C, D, E, H, and L, as shown in Figure 2.3. They can be combined as
register pairs – BC, DE, and HL – to perform some 16-bit operations.

ACCUMULATOR

The accumulator is an 8-bit register that is part of the arithmetic logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The
result of an operation is stored in the accumulator. The accumulator is also identified as
register A.

FLAGS

The ALU includes five flip-flops that are set or reset according to data conditions in the
accumulator and other registers. The microprocessor uses them to perform the third
operation; namely, testing for data conditions.

For example, after an addition of two numbers, if the sum in the accumulator is larger
than eight bits, the flip-flop that is used to indicate a carry, called the Carry flag (CY) is
set to one. When an arithmetic operation results in zero, the flip-flop called the Zero flag
(Z) is set to one. The 8085/8080A has five flags to indicate five different types of data
conditions. They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary
Carry (AC) flags. The most commonly used flags are Zero and Carry; the others will be
explained as necessary.

Figure 2.3 shows an 8-bit register, called the flag register, adjacent to the accumulator. It
is not really a register, five bit positions, out of eight, are used to store the outputs of the
five flip-flops. The flags are stored in the 8-bit register so that the programmer can
examine these flags (data conditions) by accessing the register through an instruction. In
the instruction set, the term PSW (Program Status Word) refers to the accumulator and
the flag register. This term will be discussed again in Chapter 8: Stack and Subroutines.

These flags have critical importance in the decision-making process of the

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microprocessor. The conditions (set or reset) of the flags are tested through software
instructions. For example, the instruction JC (Jump On Carry) is implemented to change
the sequence of a program when the CY flag is set. The importance of the flags cannot
be emphasized enough; they will be discussed again in applications of condition jump
instructions.
PROGRAM COUNTER (PC)

This 16-bit register deals with the fourth operation, sequencing the execution of
instructions. This register is a memory pointer. Memory locations have 16-bit address,
and that is why this is a 16-bit register.

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The microprocessor uses this register to sequence the execution of instructions. The
function of the program counter is to point to the memory address from which the next
byte is to be fetched. When a byte (machine code) is being fetched the program counter
is incremented by one point to the next memory location.

STACK POINT (SP)

The stack pointer is also a 16-bit register used as a memory pointer; initially, it will be
called the stack pointer register to emphasize that it is a register. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by
loading a 16-bit address in the stack pointer (register).

Peripheral or Externally Initiated Operations

External devices (or signals) can initiate the following operations, for which individual
pins on the microprocessor chip are assigned: Reset, Interrupt, Ready, Hold.

Reset: When the reset is activated, all internal operations are suspended and the program
counter is cleared (it holds 0000H). Now the program execution can again begin at the
zero memory address.

Interrupt: The microprocessor can be interrupted from the normal execution of

instructions and asked to execute some other instructions called service routine (for
example, emergency procedures). The microprocessor resumes its operation after
completing the service routine.

Ready: The 8085/8080A has a pin called READY. If the signal at this READY
pin is low, the microprocessor enters into a Wait state. This signal is used primarily to
synchronize slower peripherals with microprocessor.

Hold: When the HOLD pin is activated by an external signal, the microprocessor
relinquishes control of buses and allows the external peripheral to use them. For
example, the HOLD signal is used in Direct Memory Access (DMA) data transfer.

2.2.3 MEMORY

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Memory is an essential component of a microcomputer system. It stores binary
instructions and data for the microprocessor. Two types of memory were identified:
Read/Write Memory (R/WM) and Read-Only Memory (ROM). The R/W Memory is
made of registers, and each register has a group of flip-flops that stores bits of
information. The number of bits stored in a register is called a memory word; memory
devices (chips) are available in various word sizes. The MPU can read from or write into
this memory. The second type of memory, the ROM, stores information permanently in
the form of diodes; a group of diodes can be viewed as a register. The MPU can only
read information from the ROM; it cannot write into this memory.

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In a memory chip, all registers are arranged in a sequence and identified by binary
numbers called memory addresses. The assignment of memory addresses to various
registers in a memory chip and the process of communication between the MPU and the
memory are described below. The following discussion is equally applicable to R/WM
and ROM except for slight differences in Read/Write control signals.
Memory Organization (R/W Memory)
For an 8-bit microprocessor, memory is required to store eight bits of information as a
group; thus, the memory word length should be eight bits. To communicate with
memory, the MPU should be able to
1. Select the chip.
2. Identify the register.
3. Read from or write into the register.
Figure 2.4 shows a hypothetical memory chip of eight registers with three address lines,
one chip select (CS) line, one read/write (R/W) line, and eight I/O lines. The MPU uses
the CS line to select the chip, and the R/W line to control data flow. The registers are
arranged sequentially and numbered 0002 and 1112. These numbers are called memory
addresses, identifying each register as a memory location. To identify each register, the
MPU would require three address lines to place eight different addresses from 0002 to
1112. The 8085/8080A MPU with its sixteen address lines is capable of identifying or
addressing 65,536 (64K) such memory registers or locations.
1.

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Fig 2.4 A Memory Chip with Eight Registers

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The size of this hypothetical chip can be specified either as 8 byte, 8 x 8 bit, or 64 bit. A
memory chip with 256 registers (or locations) with 4 I/O lines is specified as 256 x 4 bit
or 1024 bit. For an 8-bit microprocessor, two such memory chips (256 x 4) would be
necessary to form the 8-bit memory word size, resulting in 256 bits of memory.

To read from or write into a memory location (e.g., register 5 in Figure 2.4), the
microprocessor places the address (1 0 1) on the address bus. The decoder decodes the
address and identifies the register. The control signal R/W enables the I/O lines, and the
data byte is either read from or stored in the memory location. The Chip Select CS line,
also known as Chip Enable (CE), is necessary to select one particular memory chip from
among several memory chips in a system. The 8085/8080A microprocessor has sixteen
address lines, and this hypothetical chip (Figure 2.4) requires only three address lines.

2.2.4 Memory Map

Memory map is defined as the assignment of addresses to memory registers in various

memory chips in a system. In a system based on the 8085/8080A microprocessor, the
entire memory map can range from 000H to FFFFH (216 = 65,536). This memory map
can be illustrated with an analogy of identical houses built in a sequence and their postal
addresses or numbers.

Let us assume that houses are given four-digit decimal numbers, which will enable us to
number ten thousand houses from 0000 to 9999. Since it is cumbersome to direct
someone to houses with large numbers, the numbering scheme can be devised with the
concept of a row or block. Each block will have a hundred houses to be numbered with
the last two digits from 00 to 99. Similarly, the blocks are also identified by the first two
decimal digits. For example, a house with the number 0247 is house number 47 in block
2. With this scheme, all the houses in block 0 will be identified from 0000 to 9999, in
block 20 from 2000 to 2099, and in block 99 from 9900 to 9999. This numbering scheme
with four decimal digits is capable of giving addresses to ten thousand houses from 0000
to 9999 (100 blocks of 100 houses each). A new area under development may have only
two blocks completed -- block 0 and block 20 -- the houses on these blocks can have
addresses 0000 to 0099 and 2000 to 2099, even if other blocks are still empty. Let us
also assume that all houses are identical, and have eight rooms.

The example of numbering the houses is directly applicable to assigning addresses to

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memory registers. In the binary number system, sixteen binary digits can have 65,536
(216) different combination. In the hexadecimal number system, sixteen binary bits are
equivalent to four Hex digits that can be used to assign addresses to 65,536 memory
registers from 0000H to FFFFH; however, it is easier to think in terms of two Hex digits
than four Hex digits. Therefore, the concept of memory page, similar to the concept of
block, can be devised, as explained below.

In a memory system, memory registers can be conceptually organized in a group to be

numbered with low-order two hexadecimal digits, similar to the last two digits of the
house address. With two Hex digits, 256 registers can be numbered from 00H to FFH;

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this is known as a page with 256 lines to read from or write on. Although the number
FFH is equal to 255, the total number of lines is equal to 256 because the first line is
numbered 0. Similarly, the high-order (first) two Hex digits can be used to number the
pages from 00H to FFH. For example, the memory address 020FH represents line 15
(register) on page 2, the address 07FFH represents line 255 on page 7, and the address
1064H represents line 100 on page 16 (64H = 10010 and 10H = 1610). The total memory
address will range from 0000H to FFFFH -- 256 pages with 256 lines each (256 x 256 =
65,536, known as 64K). To complete the analogy, a line (register) is equivalent to a
house, a page is equivalent to a block, and eight flip-flops in a register are equivalent to
eight rooms in a house.

Also in memory map we can summarize the following points.

1. In a numbering system, the number of digits used determines the maximum addressing
capacity of the system. Sixteen address lines (16 bits) of the 8085/8080A microprocessor
can address 65,536 memory registers; this is similar to four decimal digits providing the
postal addresses for ten thousand houses.

2. In a numbering system, the number of digits used can be conceptually divided in

groups. In memory addressing, low-order addresses from 00H to FFH are viewed as line
numbers, and high-order addresses are viewed as page numbers.

3. For a given memory chip, the number of address lines required to identify the registers
is determined by the number of registers in the chip. The remaining address lines can be
used for selecting the chip.

4. The memory map of a given chip can be changed by changing the hardware of the
Chip Select (CS) line. This line is also known as the Chip Enable (CE) line.

In certain cases, the memory map can be viewed as four pages, in reality, all the registers
are on one chip. This concept is similar to building four hundred houses in one block, but
conceptually viewing them as four blocks with one hundred houses in each block. The
house numbers will range from 0000 to 0399 in decimal (assuming the first house has the
number 0000).

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The preceding discussion concerning the memory map is equally applicable to the Read-
Only Memory (ROM). The ROM is in many ways organized the same as the R/W
memory. The primary difference between the organization of the two memories is in the
control signals. The ROM requires the Read signal from the MPU.

Memory and Instruction Fetch

The primary function of memory is to store instructions and data and to provide that
information to the MPU whenever the MPU requests it. The MPU requests the
information by sending the address of a specific memory register on the address bus and
enables the data flow by sending the control signal.

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Types of Memory

Memory can be classified into two groups: prime (or main memory) and storage
memory. The R/WM and ROM discussed in the last section are examples of prime
memory; this is the memory the microcomputer uses in executing and storing programs.
The storage memory includes cassette tape, magnetic tape, floppy disk, and hard disk.
The R/WM and ROM are general categories of the prime memory; they include several
types of memory listed below.

R/WM

As mentioned previously, this is a read/write memory popularly known as Random

Access Memory (RAM). This memory is volatile, meaning that when the power is
turned off, all the contents are destroyed. Two types of R/W memories are available,
static and dynamic.

Static memory is made up of flip-flops, and it stores a bit as a voltage. Dynamic

memory is made up of MOS transistor gates, and it stores a bit as a charge. The
advantage of dynamic memory is that a large number of transistor gates can be placed on
a memory chip; thus it has high density and is faster than static memory. The
disadvantage is that the charge (bit information) leaks; therefore, information needs to be
read and written again every few milliseconds. This is called refreshing the memory,
and it requires additional circuitry.

ROM

The ROM is a nonvolatile memory, meaning that it retains the stored information even if
the power is turned off. It is a read only memory. It is used for permanent storage. It has
random access property. ROMs are widely used for function tables (sine, cosine, square
root, logarithm, exponentials etc.), code conversion tables, multiplication and division
subroutines etc. The user cannot write into a ROM, it is not accessible. ROMs are simple,
cheap and dense.
Four types of ROM are presently available: Masked ROM, PROM, EPROM and EE-
PROM.

MASKED ROM
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In this ROM, the masking and metalization process, an expensive and specialized process
permanently record a bit pattern. Memory manufacturers are generally equipped to do
this process, but it is economical only for production quantities in the thousands.

PROM (PROGRAMMABLE READ-ONLY MEMORY)

The user can program this memory with a special PROM programmer that selectively
burns the fuses according to the bit pattern required to be stored. The process is known
as "burning the prom", and the information stored is permanent.

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EPROM (ERASABLE PROGRAMMABLE READ-ONLY MEMORY)

The information stored in this memory is semi permanent. All the information
can be erased by exposing the memory to ultraviolet light through a quartz window
installed on the chip. Then the memory chip can be reprogrammed again and again. This
memory is commonly used in product development and experimental projects.

EE-PROM (ELECTRICALLY ERASABLE PROM)

This memory is functionally similar to EPROM, except that using electrical signals at the
register level rather than erasing all the information can alter information. However, the
manufacturing process is quite complex, and some of the technical problems are yet to be
resolved. At present, it is expensive and not in common use.

In a microprocessor-based product, programs are generally written in ROM, and data that
are likely to vary are stored in R/WM. For example, in a microprocessor-controlled
oven, programs that run the oven are permanently stored in ROM, and data such as
baking period, starting time, and temperature are entered in R/W memory through the
keyboard. On the other hand, when microcomputers are used for developing software or
for learning purposes, programs are first written in R/W memory, and then stored on a
storage memory such as cassette tape or a floppy disk.

INPUT/OUTPUT (I/O)

The remaining components of the microcomputer system are Input/Output devices. The
MPU communicates with the "the outside world" through such devices. The MPU
accepts binary data as input from devices such as keyboards or floppy disks, and sends
data to output devices such as LEDs or printers. There are two different methods by
which the MPU identifies and communicates with the I/O devices. These methods are
known as Peripheral (or Direct) I/O and Memory-Mapped I/O. The methods differ in
terms of the number of address lines used in identifying an I/O device, the type of control
lines used to enable the device, and the instructions used for data transfer. The
8085/8080A MPU can use either eight address lines or sixteen address lines to identify an
I/O device, as discussed below.

Peripheral or Direct I/O

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In peripheral or direct I/O (also known as accumulator I/O) two instructions (IN and
OUT) are used for data transfer. The MPU uses eight address lines to send the address of
an I/O device. (Recall the analogy of postal address. The eight address lines are capable
of identifying 256 input devices and 256 output devices.) The input and output devices
are differentiated by the control signals I/O Read (IOR)(bar) and I/O Write (IOW)(bar).
Thus, in this method, I/O addresses range from 00 to FF. These addresses are known as
either I/O device addresses or I/O port numbers.

The steps in communicating with an I/O device are similar to those in communicating
with memory and can be summarized as follows:

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1. The MPU places an 8-bit device address on the address bus, which is decoded by the
external decode logic.
2. The MPU sends a control signal (I/O Read or I/O Write) and enables the I/O device.
3. Data are placed on the data bus for transfer.

Memory-Mapped I/O

In a memory-mapped I/O, the MPU uses sixteen address lines to identify an I/O device.
This process is similar to communicating with a memory location. The memory-mapped
I/O technique uses the same control signals (MEMR or MEMW) and instructions as
those of memory. The memory map (64K) is shared between memory and I/O devices.
The MPU views these I/O devices as if they were memory locations. In such
microprocessors as the Motorola 6800, there are no special I/O instructions; all I/Os are
part of the memory map.

2.2.5 Example Of A Microcomputer System

Based on the discussion in the previous sections, we can expand the microcomputer
system shown in Figure 2.1 to include additional details. Figure 2.9 illustrates such a
system. It shows the 8085/8080A MPU, two types of memory (EPROM and R/WM),
input and output, and the buses linking all peripherals (memory and I/Os) to the MPU.

The address lines A15 to A0 are used to address memory, and low-order address bus A7
to A0 is used to identify the input and the output. The data bus D7 to D0 is bidirectional
and common to all the devices. The four control signals generated by the MPU are
connected to different peripheral devices, as shown in Figure 2.5.

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Fig 2.5 Example of an Microcomputer System

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The MPU communicates with only one peripheral at a time by enabling the peripheral
through its control signal. For example, to send data to the output device, the MPU
places the device address (output port number) on the address bus, data on the data bus,
and enables the output device using the control signal IOW (I/O Write). The output
device latches and displays data if the output device happens to be LEDs. The other
peripherals that are not enabled remain in a high impedance state called tri-state, similar
to being disconnected from the system.

The preceding description mentions two new concepts: tri-state and data latching. It
suggests that the tri-state is a high impedance state. The concept of data latching suggests
the need for a device in addition to the output device. Figure 2.9 is a simplified block
diagram of the system; it does not show such details as data latching and tri-state devices.

Fig 2.6 The Output Section of the Microcomputer System illustrated in fig 2.5

Figure 2.6 shows an expanded version of the output section and the buses of Figure 2.5.
The block diagram includes tri-state bus drivers, a decoder, and a latch. The bus drivers
increase the current driving capacity of the buses, the decoder decodes the address to
identify the output port, and the latch holds data output for display. These devices are
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called interfacing devices. The interfacing devices are semiconductor chips that are
needed to connect peripherals to the bus system. Before we discuss interfacing concepts,
we will review these interfacing devices.

2.2.6 Interfacing Devices

Several types of interfacing devices are necessary to interconnect the components of a

bus-oriented system. The devices used in today's microcomputer systems are designed
using Medium-Scale Integration (MSI) technology. In addition, tri-state logic devices are
essential to proper functioning of the bus-oriented system, in which the same bus lines

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are shared by several components. The concept underlying the tri-state logic, as well as
commonly used interfacing devices, will be reviewed in the following section.

Tri-State Devices

Tri-state logic devices have three stages: logic 1, logic 0, and high impedance. The term
TRI-STATE is a trade mark of National Semiconductor and is used to represent three
logic states. A tri-state logic device has a third line called Enable as shown in Figure 2.7.
When this line is activated, the tri-state device functions the same way as ordinary logic
devices. When the third line is disabled, the logic device goes into a high impedance
state -- as if it were disconnected from the system. Ordinarily, current is required to drive
a device in logic 0 and logic 1 states. In the high impedance state, practically no current
is drawn from the system. Figure 2.7(a) shows a tri-state inverter. When the Enable is
high the circuit functions as an ordinary inverter; and when the Enable line is low, the
inverter stays in the high impedance state. Figure 2.7(b) also shows a tri-state inverter
with active low Enable line -- notice the bubble. When the Enable line is high, the
inverter stays in the high impedance state.

Fig 2.7 Tri-State Inverters with Active High and Active Low Enable Lines

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Fig 2.8 A Buffer and a Tri-State Buffer

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In microcomputer systems, peripherals are connected in parallel between the address bus
and the data bus. However, because of the tri-state interfacing devices, peripherals do no
load the system buses. The microprocessor communicates with one device at a time by
enabling the tri-state line of the interfacing device. Tri-state logic is critical to proper
functioning of the microcomputer.

Buffer

The buffer is a logic circuit which amplifies the current or power. It has one input line
and one output line (a simple buffer is shown in the first drawing of Figure 2.8). The
logic level of the output is the same as that of the input; logic 1 input provides logic 1
output the opposite of an inverter). The buffer is used primarily to increase the driving
capability of a logic circuit. It is also known as a driver.

Figure 2.8 also shows a tri-state buffer. When the Enable line is low, the circuit functions
as a buffer; otherwise it stays in high impedance state. The buffer is commonly used to
increase the driving capability of the data bus and the address bus.

Decoder

The decoder is a logic circuit that identifies each combination of the signals present at its
input. For example, if the input to a decoder has two binary lines, the decoder will have
four output lines (Figure 2.9). The two lines can assume four combinations of input
signals -00, 01, 10, 11 -- with each combination identified by the output lines 0 to 3. If
the input is 112, the output line 3 will be at logic 1, and the other will remain at logic 0.
This is called decoding.

Fig 2.9 2-to-4 (1-out-of-4) Decoder Logic Symbol

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Figure 2.9 shows a symbolic representation for a hypothetical 2:4 DECODER. It is also
called a 1 out-of-4 decoder. Various types of decoders are available; for example, 3-to-8,
4-to016 (to decode binary inputs), and 4-to-10 (10 decode BCD input). In additions,
some decoders have active low output lines as well as Enable lines, as shown in Figure
2.10. The decoder shown in Figure 2.10(b) will not function unless it is enabled by a low
signal.

2. A decoder is a commonly used device in interfacing I/O peripherals

and memory. In figure 2.6 the decoder (Port Select Decoder) is used

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to decode an address bus to identify the output device. Decoders are

built also internal to a memory chip to identify individual memory
locations.

3. Fig 2.10 3-to-8 (1-out-of-8) Decoder Logic Symbol

Encoder

The encoder is a logic circuit that provides the appropriate code (binary, BCD, etc.) as
output for each input signal. The process is the reverse of decoding. Figure 2.11 shows
an 8-to-3 encoder; it has eight active low inputs and three output lines. When the input
line 0 goes low, the output is 000; and when the input line 5 goes low, the output is 101.
However, this encoder is unable to provide an appropriate output code if two or more
input lines are activated simultaneously. Encoders called priority encoders can resolve
the problem of simultaneous inputs.

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Fig 2.11 Logic Symbols: 8-to-3 Encoder

Encoders are commonly used with keyboards. For each key pressed, the corresponding
binary code is placed on the data bus.

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Latch

In its simplest form, a latch is a D flip-flop. Two types of D flip-flops are available, as
shown in Figure 2.12; a transparent latch (a), and a positive-edge-triggered flip-flop
(b). In a transparent latch, when the clock signal is high, the output Q changes according
to the input D. When the clock signal goes low, the output Q will latch (hold) the last
value of the input D. A typical example of a latch is the 7475 D flip-flop. In a positive-
edge-triggered flip-flop, the output changes with the positive edge of the clock. The 7474
is a positive edge-triggered flip-flop.

Fig 2.12 D Flip-Flops

A latch is used commonly to interface output devices. When the MPU sends an output,
data are available on the data bus for only a few microseconds, and therefore, a latch is
used to hold data for display.

2.2.7 THE 8085 MPU

The term Micro Processing Unit (MPU) is similar to the term Central Processing Unit
(CPU) used in traditional computers. We define the MPU as a device or a group of
devices (as a unit) that can communicate with peripherals, provide timing signals, direct
data flow, and perform computing tasks as specified by the instructions in memory. The
unit will have the necessary lines for the address bus, the data bus, and the control

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signals, and would require only a power supply and a crystal (or equivalent frequency-
determining components) to be completed functional.

Using this description, the 8085 microprocessor can almost qualify as an MPU, but with
the following two limitations.

1. The low-order address bus of the 8085 microprocessor is multiplexed (time

shared) with the data bus. The buses need to be demultiplexed.
2. Appropriate control signals need to be generated to interface memory and I/O
with the 8085.

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This section shows how to demultiplex the bus and generate the control signals after
describing the 8085 microprocessor and illustrates the bus timings.

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Fig 2.13 The 8085 Microprocessor Pinout and Signals

2.2.8 The 8085 Microprocessor

The 8085 is an 8-bit general purpose microprocessor capable of addressing 64K of

memory. The device has forty pins, requires a +5 V single power supply, and can operate
with a 3-MHz single-phase clock. The 8085 is an enhanced version of its predecessor,
the 8080A; its instruction set is upward-compatible with that of the 8080A, meaning that
the 8085 instruction set includes all the 8080A instructions plus some additional ones.
Programs written for the 8080A will be executed by the 8085, but the 8085 and the
8080A are not pin compatible.

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Figure 2.13 shows the logic pinout of the 8085 microprocessor. All the signals can be
classified into six groups: (1) address bus, (2) data bus, (3) control and status signals, (4)
power supply and frequency signals, (5) interrupts and peripheral initiated signals, and
(6) serial I/O ports.

ADDRESS BUS

The 8085 has eight signal lines, A15 – A8, which are unidirectional and used as the high-
order address bus.

MULTIPLEXED ADDRESS/DATA BUS

The signal lines AD7 to AD0 are bi-directional, they serve a dual purpose. They are used
as the low-order address bus as well as the data bus. In executing an instruction, during
the earlier part of the cycle, these lines are used as the low-order address bus. During the
later part of the cycle, these lines are used as the data bus. (This is also known as
multiplexing the bus.) However, the low-order address bus can be separated from these
signals by using a latch.

CONTROL AND STATUS SIGNALS

This group of signals includes two control signals (RD and WR), three status signals
(IO/M, S1 and S0) to identify the nature of the operation, and one special signal (ALE) to
indicate the beginning of the operation. These signals are as follows.

1. ALE – Address Latch Enable: This is a positive point pulse generated every time
the 8085 begins an operation (machine cycle); it indicates that the bits on AD7 –
AD0 are address bits. This signal is used primarily to latch the low-order address
from the multiplexed bus and generate a separate set of eight address lines, A7 to
A0.
2. RD – Read: This is a Read control signal (active low). This signal indicates that
the selected I/O or memory advice is to be read and data are available on the data
bus.
3. WR – Write: This is a Write control signal (active low). This signal indicates that
the data on the data bus are o be written into a selected memory or I/O location.
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4. IO/M: This is a status signal used to differentiate between I/O and memory
operations. When it is high, it indicates an I/O operation; when it is low, it
indicates a memory operation. This signal is combined with RD (Read) and WR
(Write) to generate I/O and memory control signals.
5. S1 and S0: These status signals, similar to IO/M, can identify various operations,
but they are rarely used in small systems. (All the operations and their associated
status signals are listed in Table 2.1 for reference.)

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POWER SUPPLY AND CLOCK FREQUENCY

The power supply and frequency signals are as follows:

1. VCC: +5 volt power supply

2. VSS: Ground Reference
3. X1, X2: A crystal (or RC, LC network) is connected at these two pins. Two
internally divides the frequency; therefore, to operate a system at 3 MHz, the
crystal should have frequency of 6 MHz.
CLK (OUT) – Clock Output: This signal can be used as the system clock for other
devices.

Table 2.1. 8085 Machine Cycle Status and Control Signals

________________________________________________________________________
Status
Machine Cycle IO/M S1 S0 Control Signals
________________________________________________________________________

Opcode Fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I/O Read 1 1 0 RD = 0
I/O Write 1 0 1 WR = 0
Interrupt Acknowledge 1 1 1 INTA = 0
Halt Z 0 0
Hold Z X X RD, WR = Z and INTA =1
Reset Z X X
________________________________________________________________________

INTERRUPTS AND EXTERNALLY INITIATED OPERATIONS

The 8085 has five interrupt signals that can be used to interrupt a program execution.
One of the signals, INTR (Interrupt Request), is identical to the 8080A microprocessor
interrupt signal (INT); the others are enhancements to the 8080A. The microprocessor
acknowledges an interrupt by the INTA (Interrupt Acknowledge) signal.

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In addition to the interrupts, three pins – RESET, HOLD and READY – accept the
externally initiated signals as inputs. To respond to the HOLD request, it has one signal
called HLDA (Hold Acknowledge). The RESET is described below:

1. RESET IN: When the signal on this pin goes low, the program counter is set to
zero, the buses are tri-stated, and the MPU is reset.
2. RESET OUT: This signal indicates that the MPU is being reset. The signal can
be used to reset other devices.

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SERIAL I/O PORTS

The 8085 has two signals to implement the serial transmission. SID (Serial Input Data)
and SOD (Serial Output Data).

Bus Timings

To understand the functions of various signals of the 8085, we must examine the timings
of these signals in relation to the system clock. The best way to illustrate the timing is
through an example.

Table 2.2: 8085 Interrupts and Externally Initiated Signals

________________________________________________________________________
INTR (Input) Interrupt Request: This is used as a general-purpose interrupt; it is
similar to the INT signal of the 8080A.
INTA (Output) Interrupt Acknowledge: This is used to acknowledge an interrupt
RST 7.5 (Inputs) Restart Interrupt: These are vectored interrupts and transfer the
RST 6.5 program control to specific memory location. They have higher
RST 5.5 priorities than the INTR interrupt. Among these three, the priority
Order is 7.5, 6.5, and 5.5.
TRAP (Input) This is a nonmaskable interrupt and has the highest priority.
HOLD (Input) This signal indicates that a peripheral such as a DMA (Direct
Memory Access) controller is requesting the use of the address and
data buses.
HLDA (Output) Hold Acknowledge. This signal acknowledges the HOLD request
READY (Input) This signal is used to delay the microprocessor Read or Write
cycles until a slow responding peripheral is ready to send or accept
data. When this signal goes low, the microprocessor waits for an
integral number of clock cycles until it goes high.
_______________________________________________________________________

Example: Illustrate the timing of data flow when the instruction code 0 1 0 0 1 1 1 1
(4FH - MOV C, A), stored in location 2005H, is being fetched.

Solution : To fetch the byte (4FH), the MPU needs to identify the memory location
2005H and enable the data flow from memory. This is called the Fetch cycle. The data
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flow is shown in Figure 2.14, the timings (Figure 2.15) are explained below.

Figure 2.15 shows the timing of how a data byte is transferred from memory to the MPU;
it shows five different groups of signals in relation to the system clock. To fetch the byte,
the MPU performs the following steps:

Step 1: The program counter places the 16-bit memory address on the address bus (Figure
2.14)

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Figure 2.15 shows that at T1 the high-order memory address 20H is placed on the address
lines A15 to A8, the low-order memory address 05H is placed on the bus AD7 to AD0, and
the ALE signal does high. Similarly, the status signal IO/M goes low, indicating that this
is a memory related operation.

Fig 2.14: Data Flow from Memory to the MPU

Step 2: The control unit sends the control signal RD to enable the memory chip (Figure
2.14).
The control signal RD is sent out during the clock period T2, thus enabling the
memory chip (Fig 2.15). The RD signal is active during two clock periods.

Step 3: The byte from the memory location is placed on the data bus.

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When the memory is enabled, the instruction byte (4FH) is placed on the bus AD7
– AD0 and transferred to the microprocessor. The RD signal causes 4FH to be placed on
bus AD7 – AD0 (shown by the arrow), and when RD goes high, it causes the bus to go in
high impedance.

Demultiplexing the Bus AD7 – AD0

The need for demultiplexing the bus AD7 – AD0 becomes easier to understand after
examining Figure 2.15. This figure shows that the address on the high-order bus (20H)
remains on the bus for three clock periods. However, the low-order address (05H) is lost
after the first clock period. This address needs to be latched and used for identifying the

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memory address. If the bus AD7 – AD0 is used to identify the memory location (2005H),
the address will change to 204FH after the first clock period.

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Fig 2.15 Timing Transfer of byte from Memory to MPU

Figure 2.16 shows a schematic that uses a latch and the ALE signal to demultiplex the
bus. The bus AD7 – AD0 is connected as the input to the latch 74LS373. The ALE signal
is connected to the Enable (G) pin of the latch, and the Output control (OC) signal of the
latch is grounded.

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Figure 2.15 shows that the ALE goes high during T1. When the ALE is high, the latch is
transparent; this means that the output changes according to input data. During T1, the
output of the latch is 05H. When the ALE goes low, the data byte 05H is latched until
the next ALE, and the output of the latch represents the low-order address bus A7 – A0 for
the 8085. Figure 2.16 shows the entire address bus A15 – A0 after the latching operation.

Fig 2.16 Schematic of Latching Low – Order Address Bus

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Intel has circumvented the problem of demultiplexing the low-order bus by designing
special devices such as the 8155 (256 bytes of R/W memory + I/Os) and 8355 (2K ROM
+ I/Os), which are compatible with the 8085 multiplexed bus. These devices internally
demultiplex the bus using the ALE signal.

Generating Control Signals

Figure 2.15 shows the RD (Read) as a control signal. Since this signal is used both for
reading memory and for reading an input device, it is necessary to generate two different

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Read signals: one for memory and another for input. Similarly, two separate Write
signals must be generated.

Figure 2.17 shows that four different control signals are generated by combining
the signals RD, WR, and IO/M. The signal IO/M goes low for the memory operation.
This signal is ANDed with RD and WR signals by using the 74LS32 quadruple two-input
OR gates, as shown in Figure 2.17. The OR gates are functionally connected as negative
NAND gates. When both input signals go low, the outputs of the gates go low and
generate MEMR (Memory Read) and MEMW (Memory Write) control signals. When
the IO/M signal goes high, it indicates the peripheral I/O operation. Figure 2.17 shows
that this signal is complemented using the Hex inverter 74LS04 and ANDed with the RD
and WR signals to generate IOR (I/O Read) and IOW (I/O Write) control signals. These
control signals are unnecessary for Inter’s 8155 and 8355 devices because these signals
are generated internally using RD, WR, and IO/M signals.

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Fig 2.17 Schematic to Generate Read / Write Control Signals for Memory and I / O

To demultiplex the bus and to generate the necessary control signals, the 8085
microprocessor requires a latch and logic gates to build the MPU, as shown in Figure
2.18. This MPU can be interfaced with any memory or I/O.

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Fig 2.18 8085 Demultiplexed Address and Data Bus with Control Signals

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2.2.9 A Detailed Look at the 8085 MPU and Its Architecture

Figure 2.19 shows the internal architecture of the 8085 beyond the programmable
registers we discussed previously. It includes the ALU (Arithmetic and Logic Unit),
Timing and Control Unit, Instruction Register and Decoder, Register Array, Interrupt
Control, and Serial I/O Control.

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Fig 2.19 The 8085 Microprocessor: Functional Diagram

The ALU

The arithmetic logic unit performs the computing functions; it includes the accumulator,
the temporary register, the arithmetic and logic circuits, and five flags. The temporary
register is used to hold data during an arithmetic and logic operation. The result is stored
in the accumulator, and the flags (flip-flops) are set or reset according to the result of the
operation.

The flags are affected by the arithmetic and logic operations in the ALU. In most of
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these operations, the result is stored in the accumulator. Therefore, the flags generally
reflect data conditions in the accumulator – with some exceptions. The descriptions and
conditions of the flags are as follows:

1. S – Sign Flag: After the execution of an arithmetic or logic operation, if bit D7 of

the result (usually in the accumulator) is 1, the Sign flag is set. This flag is used
with the signed numbers. In a given byte, if D7 is 1, the number will be viewed as
a negative number; if it is 0, the number will be considered positive. In arithmetic
operations with signed numbers, bit D7 is reserved for indicating the sign, and the
remaining seven bits are used for represent the magnitude of a number.

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2. Z – Zero Flag: The Zero flag is set if the ALU operation results in 0, and the flag
is reset is the result is not 0. This flag is modified by the results in the
accumulator as well as in the other registers.
3. AC – Auxiliary Carry Flag: In an arithmetic operation, when a carry is generated
by digit D3 and passed on to digit D4, the AC flag is set. The flag is used only
internally for BCD (Binary Coded Decimal) operations, and is not available for
the programmer to change the sequence of a program with a jump instruction.
4. P – Parity Flag: After an arithmetic or logic operation, if the result has an even
number of 1s, the flag is set. If it has an odd number of 1s, the flag is reset. (For
example, the data byte 0 0 0 0 0 0 1 1 has even parity even if the magnitude of the
number is odd).
5. CY – Carry Flag: If an arithmetic operation results in a carry, the Carry flag is set;
otherwise it is reset. The Carry flag also serves as a borrow flag for subtraction.

The bit positions reserved for these flags in the flag register are as follows:

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Among the five flags, the AC flag is used internally for BCD arithmetic; the instruction
set does not include any conditional jump instructions based on the AC flag. Of the
remaining four flags, the Z and CY flags are those most commonly used.

TIMING AND CONTROL UNIT

This unit synchronizes all the microprocessor operations with the clock, and generates the
control signals necessary for communication between the microprocessor and peripherals.
The control signals are similar to a sync pulse in an oscilloscope. The RD and WR
signals are sync pulses indicating the availability of data on the data bus.

INSTRUCTION REGISTER AND DECODER

The instruction register and the decoder are part of the ALU. When an instruction is
fetched from memory, it is loaded in the instruction register. The decoder decodes the
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instruction and establishes the sequence of events to follow. The instruction register is
not programmable and cannot be accessed through any instruction.

REGISTER ARRAY

The programmable registers have been discussed in the last chapter. Two additional
registers, called temporary register W and Z, are included in the register array. These
registers are used to hold 8-bit data during the execution of some instructions. However,
since they are used internally, they are not available to the programmer.

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2.3 Revision Points

1. The 8085 microprocessor has a multiplexed bus AD7 – AD0 used as the low-order
address bus and the data bus.
2. The bus AD7 – AD0 can be demultiplexed by using a latch and the ALE signal.
3. The 8085 has a status signal IO/M and two control signals RD and WR. By
ANDing these signals, four control signals can be generated: MEMR, MEMW,
IOR and IOW.
4. The 8085 MPU

1. transfers data from a memory location to the microprocessor by using the

control signal Memory Read (MEMR – Active Low). This is also called
reading from memory
2. transfers data from the microprocessor to memory by using the control
signal Memory Write (MEMW – Active Low). This is also called writing
into memory.
3. accepts data from input devices by using the control signal I/O Read (IOR
– Active Low). This is also known as reading from an input port.
4. sends data to output devices by using the control signal I/O Write (IOW –
Active Low). This is also known as writing to an output port.

5. To execute an instruction, the MPU

1. places the memory address of the instruction on the address bus.
2. indicates the operation status on the status line.
3. send the MEMR control signal to enable the memory, fetches the
instruction byte and places it in the instruction decoder.
4. executes the instruction.

2.4 Intext Questions

1. What is a bus?
2. Why is data bus bi-directional?
3. What is the function of accumulator?
4. What is a flag?
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5. Why are program counter and stack pointer 16-bit registers?
6. What is the function of ALU?
7. What are control signals?
8. Discuss about RAM, ROM, PROM, and EPROM?
9. What is the memory word size required in an 8085 system?
10. What is a decoder?
11. What is the difference between a microprocessor and a computer?

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12. How many address lines are necessary to address two megabytes (2049K)?

2.5 Summary

 The microprocessor (MPU) primarily performs four operations: Memory

Read, Memory Write, I/O Read, and I/O Write. For each operation it
generates the appropriate control signal.
 To communicate with peripheral (and memory), the MPU identifies the
peripheral or the memory location by its address, transfers data, and provides
timing signals.
 Address bus a group of lines that are used to send a memory address or a
device address from the MPU to the memory location or peripheral.
 Data bus a group of bi-directional lines that are used to transfer data between
the MPU and peripherals (or memory).
 Control Bus single lines that are generated by the MPU to provide timing of
various operations.
 The 8085 microprocessor has six general purpose 8-bit registers t store data,
and an accumulator to perform arithmetic and logical operations.
 The accumulator is an 8-bit register that is part of the arithmetic logic unit
(ALU).
 The stack pointer is also a 16-bit register used as a memory pointer.
 When the reset is activated, all internal operations are suspended and the
program counter is cleared.
 Two types of memory were identified: Read/Write Memory (R/WM) and
Read-Only Memory (ROM).
 In a memory chip, all registers are arranged in a sequence and identified by
binary numbers called memory addresses.
 Memory map is defined as the assignment of addresses to memory registers in
various memory chips in a system.
 Static memory is made up of flip-flops, and it stores a bit as a voltage.
 Dynamic memory is made up of MOS transistor gates, and it stores a bit as a
charge.
 The buffer is a logic circuit which amplifies the current or power.
 The decoder is a logic circuit that identifies each combination of the signals
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present at its input.
The 8085 has five interrupt signals that can be used to interrupt a program
execution.

2.6 Terminal Exercises

 Write any two of MPU Operations.
 Write a short notes about I/O devices
 Write a short notes on ALU

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2.7 Supplementary Materials

1. Ramesh S. Goankar, “Microprocessor Architecture & Applications”, Third
Edition, Penram international Publishing (India), 1997.
2. Mathur, “Introduction to Microprocessors”, Third Edition, TMH.

2.8 Assignments
Discuss in detail about various microprocessor types and its applications.

2.9 Suggested Reading/Reference Books/Set Books

1. “Introduction to Microprocessor, Software, Hardware programming “,
L.A.Levanthal.
2. “Fundamentals of Microprocessor”, B.Ram, Dhanapat Rai & Son’s

2.10 Learning Activities

Collect information on 8085/8080A Bus Structure
Collect information on ALU operations

2.11 Keywords
Micro Processing Unit (MPU)
Central Processing Unit (CPU)
Arithmetic Logic Unit (ALU)
Read Only Memory (ROM)
Random Access Memory (RAM)
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Erasable Programmable Read Only Memory (EPROM)

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UNIT - III
3.0 Introduction
A microcomputer performs a task by reading and executing the set of instructions
written in its memory. This set of instructions, written in a sequence, is called a program.
Each instruction in the program is a command, in binary, to the microprocessor to
perform an operation. This chapter introduces 8085/8080A basic instructions, their
operations, and their applications.

3.1 Objective
This chapter is concerned with using instructions within the constraints and
capabilities of its registers and the bus system. A few instructions are introduced from
each of the five groups (Data transfer, Arithmetic, Logical, Branch, and Machine
Control) and are used to write simple programs to perform specific tasks. The simple
illustrative programs given in this chapter can be entered and executed on the single
board microcomputers used commonly in college laboratories.

3.2 Content

3.2.1 Organization of the 8085

Data and Address Busses

The 8085 is an 8-bit microprocessor available as a 40 – lead plastic ceramic package. The
data bus is 8-bit wide. This implies that 8 bits (1 byte) of data can be transferred to or
from the 8085 in parallel. There are eight pins dedicated to transmit the most significant 8
bits of the memory address. The least significant 8 bits of address are transmitted on eight
lines on which data is transmitted. Thus, data and part of the address, are transmitted over
a set of shared lines. This is known as address multiplexing . It is obvious that the data
and address (least significant 8 bits) are transmitted at different points in time. Due to this
multiplexing, the 8085 bus is also referred to as multiplexed bus.

Addressing the I / O Devices

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In any microcomputer, the μP will be connected to the memory as well as I / O devices.
We have seen in that a μP addresses any memory location. It is possible to design a μC in
such a way that an input or output device is treated by the μP as one memory location.
Thus, for example, address 5 may correspond to LED display and 6 to a keyboard. This
would mean that no byte in the memory would have an address 5 or 6. This form of
connecting I / O devices to a μP is known as memory mapped I / O.
However, it is also possible to treat I / O devices as distinct from the memory and assign
them addresses that do not conflict with memory addresses. According to this scheme, an
address such as 5 could be address of a memory location as well as an I / O device. This
scheme is known as I / O mapped I / O.

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Registers in 8085

Inside the 8085 there are several registers used during the execution of a program. There
is one 8-bit register known as the accumulator. It is used in various arithmetic and logical
operations. There are six general – purpose 8-bit registers that can be used by a
programmer for a variety of purpose. These registers are labeled as B, C, D, E, H and L.
They can be used individually, such as when operation on 8-bit data is desired, or in pairs
such as when a 16-bit address is to be stored.

There is a 16-bit register which is used by 8085 to keep track of the address of the
instruction in the memory that has to be executed next. This register is called program
counter. The contents of the program counter are automatically updated by 8085 during
the execution of an instruction so that the end of execution of this instruction it points to
address of next instruction in the memory. There is another 16-bit register, known as
stack pointer. It is used by the programmer to maintain a stack in the memory. A set of
five flip-flops, 1-bit registers, serve as flags. These registers indicate certain conditions
such as overflow or carry that arise during arithmetic and logical operations.

Instruction Set of the 8085

A machine or assembly language program is written using suitable combination of the

instructions drawn from this set. You need not study this section in detail in the first
reading.

Operation code

Fig 3.1. Single – byte instruction.

Operation code
First byte
Data / Address
Second byte

Fig 3.2. 2-byte instruction. The two bytes are stored at consecutive addresses.

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Operation code
First byte
Low order byte of data / address
Second byte
High order byte of data / address Third byte

Fig 3.3. 3-byte instruction (all 3 bytes are stored consecutively in the memory)

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3.2.2 Instruction Types

An instruction may be 1, 2, or 3 bytes in length. In any of these three types of instruction,

the first byte indicates the operation to be performed. The second and third bytes, if
present, contain either the operand or address of the operand on which the operation is to
be performed. Fig 3.1, 3.2, 3.3 show all the three types of instructions.

Classification of Instructions

For the convenience of programmers, the 8085 instructions have been classified into the
following five groups:

1. Data transfer group

2. Arithmetic group
3. Logical group
4. Branch group
5. Stack, I / O and Machine control group.

3.2.3 Data Transfer (Copy) Operations

One of the primary functions of the microprocessor is copying data, from a register (or
I/O or memory) called the source, to another register (or I/O or memory) called the
destination. In technical literature, the copying function is frequently labeled as the data
transfer function, which is somewhat misleading. In fact, the contents of the source are
not transferred, but are copied into the destination register without modifying the contents
of the source.

Several instructions are used to copy data. This section is concerned with the following
operations.

MOV : Move Copy a data byte.

MVI : Move Immediate Load a data byte directly.
OUT : Output to Port Send a data byte to an output device.
IN : Input from Port Read a data byte from an input device.

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The term copy is equally valid for input/output functions because the contents of the
source are not altered. However, the term data transfer is used so commonly to indicate
the data copy function that, in this book, these terms are used interchangeably when the
meaning is not ambiguous.

In addition to data copy instructions, it is necessary to introduce two machine control

operations to execute programs.

HLT : Halt Stop processing and wait.

NOP : No operation Do not perform any operation.

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These operations (opcodes) are explained and illustrated below with examples.

Instructions. The data transfer instructions copy data from a source into a destination
without modifying the contents of the source. The previous contents of the destination
are replaced by the contents of the source.

Important Note: Data transfer instructions do not affect the flags.

Opcode Operand Description

MOV Rd, Rs Move

This is a 1-byte instruction
Copies data from source register Rs to destination
register Rd

MVI Rd, 8-bit Move Immediate

This is a 2-byte instruction
Loads the 8 bits of the second byte into the
register specified

OUT 8-Bit Port Output to Port

Address This is a 2-byte instruction
Sends (copies) the contents of the accumulator
(A) to the output port specified in the second byte

IN 8-Bit Port Input from Port

Address This is a 2-byte instruction
Accepts (reads) data from the input port specified in the
second byte, and loads into the accumulator.

HLT Halt
This is a 1-byte instruction
The processor stops executing and enters wait state
The address bus and data bus are placed in high
impedance state. No register contents are affected.

NOP
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This is a 1-byte instruction
No operation is performed
Generally used to increase processing time or substitute
in place of an instructions. When an error occurs in
program and an instruction needs to be eliminated, it is
more convenient to substitute NOP than to reassemble the
whole program.
Example:
Load the accumulator A with the data byte 82H (the letter H indicates hexadecimal
number), and save the data in register B.

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Instructions MVI A, 82H,

MOV B, A

The first instruction is a 2-byte instruction that loads the accumulator with the data byte
82H, and the second instruction MOV B, A copies the contents of the accumulator in
register B without changing the contents of the accumulator.

3.2.4 Addressing Modes

The above instructions are commands to the microprocessor to copy 8-bit data from a
source into a destination. In these instructions, the source can be a register, an input port,
or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output
port. The sources and destinations are, in fact, operands. The various formats of
specifying the operands are called the addressing modes. The 8085/8080A instruction set
has the following addressing modes. (Each mode is followed by an example and by the
corresponding piece of restaurant conversation from the analogy).

1. Immediate Addressing -- MVI Rs, Data (Pass the buffer)

2. Register Addressing -- MOV Rd, Rs (Pass the bowl)
3. Direct Addressing -- IN/OUT Port # (Combination number 17 on the menu)
4. Indirect Addressing -- Illustrated in the next chapter (I will have what Susie has)

This classification of the addressing modes is unimportant, except that it provides some
clues in understanding mnemonics. For example, in case of the MVI opcode, the letter I
suggests that the second byte is data and not a register. What is important is to become
familiar with the instructions. After you study the examples given in this chapter, a
pattern will begin to emerge.

Illustrative Program: Data Transfer -- From Register to Output Port

PROBLEM STATEMENT

Load the hexadecimal number 37H in register B, and display the number at the output
port labelled as PORT 1.

PROGRAM ANALYSIS
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Even though this is a very simple problem it is necessary to break the problem into small
steps and to outline the thinking process in terms of the tasks described in Section 5.1

STEPS

Step 1: Load register B with a number.

Step 2: Send the number to the output port.

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QUESTION TO BE ASKED

1. Is there an instruction to load the register B? Yes -- MVI B

2. Is there an instruction to send the data from register B to the output port? No.
Review the instruction OUT. This instruction sends data from the accumulator to an
output port.
The solution appears to be as follows: copy the number from register B into
accumulator A.
3. Is there an instruction to copy data from one register to another register? YES -- MOV,
Rd, Rs.

FLOWCHART

The thinking process described here and the steps necessary to write the program can be
represented in a pictorial format, called a flowchart. Figure 3.4 describes the preceding
steps in a flow chart. Flowcharting is an art. The flowchart in Figure 3.4 does not include
all the steps described earlier. Although the number of steps that should be represented in
a flowchart is ambiguous, not all of them should be included. That would defeat the
purpose of the flowchart. It should represent a logical approach and sequence of steps in
solving the problem. A flowchart is similar to the block diagram of a hardware system or
to the outline of a chapter. Information in each block of the flowchart should be similar
to the heading of a paragraph. Generally, a flowchart is used for two purposes: to assist
and clarify the thinking process and to communicate the programmer's thoughts or logic
to others.

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Fig 3.4 Flowchart

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 Computer Architecture And Microprocessor

The flowchart in Figure 3.4 includes what steps to do and in what sequence. As a rule, a
general flowchart does not include how to perform these steps not what registers are
being used. The steps described in the flowchart are translated into an assembly language
program in the next section.

ASSEMBLY LANGUAGE PROGRAM

Tasks 8085/8080A Mnemonics

1. Load register B with 37H MVI B, 37H

2. Copy the number from B to A MOV A, B
3. Send the number to the output -- port 01H OUT, PORT1
4. End of the program HLT

TRANSLATION FROM ASSEMBLY LANGUAGE TO MACHINE LANGUAGE

Now, to translate the assembly language program into machine language, look up the
hexadecimal machine codes for each instruction in the 8085/8080A instruction set and
write each machine code in the sequence, as follows:

8085/8080A Mnemonics Hex Machine Code

1. MVI B, 37H 06
37
2. MOV A, B 78
3. OUT, PORT1 D3
01
4. HLT 76

This program has six machine codes and will require six bytes of memory to enter the
program into your system. If your single-board microcomputer has R/W memory starting
at the address 2000H, this program can be entered in the memory locations 2000H to
2005H. The format generally used to write an assembly language program is shown
below.

PROGRAM FORMAT

Memory
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Machine
Address Code Instruction
(Hex) (Hex) Opcode Operand Comments

XX00* 06 MVI B, 37H Load register B with data

37H
XX01 37
XX02 78 MOV A, B Copy (B) into (A)
XX03 D3 OUT PORT1 Display accumulator contents
XX04 PORT1** (37H) at Port1

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 Computer Architecture And Microprocessor

XX05 76 HLT End of the program

* Enter high order address of your R / W memory in place of XX.

** Enter the output port address of your system.

This program has five columns; Memory Address, Machine Code, Opcode, Operand, and
Comments. Each is described in the context of a single-board microcomputer.

Memory Address.

These are 16-bit addresses of the user (R/W) memory in the system, where the machine
code of the program is stored. The beginning address is shown as XX00; the symbol XX
represents the page number of the available R/W memory in the microcomputer, and 00
represents the line number. For example, if the microcomputer has the user memory at
2000H, the symbol XX represents page number 20H; if the user memory begins at
0300H, the symbol XX represents page 03H. Substitute the appropriate page when
entering the machine code of a program.

Machine Code.

These are the hexadecimal numbers (instruction codes) that are entered (or stored) in the
respective memory addresses through the hexadecimal keyboard of the microcomputer.
The monitor program, which is stored in Read-Only Memory (ROM) of the
microcomputer, translates the Hex numbers into binary digits and stores the binary digits
in the R/W memory.

If the system has R/W memory with the starting address at 2000H and the output port
address 01H, the program will be stored as follows:
Memory Address Memory Contents Hex Code

2000 00000110 06
2001 00110111 37
2002 01111000 78
2003 11010011 D3
2004 00000001 01
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2005
Opcode (Operation Code).
01110110 76

An instruction is divided into two parts: Opcode and Operand. Opcodes are the
abbreviated symbols specified by the manufacturer (Intel) to indicate the type of
operation or function that will be performed by the machine code.

Operand.

The operand part of an instruction specifies the item to be processed; it can be 8-bit or
16-bit data, a register, or a memory address.

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Combining an opcode and an operand forms an instruction, called a mnemonic or

mnemonic instruction. The mnemonics are used to write programs in the 8085/8080A
assembly language; and then the mnemonics in these programs are translated manually
into the binary machine code by looking them up in the instruction set.

Comments.

The comments are written as a part of the proper documentation of a program to explain
or elaborate the purpose of the instructions used. These are separated by a semicolon (;)
from the instruction on the same line. They play a critical role in the user's understanding
of the logic behind a program. Since the illustrative programs in the early part of this
chapter are simple, most of the comments are either redundant or trivial. The purpose of
the comments in these programs is to reinforce the meaning of the instructions. In actual
stage, the comments should not just describe the operation of an instruction.

HOW TO ENTER AND EXECUTE THE PROGRAM

This program assumes that one output port is available on your microcomputer system.
The program cannot be executed without modification if your microcomputer has no
independent output ports other than the system display of memory address and data or if
it has programmable I/O ports. To enter the program.

1. Push Reset key.

2. Enter the 16-bit memory address of the first machine code of your program. (Substitute
the page number of your R/W memory for the letters XX and the output port address for
the label PORT1.)
3. Enter and store all the machine codes sequentially, using the hexadecimal keyboard on
your system.
4. Reset the system.
5. Enter the memory address where the program begins and push the Execute key.

If the program is properly entered and executed, the data byte 37H will be displayed at
the output port.

HOW TO EXECUTE A PROGRAM WITHOUT AN OUTPUT PORT

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If your system does not have an output port, either eliminate the instruction OUT PORT1,
or substitute NOP (No Operation) in place of the OUT instruction. Assuming your
system has R/W memory starting at 2000H, you can enter the program as follows:

Memory Address Machine Code Mnemonic Instruction

2000 06 MVI B, 37H

2001 37
2002 78 MOV A, B

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 Computer Architecture And Microprocessor

2003 00 NOP
2004 00 NOP
2005 76 HLT

After you have executed this program, you can find the answer in the accumulator by
pushing the Examine Register Key.
The program also can be executed by entering the machine code 76 in location 2003H,
thus eliminating the OUT instruction.

Illustrative Program: Data Transfer to Control Output Devices

PROBLEM STATEMENT

A microcomputer is designed to control various appliances and lights in your house. The
system has an output port with the address 01H, and various units are connected to the
bits D7 to D0 as shown in Figure 3.5. For a cool morning you want to turn on the radio,
the coffee pot, and the space heater. Write appropriate instructions for the
microcomputer. Assume the R/W memory in your system begins at 0300H.

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Fig 3.5 Output Port to Control Devices

PROBLEM ANALYSIS

The output port in Figure 3.5 is a latch (D flip-flop). When data bits are sent to the
output port they are latched by the D flip-flop. A data bit at logic 1 supplies
approximately 5 V as output and can turn on solid-state relay.

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 Computer Architecture And Microprocessor

To turn on the radio, the coffeepot, and the space heater, set D6, D5, and D4 at logic 1, and
the other bits at logic 0.

D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 0 0 0 = 70H

The output port requires 70H, and it can be sent to the port by loading the accumulator
with 70H.

PROGRAM

Memory Machine Mnemonic

Address Code Instruction Comments

HI-LO*
0300 3E MVI A, 70H Load the accumulator with the bit
0031 70 pattern necessary to turn on the
devices

0032 D3 OUT 01H Send the bit pattern to the port 01H,
and
0033 01** turn on the devices
0034 76 HLT End of the program

* Change the higher order memory address 03 to appropriate address for your system.
** Substitute the appropriate port address.

PROGRAM OUTPUT

This program simulates controlling of the devices connected to the output port by
displaying 70H on a seven-segment LED display. If your system has individual LEDs,
the binary patter --
0 1 1 1 0 0 0 0 -- will be displayed.

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Review of Important Concepts

1. Registers are used to load data directly or to save data bytes.

2. In data transfer (copying), the destination register is modified but the source register
retains its data.
3. The 8085/8080A transfers data from an input port to the accumulator (IN) and from the
accumulator to an output port (OUT). The instruction OUT cannot send data from any
other register.

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3.2.5 Arithmetic Operations

The 8085/8080A microprocessor performs various arithmetic operations, such as

addition, subtraction, increment, and decrement. These arithmetic operations have the
following mnemonics.

ADD: Add Add the contents of a register.*

ADI: Add Immediate Add 8-bit data.
SUB: Subtract Subtract the contents of a register
SUI: Subtract Immediate Subtract 8-bit data.
INR: Increment Increase the contents of a register by 1.
DCR: Decrement Decrease the contents of a register by 1.

* Memory related arithmetic operations are excluded here.

These arithmetic operations are performed in relation to the contents of the accumulator.
However, the Increment or the Decrement operations can be performed in any register.
The instructions for these operations are explained below.

INSTRUCTIONS

These arithmetic instructions (except INR and DCR)

1. assume implicitly that the accumulator is one of the operands.

2. modify all the flags according to the data conditions in the accumulator.

3. place the result in the accumulator.

4. do not affect the contents of the operand register.

The descriptions of the instructions (including INR and DCR) are as follows:

Opcode Operand Description

ADD R Add
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UNIVERSITY This is a 1-byte instruction
Adds the contents of register R to the contents of the
accumulator
ADI 8-bit Add Immediate
This is a 2-byte instruction
Adds the second byte to the contents of the
accumulator
SUB R Subtract
This is a 1-byte instruction
Subtracts the contents of register R from the contents
of the accumulator

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SUI 8-bit Subtract Immediate

This is a 2-byte instruction
Subtracts the second byte from the contents of the
accumulator
INR R Increment
This is a 1-byte instruction
Increases the contents of register R by 1
Caution: All flags except the CY are affected
DCR R Decrement
This is a 1-byte instruction
Decreases the contents of register R by 1
Caution: All flags except the Cy are affected

Addition

The 8085/8080A performs addition with 8-bit binary numbers and stores the sum in the
accumulator. If the sum is larger than eight bits (FFH), it sets the Carry flag. Addition
can be performed either by adding the contents of a source register (B, C, D, E, H, L, or
memory) to the contents of the accumulator (ADD) or by adding the second byte directly
to the contents of the accumulator (ADI).

Example Instruction ADD C

When the 8085/8080A adds these two numbers, the accumulator will have 4AH in
binary, and the Carry flag will be set.

CY D7 D6 D5 D4 D3 D2 D1 D0
(A) : 93H = 1 0 0 1 0 0 1 1

(B) : 93H = 1 0 1 1 0 1 1 1

1 1 1 1 1 1 Carry
______________________________________________________________________
SUM (A) :(1) 4AH = ( 1) 0 1 0 0 1 0 1 0
CY

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Flag Status: UNIVERSITY
S = 0, Z = 0, CY = 1

When the 8085/8080A adds these two numbers, the accumulator will have 4AH in
binary, and the Carry flag will be set.

Example Add the number 35H directly to the sum in the previous example when
CY flag is set.

Instruction ADI 35H

CY

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 Computer Architecture And Microprocessor

(A) : 4AH = (1) 0 1 0 0 1 0 1 0

(Data) : 35H = 0 0 1 1 0 1 0 1

__________________________________________________________________

(A) : 7FH = (0) 1 1 1 1 1 1 1 1

Flag Status: S = 0, Z = 0, CY = 0

The addition of 4AH and 35H does not generate a carry and will reset the previous Carry
flag. Therefore, in adding numbers, it is necessary to count how many times CY flag is
set by using some other programming techniques.

Example Assume the accumulator holds the data byte FFH. Illustrate the
differences in the flags set by adding 01H and by incrementing the
accumulator contents.

Instruction ADI 01H

CY
(A) : FFH = 1 1 1 1 1 1 1 1

(Data) : 01H = 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 Carry

__________________________________________________________________
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(A) UNIVERSITY
:(1) 00H = 1 0 0 0 0 0 0 0 0
CY

Flag Status: S = 0, Z =1, CY =1

Instruction INR A

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The accumulator contents will be 00H, same as before. However, the instruction INR
will not set the Carry flag.

Flag Status: S = 0, Z = 1 and CY = 0

Illustrative Program: Arithmetic Operations -- Addition and Increment

PROBLEM STATEMENT

Write a program to perform the following functions, and verify the output.

1. Load the number 8BH in register D.

2. Load the number 6FH in register C.
3. Increment the contents of register C by one.
4. Add the contents of registers C and D and display the sum at the output PORT1.

PROGRAM

The illustrative program for arithmetic operations using addition and increment is
presented.

PROGRAM DESCRIPTION

1. The first four machine codes load 8BH in register D and 6FH in register C.

Memory Machine Instruction

Address Code Opcode Operand

HI-LO
XX00 16 MVI D, 8BH
01 8B
02 0E MVI C, 6FH
03 6F
04 0C INR C
05 79 MOV A, C
06
07
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82
D3
ADD
OUT
D
PORT1
08 PORT# PORT1
09 76 HLT

2. Instruction INR C adds 1 to 6FH and changes the contents of C to 70H.

3. To add (C) to (D), the contents of one of the registers must be transferred to the
accumulator because the 8085/8080A cannot add two registers directly. Review the
ADD instruction. The instruction MOV, A, C copies 70H from register C into the
accumulator without affecting (C).

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4. Instruction ADD D adds (D) to (A), stores the sum in A, and sets the Sign flag as
shown below:

(A) : 70H = 0 1 1 1 0 0 0 0
+
(D) : 8BH = 1 0 0 0 1 0 1 1
___________________________
(A) : FBH = (0) 1 1 1 1 1 0 1 1
CY

Flag Status: S = 1, Z = 0, CY = 0

5. The sum FBH is displayed by the OUT instruction.

PROGRAM OUTPUT

This program will display FBH at the output port. If an output port is not available, the
program can be executed by entering NOP instructions in place of the OUT instruction
and the answer FBH can be verified by examining the accumulator A. (Most systems
have Examine-Register operation.) Similarly, the contents of registers C, D and the flags
can also be verified.

By examining the contents of the registers, the following points can be confirmed.

1. The sum is stored in the accumulator.

2. The contents of the source registers are not changed.
3. The Sign (S) flag is set.

Even though the Sign (S) flag is set this is not a negative sum. The microprocessor sets
the Sign flag whenever an operation results in D7 = 1. The microprocessor cannot
recognize whether FBH is a sum, a negative number, or a bit pattern. It is your
responsibility to interpret and use the flags. In this example, the addition is not
concerned with the signed numbers. With the signed numbers, bit D7 is reserved for a
sign by the programmer (not by the microprocessor), and no number larger than +127 10
can be entered.

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Subtraction UNIVERSITY
The 8085/8080A performs subtraction by using the method of 2's complement.

Subtraction can be performed either by using the instruction SUB to subtract the contents
of a source register or the instruction SUI to subtract an 8-bit number from the contents of
the accumulator. In either case, the accumulator contents are regarded as the minuend
(the number from which to subtract).

The 8085/8080A performs the following steps internally to execute the instruction SUB
(or SUI).

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Step 1: Converts subtrahend (the number to be subtracted) into its 1's complement.
Step 2: Adds 1 to 1's complement to obtain 2's complement of the subtrahend.
Step 3: Adds 2's complement to the minuend (the contents of the accumulator).
Step 4: Complements the Carry flag.

These steps are illustrated in the following example.

Example:

Register B has 65H and the accumulator has 97H. Subtract the contents of register B
from the contents of the accumulator.

Instruction SUB B

Subtrahend (B) : 65H = 0 1 1 0 0 1 0 1

Step 1: 1’s complement of 65H = 1 0 0 1 1 0 1 0
(Substitutte 0 for 1 and
1 for 0)
+

Step 2:Add 01 to obtain 0 1 1 0 0 1 0 1

2’s complement of 65H -------------------------
= 1 0 0 1 1 0 1 1

To subtract: 97H – 65H,

Add 97H to 2’s complement of 65H = 1 0 0 1 0 1 1 1
1 1 1 1 1 Carry
_________________

Step 3: CY(1) 0 0 1 1 0 0 1 0
Step 4: Complement Carry (0) 0 0 1 1 0 0 1 0

Result (A) : 32H

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Flag Status: S = 0, Z = 0, CY =0

If the answer is negative, it will be shown in 2's complement of the actual magnitude.
For example, if the above subtraction is performed as 65H - 97H, the answer will be the
2's complement of 32H with the Carry (Borrow) flag set.

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Illustrative Program: Subtraction of Two Unsigned Numbers

PROBLEM STATEMENT

Write a program to do the following:

1. Load the number 30H in register B and 39H in register C.

2. Subtract 39H from 30H.
3. Display the answer at PORT1.

Memory Machine Instruction

Address Code Opcode Operand

HI-LO
XX00 16 MVI B, 30H
01 30
02 0E MVI C, 39H
03 39
04 78 MOV A, B
05 91 SUB C
06 D3 OUT PORT1
07 PORT#
09 76 HLT

PROGRAM

The illustrative program for subtraction of two unsigned numbers is presented above.
PROGRAM DESCRIPTION

1. Registers B and C are loaded with 30H and 39H, respectively. The instruction MOV
A, B copies 30H into the accumulator. This is an essential step because the contents of a
register can only be subtracted from the contents of the accumulator and not from any
other register.
2. To execute the instruction SUB C the microprocessor performs the following steps
internally:

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Step 1: UNIVERSITY 39H
1’s complement of 39H
=0 0 1 1 1 0 0 1
=1 1 0 0 0 1 1 0
+
Step 2:
Add 01 =0 0 0 0 0 0 0 1
_________________
2’s complement of 39H =1 1 0 0 0 1 1 1
+
Step 3: Add 30H to 2’s complement of 39H = 0 0 1 1 0 0 0 0
_________________

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CY (0) 1 1 1 1 0 1 1 1
Step 4: Complement Carry (1) 1 1 1 1 0 1 1 1 = F7H

Flag Status: S = 1, Z = 0, CY =1

3. The number F7H is a 2's complement of the magnitude (39H - 30H) = 09H.

4. The instruction OUT displays F7H at PORT1.

PROGRAM OUTPUT

This program will display F7H as the output. In this program, the unsigned numbers
were used to perform the subtraction. Now, the question is: How do you recognize that
the answer F7H is really a 2's complement of 09H and not a straight binary F7H?

The answer lies with the Carry flag. If the Carry flag (also known as Borrow flag in
subtraction) is set, the answer is in 2's complement. The Carry flag raises a second
question: Why isn't it a positive sum with a carry? The answer is implied by the
instruction SUB (it is a subtraction).

There is not way to differentiate between a straight binary number and 2's complement by
examining the answer at the output port. The flags are internal and not easily displayed.
However, a programmer can test the Carry flag by using the instruction Jump On Carry
(JC) and can find a way to indicate that the answer is in 2's complement.

Review of Important Concepts

1. The arithmetic operations implicitly assume that the contents of the accumulator are
one of the operands.
2. The results of the arithmetic operations are stored in the accumulator; thus the previous
contents of the accumulator are altered.
3. The flags are modified to reflect the data conditions of an operation.
4. The contents of a register are not changed as a result of an arithmetic operation
5. In the add operation, if the sum is larger than 8-bit CY is set.
6. The subtract operation is performed by using the 2's complement method, and CY is
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complemented after the subtraction.
7. If a subtraction results in a negative number, the answer is in 2's complement and CY
(the Borrow flag) is set.
8. In unsigned arithmetic operations, the Sign flag (S) should be ignored.
9. The instructions INR (Increment) and DCR (Decrement) are special cases of the
arithmetic operations. These instructions can be used for any one of the registers, and
they do not set CY, even if the result is larger than 8-bit.

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3.2.6 Flag Concepts and Cautions

As described earlier, the flags are flip-flops that are set or reset after the execution of
arithmetic and logic operations, with some exceptions. In many ways, the flags are like
signs on an interstate highway that help drivers find their destinations. Drivers may see
one or more signs at a time. They may take the exit when they find the sign they are
looking for, or they may continue along the interstate and ignore the signs.

Similarly, flags are signs of data conditions. After an operations, one or more flags may
be set, and they can be used to change the direction of the program sequence by using
Jump instructions, which will be described later. However, the programmer should be
alert for them to make a decision. If the flags are not appropriate for the tasks, the
programmer can ignore them.

Caution #1. The critical concept here is that if the programmer ignores the flag, it can
be lost after the subsequent instructions. However, the flag can be ignored when the
programmer is not interested in using it.

Caution #2. The programmer may use one or more flags to make decisions or may
ignore them if they are irrelevant.

Caution #3. The CY flag has a dual function; it is used as a carry in addition and as a
borrow in subtraction.

Caution #4. If the sign flag is set, it indicates that bit D7 in the accumulator (or in the
result) is 1; this does not necessarily imply a negative number in the accumulator or the
negative result.

3.2.7 Logic Operations

A microprocessor is basically a programmable logic chip. It can perform all the logic
functions of the hard-wired logic through its instruction set. The 8085/8080A instruction
set includes such logic functions as AND, OR, Ex OR, and NOT (complement). The
opcodes of these operations are as follows:
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AND :
UNIVERSITY
AND Logically AND the contents of a register.
ANI : AND Immediate Logically AND 8-bit data.
ORA : OR Logically OR the contents of a register.
ORI : OR Immediate Logically OR 8-bit data.
XRA : X-OR Exclusive-OR the contents of a register.
XRI : X-OR Exclusive-OR 8-bit data.

All logic operations are performed in relation to the contents of the accumulator. The
instructions of these logic operations are described below.

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INSTRUCTIONS
The logic instructions
1. implicitly assume that the accumulator is one of the operands.
2. reset (clear) CY and AC flags. The instructions ANA and ANI in the 8085 and CMA
are exceptions to this.
3. modify Z, P, and S flags according to the data conditions of the result.
4. place the result in the accumulator.
5. do not affect the contents of the operand register.
Opcode Operand Description

ANA R Logical AND with Accumulator

This is a 1-byte instruction
Logically ANDs the contents of the register R with the
contents of the accumulator 8085: CY is reset and AC
is set

ANI 8-bit AND Immediate with Accumulator

This is a 2-byte instruction
Logically ANDs the second byte with the contents of
the accumulator 8085: CY is reset and AC is set

ORA R Logically OR with Accumulator

This is a 1-byte instruction
Logically ORs the contents of the register R with the
contents of the accumulator

ORI 8-bit OR Immediate with Accumulator

This is a 2-byte instruction
Logically ORs the second byte with the contents of
the accumulator

XRA R Logically Exclusive-OR with Accumulator

This is a 1-byte instruction
Exclusive-ORs the contents of register R with the
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XRI 8-bit Exclusive-OR Immediate with Accumulator

This is a 2-byte instruction
Exclusive-ORs the second byte with the contents of
the accumulator

CMA Complement Accumulator

This is a 1-byte instruction that complements the
contents of the accumulator
No flags are affected

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3.2.8 Data Masking with Logic AND

The process of performing logic operations through the software instructions is slightly
different from the hardwired logic. The AND gate shown in Figure 3.6(a) has two inputs
and one output. On the other hand, the instruction ANA simulates eight AND gates
(Figure.3.6(b)). For example, assume that register B holds 77H and the accumulator A
holds 81H. The result of the instruction ANA B is 01H and is placed in the accumulator
replacing the previous contents as shown in Figure 3.6(b)

Fig 3.6 AND Gate (a) and a Simulated ANA Instruction (b)

Figure 3.6(b) shows that each bit of register B is independently ANDed with each bit of
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the accumulator, thus simulating eight 2-input AND gates. To simulate one 2-input AND
gate, all other bits can be masked or eliminated, as illustrated in the next program.

Illustrative Program: Data Masking with Logic AND

PROBLEM STATEMENT

To conserve energy and to avoid an electrical overload on a hot afternoon, implement the
following procedures to control the appliances throughout the house (Figure 3.7).
Assume that the control switches are located in the kitchen, and they are available to
anyone in the house. Write a set of instructions to

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1. turn on the air conditioner is switch S7 of the input port 00H is on.
2. ignore all other switches of the input port even if someone attempts to turn on other
appliances.

(To perform this experiment on your single-board microcomputer, simulate the reading of
the input port 00H with the instruction MVI A, 8-bit data.)

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Fig 3.7 Input Port to Control Appliances

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PROBLEM ANALYSIS

In this problem you are interested in only one switch position S 7, which is connected to
data line D7. Assume that various persons in the family have turned on the switches of
the air conditioner (S7), the radio (S4), and the lights (S3, S2, S1, S0).

If the microprocessor reads the input port (IN 00H), the accumulator will have data byte
9FH. This can be simulated by using the instruction MVI A, 9FH. However, if you are
interested in knowing only whether S7 is on, you can mask bits D6 through D0 by
ANDing the input data with a byte that has 0 in bit positions D6 through D0 and 1 in bit
position D7.

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 00 0 0 0 = 80H

After bits D6 through D0 have been masked, the remaining byte can be sent to the output
port to simulate turning on the air conditioner.

PROGRAM

Memory Machine Instruction

Address Code Opcode Operand Comments

HI-LO
XX00 3E MVI A, Data This instruction simulates the
01 9F instruction IN 00H
02 E6 ANI 80H Mask all the bits except D7
03 80
04 D3 OUT 01H Turn on the air conditioner if
05 01 S7 is on
06 76 HLT End of the program

PROGRAM OUTPUT

The instruction ANI 80H ANDs the accumulator data as follows.

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(A) = 1 0 0 1 1 1 1 1 (9FH)

AND
(Masking Byte) = 1 0 0 0 0 0 0 0 (80H)
__________________________________

(A) = 1 0 0 0 0 0 0 0 (80H)

Flag Status: S = 1, Z = 0, CY = 0

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The ANDing operation always resets the CY flag. The result (80H) will be placed in the
accumulator and then sent to the output port, and logic 1 of data bit D7 turns on the air
conditioner. In this example, the output (80H) is the same as the masking data byte
(80H) because switch S7 (or data bit D7) is on. If S7 is off, the output will be zero.

OR, Exclusive-OR, and NOT

The instructions ORA (and ORI) simulates logic ORing with eight 2-input OR gates; this
process is similar to that of ANDing, explained in the previous section. The instruction
XRA (and XRI) performs Exclusive-ORing of eight bits, and the instruction CMA inverts
the bit of the accumulator.

Example Assume register B holds 93H and the accumulator holds 15H. Illustrate
the results of the instructions ORA B, XRA B and CMA

1. The instruction ORA B will perform the following operation:

(B) = 1 0 0 1 0 0 1 1 (93H)

OR
(A) = 0 0 0 1 0 1 0 1 (15H)
___________________________
(A) = 1 0 0 1 0 1 1 1 (97H)

Flag Status: S = 1, Z = 0, CY = 0

The result 97H will be placed in the accumulator, the CY flag will be reset, and the other
flags will be modified to reflect the data conditions in the accumulator.

2. The instruction XRA B will perform the following operation.

(B) = 1 0 0 1 0 0 1 1 (93H)

X-OR
(A) = 0 0 0 1 0 1 0 1 (15H)
___________________________
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(A) = 1 0 0 0 0 1 1 0 (86H)

Flag Status: S = 1, Z = 0, CY = 0

The result 86H will be placed in the accumulator, and the flags will be modified as
shown.

3. The instruction CMA will result in

(A) = 0 0 0 1 0 1 0 1 (15H)

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CMA
(A) = 1 1 1 0 1 0 1 0 (EAH)

The result EAH will be placed in the accumulator and no flags will be modified.

Review of Important Concepts

1. Logic operations are performed in relation to the contents of the accumulator.

2. Logic operations simulate eight 2-input gates (or inverters).
3. The Sign, Zero (and Parity) flags are modified to reflect the status of the operation.
The Carry flag is reset. However, the NOT operation does not affect any flags.
4. After a logic operation has been performed, the answer is placed in the accumulator
replacing the original contents of the accumulator.
5. The logic operations cannot be performed directly with the contents of two registers.
6. The individual bits in the accumulator can be set or reset using logic instructions.

3.2.9 Branch Operations

The branch instructions are the most powerful instructions because they allow the
microprocessor to change the sequence of a program, either unconditionally or under
certain test conditions. These instructions are the key to the flexibility and versatility of a
computer.

The microprocessor is a sequential machine; it executes machine codes from one memory
location to the next. Branch instructions instruct the microprocessor to go to a different
memory location, and the microprocessor continues executing machine codes from that
new location. The address of the new memory location is either specified explicitly or
supplied by the microprocessor or by extra hardware. The branch instructions are
classified in three categories.

1. Jump instructions
2. Call and Return instructions
3. Restart instructions

The Jump instructions specify the memory location explicitly. They are 3-byte
instructions: one byte for the operation code, followed by a 16-bit memory address.
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Jump instructions are classified into two categories:
Conditional Jump.
Unconditional Jump and

Unconditional Jump

The 8085/8080A instruction set includes one unconditional Jump instruction. The
unconditional Jump instruction enables the programmer to set up continuous loops.

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INSTRUCTION

Opcode Operand Description

JMP 16-bit Jump

This is a 3-byt instruction
The second and third bytes specify the 16-bit memory
address. However, the second byte specifies the low-
order and the third byte specifies the high-order
memory address.

For example, to instruct the microprocessor to go to the memory location 2000H,

the mnemonics and the machine code entered will be as follows:

Machine Code Mnemonics

C3 JMP 2000H
00
20

Note the sequence of the machine code. The 16-bit memory address of the jump location
is entered in the reverse order, the low-order byte (00H) first followed by the high-order
byte (20H). The 8085/8080A is designed for such a reverse sequence. The jump location
can also be specified using a label. While writing a program, you may not know the
exact memory location to which a program sequence should be directed. In that case, the
memory address can be specified with a label (or a name). This is particularly useful and
necessary for an assembler. However, you should not specify both a label and its 16-bit
address in a Jump instruction. Furthermore, you cannot use the same label for different
memory locations. The next illustrative program shows use of the Jump instruction.

Illustrative Program: Unconditional Jump to Set Up a Continuous Loop

PROBLEM STATEMENT

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Modify the program in Example 5.2 to read the switch positions continuously and turn on
the appliances accordingly.

PROBLEM ANALYSIS

One of the major drawbacks of the program in Example 5.2 is that the program reads
switch positions once and then stops. Therefore, if you want to turn on/off different
appliances, you have to reset the system and start all over again. This is impractical in
real-life situations. However, the unconditional Jump instruction, in place of the HLT
instruction, will allow the microcomputer to monitor the switch positions continuously.

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PROGRAM

Memory Machine
Address Code Label Mnemonics Comments

2000 DB START: IN 00H Read input switches

2001 00
2002 D3 OUT 01H Turn on devices
according
2003 01 to switch positions
2004 C3 JMP START Go back to beginning
and read the switches
2005 00 again
2006 20

PROGRAM FORMAT

The program includes one more column called label. The memory location 2000H is
defined with a label START; therefore, the label START can specify the operand of the
Jump instruction. The program sets up the endless loop, and the microprocessor monitors
the input port continuously. The output will reflect any change in the switch positions.

Conditional Jumps

Conditional Jump instructions allow the microprocessor to make decisions based on

certain conditions indicated by the flags. After logic and arithmetic operations, flip-flops
(flags) are set or reset to reflect data conditions. The conditional Jump instructions check
the flag conditions and make decisions to change or not to change the sequence of a
program.

Flags.

The 8085/8080A status register has five flags, one of which (Auxiliary Carry) is used
internally. The other four flags used by the Jump instructions are

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1. Carry flag
2. Zero flag UNIVERSITY
3. Sign flag
4. Parity flag

Two Jump instructions are associated with each flag. The sequence a program can be
changed either because the condition is present or because the condition is absent. For
example, while adding the numbers you can change the program sequence either because
the carry is present (JC = Jump On Carry) or because the carry is absent (JNC = Jump On
No Carry).

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Instructions.

All conditional Jump instructions in the 8085/8080A are 3-byte instructions; the second
byte specifies the low-order (line number) memory address, and the third byte specifies
the high-order (page number) memory address. The following instructions transfer the
program sequence to the memory location specified under the given conditions:

Opcode Operand Description

JC 16-bit Jump On Carry (If result generates carry and CY = 1)

JNC 16-bit Jump On No Carry (CY = 0)
JZ 16-bit Jump On Zero (If result is zero and Z = 1)
JNZ 16-bit Jump On No Zero (Z = 0)
JP 16-bit Jump On Plus (If D7 = 0, and S = 0)
JM 16-bit Jump On Minus (If D7 = 1, and S = 1)
JPE 16-bit Jump On Even Parity (P = 1)
JPO 16-bit Jump On Odd Parity (P = 0)

All the Jump instructions are listed here for an overview. The Zero and Carry flags and
related Jump instructions are used frequently. They are illustrated in the following
examples.

Illustrative Program: Testing of the Carry Flag

PROBLEM STATEMENT

Load the two hexadecimal numbers 9BH and A7H in registers D and E respectively, and
add the numbers. If the sum is greater than FFH, display 01H at output PORT 0;
otherwise, display the sum.

PROBLEM ANALYSIS AND FLOWCHART

The problem can be divided into the following steps:

1. Load the numbers in the registers.

2. Add the numbers.
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3. Check the sum.

Is the sum > FFH

If yes then Get ready to display 01
If No then Go to Step 5 to display the sum

5. Display.
6. End

Assuming your R/W memory begins at 2000H, the preceding assembly language
program can be translated as follows:

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Memory Machine Label Mnemonics

Address Code

2000 16 START: MVI D, 9BH

2001 9B
2002 1E MVI E, A7H
2003 A7
2004 7A MOV A, D
2005 7A
2006 83 ADD E
2007 D2 JNC DSPLAY
2008 X
2009 3E MVI A, 01H
200A 01
200B D3 DSPLAY: OUT 00H
200C 00
200D 76 HLT

While translating into the machine code, we leave memory locations 20007H and 2008H
blank because the exact location of the transfer is not known. What is known is that two
bytes should be reserved for the 16-bit address. After completing the straight line
sequence, we know the memory address of the label DSPLAY; i.e., 200BH. This address
must be placed in the reversed order as shown:

2007 OB Low-order: Line Number

2008 20 High-order: Page Number

Review of Important Concepts

1. The Jump instructions change program execution from its sequential order to a
different memory location.
2. The Jump instructions can transfer program execution ahead of the sequence (Jump
Forward) or behind the sequence (Jump Backward).
3. The unconditional Jump is, generally, used to set up continuous loops.
4. The conditional Jumps are used for the decision-making process based on the data
conditions in the accumulator (or of the result), reflected by the flags.
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5. Arithmetic and logic instructions modify the flags according to the data in the
accumulator (or of the result), and the conditional branch instructions use them to make
decisions. However, the branch instructions do not affect the flags.

CAUTION

The conditional Jump instructions will not function properly unless the preceding
instruction sets the necessary flag. Data Copy instructions do not affect the flags;
furthermore, some arithmetic and logic instructions either do not affect the flags or affect
only certain flags.

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Write Assembly Language Programs

Communicating with a microcomputer -- giving it commands to perform a task and

watching it perform them -- is exciting. However, one can be uneasy communicating in
strange mnemonics and hexadecimal machine codes. This feeling is like the uneasiness
one has when beginning to speak a foreign language. How do we learn to communicate
with a microcomputer in its assembly language? By using a few mnemonics at a time
such as the mnemonics for Read the switches and Display the data. This chapter has
introduced a group of basic instructions that can command the 8085/8080A
microprocessor to perform simple tasks.

After we know a few instructions, how do we begin to write a program? Any program,
no matter how large it may appear, begins with mnemonics. And, just as several persons
contribute to the construction of a hundred-story building, so the writing of a large
program is usually the work of a team. In addition, the 8085 instruction set contains only
74 different instructions, some of them used quite frequently.

In a hundred-story building, most of the rooms are similar. If one known the basic
fundamentals of constructing a room, one can learn how to tie these rooms together in a
coherent structure. However, planning and forethought are critical. Before beginning to
build a structure, an architectural plan must be drawn. Similarly, to write a program, one
needs to draw up a plan of logical thoughts. A given task should be broken down into
small units that can be built independently. This is called the modular design approach.

Getting Started

Writing a program is equivalent to giving specific commands to the microprocessor in a

sequence to perform a task. The italicized words provide clues to writing a program. Let
us examine these terms.

1. Perform a Task. What is the task you are asking it to do?

2. Sequence. What is the sequence you want it to follow?
3. Commands. What are the commands (instruction set) it can understand?

These terms can be translated into steps as follows:

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Step 1: Read the problem carefully.
Step 2: Break it down into small steps.
Step 3: Represent these small steps in a possible sequence with a flowchart -- a plan of
attack.
Step 4: Translate each block of the flowchart into appropriate mnemonic instructions.
Step5: Translate mnemonics into the machine code.
Step 6: Enter the machine code in memory and execute. Only on rare occasions is a
program successfully executed on the first attempt.
Step 7: Start troubleshooting.

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3.2.10 LOOPING, COUNTING

The programming examples illustrated in previously are simple and can be solved
manually. However, the computer surpasses manual efficiency when tasks must be
repeated, such as adding a hundred numbers or transferring a thousand bytes of data. It is
fast and accurate.

The programming technique used to instruct the microprocessor to repeat tasks is called
looping. A loop is set up by instructing the microprocessor to change the sequence of
execution and perform the task again. This process is accomplished by using Jump
instructions. In addition, techniques such as counting and indexing (described below) are
used in setting up a loop.

Loops can be classified into two groups:

1. Continuous Loop – repeats a task continuously.

2. Conditional Loop – repeats a task until certain data conditions are met

Continuous Loop

A continuous loop is set up by using the unconditional Jump instruction shown in the
flowchart(Figure 3.8).

A program with a continuous loop does not stop repeating the tasks until the system is
reset. Typical examples of such a program include a continuous counter or a continuous
monitor system.

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Fig 3.8. Flowchart of a Continuous Loop
Conditional Loop

A conditional loop is set up by the conditional Jump instructions. These instructions

check flags (Zero, Carry, etc.) and repeat the specified tasks if the conditions are
satisfied. These loops usually include counting and indexing.

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CONDITIONAL LOOP AND COUNTER

A counter is a typical application of the conditional loop. For example, how does the
microprocessor repeat a task five times? The process is similar to that of a car racer in
the Indy 500 going around the track 500 times. How does the racer know when 500 laps
have been completed? The racing team manager sets up a counting and flagging method
for the racer. This can be symbolically represented as in Figure 3.9(a). A similar
approach is needed for the microprocessor to repeat the task five times. The
microprocessor needs a counter; and when the counting is completed, it needs a flag.
This can be accomplished with the conditional loop, as illustrated in the flowchart in
Figure 3.9(b).

The computer flowchart (Figure 3.9(b)) is translated into a program as follows:

1. Counter is set up by loading an appropriate count in a register.

2. Counting is performed by either incrementing or decrementing the counter.

3. Loop is set up by a conditional Jump instruction.

4. End of Counting is indicated by a flag.

It is easier to count down to zero than to count up because the Zero flag is set when the
register becomes zero.

Conditional Loop, Counter, and Indexing.

Another type of looping includes indexing along with a counter. (Indexing means
pointing or referencing objects with sequential numbers. In a library, books are arranged
according to numbers, and they are referred to or sorted by numbers. This is called
indexing.) Similarly, data bytes are stored in memory locations, and those data bytes are
referred to by their memory locations.

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Fig 3.9 Flowcharts to Indicate Number of Repetitions Completed

Example Illustrate the steps necessary to add ten bytes of data stored in memory
locations starting at a given location, and display the sum. Draw a flowchart.

Procedure. The microprocessor needs

a. a counter to count 10 data bytes
b. an index or a pointer to locate where data bytes are stored
c. to transfer data from a memory location to the microprocessor (ALU)
d. to perform addition

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e. registers for temporary storage of partial answers

f. a flag to indicate the completion of the task
g. to store or output the result

These steps can be represented in the form of a flowchart as in Figure 3.10

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Fig 3.10. Generalized Programming Flowchart

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1. This is a planning stage where the initial setting up is done. This is the most
difficult step because the initial set-up depends on the requirements of the
following steps (steps a and b in Example: setting up counter and indexing).
2. Data are generally stored in memory or read from an input port. This step is
concerned with bringing data into the microprocessor (step c: transfer of data
from a memory location to the microprocessor).
3. This step involves all data manipulations (step d: addition)
4. This step involves storing data of partial results (step e).
5. At this point, the microprocessor does not know whether it has completed all
the operations. ; Before it can repeat the task, it needs to get ready for the next
operation; for example, go to next index or count.
6. This is a decision making step, it decides whether to change the sequence of
execution and repeat, or to go to the next instruction (step f: a flag check).
7. This step involves either sending the result to an output port or storing in
memory (step g).

This generalized flowchart can be used in solving many problems. Some blocks may
have to be expanded with additional loops, or some blocks may need to interchange their
positions.

Review of Important Concepts

1. Programming is a logical approach to instruct the microprocessor to perform

operations in a given sequence.

2. The computer is at its best in repeating tasks. It is fast and accurate.

3. Loops are set up by using the looping technique along with counting and
indexing.

4. The computer is a versatile and powerful computing tool because of its capability
to set up loops and to make decisions based on data conditions.

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The programming techniques and the flowcharting introduced in this section will be
illustrated with various applications throughout the chapter. Additional instructions
necessary for these applications will be introduced first. The primary focus here is to
analyze a given programming problem in terms of the basis building blocks of the
flowchart shown in Figure 3.10.

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3.3 Revision Points

Registers in 8085
Inside the 8085 there are several registers used during the execution of a program. There
is one 8-bit register known as the accumulator. It is used in various arithmetic and logical
operations.

One of the primary functions of the microprocessor is copying data, from a register (or
I/O or memory) called the source, to another register (or I/O or memory) called the
destination. In technical literature, the copying function is frequently labeled as the data
transfer function,

The 8085/8080A microprocessor performs various arithmetic operations, such as

addition, subtraction, increment, and decrement. These arithmetic operations have the
following mnemonics.

ADD: Add Add the contents of a register.*

ADI: Add Immediate Add 8-bit data.
SUB: Subtract Subtract the contents of a register
SUI: Subtract Immediate Subtract 8-bit data.
INR: Increment Increase the contents of a register by 1.
DCR: Decrement Decrease the contents of a register by 1.

1. The arithmetic operations implicitly assume that the contents of the accumulator are
one of the operands.
2. The results of the arithmetic operations are stored in the accumulator; thus the previous
contents of the accumulator are altered.
3. The flags are modified to reflect the data conditions of an operation.
4. The contents of a register are not changed as a result of an arithmetic operation
5. In the add operation, if the sum is larger than 8-bit CY is set.
6. The subtract operation is performed by using the 2's complement method, and CY is
complemented after the subtraction.
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7. If a subtraction results in a negative number, the answer is in 2's complement and CY
(the Borrow flag) is set.
8. In unsigned arithmetic operations, the Sign flag (S) should be ignored.
9. The instructions INR (Increment) and DCR (Decrement) are special cases of the
arithmetic operations. These instructions can be used for any one of the registers, and
they do not set CY, even if the result is larger than 8-bit.
10. Registers are used to load data directly or to save data bytes.

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11. In data transfer (copying), the destination register is modified but the source register
retains its data.
12. The 8085/8080A transfers data from an input port to the accumulator (IN) and from
the accumulator to an output port (OUT). The instruction OUT cannot send data from
any other register.
3.4 Intext Questions
1. What is Opcode?
2. What is an Operand?
3. Write a brief note on Classification of Instructions?
4. Describe the various addressing modes?
5. What is an Jump instruction?
6. What are the types of flags?
7. List the various jump instructions?
8. What is looping?
9. Load the hexadecimal number 63H in register C, and 91H in accumulator A.
Display the numbers 63H at PORT0 and 91H at PORT1.
10. What operation can be performed by using the instruction ADD A?

3.5 Summary
 A microcomputer performs a task by reading and executing the set of
instructions written in its memory.
 Registers are used to load data directly or to save data bytes.
 In data transfer (copying), the destination register is modified but the source
register retains its data.
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
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The 8085/8080A transfers data from an input port to the accumulator (IN) and
from the accumulator to an output port (OUT). The instruction OUT cannot
send data from any other register.
 The 8085/8080A performs subtraction by using the method of 2's
complement.
 The results of the arithmetic operations are stored in the accumulator; thus the
previous contents of the accumulator are altered.

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 In the add operation, if the sum is larger than 8-bit CY is set.

 In unsigned arithmetic operations, the Sign flag (S) should be ignored.
 A microprocessor is basically a programmable logic chip.
 The branch instructions are the most powerful instructions because they allow
the microprocessor to change the sequence of a program, either
unconditionally or under certain test conditions.
 The unconditional Jump is, generally, used to set up continuous loops.
 The conditional Jumps are used for the decision-making process based on the
data conditions in the accumulator (or of the result), reflected by the flags.
 The programming technique used to instruct the microprocessor to repeat
tasks is called looping

3.6 Terminal Exercises

1. Write any four instructions
2. What is machine code?
3. Write short notes on arithmetic operations
4. Define assembly language programs.

3.7 Supplementary Materials

1. Ramesh S. Goankar ,“Microprocessor Architecture & Applications”, Third
Edition , Penram international Publishing (India),1997.
2. Mathur, “ Introduction to Microprocessors”, Third Edition, TMH.

3.8 Assignments

Perform the following task with a small group of students

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1. Various types of logic gates
2. Flow chart representation.

3.9 Suggested Reading/Reference Books/Set Books

1. “Introduction to Microprocessor, Software, Hardware programming “,

L.A.Levanthal.
2. “Fundamentals of Microprocessor”, B.Ram, Dhanapat Rai & Son’s

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3.10 Learning Activities

1. Collect information on Flowchart and its components

2. Collect information on logic gates from internet.

3.11 Keywords
MOV
HLT
ADD
ADI
SUB
SUI
INR
DCR

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UNIT - IV

4.0 Introduction
Designing a counter is a frequent programming application. Counters are used
primarily to keep track of events, while time delays are important in setting up reasonably
accurate timing between two events. The process of designing counters and time delays
using software instructions is far more flexible and less time consuming than the design
process using hardware.

4.1 Objective
This lesson provides you the detailed study about counter, time delay. The content
of the lesson starts with the counter and time delay. It gives you the detailed
implementation of the counters and time delays with flow chart representation. It also
provides knowledge about conversion , stack and subroutine.

4.2 Content

4.2.1 Counter
A counter is designed simply by loading an appropriate number into one of the
registers and using the INR (Increment by One) or the DCR (Decrement by One)
instructions. A loop is established to update the count, and each count is checked to
determine whether it has reached the final number, if not, the loop is repeated.

The flowchart shown in Figure 4.1 illustrates these steps. However, this counter has one
major drawback; the counting is performed at such high speed that only the last count can
be observed. To observe counting, there must be an appropriate time delay between
counts.

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Fig 4.1 Flowchart of a counter

4.2.2 Time Delay

The procedure used to design a specific delay is similar to that used to set up a counter.
A register is loaded with a number, depending on the time delay required, and then the
register is decremented until it reaches zero by setting up a loop with a conditional Jump
instruction. The loop caused the delay, depending upon the clock period of the system, as
illustrated in the next sections.
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Time Delay Using One Register

The flowchart in Figure 4.2 shows a time-delay loop. A count is loaded in a register, and
the loop is executed until the count reaches zero. The set of instructions necessary to set
up the loop is also shown in Figure 4.2.

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Fig 4.2 Time Delay Loop: Flowchart and Instructions

The last column in the instructions shows the T-states (clock periods) required by the
8080A microprocessor to execute each instruction. For some instructions, the 8080A
requires a different number of T-states than does the 8085. For example, the 8085
executes the instruction DCR in four T-states whereas the 8080A takes five T-states. The
calculation shown here are based on the 8080A instructions.

Figure 4.2 shows that instruction MVI requires seven clock periods. An 8080A based
microcomputer with 2 MHz clock frequency will execute the instruction MVI in 3.5 s as
follows:

Clock frequency of the system f = 2 MHz

Clock period T = 1/f x 10-6 = 0.5 s
Time to execute MVI = 7 T-states x 0.5
= 3.5 s
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However, if the clock frequency of the system is 1 MHz, the microprocessor will require
7 s to execute the same instruction. To calculate the time delay in a loop, we must
account for the T-states required for each instruction, and for the number of times the
instructions are executed in the loop.

In Figure 4.2, register C is loaded with the count FFH(25510) by the instruction MVI,
which is executed once and takes seven T-states. The next two instructions, DCR and
JNZ, form a loop with a total of fifteen (5 + 10) T-states. The loop is repeated 255 times
until register C = 0.

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The time delay in the loop TL with 2 MHz clock frequency is calculated as

TL = (T x Loop T-states x N10)

Where TL = Time delay in the loop
T = System clock period
N10 = Equivalent decimal number of hexadecimal count loaded in the delay
register = (0.5 x 10-6 x 15 x 255)
= 1912.5 s
= 1.9 ms

In most applications, this approximate calculation of the time delay is considered

reasonably accurate. However, to calculate the time delay more accurately, the time for
the execution of the initial instruction MVI should be included in the total time delay TD
as
Delay TD = Time to Execute + Time to Execute
Instructions Outside Loop Loop Instructions
= TO + TL
= (7 x 0.5 s) + 1912.5 s
= 1916 s
= 1.9 ms

The difference between the two calculations is only 3.5 s and can be ignored in most
instances.

The time delay can be varied by changing the count number FF; however, to increase the
time delay beyond 1.9 ms in 2 MHz microcomputer systems, you must use either
additional instructions or a register pair.

Time Delay Using a Register Pair

The time delay can be considerably increased by setting a loop and using a register pair
with a 16-bit number (maximum FFFH). The 16-bit number is decremented by using the
instruction DCX. However, the instruction DCX does not set the Zero flag and, without
the test flags, Jump instructions cannot be executed. Additional techniques, therefore,
must be used to set the Zero flag.

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The following set of instructions uses a register pair to set up a time delay

Label Opcode Operand Comments

LXI B, 208FH ;Load register pair BC with 16-bit
count
LOOP: DCX B ;Decrement (BC) by one
MOV A, C ;Load accumulator with contents of
Register C
ORA B ;OR (B) with (C) to set Zero flag
JNZ LOOP ;If result  0, jump back to LOOP

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In this set of instructions, the instruction LXI B, 208FH loads register B with the number
20H, and register C with the number 8FH. The instruction DCX decrements the entire
number by one (e.g., 208FH becomes 208EH). The next two instructions are used only
to set the Zero flag; otherwise, they have no function in this problem. The OR instruction
sets the Zero flag only when the contents of B and C are simultaneously zero. Therefore,
the loop is repeated 208FH times, equal to the count set in the register pair.

Time Delay

The time delay in the loop is calculated as in the previous example. The loop includes
four instructions: DCX, MOV, ORA, and JNZ, and takes 24 clock periods for execution.
The loop is repeated 208FH times, which is converted to decimals as

208FH = 2 x (163) + 0 x (16)2 + 8 x (16)1 + 15(160)

= 833510

If the clock period of the system = 0.5 s, the delay in the Loop TL

TL = (0.5 x 24 x 833510)
= 100 ms
Total Delay TD = 100 ms + TO
 100 ms (The instruction LXI adds only 5 s)

A similar time delay can also be achieved by using the technique of two loops. For
example, register C is used in the inner loop and register B is used in the outer loop
(Figure 4.3).

Furthermore, the time delay within a loop can be increased by using instructions that will
not affect the program except to increase the delay. For example, the instruction NOP
(No Operation) can add four T-states in the delay loop. The desired time delay can be
obtained by using any or all available registers.

The procedure for calculating time delays in an 8085 system is the same as explained for
the 8085A except that appropriate T-states should be used in the delay calculations.

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However, the execution of a conditional Jump instruction adds a few complications to the
calculations. The 8085 requires ten T-states to execute a conditional

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Fig 4.3 Flowchart for Time Delay with Two Loops

Jump instruction when it changes the sequence of the program, and seven T-states when
the program continues in the same sequence. For example, the JNZ instruction in the last
loop of Figure 4.2 is executed in seven T-states. This means the number of T-states in
the loop will be reduced by three T-states, which can be easily ignored.

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Additional Techniques for Time Delay

The disadvantages in using software delay techniques for real-time applications in which
the demand for time accuracy is high, such as digital clocks, are as follows:

1. The accuracy of the time delay depends on the accuracy of the system’s clock.
2. The microprocessor is occupied simply in a waiting loop; otherwise it could be
employed to perform other functions.
3. The task of calculating accurate time delays is tedious.

The real-time applications, timers (integrated timer circuits) are commonly used. The
Inter 8253 (described in Chapter 15) is a programmable timer chip that can be interfaced
with the microprocessor and programmed to provide timings with considerable accuracy.
The disadvantages of using the hardware chip include the additional expense and the
need for an extra chip in the system.

4.2.3 Counter Design with Time Delay

The design a counter with a time delay, the techniques illustrated in Figures 4.1 and 4.2
can be combined. The combined flowchart is shown in Figure 4.4.

The blocks shown in the flowchart are similar to those in the generalized flowchart. The
block numbers shown in Figure 4.4 correspond to the block numbers in the generalized
flowchart. Note the following points about the counter flowchart (Figure 4.4):

1. The output (or display) block is a part of the counting loop.

2. The data processing block is replaced by the time-delay block.
3. The save-the-partial-answer block is eliminated because the count is saved in a
counter register, and a register can be incremented or decremented without
transferring the count to the accumulator.

The flowchart in Figure 4.4 shows the basic building blocks. However, the
sequence can be changed, depending upon the nature of the problem, as shown in Figure
4.5 a and b.

The flowchart in Figure 4.4 displays the count after initialization. For example, an up-
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counter starting at zero can be initialized as 00H using the logic shown in Figure 4.4.
However, the flowchart in Figure 4.5 (a) updates the counter immediately after
initialization. In this case, an up-counter should be initialized at FFH in order to display
the count 00H.

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Fig 4.4 Flowchart of a counter with a Time Delay

Similarly, the decision-making block differs slightly in these flowcharts. For example, if
a counter was counting up to 9, the question in Figure 4.4 would be: Is the count 10? In
Figure 4.5(a) the question would be: Is the count 9? The flowchart in Figure 4.5(b)
illustrates another way of designing a counter.
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ILLUSTRATIVE PROGRAM: HEXADECIMAL COUNTER

PROBLEM STATEMENT

Write a program to count continuously in hexadecimal from FFH to 00H in a system with
a 0.5 s clock period. Use register C to set up a one millisecond (ms) delay between each
count and display the numbers at one of the output ports.

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PROBLEM ANALYSIS

The problem has two parts; the first is to set up a continuous down-counter, and the
second is to design a given delay between two counts.

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Fig 4.5 Variations of Counter Flowchart

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1. The hexadecimal counter is set up by loading a register with an appropriate

starting number and decrementing it until it becomes zero (shown by the outer
loop in the flowchart, Figure 4.6). After the zero count, the register goes back to
FF because decrementing zero results in a (-1), which is FF in 2’s complement.
2. The one millisecond (ms) delay between each count is set up by using the
procedure explained previously in – Time Delay Using One Register. Figure 4.2
is identical with the inner loop of the flowchart shown in Figure 4.6. The delay
calculations are shown later.

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Fig 4.6 Program and Flowchart for a Hexadecimal Counter

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FLOWCHART AND PROGRAM

The flowchart in Figure 4.6 shows the two loops discussed earlier – one for the counter
and another for the delay. The counter is initialized in the first block, and the counter is
displayed in the outer loop. The delay is accomplished in the inner loop. This flowchart
in Figure 4.6 is similar to that in Figure 4.5 (a). You should study the flowchart carefully
to differentiate between the counter loop and the delay loop because they may at first
appear to be similar.

Delay Calculations. The delay loop includes two instructions: DCR C and JNZ with 15
T-states. Therefore, the time delay TL in the loop:

TL = 15 T-states x T (Clock period) x Count

= 15 x (0.5 x 10-6) x Count
= (7.5 x 10-6) x Count

The delay outside the loop includes the following instructions:

DCR B 5T Delay Outside = 40 T-states x T

MVI C, COUNT 10T the loop: To
MOV A, B 5T = 40 x (0.5 x 10-6)
OUT PORT 10T = 20 s
JMP 10T
___________________
40 T-states

Total Time Delay TD = TO + TL

1 ms = 20 x 10 + (7.5 x 10-6) x Count
-6

Count = 1 x 10-3 – 20 x 10-6 = 13010

7.5 x 10-6

Therefore, the delay count 82H (13010) must be loaded in register C to obtain 1 ms delay

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between each count.

PROGRAM DESCRIPTION

Register B is used as a counter, and register C is used for delay. Register B initially starts
with number 00h; when it is decremented by the instruction DCR, the number becomes
FFH. (Verify this by subtracting one from zero in 2’s complement). Register C is loaded
with the delay count 80H to provide a 1 ms delay in the loop. The instruction DCR C
decrements the count and the instruction JNZ (Jump On No Zero) checks the Zero flag to
see if the number in register C has reached zero. If the number is not zero, instruction

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JNZ causes a jump back to the instruction labeled “DELAY” in order to decrement ©
and, thus, the loop is repeated 12810 times.
The count is displayed by moving (B) to the accumulator, and then to the output port.
The instruction JMP causes an unconditional jump for the next count in register B,
forming a continuous loop to count from FFH to 00H. After the count reaches zero, (B)
is decremented, becoming FFH, and the counting cycle is repeated.

PROGRAM OUTPUT

When the program is executed, the actual output seen my vary according to the device
used as the output for the display. The eye cannot see the changes in a count with a 1 ms
delay. If the output port has eight LEDs, the LEDs representing the low-order bits will
appear to be on continuously, and the LEDs with high-order bits will go on and off
according to the count. If the output port is a seven-segment display, all segments will
appear to be on; a slight flicker in the display can be noticed. However, the count and the
delay can be measured on an oscilloscope.

4.2.4 Stack

The stack in an 8085/8080A microcomputer system can be described as a set of memory

locations in the R/W memory, specified by a programmer in a main program. These
memory locations are used to store binary information (bytes) temporarily during the
execution of a program.

The beginning of the stack is defined in the program by using the instruction LXI SP,
which loads a 16-bit memory address in the stack pointer register of the microprocessor.
Once the stack location is defined, storing of data bytes begins at the memory address
that is one less than the address in the stack pointer register. For example, if the stack
pointer register is loaded with the memory address 2099H (LXI SP, 2099H), the storing
of data bytes begins at 2098H and continues in reversed numerical order (decreasing
memory addresses such as 2098H, 2097H, etc). Therefore, as a general practice, the
stack is initialized at the highest available memory location to prevent the program from
being destroyed by the stack information. The size of the stack is limited only by the
available memory.

Data bytes in the register pairs of the microprocessor can be stored on the stack (two at a
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time) in reverse order (decreasing memory address) by using the instruction PUSH. Data
bytes can be transferred from the stack to respective registers by using the instruction
POP. The stack pointer register tracks the storage the retrieval of the information. Two
data bytes are being stored at a time, the 16-bit memory address in the stack pointer
register is decremented by two; when data bytes are retrieved, the address is incremented
by two. An address in the stack pointer register indicates that the next two memory
location (in descending numerical order) can be used for storage.

The stack is hared by the programmer and the microprocessor. The programmer can
store and retrieve the contents of a register pair by using PUSH and POP instructions.

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Similarly, the microprocessor automatically stores the contents of the program counter
when a subroutine is called. The instructions necessary for using the stack are explained
below.

INSTRUCTIONS

Opcode Operand

LXI SP, 16-bit Load the stack pointer register with a 16 – bit address.
PUSH Rp This is a 1-byte instruction
PUSH B It copies the contents of the specified register pair
PUSH D on the stack as described below
PUSH H The stack pointer register is decremented, and the contents
PUSH PSW of the high-order register (e.g., register B) are copied in
the location shown by the stack pointer register
The stack pointer register is again decremented, and the
contents of the low-order register (e.g., register C) are
copied in that location
The operands B, D, and H represent register pairs BC, DE,
HL, respectively.
The operand PSW represents Program Status Word,
meaning the contents of the accumulator and the flags
POP Rp This is a 1-byte instruction
POP B It copies the contents of the top two memory locations
POP D of the stack into the specified register pair
POP H First, the contents of the memory location indicated by the
POP PSW stack pointer register are copied into the low-order register
(e.g., register L), and then the stack pointer register is
incremented by 1
The contents of the next memory location are copied into
the high-order register (e.g., register H), and the stack
pointer register is again incremented by 1.

All three of these instructions belong to the data transfer (copy) group; thus, the contents
of the source are not modified, and no flags are affected.

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Example : In the following set of instructions ( illustrated in Figure 4.7 ), the stack
pointer is initialized, and the contents of register pair HL are stored on the stack by using
the PUSH instruction. Register pair HL is used for delay counter ( actual instructions are
not shown); and at the end of delay counter, the contents of HL are retrieved by using the
instruction POP. Assuming the available user memory ranges from 2000H to 20FFH,
show the contents of various registers when PUSH and POP instructions are executed.

Solution. In this example, the first instruction – LXI SP, 2099H – loads the stack
pointer register with the address 2099H (Figure 4.7.) This instruction indicates to the
microprocessor that memory space is reserved in the R/W memory as the stack, and that

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the locations beginning at 2098H and moving upward can be used for temporary storage.
This instruction also suggests that the stack can be initialized anywhere in the memory;
however, the stack location should not interfere with a program. The next instruction –
LXI H – loads data in the HL register pair, as shown in Figure 4.7.

Fig 4.7 Instructions and Register Contents in the above example.

When instruction PUSH H is executed, the following sequence of data transfer takes
place. After the execution, the contents of the stack and the register are as shown in
Figure 4.8.

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Fig 4.8 Contents on the Stack and in the Registers After the PUSH Instruction

1. The stack pointer register is decremented by one to 2098H, and the contents of the
H register are transferred to memory location 2098H.
2. The stack pointer register is again decremented by one to 2097H, and the contents
of the L register are transferred to memory location 2097H.
3. The contents of the register pair HL are not destroyed; however, HL is made
available for the delay counter.

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After the delay counter, the instruction POP H restores the original contents of the
register pair HL, as follows. Figure 4.9 illustrates the contents of the stack and the
registers following the POP instruction.

Fig 4.9 Contents on the Stack and in the Registers After the POP Instruction.

1. The contents of the top of the stack location shown by the stack pointer are
transferred to the L register, and the stack pointer register is incremented by one
to 2098H.
2. The contents of the top of the stack (now it is 2098H) are transferred to the H
register, and the stack pointer is incremented by one.
3. The contents of memory locations 2097h and 2098H are not destroyed until some
other data bytes are stored in these locations.

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Fig 4.10 Instructions and Register Content in Example.

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The available user memory ranges from 2000H to 23FFH. A program of data transfer
and arithmetic operations is stored in memory locations from 2000H to 2050H, and the
stack pointer is initialized at location 2400H. Two sets of data are stored, starting at
locations 2150H and 2280H. Registers HL and BC are used as memory pointers to the
data locations. A segment of the program is shown in Figure 4.10.

Fig 4.11 Stack Contents After the Execution of PUSH Instructions.

1. Explain how the stack pointer can be initialized at one memory location beyond
the available user memory.
2. Illustrate the contents of the stack memory and registers when PUSH and POP
instructions are executed, and explain how memory pointers are exchanged.
3. Explain the various contents of the user memory.

Solution.
1. The program initializes the stack pointer register at location 2400H, one location
beyond the user memory (Figure 4.10). This procedure is valid because the initialized
location is never used for storing information. The instruction PUSH first decrements the
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stack pointer register, and then stores a data byte
2. Figure 4.11 shows the contents of the stack pointer register and the contents of the
stack locations after the three PUSH instructions are executed. After the execution of the
PUSH (H, B, and PSW) instructions, the stack pointer moves upward (decreasing
memory locations) as the information is stored. Thus the stack can grow upward in the
user memory, even to the extent of destroying the program.

Figure 4.12 shows how the contents of various register pairs are retrieved. To restore the
original contents in the respective registers, follow the sequence Last-In-First-Out
(LIFO0. In the example, the register contents were pushed on the stack in the order of

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HL, BC, and PSW. The contents should have been restored in the order of PSW, BC, and
HL. However, the order is altered in this example to demonstrate how register contents
are exchanged.

Fig 4.12 Register Content after the Execution of POP Instruction

The instruction POP PSW transfers the contents of the two top locations to the flag
register and the accumulator, respectively, and increments the stack pointer by two to
23FCH. The next instruction, POP H, takes the contents of the top two locations (23FC
and 23FD), transfers them to registers L and H, respectively, while incrementing the
stack pointer by two, to 23FEH. The instruction POP B transfers the contents of the next
two locations to registers C and B, incrementing the stack pointer to 2400H.

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Fig 4.13 R / W Memory Contents

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By reversing the positions of two instructions, POP H and POP B, the contents of the BC
pair are exchanged with those of the HL pair. It is important to remember that the
instruction POP H does not restore the original contents of the HL pair; instead it
transfers the contents of the top two locations shown by the stack pointer to the HL pair.
3. Figure 4.13 shows the sketch of the memory map. The R/W memory includes three
types of information. The user program is stored from 2000H to 2050H. The data are
stored, starting at locations 2150H and 2280H. The last section of the user memory is
initialized as the stack where register contents are stored as necessary, using the PUSH
instructions. In this example, the memory locations from 23FFH to 23FAH are used as
the stack, which can be extended up to the locations of the second data set.

Important Concepts

The following points can be summarized from the preceding examples:

1. Memory locations in R/W memory can be employed as temporary storage for

information by initializing (loading) a 16-bit address in the stack pointer register.
2. Read/Write memory generally is used for three different purposes.
a. to write programs or some temporary instruction.
b. To store data;
c. To store information temporarily in defined memory locations called the
stack during the execution of the program.
3. The stack space grows upward in the numerically decreasing order of memory
addresses.
4. The stack can be initialized anywhere in the user memory map. However, as a
general practice, the stack is initialized as the higher user memory location so that
it will be less likely to interfere with a program.
5. A programmer can employ the stack to store the contents of register pairs by
using the instruction PUSH and can restore the contents of register pairs by using
the instruction POP. The address in the stack pointer register always points to the
top of the stack, and the address is decremented or incremented as information is
stored or retrieved.

The storage and retrieval of data types on the stacks should follow the LIFO (Last-In-
First-Out) sequence. Information in stack locations is not destroyed until new
information is stored in those locations.
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Illustrative Program: Resetting and Displaying Flags

PROBLEM STATEMENT

Write a program to perform the following functions:

1. Clear all the flags.

2. Load 00H in the accumulator, and demonstrate that the Zero flag is not affected
by the data transfer instruction.

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3. Logically OR the accumulator with itself to set the Zero flag, and display the flag
at PORT1 or store all the flags on the stack.

PROBLEM ANALYSIS

The problem concerns examining the Zero flag after instructions have been executed.
There is no direct way of observing the flags; however, they can be stored on the stack by
using the instruction PUSH PSW. The contents of the flag register can be retrieved in
any one of the registers by using the instruction POP, and the flags can be displayed at an
output port. In this example, the result to be displayed is different from the result to be
stored on the stack memory. To display only the Zero flag, all other flags should be
masked; however, the masking is not necessary in order to store all the flags.

PROGRAM

Memory Machine
Address Code Instructions Comments

XX00 31 LXI SP, XX99H ;Initialize the stack

01 99
02 XX
03 2E MVI L, 00H ;Clear flag contents in L
04 00
05 E5 PUSH H ;Place (L) on stack
06 F1 POP PSW ;Clear flags
07 3E MVI A, 00H
08 00
09 F5 PUSH PSW ;Save flags on stack
0A E1 POP H ;Retrieve flags in L
0B 7D MOV A, L
0C D3 OUT PORT0 ;Display flags
0D PORT0
0EE B7 ORA A ;Set flags and reset CY, AC
0F F5 PUSH PSW ;Save flags on stack
10 E1 POP H ;Retrieve flags in L
11 7D MOV A, L
12
13
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E6
40
UNIVERSITY ANI 40H ;Mask all flags except Z

14 D3 OUT PORT1
15 PORT1
16 76 HLT ;End of program

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________________________________________________________________________
Storing in Memory: Alternative to Output Display
_______________________________________________________________________

XX0C B7 ORA A ;Set flags and reset CY and AC

0D F5 PUSH PSW ;Save flags on stack
0E 76 HLT ;End of program

Program Description. The stack pointer register is initialized at XX99H. The

instruction MVI L clears (L), and (L) is placed on the stack, which is subsequently placed
into the flag register to clear all the flags.

To verify the flags after the execution of the MVI A instruction, the PUSH and POP
instructions are used in the same way as these instructions were used to clear the flags,
and the flags are displayed at PORT10. Similarly, the Zero flag is displayed at PORT1
after the instruction ORA.

Program Output. Data transfer (copy) instructions do not affect the flags; therefore,
no flags should be set after the instruction MVI A, even if (A) is equal to zero. PORT0
should display 00H. However, the instruction ORA will set the Zero and the Parity flags
to reflect the data conditions in the accumulator, and it also reset the CY and AC flags.
In the flag register, bit D6 represents the Z flag, and the ANI instruction masks all flags
except the Z flag. PORT1 should display 40H as shown below.

D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 1 0 0 = 40H
S Z AC P CY

Storing Output in Memory. If output ports are not available, the results can be stored in
the stack memory. The machine code (F5) at memory location XX0BH saves the flags
affected by the instruction MVI A, 00H. Then the instructions can be modified starting
from memory location XXOCH. The alternative set of instructions is shown above; it
sets the flags (using ORA instruction), and saves them on the stack without masking.
The result (44H) includes the parity flag. The contents of the stack locations should be as
shown in Figure 4.14.

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Fig 4.14 Output Stored in Stack Memory

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4.2.5 Subroutine

A subroutine is a group of instructions written separately from the main program to

perform a function that occurs repeatedly in the main program. For example, if a time
delay is required between three successive events, three delays can be written in the main
program. To avoid repetition of the same delay instructions, the subroutine technique is
used. Delay instructions are written once, separately from the main program, and are
called by the main program when needed.

The 8085/8080A microprocessor has two instructions to implement subroutines: CALL

(call a subroutine), and RET (return to main program from a subroutine). The CALL
instruction is used in the main program to call a subroutine, and the RET instruction is
used at the end of the subroutine to return to the main program. When a subroutine is
called, the contents of the program counter, which is the address of the instruction
following the CALL instruction, is stored on the stack and the program execution is
transferred to the subroutine address. When the RET instruction is executed at the end of
the subroutine, the memory address stored on the stack is retrieved, and the sequence of
execution is resumed in the main program. This sequence of events is illustrated in
Example further below.

INSTRUCTIONS

Opcode Operand

CALL 16-Bit Memory Call Subroutine Unconditionally

Address of a This is 3-byte instruction that transfers the
Subroutine program sequence to a subroutine address.
Saves the contents of the program counter (the
address of the next instruction) on the stack.
Decrements the stack pointer register by two.
Jumps unconditionally to the memory location
Specified by the second and third bytes. The
Second byte specifies a line number and the third
Byte specifies a page number.
This instruction is accompanied by a return
instruction in the subroutine.
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UNIVERSITY Return from Subroutine Unconditionally
This is a 1-byte instruction.
Inserts the two bytes from the top of the stack
Into the program counter and increments the stack
Pointer register by two.
Unconditionally returns from a subroutine.

The conditional Call and Return instructions will be described later in the chapter.

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Example. Illustrate the exchange of information between the stack and the program
counter for the following program if the available user memory ranges from 2000H to
23FFH.

Memory
Address

2000 LXI SP, 2400H ; Initialize the stack pointer at 2400H

2040 CALL 2070H ; Call the subroutine located at 2070H. This

2041 is a 3-byte instruction
2042
2043 NEXT INSTRUCTION ; The address of the next instruction
following the CALL instruction.

205F HLT ; End of the main program

2070 First Subroutine ; Beginning of the subroutine
Instruction

207H RET ; End of the subroutine

2080
Other subroutines
2398
23FF Empty space
2400 ; The stack is initialized at 2400H

Solution. After reviewing the above program note the following points:

1. The available user memory is from 2000H to 23FFH (1024 or 1K bytes);

however, the stack pointer register is initialized at 2400H, one location beyond the
user memory. This allows maximum use of the memory because the actual stack
begins at 23FFH. The stack can expand up to the location 2398H without
overlapping with the program.
2. The main program is stored at memory locations from 2000H to 205FH.
3. The CALL instruction is located at 2040H to 2042H (3-byte instruction). The
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next instruction is at 2043H.
4. The subroutine begins at the address 2070H and ends at 207FH.

PROGRAM EXECUTION

The sequence of the program execution and the events in the execution of the CALL and
subroutine are shown in Figure 4.15 and 4.16.

CALL EXECUTION

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Memory Machine
Address Code Mnemonics Comments

2040 CD CALL 2070H ; Call subroutine located at the

2041 70 memory location 2070H
2042 20
2043 NEXT INSTRUCTION

The sequence of events in the execution of the CALL instruction by the 8085 is shown in
Figure 8.10. The instruction requires five machine cycles and eighteen T-states
(seventeen T-states for the 8080A).

Fig 4.15 Subroutine Call and Program Transfer

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Fig 4.16 Data Transfer During the Execution of the CALL instruction

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The sequence of events in each machine cycle is as follows.

1. M1 – Opcode Fetch: In this machine cycle, the contents of the program counter
(2040H) are placed on the address bus, and the instruction code CD is fetched
using the data bus. At the same time, the program counter is upgraded to the next
memory address, 2041H. After the instruction is decoded and executed, the stack
pointer register is decremented by one to 23FFH.
2. M2 and M3 - Memory Read: These are two Memory Read cycles during which
the 16-bit address (2070H) of the CALL instruction is fetched. The low-order
address 70H is fetched first and placed in the internal register Z. The high-order
address 20H is fetched next, and placed in register W. During M3, the program
counter is upgraded to 2043H, pointing to the next instruction.
3. M4 and M5 – Storing of Program Counter: At the beginning of the M4 cycle, the
normal operation of placing the contents of the program counter on the address
bus is suspended, instead the contents of the stack pointer register 23FFH are
placed on the address bus. The high-order byte of the program counter (PCH =
20H) is placed on the data bus and stored in the stack location 23FFH. At the
same time, the stack pointer register is decremented to 23FEH.
During machine cycle M5, the contents of the stack pointer 23FEH are
placed on the address bus. The low-order byte of the program counter (PCL =
43H) is placed on the data bus and stored in stack location 23FEH.
4. Next Instruction Cycle: In the next instruction cycle, the program execution
sequence is transferred to the CALL location 2070H by placing the contents of W
and Z registers (2070H) on the address bus. During M1 of the next instruction
cycle, the program counter is upgraded to location 2071 (W, Z + 1).

In summary: After the CALL instruction is fetched, the 16-bit address (the operand) is
read during M2 and M3 and stored temporarily in W/Z registers. (Examine the contents
of the address bus and the data bus in Figure 4.16). In the next two cycles, the contents
of the program counter are stored on the stack. This is the address where the
microprocessor will continue the execution of the program after the completion of the
subroutine. Figure 4.17 shows the contents of the program counter, the stack pointer
register, and the stack during the execution of the CALL instruction.

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Fig 4.17 Contents of the Program Counter, the Stack Pointer, and the Stack During the
Execution of CALL Instruction.

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RET EXECUTION

At the end of the subroutine, when the instruction RET is executed, the program
execution sequence is transferred to the memory location 2043H. (The address 2043H
was stored in the top two location of the stack (23FEH and 23FFH) during the CALL
instruction. Figure 4.18 shows the sequence of events that occurs as the instruction RET
is executed.

Fig 4.18 Data Transfer During the Execution of the RET Instruction

M1 is a normal Opcode Fetch cycle. However, during M2 the contents of the

stack pointer register are placed on the address bus, rather than those of the program
counter. Data byte 43H from the top of the stack is fetched and stored in the Z register,
and the stack pointer register is upgraded to the next location, 23FFH. During M2, the
next byte – 20H – is copied from the stack and stored in register W, and the stack pointer
register is again upgraded to the next location, 2400H.

The program sequence is transferred to location 2043H by placing the contents of the
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W/Z registers on the address bus at the beginning of the next instruction cycle.

Illustrative Program: Traffic Signal Controller

PROBLEM STATEMENT

Write a program to provide given on/off timer to three traffic lights (Green, Yellow, and
Red) and two pedestrian signs (WALK and DON’T WALK). The signal lights and signs
are turned on/off by the data bits of an output port as shown below:

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Lights Data Bits On Time

1. Green D0 15 seconds
2. Yellow D2 5 seconds
3. Red D4 20 seconds
4. WALK D6 15 seconds
5. DON’T WALK D7 25 seconds

The traffic and pedestrian flow are in the same direction; the pedestrian should cross the
road when the Green light is on.
PROBLEM ANALYSIS
The problem is primarily concerned with providing various time delays for a complete
sequence of 40 seconds. The on/off times for the traffic signals and pedestrian signs are
as follows:
Time Sequence DON’T Hex
in Seconds WALK WALK Red Yellow Green Code

D7 D6 D5 D4 D3 D2 D1 D0
0
(15) 0 1 0 0 0 0 0 1 = 41H
15
(5) 1 0 0 0 0 1 0 0 = 84H
20
(20) 1 0 0 1 0 0 0 0 = 90H
40

Sending data byte 41H to the output port can turn on the Green light and the WALK sign.
Using a 1-second subroutine and a counter with a count of 1510 can provide the 15-
second delay. Similarly, the next two bytes, 84H and 90H, will turn on/off the
appropriate lights/signs as shown in the flowchart (Figure 4.19). Changing the values of
the count in the counter provides the necessary time delays.
PROGRAM
Memory
Address Code Mnemonics Comments

XX00
01
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31
99
UNIVERSITY LXI SP, XX99 ;Initialize stack pointer at location
XX99H
02 XX ;High-order address of user memory
03 3E START: MVI A, 41H ;Load accumulator with the pattern
04 41 for Green light and WALK sign
05 D3 OUT PORT# ;Turn on Green light and WALK
06 PORT# sign
07 06 MVI B, 0FH ;Use B as a counter to count 15
08 0F seconds. B is decremented
in the subroutine

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Fig 4.19 Flowchart for Traffic Signal Controller

09 CD CALL DELAY ;Call delay subroutine located

0A 50 at XX50H
0B XX ;High-order address of user memory
0C 3E ;Load accumulator with the bit
0D 84 pattern for Yellow light and DON’T
WALK
0E D3 OUT PORT# ;Turn on Yellow light and DON’T
0F PORT# WALK and turn off Green light and

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WALK
10 06 MVI B, 05 ;Set up 5-second delay counter
11 05
12 CD CALL DELAY
13 50
14 XX ;High-order address of user memory
15 3E MVI A, 90H ;Load accumulator with the bit
16 90 pattern for Red light and DON’T
WALK
17 D3 OUT PORT# ;Turn on Red light, keep DON’T
18 PORT# WALK on, and turn off Yellow
light
19 06 MVI B, 14H ;Set up the counter for 20-second
delay
1A 14
1B CD CALL DELAY
1C 50
1D XX
1E C3 JMP START ;Go back to location START to
1F 03 repeat the sequence
20 XX

DELAY: This is a1-second delay subroutine and provides delay according to the
parameter specified in register B
;Input: Number of seconds is specified in register B
;Output: None
;Registers Modified: Register B
XX50 D5 DELAY: PUSH D ;Save contents of DE and
accumulator
51 F5 PUSH PSW
52 11 SECOND: LXI D, Count ;Load register pair DE with data byte
for 1-second delay
53 LO
54 HI
55 1B Loop: DCX D ;Decrement register pair DE
56 7A MOV A,D
57
58
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B3
C2
UNIVERSITY ORA E
JNZ LOOP
;OR (D) and (E) to set Zero flag
;Jump to Loop if delay count is not
equal to 0
59 55
5A XX
5B 05 DCR B ;End of 1 second delay; decrement
the counter
5C C2 JNZ SECOND ;Is this the end of time needed? If
not, go back to repeat 1-second delay
5D 52

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5E XX ;High-order memory address of user

memory
5F F1 POP PSW ;Retrieve contents of saved registers
60 D1 POP D
61 C9 RET ;Return to main program

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Fig 4.20 Multiple – Calling for a Subroutine

PROGRAM DESCRIPTION
The stack pointer register is initialized at XX99H so that return addresses can be stored
on the stack whenever a CALL instruction is used. As shown in the flowchart this

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program loads the appropriate bit pattern in the accumulator, sends it to the output port,
and calls the delay routine. Register B is loaded in the main program and used in the
subroutine to provide appropriate timing.

The DELAY subroutine is similar to the delays discussed in Chapter 7 except it requires
the instruction RET at the end of the routine.

This example illustrates the type of subroutine that is called many times from various
locations in the main program, as illustrated in Figure 8.14.

In this program, the subroutine is called from the locations XX09, 0A, and 0BH. The
return address, XX0C, is stored on the stack, and the stack pointer is decremented by two
to location XX97H. At the end of the subroutine, the contents of the top two locations of
the stack (XXOC) are retrieved, the stack pointer register is incremented by two to the
original location (XX99H), and the main program is resumed. This sequence is repeated
two more times in the main program, as shown in Figure 4.20.

4.2.6 BCD TO BINARY CONVERSION

In most microprocessor-based products, data are entered and displayed in decimal

numbers. For example, in an instrumentation laboratory, readings such as voltage and
current are maintained in decimal numbers, and data are entered through a decimal
keyboard. The system-monitor program of the instrument converts each key into an
equivalent 4-bit binary number, and stores two BCD numbers in an 8-bit register or a
memory location. These numbers are called packed BCD. Even if data are entered in
decimal digits, it is inefficient to process data in BCD numbers because, in each 4-bit
combination, digits A through F go unused. Therefore, BCD numbers are generally
converted into binary numbers for data processing.

The conversion of a BCD number into its binary equivalent employs the principle of
positional weighting in a given number.
For example: 7210 = 7 x 10 + 2

The digit 7 represents 70, based on its second position from the right. Therefore,
converting 72BCD into its binary equivalent requires multiplying the second digit by 10,
and adding the first digit.
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Converting a 2-digit BCD number into its binary equivalent requires the following steps:

1. Separate an 8-bit packed BCD number into two 4-bit unpacked BCD digits: BCD1
and BCD2.
2. Convert each digit into its binary value according to its position.
3. Add both binary numbers to obtain the binary equivalent of the BCD number.

Example. Convert (72)BCD into its binary equivalent

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Solution. 7210 = 0111 0010BCD

Step 1: 0111 0010 0000 0010 Unpacked BCD1

0000 0111 Unpacked BCD2
Step 2: Multiply BCD2 by 10 (7 x 10)
Step 3: Add BCD1 to the answer in Step 2.

The multiplication of BCD2 by 10 can be performed by various methods. One

method is multiplication with repeated addition: add 10 seven times. This technique is
illustrated in the next program.

Illustrative Program: 2-Digit BCD to Binary Conversion

PROBLEM STATEMENT

A BCD number between 0 and 99 is stored in a R/W memory location called the Input
Buffer. Write a main program and a conversion subroutine (BCDBIN) to convert the
BCD number into its equivalent binary number. Store the result in a memory location
defined as the Output Buffer.

PROGRAM

START: LXI SP, STACK ;Initialize stack pointer

LXI H, INBUF ;Point HL index to the Input Buffer memory
Location where BCD number is stored
LXI B, OUTBUF ;Point BC index to the Output Buffer memory
Where binary number will be stored
MOV A, M ;Get BCD number
CALL BCDBIN ;Call BCD to binary conversion routine
STAX B ;Store binary number in the Output Buffer
HLT ;End of program

BCDBIN: Function: This subroutine converts a BCD number into its binary
Equivalent
;Input: A 2-digit packed BCD number in the accumulator
;Output: A binary number in the accumulator
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;No other register contents are destroyed

PUSH B ;Save BC registers

PUSH D ;Save DE registers
MOV B, A ;Save BCD number
ANI 0FH ;Mask most significant four bits
MOV C, A ;Save unpacked BCD1 in C
MOV A, B ;Get BCD again
ANI F0H ;Mask least significant four bits
RRC ;Convert most significant four

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RRC ;bits into unpacked BCD2

RRC
RRC
MOV D, A ;Save BCD2 in D
XRA A ;Clear accumulator
MVI E, 0AH ;Set E as multiplier of 10
Sum: ADD E ;Add 10 until (D) = 0
DCR D ;Reduce BCD2 by one
JNZ SUM ;Is multiplication complete?
;If not, go back and add again.
ADD C ;Add BCD1
POP D ;Retrieve previous contents
POP B
RET

PROGRAM DESCRIPTION
1. In writing assembly language programs, the use of labels is a common practice.
Rather than writing a specific memory location or a port number, a programmer
uses such labels as INBUF (Input Buffer) and OUTBUF (Output Buffer). Using
labels gives flexibility and ease of documentation.
2. The main program initializes the stack pointer and two memory indexes. It brings
the BCD number into the accumulator and passes that parameter to the
subroutine.
3. After returning from the subroutine, the main program stores the binary
equivalent in the Output Buffer memory.
4. The subroutine saves the contents of the BC and DE registers because these
registers are used in the subroutine. Even if this particular main program does not
use the DE registers, some other program in which the DE registers are being
used may call the subroutine. Therefore, it is a good practice to save the registers
that are used in the subroutine, unless parameters are passed to the subroutine.
The accumulator contents are not saved because that information is passed on to
the subroutine.
5. The conversion from BCD to binary is illustrated in the subroutine with the
example of 72BCD converted to binary.

The illustrated multiplication routine is easy to understand; however, it is rather long and
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inefficient. UNIVERSITY
PROGRAM EXECUTION
To execute the program on a single-board computer, complete the following steps:

1. Assign memory addresses to the instructions in the main program and in the
subroutine.
2. Define STACK: the stack location with a 16-bit address in the R/W memory
(such as 2099H).

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3. Define INBUF (Input Buffer) and OUTBUF (Output Buffer): two memory
locations in the R/W memory (e.g., 2050H and 2060H).
4. Enter a BCD byte in the Input Buffer (e.g., 2050H).
5. Enter and execute the program
Check the contents of the Output Buffer memory location (2060H).

4.2.7 BINARY TO BCD CONVERSION

In most microprocessor-based products, numbers are displayed in decimal. However, if

data processing inside the microprocessor is performed in binary, it is necessary to
convert the binary results into their equivalent BCD numbers just before they are
displayed. Results are quite often stored in R/W memory locations called the Output
Buffer.

Dividing the number by the powers of ten performs the conversion of binary to BCD; the
division is performed by the subtraction method.

1 1 1 1 1 1 1 12 (FFH) = 25510

To represent this number in BCD requires twelve bits or three BCD digits, labeled here as
BCD3 (MSB), BCD2, and BCD1(LSB),

=0 0 1 0 0 1 0 1 0 1 0 1
BCD3 BCD2 BCD1

The conversion can be performed as follows:

Step 1: If the number is less than 100, go to Step 2: Example Quotient
Otherwise, divide by 100 or subtract 100 255
Repeatedly until the remainder is less than 100. -100 = 155 1
The quotient is the most significant BCD digit -100 = 5 1
BCD3. BCD3 = 2
Step 2: If the number is less than 10, go to Step 3; 55
Otherwise divide by 10 repeatedly until the -10 = 45 1
Remainder is less than 10. The quotient is BCD2. -10 = 35 1
-10 = 25 1
-10 = 15 1
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BCD2
05
=
1
5
BCD1 = 5

Step 3: The remainder from step 2 is BCD1.

These steps can be converted into a program as illustrated next.

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Illustrative Program: Binary to Unpacked BCD Conversion

PROBLEM STATEMENT

A binary number is stored in memory location BINBYT. Convert the number into BCD,
and store each BCD as unpacked BCD digits in the Output Buffer. To perform this task,
write a main program and two subroutines: one to supply the powers of ten, and the other
to perform the conversion.

PROGRAM

This program converts an 8-bit binary number into a BCD number; thus it requires twelve
bits to represent three BCD digits. The result is stored as three unpacked BCD digits in
three Output-Buffer memory locations.

START; LXI SP, STACK ;Initialize stack pointer

LXI H, BINBYT ;Point HL index where binary number is stored
MOV A, M ;Transfer byte
CALL PWRTEN ;Call subroutine to load powers of 10
HLT

PWRTEN: ;This subroutine loads the powers of 10 in register B and calls the binary
;to BCD conversion routine
;Input: Binary number in the accumulator
;Output: Powers of ten and store BCD1 in the first Output-Buffer memory
;Calls BINBCD routine and modifies register B

LXI H, OUTBUF ;Point HL index to Output-Buffer memory

MVI B, 64H ;Load 100 in register B
CALL BINBCD ;Call conversion
MVI B, 0AH ;Load 10 in register B
CALL BINBCD
MOV M, A ;Store BCD1
RET

BINBCD: ;This subroutine converts a binary number into BCD and stores BCD2 and
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;BCD3 in the Out put Buffer.
;Input: Binary number in accumulator and powers of 10 in B
;Output: BCD2 and BCD3 in Output Buffer
;Modifies accumulator contents

MVI M, FFH ;Load buffer with (0 -1)

NXTBUF: INR M ;Clear buffer and increment for each subtraction
SUB B ;Subtract power of 10 from binary number
JNC NXTBUF ;Is number > power of 10? If yes, add 1 to buffer
ADD B ;If no, add power of 10 to get remainder

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INX H ;Go to next buffer location

RET

PROGRAM DESCRIPTION

This program illustrates the concepts of the nested subroutine and the multiple-call
subroutine. The main program calls the PWRTEN subroutine; in turn, the PWRTEN
calls the BINBCD subroutine twice.

1. The main program transfers the byte to be converted to the accumulator and calls
the PWRTEN subroutine.
2. The subroutine PWRTEN supplies the powers of ten by loading register B and the
address of the first Output-Buffer memory location, and calls conversion routine
BINBCD.
3. In the BINBCD conversion routine, the Output-Buffer memory is used as a
register. It is incremented for each subtraction loop. This step also can be
achieved by using a register in the microprocessor. The BINBCD subroutine is
called twice, once after loading register B with 64H(10010), again after loading
register B with 0AH(1010).
4. During the first call of BINBCD, the subroutine clears the Output Buffer, stores
BCD3, and points the HL registers to the next Output-Buffer location. The
instruction ADD B is necessary to restore the remainder because one extra
subtraction is performed to check the borrow.
5. During the second call of BINBCD, the subroutine again clears the output buffer,
stores BCD2, and points to the next buffer location. BCD3 is already in the
accumulator after the ADD instruction, which is stored in the third Output-Buffer
memory by the instruction MOV M, A in the PWRTEN subroutine.

This is an efficient subroutine; it combines the functions of storing the answer and
finding a quotient. However, two subroutines are required, and the second subroutine is
called twice for a conversion.

4.2.8 BCD TO SEVEN-SEGMENT LED CODE CONVERSION

When a BCD number is to be displayed by a seven-segment LED, it is necessary to

convert the BCD number to its seven-segment code. The code is determined by hardware
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considerations such as common cathode or common anode LED; the code has no direct
relationship to binary numbers. Therefore, to display a BCD digit at a seven-segment
LED, the table look-up technique is used.

In the table look-up technique, the codes of the digits to be displayed are stored
sequentially in memory. The conversion program locates the code of a digit based on its
magnitude, and transfers the code to the MPU to send out to a display port. The table
look-up technique is illustrated in the next program.

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Illustrative Program: BCD to Common Cathode LED Code Conversion

PROBLEM STATEMENT

A set of three packed BCD numbers (six digits) representing time and temperature are
stored in memory locations starting at XX50H. The seven-segment codes of the digits 0
to 9 for a common cathode LED are stored in memory locations starting at XX70H, and
the Output-Buffer memory is reserved at XX90H.

Write a main program and two subroutines, called UNPAK and LEDCOD, to unpack the
BCD numbers and select an appropriate seven-segment code for each digit. The codes
should be stored in the Output-Buffer memory.

PROGRAM

LXI SP, STACK ;Initialize stack pointer

LXI H, XX50H ;Point HL index where BCD digits are stored
MVI D, 03H ;Number of digits to be converted is placed in D
CALL UNPAK ;Call subroutine to unpack BCD numbers
HLT ;End of conversion
UNPAK: ;This subroutine unpacks the BCD number into two single digits.
;Input: Starting memory address of the packed BCD numbers in HL
;registers: Number of BCDs to be converted in register d
;Output: Unpacked BCD into accumulator and Output
Buffer address in BC
;Calls subroutine LEDCOD

LXI B, BUFFER ;Point BC index to the buffer memory

NXTBCD: MOV A, M ;Get packed BCD number
ANI F0H ;Masked BCD1
RRC ;Rotate four times to place BCD2 as unpacked
RRC ;single digit BCD
RRC
RRC
CALL LEDCOD ;Find seven-segment code
INX B ;Point to next buffer location
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MOV A, M
ANI 0FH
;Get BCD number again
;Separate BCD1
CALL LEDCOD
INX B
INX H ;Point to next BCD
DCR D ;One conversion complete, reduce BCD count
JNZ NXTBCD ;If all BCDs are not yet converted, go back to
;convert next BCD
RET

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LEDCOD: ;This subroutine converts an unpacked BCD into its seven-segment LED
;code
;Input: An unpacked BCD in accumulator
:Memory address of the buffer in BC register
;Output: Stores seven-segment code in the output buffer

PUSH H ;Save HL contents of the caller

LXI H, CODE ;Point index to beginning of 7-segment code
ADD L ;Add BCD digit to starting address of code
MOV L, A ;Point HL to appropriate code
MOV A, M ;Get seven-segment code
STAX B ;Store code in buffer
POP H
RET

CODE: 3F ;Digit 0:Common cathode codes

06 ;Digit 1
5B ;Digit 2
4F ;Digit 3
66 ;Digit 4
6D ;Digit 5
7D ;Digit 6
07 ;Digit 7
7F ;Digit 8
6F ;Digit 9
00 ;Invalid Digit

PROGRAM DESCRIPTION/OUTPUT

1. The main program initializes the stack pointer, the index for BCD digits, and the
counter for the number of digits; and calls the UNPAK subroutine.
2. The UNPAK subroutine transfers a BCD number into the accumulator, and
unpacks it into two BCD digits by using the instruction ANI and RRC. This
subroutine also supplies the address of the buffer memory to the next subroutine,
LEDCOD. The subroutine is repeated until counter D becomes zero.
3. The LEDCOD subroutine saves the memory address of the BCD number and
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points the HL register to the beginning address of the code.
4. The instruction ADD L adds the BCD digit in the accumulator to the starting
address of the code. After storing the sum in register L, the HL register points to
the seven-segment code of that BCD digit.
5. The code is transferred to the accumulator and stored in the buffer.

This illustrative program uses the technique of the nested subroutine (one subroutine
calling another). Parameters are passes from one subroutine to another; therefore, you
should be careful in using Push instructions to store register contents on the stack. In

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addition, the LEDCOD subroutine does not account for a situation if by adding the
register L a carry is generated

4.2.9 Binary to ASCII and ASCII to Binary Code Conversion

The American Standard Code for Information Interchange (known as ASCII) is

used commonly in data communication. It is a seven-bit code, and its 128(27)
combinations are assigned different alphanumeric characters. For example, the
hexadecimal numbers 30H to 39H represent 0 to 9 ASCII decimal numbers, and 41H to
5AH represent capital letters A through Z; in this code, bit D7 is zero. In serial data
communication, bit D7 can be used for parity checking.

The ASCII keyboard is a standard input device for entering programs in a

microcomputer. When an ASCII character is entered, the microprocessor receives the
binary equivalent of the ASCII Hex number. For example, when the ASCII key for digit
9 is pressed, the microprocessor receives the binary equivalent of 39H, which must be
converted to the binary 1001 for arithmetic operations. Similarly, to display digit 9 at the
terminal, the microprocessor must send out the ASCII Hex code (39H). These
conversions are done through software, as in the following illustrative program.

Illustrative Program: Binary to ASCII Hex Code Conversion

PROBLEM STATEMENT

An 8-bit binary number (e.g., 9FH) is stored in memory location XX50H.

1. Write a program to
a. Transfer the byte to the accumulator.
b. Separate the two nibbles (as 09 and 0F).
c. Call the subroutine to convert each nibble into ASCII Hex code.
d. Store the codes in memory locations XX60H AND XX61H.
2. Write a subroutine to convert a binary digit (0 to F) into ASCII Hex code.

MAIN PROGRAM

LXI SP, STACK ;Initialize stack pointer

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LXI H, XX50H
LXI D, XX60H
;Point index where binary number is stored
;Point index where ASCII code is to be stored
MOV A, M ;Transfer byte
MOV B, A ;Save byte
RRC ;Shift high-order nibble to the position of low-order nibble
RRC
RRC
RRC
CALL ASCII ;Call conversion routine
STAX D ;Store first ASCII Hex in XX60H

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INX D ;point to next memory location, get ready to store next byte
MOV A, B ;Get number again for second digit
CALL ASCII
STAX D
HLT

ASCII: ;This subroutine converts a binary digit between 0 and F to ASCII Hex
;code
;Input: Single binary number 0 to F in the accumulator
;Output: ASCII Hex code in the accumulator

ANI 0FH ;Mask high-order nibble

CIP 0AH ;Is digit less than 1010?
JC CODE ;If digit is less than 1010, go to CODE to add 30H
ADI 07H ;Add 7H to obtain code for digits from A to F
CODE: ADI 30H ;Add base number 30H
RET

PROGRAM DESCRIPTION

1. The main program transfers the binary data byte from the memory location to the
accumulator.
2. It shifts the high-order nibble into the low-order nibble, calls the conversion
subroutine, and stores the converted value in the memory.
3. It retrieves the byte again and repeats the conversion process for the low-order
nibble.

In this program, the masking instruction ANI is used once in the subroutine rather than
twice in the main program as illustrated in the program for BCD to Common Cathode
LED Code Conversion.

Illustrative Program: ASCII Hex to Binary Conversion

PROBLEM STATEMENT

Write a subroutine to convert an ASCII Hex number into its binary equivalent. A calling
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program places the ASCII number in the accumulator, and the subroutine should pass the
conversion back to the accumulator.

SUBROUTINE

ASCBIN: ;This subroutine converts an ASCII Hex number into its binary
;Input: ASCII Hex number in the accumulator
;Output: Binary equivalent in the accumulator

SUI 30H ;Subtract 0 bias from the number

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CPI 0AH ;Check whether number is between 0 and 9

RC ;If yes, return to main program
SUI 07H ;If not, subtract 7 to find number between A and F
RET

PROGRAM DESCRIPTION

This subroutine subtracts the ASCII weighting digits from the number. This process is
exactly opposite to that of the Illustrative Program that converted binary into ASCII Hex.
However, this program uses two return instructions, an illustration of the multiple-ending
subroutine.

MULTIPLICATION

Multiplication can be performed by repeated addition; this technique is used in BCD-to-

binary conversion. It is, however an inefficient technique for a large multiplier. A more
efficient technique can be devised by following the model of manual multiplication of
decimal numbers. For example

108
x 15
Step 1: (108 x 5) = 540
Step 2: Shift left and add
(108 x 1) = + 108
1620

In this example, the multiplier multiplies each digit of the multiplicand, starting from the
farthest right, and adds the product by shifting to the left. The same process can be
applied in binary multiplication.

Illustrative Program: Multiplication of Two 8-Bit Unsigned Numbers

PROBLEM STATEMENT

A multiplicand is stored in memory location XX50H and a multiplier is stored in location

XX51H. Write a main program to
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1. Transfer the two numbers from memory locations to the HL registers.
2. Store the product in the Output Buffer at XX90H.

Write a subroutine to

1. Multiply two unsigned numbers placed in registers H and L.

2. Return the result into the HL pair.

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MAIN PROGRAM

LXI SP, STACK

LHLD XX50H ;Place contents of XX50 in L register and contents
;of XX51 in H register
XCHG ;Place multiplier in D and multiplicand in E
CALL MLTPLY ;Multiply the two numbers
SHLD XX90H ;Store the product in locations XX90 and 91H
HLT

Subroutine
;MLTPLY : This subroutine multiplies two 8-bit unsigned numbers
;Input : Multiplicand in register E and multiplier in register D
;Output : Results in HL register

MLTPLY: MOV A, D ;Transfer multiplier to accumulator

MVI D, 00H ;Clear D to use in DAD instruction
LXI H, 0000H ;Clear HL
MVI B, 08H ;Set up register B to count eight rotations
NXTBIT: RAR ;Check if multiplier bit is 1
JNC NOADD ;If not, skip adding multiplicand
DAD D ;If multiplier is 1, add multiplicand to HL and place
;partial result in HL
NOADD: XCHG ;Place multiplicand in HL
DAD H ;And shift left
XCHG ;Retrieve shifted multiplication
DCR B ;One operation is complete, decrement counter
JNZ NXTBIT ;Go back to next bit
RET

PROGRAM DESCRIPTION

1. The objective of the main program is to demonstrate use of the instruction LHLD,
SHLD, and XCHG. The main program transfers the two bytes (multiplier and
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multiplicand) from memory locations to the HL registers by using the instruction
LHLD, places them in the DE register by the instruction XCHG, and places the
result in the Output Buffer by the instruction SHLD.
2. The multiplier routine follows the format – add and shift to the left – illustrated at
the beginning. The routine places the multiplier in the accumulator and rotates it
eight times until the counter (B) becomes zero. The reason for clearing D is to
use the instruction DAD to add register pairs.
3. After each rotation, when a multiplier bit is 1, the instruction DAD D performs
the addition, and DAD H shift bits to the left. When a bit is 0, the subroutine
skips the instruction DAD D and just shifts the bits.

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4.2.10 Software Development System

A software development system is simply a computer that enables the user to write,
modify, debut, and test programs. In a microprocessor-based development system, a
microcomputer is used to develop software for a particular microprocessor. Generally,
the microcomputer has a large R/W memory (64K), disk storage, and a video terminal
with ASCII keyboard. The system includes programs that enable the user to develop
software either assembly language or high-level languages. This text will focus on
developing programs in the 8085/8080A assembly language.

Conceptually, this type of microcomputer is similar to a single-board microcomputer

except that it has features that can assist in developing large programs. Programs are
accessed and stored under a file name (title), and they are written by using other
programs such as text editors and assembler. The system (I/Os, files, programs, etc.) is
managed by a program called the operating system.

Operating Systems and CP/M

The operating system of a computer is a group of programs that manages or oversees all
the operations of the computer. The computer transfers information constantly among
peripherals such as floppy disk, printer, keyboard, and video monitor. It also stores user
programs under file names on a disk. A file is defined as related records stored as a
single entity. The operating system is responsible primarily for managing the files on the
disk and the communication between the computer and its peripherals.

Each computer has its own operating system. CP/M (Control Program/Monitor) is by far
the most widely used operating system for microcomputers designed around the
8085/8080A and the Z-80 microprocessors. The CP/M design is, for the most part
independent of the machine, so that microcomputer manufacturers can adapt it to their
own designs with minimum changes. Other popular microcomputers, such as the TRS-80
(Radio Shack), Cromemco, or North Star, have their own operating systems. To illustrate
the operation of a software development system, CP/M is briefly described in reference to
a system with 64 R/W memory.

CP/M
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The operating system is divided into three components: BIOS (Basic Input/Output
System), BDOS (Basic Disk Operating System), and CCP (Console Command
Processor).

BIOS
The BIOS program consists of input/output routines; it manages data transfer between the
microprocessor and various peripherals. This section of CP/M is accessible to the user.
Each manufacturer modifies I/O port addresses in this section according to the hardware
design in a particular system.

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BDOS
The BDOS program directs the activities of the disk controller and manages the file
allocation on the disk and is not accessible to the user. The BDOS program allocates
memory spaces under a file name.

Fig 4.21 CP / M Memory Map with 64K R / W Memory

CCP
The CCP program reads and interprets the CP/M commands from the keyboard. These
commands include operations such as listing the programs on the disk, copying, erasing,
and renaming a file. CCP also transfers the program control from CP/M to user or other
programs.

When CP/M is loaded into a system’s R/W memory, it occupies approximately 6K of

memory at the highest available locations, as shown in Figure 4.21. In addition, the first
256 location (from 0000 to 00FFH) are reserved for system parameters. The rest of the
R/W memory (approximately 58K) is available for the user. Once the operating system
is loaded into R/W memory, the user can write, assemble, test, and debug programs by

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using utility programs.

Tools for Developing Assembly Language Programs

The CP/M operating system includes programs called utility programs. These programs
can be classified in two categories; file management utilities, and program development
utilities. The file management utilities are programs that enable the user to perform
functions such as copying, printing, erasing, and renaming files. The program
development utilities enable the user to write, assemble, and test assembly language
programs; they include programs such as Editor, Assembler, Loader, and Debugger.

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EDITOR
The Editor is a program that allows the user to enter, modify, and store a group of
instructions or text under a file name. To write text, the user must call the Editor under
CP/M control. As soon as the Editor program is transferred from the disk to the system
memory, the program control is transferred from CP/M to the Editor program. The
Editor has its own commands, and the user can enter and modify text by using those
commands. Some Editor programs, such as “Word Star”, are very easy to use. At the
completion of writing a program, the exit command of the Editor will save the program
on the disk under the file name, and will transfer the program control to CP/M. This file
is known as a source file or a source program. If the source file is intended to be a
program in the 8085/8080A assembly language, the user should follow the syntax of the
assembly language and the rules of the assembler program that is described next. The
Editor program is not concerned with whether one is writing a letter or an assembly
language program.

ASSEMBLER
The Assembler (ASM) is a program that translates mnemonics into the Intel Hex code of
8085/8080A microprocessor and generates a file called the Hex file. This function is
similar to manual assembly, whereby the user looks up the code for each mnemonic in
the listing. In addition to translating mnemonics, the Assembler performs various
functions, such as error checking and memory allocations. The Assembler is described in
more detail in Section 10.2.

LOADER
The Loader (LOAD) is a program that takes the Hex file generated by the assembler and
generates a file in binary code called COM file or the object code. The COM file is the
only executable file: i.e., the only file that can be executed by the microcomputer. To
execute the program, the COM file is called under CP/M control and executed.

DEBUGGER
The Debugger, also known as DDT (Dynamic Debugging Tool), is a program that allows
the user to test and debug the object file. The user can employ this program to perform
the following functions:
1. Make changes in the object code.
2. Examine and modify the contents of memory.
3. Set breakpoints, execute a segment of the program, and display register contents
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after the execution.
4. Trace the execution of the specified segment of the program, and display the
register and memory contents after the execution of each instruction.
5. Disassemble a section of the program; i.e., convert the object code into the source
code or mnemonics.

In the CP/M assembler, translating mnemonics into binary code is a two-step process:
first, the source file is converted into the Hex file by the ASM program; then, the Hex
file is converted into the binary object file by the LOAD program. This is called
program assembly, and the two programs in combination (ASM and LOAD) can be

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viewed as the CP/M assembler. In addition, the assembler also generates the print
(PRN) file and the backup (BAK) file. The PRN file is generated for documentation,
and the BAK file is generated when the user calls the ASM file for reediting; the
BAK file is the copy of the previous file before the user begins to reedit. The BAK
file is generated as a precautionary measure, in the event the user wishes to go back to
the previous file. At the completion of the assembly process, the CP/M user will have
the following five files:

ASM File: This is the source file written by the user.

HEX File: This is generated by the assembler program and contains the program code
in hexadecimal notations.
PRN File: This is the print file generated by the assembler program for
documentation purposes. It contains memory locations, Hex code, mnemonics, and
comments.
COM File: This is the executable file generated by the loader program, and it
contains binary code.
BAK File: When the ASM file is called for reediting, the previous file is saved as the
BAK file.

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4.3 Revision Points

Counter
The counter is designed simply by loading an appropriate number into one of the registers
and using the INR or the DCR.

Time Delay
The procedure used to design a specific delay is similar to that used to set up a counter.
A register is loaded with a number, depending on the time delay required, and then the
register is decremented until it reaches zero by setting up a loop with a conditional Jump
instruction. The loop caused the delay, depending upon the clock period of the system

Stack
The stack in an 8085/8080A microcomputer system can be described as a set of memory
locations in the R/W memory, specified by a programmer in a main program.

Subroutine
A subroutine is a group of instructions written separately from the main program to
perform a function that occurs repeatedly in the main program.

4.4 Intext Questions

1. What is time delay?
2. What is a stack
3. Explain the need for a subroutine?
4. Explain the stack operations?
5. Explain use of a counter?

4.5 Summary
 Counters are used primarily to keep track of events, while time delays are
important in setting up reasonably accurate timing between two events.

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 The stack in an 8085/8080A microcomputer system can be described as a set of
memory locations in the R/W memory, specified by a programmer in a main
program.
 The beginning of the stack is defined in the program by using the instruction
LXI SP, which loads a 16-bit memory address in the stack pointer register of
the microprocessor.

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 The stack space grows upward in the numerically decreasing order of memory
addresses.
 The stack can be initialized anywhere in the user memory map.
 A subroutine is a group of instructions written separately from the main
program to perform a function that occurs repeatedly in the main program.
 The operating system is divided into three components: BIOS (Basic
Input/Output System), BDOS (Basic Disk Operating System), and CCP
(Console Command Processor).
 The Assembler (ASM) is a program that translates mnemonics into the Intel
Hex code of 8085/8080A microprocessor and generates a file called the Hex
file.
 The Loader (LOAD) is a program that takes the Hex file generated by the
assembler and generates a file in binary code called COM file or the object
code.

4.6 Terminal Exercises

1. What is counter?
2. Why assembler is needed?
3. What happens when RET instruction is encountered?
4. What does POP and PUSH do?

4.7 Supplementary Materials

1. Ramesh S. Goankar, “Microprocessor Architecture & Applications”, Third
Edition, Penram international Publishing (India), 1997.
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2. Mathur, “Introduction to Microprocessors”, Third Edition, TMH.

4.8 Assignments

1. Discuss in detail about stack and its operations

2. Write a program with subroutine.

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4.9 Suggested Reading/Reference Books/Set Books

1. “Introduction to Microprocessor, Software, Hardware programming “,

L.A.Levanthal.
2. “Fundamentals of Microprocessor”, B.Ram, Dhanapat Rai & Son’s

4.10 Learning Activities

Programming sequences, hence there are no learning activities.

4.11 Keywords
INR
DCR
CALL
RET
POP
PUSH

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UNIT - V
5.0 Introduction
The primary function of the microprocessor (MPU) is to accept data from input
devices such as keyboards and A/D converters, read instructions, and send the results to
output devices such as LEDs, printers, and video monitors. These input and output
devices are called either peripherals or I / Os; memory can be viewed as a special type
of I / O. Designing logic circuits (hardware) and writing instructions (software) to enable
the microprocessor to communicate with these peripherals is called interfacing, and the
logic circuits are called I / O ports or interfacing devices.

The microprocessor (MPU) communicates with the peripherals in either of two

formats: asynchronous or synchronous. Similarly, it transfers data in either of two
modes: parallel I / O or serial I / O. The 8085 identifies peripherals either as memory -
mapped I / O or peripheral I / O based on their interfacing logic circuits.

In peripheral I / O, peripheral is identified with an 8-bit address. The 8085 has

two instructions – IN and OUT – to implement data transfer between the microprocessor
and peripherals. These are 2-byte instructions; the second byte specifies the address or the
port number of a peripheral. The instruction IN transfers (copies) data from an input
device to the accumulator, and the instruction OUT transfer’s data from accumulator to
an output device.

5.1 Objective
This lesson provides you the detailed study about 8080A and 8085 interrupt,
Concepts of serial I/O, Synchronous and Asynchronous transmission, Programmable
interface devices, 8185/8186 programmable I/O ports and timer and the 8279
Programmable Keyboard/Display interface. Towards end of this lesson student can
understand the applications of microprocessors and a temperature monitoring system.

5.2 Content

5.2.1 The 8080A Interrupt

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The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which
is internal to the processor and can be set or reset by using software instructions. If the
flip-flop is enabled and the input to the interrupt signal INT (pin 14) goes high, the
microprocessor is interrupted. This is a maskable interrupt and can be disabled. The
8080A has only one interrupt signal; it does not have a nonmaskable interrupt. The 8085
has an interrupt signal called INTR (pin 10), functionally identical with the 8080A
interrupt. However, the 8085 has additional interrupt signals as well. To avoid
confusion, we will refer to the interrupt process that is common to both the processors as
the 8080A interrupt. The best way to describe the 8080A interrupt process is to compare

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it to a telephone with a blinking light instead of a ring. Assume that you are reading an
interesting novel at your desk where there is a telephone. In order for you to receive and
respond to a telephone call, the following steps should occur.

1. The telephone system should be enabled, meaning that the receiver should be on
the hook.
2. You should glance at the light at certain intervals to check whether someone is
calling.
3. If you see a blinking light, you should pick up the receiver, say hello, and wait for
a response. Once you pick up the phone, the line is busy, and no more calls can
be received until you replace the receiver.
4. Assuming that the caller is you roommate, the request may be: It is going to rain
today. Will you please shut all the windows in my room?
5. You insert a bookmark on the page you are reading.
6. You replace the receiver on the hook
7. You shut your roommate’s windows.
8. You go back your book, find your mark, and start reading again.

Steps 6 and 7 may be interchanged, depending on the urgency of the request. If the
request is critical and you do not want to be interrupted while attending to the request,
you like to attend to the request first, then put the receiver back on the hook. The 8080A
interrupt process can be described in terms of those eight steps.

Step 1: writing the instruction EI in the main program should enable the interrupt process.
This is similar to keeping the phone receiver on the hook. The instruction EI sets the
Interrupt Enable flip-flop. The instruction DI resets the flip-flop and disables the
interrupt process.

Instruction EI (Enable Interrupt)

1. This is a 1-byte instruction.
2. The instruction sets the Interrupt Enable flip-flop and enables the interrupt
process..
3. System reset or an interrupt disables the interrupt process.

Instruction DI (Disable Interrupt)

1. This is a1-byte instruction.
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2. The instruction resets the Interrupt Enable flip-flop and disables the
interrupt.
3. It should be included in a program segment where an interrupt from an
outside source cannot be tolerated.

Step 2: When the microprocessor is executing a program, it checks the INT line (INTR in
the 8085) during the execution of each instruction.

Step 3: If the line INT is high and the interrupt is enabled, the microprocessor completes
the current instruction, disables the Interrupt Enable flip-flop and sends a signal called

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INTA – Interrupt Acknowledge (active low). The processor cannot accept any interrupt
requests until the interrupt flip-flop is enabled again.

Step 4: The signal INTA is used to insert an instruction, preferably, a restart (RST)
instruction, through additional hardware. The RST instruction is a 1-byte call instruction
(explained below) that transfers the program control to a specific memory location on
page 00H and restarts the execution at that memory location after executing Step 5.

Step 5: If the microprocessor receives an RST instruction, it saves the memory address of
the next instruction on the stack. This is similar to inserting a bookmark. The program is
transferred to the CALL location.

Step 6: Assuming that the task to be performed is written as a subroutine at the specified
location, the processor performs the task. This subroutine is known as a service routine.

Step 7: The service routine should include the instruction EI to enable the interrupt again.
This is similar to putting the receiver back on the hook.
Step 8: At the end of the subroutine, the RET instruction retrieves the memory address
where the program was interrupted and continues the execution. This is similar to
finding the page where you interrupted by the phone call and continuing to read.
We will elaborate further on the restart instructions and additional hardware mentioned in
Step 4.
RST (RESTART) INSTRUCTIONS
The 8085/8080A instruction set includes eight RST (Restart) instructions. These are 1-
byte Call instructions and transfer the program execution to a specific location on page
00H, as listed in Table 5.1.

Table 5.1 Restart Instructions

Hex Call Location
Binary Code
Code in Hex
Mnemonics D7 D6 D5 D4 D3 D2 D1 D0

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1 1 0 0 0 1 1 1 C7 0000
RST 1 1 1 0 0 1 1 1 1 CF 0008
RST 2 1 1 0 1 0 1 1 1 D7 0010
RST 3 1 1 0 1 1 1 1 1 DF 0018
RST 4 1 1 1 0 0 1 1 1 E7 0020
RST 5 1 1 1 0 1 1 1 1 EF 0028
RST 6 1 1 1 1 0 1 1 1 F7 0030
RST 7 1 1 1 1 1 1 1 1 FF 0038

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To implement Step 4 in the interrupt process, insert one of these instructions in the
microprocessor by using external hardware and the signal INTA (Interrupt
Acknowledge), as shown in Figure 5.1.

Fig 5.1 A circuit to implement the Instruction RST 5

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Fig 5.2 8085 Timing of the Interrupt Acknowledge Machine Cycle an Execution

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In Figure 5.1, the instruction RST 5 is built using resistors and a tri-state buffer. Figure
5.2 shows the timing of the 8085 Interrupt Acknowledge machine cycle. In response to
the INTR (Interrupt Request) high signal, the 8085 send the INTA (Interrupt
Acknowledge) low signal, which is used to enable the buffer, and the RST instruction is
placed on the data bus during M1. During M1, the program counter holds the memory
address of the next instruction, which should be stored on the stack so that the program
can continue after the service routine. During M2, the address of the stack pointer minus
one (SP – 1) location is placed on the address bus, and the high-order address of the
program counter is stored on the stack. During M3, the low-order address of the program
counter is stored in the next location (SP – 2) of the stack.

The machine cycle M1 of the interrupt acknowledge is identical with the Opcode Fetch
cycle, with two exception. The INTA signal is sent out instead of the RD signal, and the
status lines (IO/M, S0 and S1) are ! 1 1 instead of 0 1 1 (see Figure 12.2). During M1,
the RST 5 is decoded, a 1-byte Call instruction to location 0028H. The Machine cycles
M2 and M3 are Memory Write Cycles that store the contents of the program counter on
the stack, and then a new instruction cycle begins.

In this next instruction cycle, the program is transferred to location 0028H. However,
there are only eight memory locations available for RST 5 if RST 6 is being used in the
system; RST 6 begins at 0030H. If the service routine requires more than eight locations,
the routine is written somewhere else in R/W memory, and the Jump instruction is
written at 0028H to specify the address of the service routine.

5.2.2 The 8085 Interrupts

The 8085 has five interrupt inputs (Figure 5.3). One is called INTR, which is identical
with the INT input in the 8080A. The other four are automatically vectored (transferred)
to specific locations on memory page 00H without any external hardware. They do not
require the INTA signal or an input port; the necessary hardware is already implemented
inside the 8085. These interrupts and their call locations are as follows:

Interrupts Call Locations

1. TRAP 0024H
2. RST 7.5 003CH
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3.
4.
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RST 6.5
RST 5.5
0034H
002CH

The TRAP has the highest priority, followed by RST 7.5, 6.5, 5.5, and INTR, in that
order.

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Fig 5.3 The 8085 Interrupts and Vector Locations

TRAP

TRAP, a nonmaskable interrupt known as NMI, is analogous to the smoke detector

described earlier: It has the highest priority; it need not be enabled; and it cannot be
disabled. It is level and edge sensitive, meaning that the input should go high and stay
high to be acknowledged. It cannot be acknowledged again until it makes a transition
from high to low to high.

Figure 5.3 shows that when this interrupt is triggered, the program control is transferred
to location 0024H without any external hardware or the interrupt enable instruction EI.
TRAP is generally used for such critical events as power failure and emergency shut-off.
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RST 7.5, 6.5,and 5.5

These maskable interrupts (shown in Figure 5.4) are enabled under program control with
two instructions: EI (Enable Interrupt) described earlier, and SIM (Set Interrupt Mask)
described below:

Instruction. SIM: Set Interrupt mask

1. This is a 1-byte instruction.

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2. This instruction reads the contents of the accumulator and enables or disables the
interrupts according to the contents of the accumulator.
3. Bits D7 and D6 of the accumulator are used for serial I/O and do not affect the
interrupts. D6 = 1 enables the serial I/O.
4. Bit D3 is a control bit and should = 1, in order for bits D0, D1, and D2 to be
effective. Logic 0 in D0, D1, and D2 will enable the corresponding interrupts, and
logic 1 will disable the interrupts.
5. Bit D4 is additional control for the RST 7.5. If D4 = 1, the RST 7.5 flip-flop is
reset. This is used to override RST 7.5 without servicing it.

Fig 5.4 Interpretation of the Accumulator Bit Pattern

The mnemonic SIM is confusing. The wording – Set Interrupt Mask – implies that the
instruction masks the interrupts. However, the instruction must be executed in order to
use the interrupts. The process required to enable these interrupts can be likened to a
switchboard controlling three telephone extensions in a company. Let us assume these
phone extensions are assigned to the president (RST 7.5), the vice-president (RST 6.5)
and the manager (RST 5.5), in that priority, and are monitored by their receptionist
according to the instructions given. The protocols are placing a telephonic call to one of
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the executives and of interrupting the microprocessor using RST 7.5, 6.5, and 5.5 can be
compared as follows:

Placing a telephone call Interrupting 8085 (Figure 5.4)

1. The switchboard is functional and all 1. The interrupt process is enabled.

telephones lines are open. The instruction EI sets the
Interrupt Enable flip-flop, and one
of the inputs to the AND gates is
set to logic 1 (Figure 5.3). These
AND gates activate the program

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transfer to various vectored

locations.

2. All executives leave instructions on the 2. An appropriate bit pattern is

receptionist’s desk as to whether they loaded into the accumulator.
wish to receive any phone calls.

3. The receptionist reads the instructions. 3. If bit D3 = 1, the respective

interrupts are enabled according to
bits D2 – D0

4. The receptionist is on duty, and send 4. RST 7.5, 6.5, and 5.5 are being
calls through for whomever is available. Monitored.

5. The receptionist is busy typing. 5. If bit D3 = 0, bits D2 – D0 have

Phone calls can be received directly no effect on previous conditions.
According to previous instructions.

6. No calls for the president now. Call 6. Bit D4 = 1, this resets RST 7.5
back later.

This analogy can be extended to the interrupt INTR, which is viewed as one telephone
line shared by eight engineers with a switchboard operator (external hardware) who rings
the appropriate extension.

The entire interrupt process (except TRAP) is disabled by resetting the Interrupt Enable
flip-flop (Figure 5.3). The flip-flop can be reset in one of the three ways: by instruction
DI, system Reset, or by recognition of an interrupt request. Figure 5.3 shows that these
three signals are ORed and the output of the OR gate is used to reset the flip-flop.

TRIGGERING LEVELS
These interrupts are sensitive to different types of triggering as listed below:

1. RST 7.5. This is positive edge sensitive and can be triggered with a short pulse.
The request is stored internally by the D flip-flop (Figure 5.3) until the
microprocessor responds to the request or until it is cleared by Reset or by
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bit D4 in SIM instruction.

2. RST 6.5 and RST 5.5. These interrupts are level sensitive, meaning that the
triggering level should be on until the microprocessor completes the
execution of the current instruction. If the microprocessor is unable to
respond to these requests immediately, they should be stored or held by
external hardware.

Example. Enable all the interrupts in an 8085 system.

Instructions.

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EI ;Enable Interrupts
MVI A, 08H ;Load bit pattern to enable RST 7.5, 6.5 and 5.5
SIM ;Enable RST 7.5, 6.5 and 5.5

Bit D3 =1 in the accumulator makes the instruction SIM functional, and bits D2, D1 and
D0 = 0 enable the interrupts 7.5, 6.5 and 5.5

Example. Reset the 7.5 interrupt from previous Example

Instructions

MVI A, 18H ;Set D4 = 1

SIM ;Reset 7.5 interrupt flip-flop

PENDING INTERRUPTS

Because there are several interrupt lines, when one interrupt request is being served, other
interrupt requests may occur and remain pending. The 8085 has an additional instruction
called RIM (Read Interrupt Mask) to sense these pending interrupts.

Fig 5.5. Interpretation of the Accumulator Bit Pattern for the RIM Instruction

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Instruction UNIVERSITY
RIM: Read Interrupt Mask

1. This is a1-byte instruction

2. This instruction loads the accumulator with eight bits indicating the current status
of the interrupts masks, the interrupt enable, pending interrupts, and serial input data.
See Figure 5.5.

Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if
RST 6.5 is pending. If it is pending, enable RST 6.5 without affecting any other
interrupts; otherwise, return to the main program.

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Instructions

RIM ;Read interrupt mask.

MOV B,A ;Save mask information
ANI 20H ;Check whether RST 6.5 is pending
JNZ NEXT
EI
RET ;RST 6.5 is not pending, return to main program.
NEXT: MOV A, B ;Get bit patter, RST 6.5 is pending.
ANI 0DH ;Enables RST 6.5 by setting D1 = 0.
ORI 08H ;Enable SIM by setting D3 = 1
SIM
JMP SERV ;Jump to service routine for RST 6.5

The instruction RIM checks for a pending interrupt. Instruction ANI 20H masks all the
bits except D5 to check pending RST 6.5. If D5 = 0, the program control is transferred to
the main program. D5 = 1 indicates that RST 6.5 is pending. Instruction ANI 0DH sets
D1 = 0 (RST 6.5 for SIM), instruction ORI sets D3 = 1 (this is necessary for SIM to be
effective), and instruction SIM enables RST 6.5 without affecting any other interrupts.
The JMP instruction transfers the program to the service routine (SERV) written for RST
6.5.

5.2.3 Concepts in Serial I/O

The basic concepts concerning the serial I/O mode can be classified into the categories as
shown; they will be discussed in the following sections.

1. I/O requirements
2. Alphanumeric codes
3. Transmission format
4. Serial transmission standards
5. Software vs. programmable hardware approaches

I/O Requirements

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The 8085/8080A MPU identifies a serial I/O peripheral in the same manner that it
identifies any other peripheral – through a decoder port address and the control signals
IOR and IOW. The control signal IOR is used to receive data, IOW is used to transmit
data, as shown in Figure 5.6.

Similarly, the memory-mapped I/O technique can be employed using the memory-related
control signal MEMR and MEMW. The primary differences between parallel I/O and

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Fig 5.6 Block Diagram: Serial I/O and Control Signals

serial I/O are the number of data lines and the number of bits transferred by the I/O
instructions. The 8085/8080A MPU can transfer bits serially under various conditions
depending upon the type of peripheral and its interfacing logic. Serial I/O data transfer
can be unconditional, with the status check, or with the interrupt.

Alphanumeric Codes

A computer is a binary machine; in order to communicate with the computer in

alphabetic letters and decimal numbers, translation codes are necessary. The commonly
used code known as ASCII, the American Standard Code for Information Interchange. It
is a 7-bit code with 128(27) combinations, and each combination from 00H to 7FH is
assigned to a letter, a decimal number, a symbol, or a machine command. For example,
hexadecimals 30H to 39H represent numerals 0 to 9; 41H to 5AH represent capital letter
A through Z; 21H to 2FH represent various symbols; and the initial codes 00H to 1FH
represent machine commands such as Carriage Return (CR) or Line Feed (LF). Devices
that use ASCII characters include ASCII terminals, teletype machine (TTY), and printers.
When the key 9 is pressed on an ASCII terminal, the computer receives 39H in binary,
and the system programs translate ASCII characters into appropriate binary or BCD
numbers.
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Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is
widely used in IBM computer. This is an 8-bit code representing 256 combinations;
however, several combinations are not being used.

Transmission Format

A transmission format is concerned with issues such as synchronization, direction of data

flow, speed, errors, and medium of transmission (telephone lines for example).

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5.2.4 Synchronous Vs. Asynchronous Transmission

Serial communication occurs either in synchronous or asynchronous format. In the

asynchronous format, a receiver and a transmitter are synchronized; a block of characters
is transmitted along with the synchronization information, as in Figure 16.2(a). This
format is generally used for high-speed transmission (more than 20k bits/second).

Fig 5.7 Transmission Format: Synchronous (a) and Asynchronous (b)

The asynchronous format is character-oriented. Each character carries the information of

the START and the STOP bits, shown in Figure 5.7(b). When no data are being
transmitted, a receiver stays high at logic 1, called MARK; logic 0 is called SPACE.
Transmission begins with one START bit (low), followed by a character and one or two
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STOP bits (high). This is also known as framing. Figure 5.7(b) shows the transmission
of eleven bits for an ASCII character in the asynchronous format: one START bit, eight
character bits, and two STOP bits. The format shown in Figure 5.7(b) is similar to Morse
code, but the dots and dashes are replaced by logic 0s and 1s. The asynchronous format
is generally used in low speed transmission (less than 20 k bits/second.)

SIMPLEX AND DUPLEX TRANSMISSION

Serial communication also can be classified according the direction and simultaneity of
data flow.

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In simplex transmission, data are transmitted in only one direction. A typical example is
the transmission from a microcomputer to a printer.

In duplex transmission, data flow in both directions. However, if the transmission goes
one way at a time, it is called half duplex; if it goes both ways simultaneously, it is called
full duplex. Generally, transmission between two computers or between a computer and
a terminal is full duplex.

PARITY CHECK

During transmission, data bits may change (e.g., because of noise) and a receiver may
receive a wrong character. The MSB bit in the ASCII code can be used to check an error;
this process is called parity check.

To check the parity, the transmitter simply counts whether the number of 1s in a character
is odd or even, and transmits that information to the receiver as the MSB bit. The
receiver checks the MSB bit and the number of 1s in the received character. If there is an
error, the receiver sends back an error message to the transmitter.

The parity check can be either odd or even, depending upon the system. In an odd parity
system, when a character has an even number of 1s, bit D7 is set to 1 and an odd number
of 1s is transmitted. For example, the code for the character G is 47H (01000111) with
four 1s. When the character G is transmitted in an odd parity system, the transmitter will
set bit D7 to 1, making the code C7H (11000111). On the other hand, the character I
(49H = 01001001) has three 1s; when the character I is transmitted, bit D7 is set to 0,
keeping the code 49H. The parity check cannot detect multiple errors in any given
character.

The 8085/8080A microprocessor sets a parity flag when the number of 1s in the
accumulator is even. This flag can be used for the parity check in an 8085/8080A
system.

BAUD

The rate at which the bits are transmitted – bits/second – is called a baud in serial I/O;
however, technically, it is defined as the number of signal changes/second. Each piece of
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equipment has its own baud requirement. For example, a teletype (TTY) generally runs
on a 110 baud. However, in most terminals and printers, the baud is adjustable, typically,
in the range of 50 to 9600 baud.

MODEM

A modem (Modulator / Demodulator) is a circuit that translates digital data into audio
tone frequencies for transmission over telephone lines an converts audio frequencies into
digital data for reception. The modulation technique generally used is called frequency

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shift keying (FSK); it converts logic 1 (MARK) and logic 0 (SPACE) into audio tones
around 1200 and 2000 Hz frequencies.

Fig 5.8 Communication between Two Computers Using Modems

Computers can exchange information over telephone lines by using two modem – one on
each side (Figure 5.8). A calling computer (or a terminal) contacts a receiving computer
through a telephone number, and a communication link is established after control signals
have been exchanged between computers and modems.

A typical process of communication is shown in Figure 5.8. A parallel word is converted

into serial bits; in turn, they generate two audio frequencies according to logic 0 or 1, and
these audio frequencies are transmitted over telephone lines. At the receiving end, audio
frequencies are converted back into 0s and 1s, and serial bits are converted into a parallel
word that can be read by the receiver computer.

5.2.5 Programmable Interface Devices

A programmable interface device is designed to perform various input/output functions.

Such a device can be set up to perform specific functions by writing an instruction (or
instructions) in its internal register, called the control register. Furthermore, functions
can be changed anytime during execution of the program by writing a new instruction in
the control register. These devices are flexible, and multifunctional. They are widely
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used in microprocessor-based products.

The I/O functions of a programmable device are determined through software

instructions. The MPU writes an appropriate instruction (or instructions) in the device to
define its I/O functions.
The functions performed by the interfacing I/O devices, are as follows:

1. A latch is used as an output port to hold and display data.

2. A tri-state buffer is used as an input port to read data from devices such as a keyboard
or data converters.

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3. A tri-state buffer is used as a 1-bit input port to check the status and determine whether
the device is ready to input data.
4. An interrupt signal can be generated by an interfacing device.

Therefore, a programmable device should include at least these functions in its hardware.
In addition, it should have control logic, chip select logic, and a register (or registers) in
which to write an instruction for defining its hardware functions.

The programmable I/O device is likely to have the following elements:

1. A control register in which the MPU can write an instruction.

2. A status register that can be read by the MPU.
3. I/O devices or registers.
4. Control logic.
5. Chip Select logic.
6. Bidirectional data bus.
7. Handshake signals and Interrupt logic.

A programmable I/O device is programmed by writing a specific word, called the control
word, according to the internal logic; its status can be verified by reading the status
register. This I/O device can be expanded to include elements such as multiple I/O ports,
counter, and parallel to serial register.

The 8155 and the 8355 are two multipurpose programmable devices specifically designed
to be compatible with the 8085 microprocessor. The ALE, IO/M, RD, and WR signals
from the 8085 can be connected directly to these devices; this eliminates the need for
external demultiplexing of the low-order bus AD7 - AD0 and generation of the control
signals such as MEMR, MEMW, IOR and IOW.

The 8155 includes 256 bytes of R/W memory, three I/O ports, and a timer. The 8156 is
identical with 8155, except that the 8156 requires Chip Enable (CE) active high. The
8355 includes 2K of ROM and two I/O ports. The 8755 is similar to the 8355, except
that the 8755 is EPROM. The programmable I/O sections of these devices are illustrated
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in the following sections.

5.2.6 The 8155/8156 Programmable I/O Ports and Timer

The 8155/8156 is a device with two sections: the first is 256 bytes of R/W memory, and
the second is a programmable I/O. Functionally, these two sections can be viewed as two
independent chips. The I/O section includes two 8-bit parallel I/O ports (A and B), one
6-bit port (C), and a timer (Figure 5.9). All the ports can be configured simply as
input/output ports -- similar to the 8212. Ports A and B also can be programmed in the
handshake mode, each port using three signals as handshake signals from port C. The

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timer is a 14-bit down-counter and has four modes. Pins PA, PB, and PC, shown in
Figure 5.9, correspond to ports A, B, and C.

Fig 5.9 8155 Pin Configuration and Block Diagram

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The control logic of the 8155 is specifically designed to eliminate the need for externally
demultiplexing lines AD7 -- AD0 and generating separate control signals for memory and
I/O. Figure 14.5 shows five control signals; all except the Chip Enable (CE) are input
signals directly generated by the 8085.

1. CE -- Chip Enable: This is a master Chip Select signal connected to the decoded high-
order bus.

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2. IO/M -- When this signal is low, the memory section is selected, and when it is high
the I/O section (including timer) is selected.
3. ALE -- Address Latch Enable: This signal latches the low-order address AD7 -- AD0,
CE, and IO/M into the chip.
4. RD and WR -- These are control signals to read from and write into the chip registers
and memory.
5. RESET -- This is connected to RESET OUT of the 8085 and this resets the chip and
initializes I/O ports as input.

THE 8155 I/O PORTS

The I/O section of the 8155 includes a control register, three I/O ports, and two registers
for the timer (Figure 5.10). The 8155 I/O section requires three address lines -- AD2 to
AD0 and the Chip Enable logic to specify one of the seven registers. In addition, two
control signals, RD and WR, are necessary to read from and write into these I/O registers.

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Fig 5.10 Expanded Block Diagram of the 8155 (a) and Its I/O Address: Selection (b)

To communicate with peripherals through the 8155 the following steps are necessary:

1. Determine the addresses (port numbers of the registers and I/Os) based on the Chip
Enable logic and address lines AD0, AD1, and AD2.
2. Write a control word in the control register to specify I/O functions of the ports and the
timer characteristics.
3. Write I/O instructions to port addresses to communicate with peripherals.

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4. Read the status register, if necessary, to verify the status of the I/O ports and the timer.
In simple applications, this step is not necessary.

CHIP ENABLE LOGIC AND PORT ADDRESSES

Address lines AD2 to AD0, also shown as A2 to A0 after internal demultiplexing, select
one of the registers as shown in Figure 5.10(b). Address A3 to A7 are don't care lines;
however, the logic levels on the corresponding high-order lines, A11 to A15, will be
duplicated on lines A3 to A7, as explained in the next example.

Example 1. Determine the addresses of the control/status register, I/O ports, and timer
registers in Figure 5.11

Solution. To select the chip, the output line O4 of the 8205 (3-to-8) decoder (Figure
5.11) should go low. Therefore, the logic levels of A15 to A11 should be as follows:

A15 A14 A13 A12 A11

0 0 1 0 0

Enable Input logic to activate

lines of the output line 4 of the
the 8205 8205

By combining five high-order address lines with three low-order address lines (A2 - A0),
the port numbers in Figure 14.8 will range from 20H to 25H, as shown below.

A15 A14 A13 A12 A11 AD2 AD1 AD0 Addresses Ports
0 0 1 0 0 0 0 0 = 20H -- Control or
status register
0 0 1 = 21H -- Port A
0 1 0 = 22H -- Port B
(2H) 0 1 1 = 23H -- Port C
1 0 0 = 24H -- Timer (LSB)
A7 A6 A5 A4 A3 1 0 1 = 25H -- Timer (MSB)
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This raises a question: How is it possible to combine five high-order address lines with
three low-order address lines to generate a port address? To find an answer to this
question, examine the execution of either the IN or OUT instruction. When these
instructions are executed, the high-order and low-order address buses carry the same
information. In this case, the logic levels required on lines A15 to A11 for the Chip Enable
are also duplicated on the address lines from A7 through A3, as shown above.

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Fig 5.11 Interfacing 8155 I/O Ports

CONTROL WORD

Writing a control word in the control register can configure the I/O ports and the timer.
The control register bits are defined as shown in Figure 5.12.

In this control word, outputs are defined with logic 1 and inputs with logic 0. The first
two LSBs, D0 and D1, determine I/O functions of ports A and B; and the MSBs, D7 and
D6, determine timer functions. Bits D4 and D5 are used only in the interrupt mode to
enable or disable internal flip-flops of the 8155. These bits do not have any effect on the
Interrupt Enable flip-flop (INTE) of the MPU.

The next section shows an application of the 8155 to design two output ports for the
SDK-85 system. An application of the 8155 in the handshake mode is illustrated later.

Illustration: Interfacing Seven-Segment LED Output Ports Using the 8155

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PROBLEM STATEMENT

1. Design two seven-segment LED displays using ports A and B of the 8155.
2. Write initialization instructions and display data bytes at each port.

HARDWARE DESCRIPTION

Figure 5.13 shows two seven-segment output ports: port A with the Hewlett Packard HP
5082/7340, and port B with the Fairchild FND 507, and 9370. The HP 5082 includes an
internal decoder/driver, while the FND 507 is driven by a separate decoder/driver 9370.

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Fig 5.12 Control Word Definition in the 8155 (a) and Table of Port C Bit
Assignments (b)

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Fig 5.13 Interfacing 8155 I/O Ports with Seven-Segment LEDs

Both are functionally similar; however, a seven-segment display with an internal built-in
decoder/driver is more expensive.

The decode logic is the same as that used in the previous discussion; therefore, the port
addresses are as follows:

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Control Register
Port A = 21H
= 20H

Port B = 22H

CONTROL WORD

To configure ports A and B as outputs, the control word is as follows:

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D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 1 1 = 03H

Port A Output
Port B Output
No effect Not Port C is
on timer Appli- not being
cable used for
handshake

PROGRAM

MVI A, 03H ; Initialize ports A and B as output ports.

OUT 20H
MVI A, BYTE1
OUT 21H ; Display BYTE1 at port A.
MVI A, BYTE2
OUT 22H ; Display BYTE2 at port B.
HLT

PROGRAM DESCRIPTION

The instruction MVI A, 03H initializes ports A and B as simple output ports, and the
following instructions display data BYTE1 and data BYTE2 at ports A and B,
respectively.

The 8155 Timer

The timer section of the 8155 has two 8-bit registers; fourteen bits are used for counter,
two bits for the timer mode, and it requires a clock as an input. This 14-bit down-counter
provides output in four different modes, as described below.

Figure 5.14 (a) shows two registers for a 14-bit count, one for LSB (low significant byte)
and one for MSB (most significant byte). The most significant bits M2 and M1 are used
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to specify the timer mode.

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Fig 5.14 Timer Loading Format (a) and Modes (b)

To operate the timer, a 14-bit count and mode bits are loaded in the registers. An
appropriate control word starts the counter, which decrements the count at each clock
pulse. The timer outputs vary according to the mode specified (Figure 5.14(b)).

The timer can be stopped either in the midst of counting, or at the end of a count
(applicable to Modes 1 and 3). In addition, the actual count at a given moment can be

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obtained by reading the status register. These details will be described later.

Illustration: Designing a Square Wave Generator Using the 8155 Timer

PROBLEM STATEMENT

Design a square wave generator with a pulse width of 100 s by using the 8155 timer.
Set up the timer in Mode 1 if the clock frequency is 3 MHz. Use the same decode logic
and the port addresses as in Example1 (Figure 5.11).

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PROBLEM ANALYSIS

Timer Count. The pulse width required is 100 s; therefore, the count should be
calculated for the period of 200 s. The timer output stays high for only half the count.

Clock Period = 1/f = 1/3 x 106 = 330 ns

Timer Count = Pulse Period / Clock Period = 200 x 10-6 / 330 x 10-9 = 606

Count = 025EH

Assuming the same decode logic for the 8185 Chip Enable line as in Example 1, the port
addresses for the timer registers are

Timer LSB = 24H

Timer MSB = 25H

The least significant byte, 5EH (of the count 025EH), should be loaded in the timer
register with address 24H.

The most significant byte is determined as follows:

M2 M1 T13 T12 T11 T10 T9 T8

0 1 0 0 0 0 1 0 = 42H

Timer Mode 1 MSB

Therefore, 42H should be loaded in the timer register with the address 25H.

Control Word. Assuming the same configuration for ports A and B as before, only
bits D7 and D6 should be set to 1 to start the counter (see control word definition in
Figure 14.8).

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Therefore, Control Word: 1100 0011 = C3H

Initialization Instructions

MVI A, 5EH ; LSB of the count

OUT 24H ; Load the LSB timer register
MVI A, 42H ; MSB of the count
OUT 25H ; Load the MSB timer register
MVI A, C3H
OUT 20H ; Start the timer
HLT

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The 8185 I/O Ports in Handshake Mode

In the handshake mode, data transfer occurs between the MPU and peripherals using
control signals called handshake signals. Two I/O ports of the 8155, A and B, can be
configured in the handshake mode; each uses three signals from port C as control signals
(Figure 5.15). Another alternative (ALT 3 in the Table in Figure 5.12) available in the
8155 is to configure port A in the handshake mode with three control signals from port C;
configure port B as simple I/O; and configure the remaining three bits of port C as
outputs. The details of configuring ports A and B in the handshake mode by using the
pins of port C are given below.

Fig 5.15 8155 with Handshake Mode

CONTROL SIGNALS IN HANDSHAKE MODE

When both ports A and B are configured in the handshake mode, port A uses the lower
three signals of port C (PC0, PC1, and PC2), and port B uses the upper three signals (PC3,
PC4, and PC5) as shown in Figure 5.15. The functions of these signals are as follows:

1. STB (Strobe Input): This is an input handshake signal from a peripheral to the 8155.
The low on this signal informs the 8155 that data are strobed into the input port.
2. BF (Buffer Full): This is an active high signal, indicating the presence of a data byte
in the port.
3. INTR (Interrupt Request): This signal is generated by the rising edge of the STB
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signal if the interrupt flip-flop (INTE) is enabled. This signal can be used to interrupt the
MPU.
4. INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable the
interrupt capability of the 8155. Bits D4 and D5 control the interrupts for port A and port
B, respectively, in the control register.

These control signals can be used to implement either interrupt I/O or status check I/O.

INPUT
Figure 5.16(a) shows the sequence of events and timing in data input to the 8155; they
can be described as follows:

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1. An external peripheral places data in the input port and informs the 8155 by causing
the STB signal to go low.

Fig 5.16 Timing Waveforms of the 8155 I/O Ports with Handshake: Input Mode (a) and
Output Mode (b)

2. The falling edge of the STB sets signal BF (Buffer Full) high, informing the peripheral
to wait.
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3. When the STB goes high, the rising edge of the STB can generate signal INTR if the
internal interrupt flip-flop INTE is set. The interrupt flip-flops are set or reset by the
control word.
4. The last step is to transfer data from the 8155 input port to the MPU. This can be done
either by interrupting the MPU with the INTR signal or by checking the status of signal
BF. The MPU can check the status by reading the status register (described later). When
the MPU reads data, the INTR and BF signals are reset. When the BF signal goes low, it
informs the peripheral that the port is empty, and the device is ready for the next byte.

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OUTPUT

The sequence of events and timing in data output from the 8155 port to a peripheral are
as follows (see Figure 5.16(b));

1. When the output port is empty, the MPU writes a byte in the port.
2. The falling edge of WR signal resets the INTR signal and the rising edge sets the BF
(Buffer Full) signal high, which is used to inform the peripheral that a byte is available in
the port.
3. After receiving the data byte, the peripheral acknowledges by sending the STB signal
(active low).
4. The STB signal resets the BF signal low and generates the interrupt request by setting
INTR high. Now the MPU can be informed by the interrupt signal to send the next byte,
or the MPU can sense that the port is empty through status check.

STATUS WORD

The MPU can read the status register to check the status of the ports or the timer. The
control register and the status register have the same port address; they are differentiated
only be the RD and WR signals. The status register bits are defined in Figure 5.17.

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Fig 5.17 Status Word Definition

Illustration: Interfacing I/O Ports in Handshake Mode Using the 8185

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PROBLEM STATEMENT

Design an interfacing circuit using the 8155 to read and display data from an A/D
converter to meet the following requirements:

1. Set up port A in the handshake mode to read data from an A/D converter.
2. Set up port B as an output port to display data at seven-segment LEDs.
3. Use line PC3 from port C to initiate a conversion.
4. Use the same decode logic as in Example 14.2 (Figure 14.7) to assign I/O port
addresses.
5. Use the 8155 timer to record the conversion time.

PROBLEM ANALYSIS

Figure 5.18 shows an interfacing circuit that uses the 8155 I/O ports as follows:

1. Port A is configured as an input port in the handshake mode for reading data from the
A/D converter.
2. Port B is configured as a simple output port for seven-segment LEDs.
3. The upper half of port C is a simple output port, and bit PC 3 is being used to start
conversion.
4. The lower half of port C provides handshake signals for port A. Bit PC2 is being used
as a strobe (STB) to inform the 8155 that the conversion is complete and that the output of
the converter has been placed in port A.

INPUT WITH STATUS CHECK

The circuit shows that the INTR signal (bit PC0) is not being used. This suggests that
port A is configured for status check and not for interrupt I/O. Therefore, the control
word (see Figure 5.12) required to set up the ports as specified above and the masking
byte to check the Data Ready (DR) line are as follows:

Control Word

D7
0
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D6
0
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D5
0
D4
0
D3
0
D2
1
D1
1
D0
0 = 06H

Do not affect Interrupts are Port A =

counter are not being used Input
operation Port B =
Output
Port CH = Output
ALT3 Port CL = Handshake signals

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Fig 5.18 Interfacing the A/D Converter AD570 in the Handshake Mode

Status Word. The MPU needs to check bit D1 of the status register to verify the end of
conversion and the availability of data in port A. The status word will have the following
information (see Figure 14.13):

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D7
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D6 D5 D4 D3 D2 D1 D0

X X X X X X BFA X

Timer INTEB BFB INTRB INTEA INTRA

When the status word is masked with byte 02H, the availability of a data byte in port A
can be verified.

8155 TIMER

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The timer can be used to calculate the conversion time. When a conversion begins, the
timer should be started with a known count, and at the end of conversion the timer should
be stopped. The difference between the two counts multiplied by the clock period of the
timer should provide a fairly accurate reading of the conversion time.

To start the timer, set bits D7 and D6 of the control register to 1 without affecting the
other bits of the register. Therefore, to start the timer, the control word should be:

= 1 1 0 0 0 1 1 0 = C6H

Start Timer I/O Assignments

To stop the timer, the control word should be:

0 1 0 0 0 1 1 0 = 46H

Stop Timer I/O Assignments

PORT ADDRESSES

The decode logic is the same as in Example 1; therefore, the I/O port addresses range
from 20H (control register) to 25H (Timer -- MSB).

PROGRAM

MVI A, 06H Control word for I/O ports

OUT 20H Set up ports as specified
MVI A, 00H Load 0000H in the timer registers
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OUT 24H
OUT 25H
MVI A, 08H Byte to set PC3 = 1
OUT 23H Send START pulse
MVI A, C6H Control word to start timer
OUT 20H Start timer
MVI A, 00H Byte to set PC3 = 0
OUT 23H Start conversion
STATUS: IN 20H Read status register
ANI 02H Check status of DR
JZ STATUS If BFA = 0, wait in the loop until a data byte is available

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MVI A, 46H Byte to stop counter

OUT 20H Stop counter
IN 21H Read A/D converter output
OUT 22H Display data at port B
IN 24H Read LSB of timer count
MOV L, A Save timer count in register L
IN 25H Read MSB of timer count
ANI 3FH Delete D7 and D6 from the MSB; they represent timer mode
MOV H, A Save MSB timer count in H
LHLD RWM Store timer count from HL register in R/W memory
locations
HLT

PROGRAM DESCRIPTION

The comments are self explanatory; however, some explanation is needed for the timer
count, start conversion (convert) pulse, and status check.

The program loads 0000H in the timer register, and after the first decrement, the count
becomes 3FFFH. This is a 14-bit counter, with bits D15 and D14 reserved to specify the
mode. However, in this particular problem, the counter mode is irrelevant. This program
assumes that the A/D conversion time is less than time period given by the maximum
count. The difference between the initial count and the final count will provide the
necessary value to calculate the conversion time. The program does not perform this
subtraction; it just stores the final count in two consecutive memory locations labeled as
RWM.

The second item needing explanation is the start conversion (convert) pulse. This is an
active high pulse provided by turning on and off bit PC3 in port C.

Finally, instruction IN 20H reads the status register, and instructions ANI 02 and JZ
check whether the buffer in port A (BFA) is full. The program stays in the loop until the
BFA goes high, indicating the availability of data.

INTERRUPT I/O
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This example illustrates all the important I/O operations of the 8155 except the interrupt
I/O in the handshake mode. To implement the interrupt I/O in the above example, the
INTRA -- the output bit PC0 -- should be connected to a vectored interrupt such as RST
6.5 and the control word should be changed accordingly.

5.2.7 Interfacing the 8355/8755 Programmable I/O Ports

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The 8355/8755 is a 2K-byte (2048 x 8) memory with two I/O ports; each I/O line of the
ports can be programmed either as input or output. The 8355 is ROM and the 8755 is
EPROM

Figure 5.19 shows: (a) the block diagram of the 8755, and (b) the internal control
registers called Data Direction Registers (DDR). Each bit in the DDR registers controls
the corresponding bit in the I/O ports. The port addresses of the DDR registers and I/O
ports are determined by the Chip Enable (CE) logic and address lines AD0 and AD1. The
table, Figure 14.15(c) shows the logic levels required for address lines AD0 and AD1 to
select a port. These logic levels are combined with CE logic to determine the port
addresses, as explained below.

Figure 5.20 is a schematic from the SDK-85 system. The interfacing logic shows the 3-
to-8 decoder; its output line 0 is connected to the CE signal of the 8755.

To select the 8755, the logic on the address lines should be as follows:

A15/ A14/ A13/ A12/ A11/ AD2 AD1 AD0 Selected

AD7 AD6 AD5 AD4 AD3 Register

0 0 0 0 0 X 0 0 = 00 A
0 1 = 01 B
1 0 = 02 DDR A
1 1 = 03 DDR B

The logic levels on the high-order address lines (A15 -- A11) are duplicated on the low-
order address lines (AD7 -- AD3).

Each bit of port A and port B can be programmed by writing control words in their
respective DDR registers; logic 0 in a DDR register specifies input mode for the
corresponding bit in the I/O port. For example, byte F0H in the DDRA specifies that lines
PA0 to PA3 are inputs and lines PA4 to PA7 are outputs.

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Fig 5.19 8755 Block Diagram (a), Data Direction Register (b), and I/O Selection
Table (c)

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Fig 5.20 Interfacing the 8755 I/O Ports

Example 2. Write initialization instructions to configure port A and port B as output

ports, and display 32H at port A.

Instructions

MVI A, FFH ; Control word to set up all bits as output bits

OUT 02H ; Initialize port A as output
OUT 03H ; Initialize port B as output
MVI A, 32H
OUT 00H ; Display 32H at port A
HLT

5.2.8 The 8279 Programmable Keyboard/Display Interface

The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed

display. There is a software approach to interfacing a matrix keyboard and a multiplexed
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display of seven-segment LEDs. The disadvantage of the software approach is that the
microprocessor is occupied for a considerable amount of time in checking the keyboard
and refreshing the display. The 8279 relieves the processor from these two tasks. The
disadvantage of using the 8279 is the cost. The trade-offs between the hardware approach
and the software approach are the production cost vs. the processor time and the software
development cost.

The 8279 (Figure 5.21) is a 40-pin device with two major segments: keyboard and
display. The keyboard segment can be connected to a 64-contact key matrix. Keyboard
entries are debounced and stored in the internal FIFO (First-In-First-Out) memory, while
an interrupt signal is generated with each entry. The display segment can provide a

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sixteen-character scanned display interface with such devices as LEDs. This segment has
16 x 8 R/W memory (RAM), which can be used to read/write information for display
purposes. The display can be set up either in right-entry or left-entry format.

Fig 5.21 The 8279 Logic Pinout

Block Diagram of the 8279

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The block diagram (Figure 5.22) shows four major sections of the 8279: keyboard, scan,
display, and MPU interface. The functions of these sections are described below.

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Fig 5.22 The 8279 Logic Block Diagram

KEYBOARD SECTION

This section has eight lines (RL0 -- RL7) that can be connected to eight columns of a
keyboard, plus two additional lines: Shift and CNTL/STB (Control/Strobe). The status of
the SHIFT key and the Control key can be stored along with a key closure. The keys are
automatically debounced, and the keyboard can operate in two modes: two-key lockout
or N-key rollover. In the two-key lockout mode, if two keys are pressed almost
simultaneously, only the first key is recognized. In the N-key rollover mode,
simultaneous keys re recognized and their codes are stored in the internal buffer; it can
also be set up so that no key is recognized until only one key remains pressed.

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The keyboard section also includes 8 x 8 FIFO (First-In-First-Out) RAM. The FIFO
RAM consists of eight registers that can store eight keyboard entries; each is then read in
the order of entries. The status logic keeps track of the number of entries and provides an
IRQ (Interrupt Request) signal when the FIFO is not empty.

SCAN SECTION

The scan section has a scan counter and four scan lines (SL0 -- SL3). These four scan
lines can be decoded using a 4-to-16 decoder to generate sixteen lines for scanning.

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These lines can be connected to the rows of a matrix keyboard and the digit drivers of a
multiplexed display.

DISPLAY SECTION

The display section has eight output lines divided into two groups, A0 - A3 and B0 - B3.
These lines can be used, either as a group of eight lines or as two groups of four, in
conjunction with the scan lines for a multiplexed display. The display can be blanked by
using the BD line. This section includes 16 x 8 display RAM. The MPU can read from
or write into any of these registers.

MPU INTERFACE SECTION

This section includes eight bidirectional data lines (DB0 - DB7), one Interrupt Request
line (IRQ), and six lines for interfacing, including the buffer address line (A0).

When A0 is high, signals are interpreted as control words or status; when A0 is low,
signals are interpreted as data. The IRQ line goes high whenever data entries are stored
in the FIFO. This signal is used to interrupt the MPU to indicate the availability of data.

PROGRAMMING THE 8279

The 8279 is a complex device that can accept eight different commands to perform
various functions. The discussion here is specific to the circuit in the SDK-85 system.

The initialization commands can specify

1. left or right entry and key rollover.

2. clock frequency prescaler.

3. starting address and incrementing mode of the FIFO RAM.

4. RAM address to read and write data and incrementing mode.

5. blanking format.
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In order to illustrate important command words, the next section will illustrate the
keyboard/display circuit from the SDK-85 system.

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ILLUSTRATION: SDK-85 KEYBOARD SCHEMATIC

Fig 5.23 SDK – 85 Keyboard / Display Circuit

CIRCUIT DESCRIPTION
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Figure 5.23 shows the following components:

1. The 8279 Programmable Keyboard/Display Interface.

2. A matrix keyboard with 22 keys.
3. Six seven-segment LEDs: DS1 - DS6. (Only one is shown; other five are identical).
4. The 74LS156 decoder with open collector outputs.
5. Transistors as current drivers.
6. The 8205 decoder for the decoding logic.

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Lines RL0 - RL7 (Return Lines) of the 8279 are connected to the columns of the matrix
keyboard, and the output lines (A0 - A3 and B0 - B3) are connected to drive the LED
segments through the transistors. The three scan lines are connected to the decoder, the
74LS156, to generate eight decoded signals. In this circuit, six output lines of the
decoder are connected as digit drivers to turn on six seven-segment LEDs; two output
lines are unused. In addition, the first three output lines are also used to scan the rows of
the keyboard. The 8279 has four scan lines that can be decoded to generate sixteen
output lines to drive sixteen displays. The data lines of the 8279 are connected to the data
bus of the 8085, and IRQ (Interrupt Request) is connected to the RST 5.5 of the system.

Four signals -- RD, WR, CLK, and RESET OUT -- are connected directly from the 8085.
The system has a 3.072 MHz clock; and when the 8279 is reset, the clock prescaler is set
to 31. This divides the clock frequency by 31 to provide the scan frequency of
approximately 100 kHz. The RESET signal also sets the 8279 in the mode of sixteen
character display with two-key lockout keyboard.

After the initialization of the 8279, the respective codes are sent to the display RAM to
display any characters. The 8279 takes over the task of displaying the characters by
outputting the codes and digit strobes. To read the keyboard, the 8279 scans the
columns; if a key closure is detected, it debounces the key. If a key closure is valid, it
loads the key code into the FIFO, and the IRQ line goes high to interrupt the system.

DECODING LOGIC AND PORT ADDRESSES

The port addresses of the 8279 registers are determined by two signals: CS and A0. The
CS signal of the 8279 is connected to the CS-3 output of the 8205 decoder, and A0 is
directly connected to the address line A8 of the 8085. For commands and status, and A0
should be high. For data transfer, A0 should be low. By examining the decoder input
lines and assuming logic 0 for the don't care address lines, one can determine that the port
addresses are as follows:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 0 I/O 0 0 0 0 0 0 0 0 = 1900H/1800H

Enable
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Decoder
Input
Don't
Care
A0
of
Don't Care

8279

Command/Status Port: 1900H

Data Port : 1800H

INITIALIZATION INSTRUCTIONS

In the SDK-85 system, the 8279 is initialized for the keyboard/display mode: Two-key
Lockout; Left Entry; and 8-bit, 8-Character Display. The RESET signal sets the clock

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prescaler to 31; thus, the scan frequency is approximately 100 kHz. When the 8279
detects a key closure, the IRQ signal interrupts the 8085, using RST 5.5. The interrupt
service routine sends the command word to read from the keyboard (Command Port
1900H), reads the character data from the keyboard (Data Port 1800H), and stores it in
the input buffer of the system's R/W memory. The following instructions illustrate the
initialization and the interrupt-service routine.

Initialization
Keyboard/Display Mode
MVI A, 00H Control word to set mode: Left 0 0 0 D D K K K
entry, 8-character, 2-key lockout
encoded scan keyboard
STA 1900H Initialize 8279

Interrupt Routine to Read Keyboard

PUSH H
PUSH PSW Read FIFO RAM: Control Word
LXI H, 1900H Keyboard control 0 1 0 A1 X A A A
register address
MVI M, 40H Control word to read
from keyboard
DCR H Data Port Address
1800H

MOV A, M Read data Data Format

D7 D6 D5 D4 D3 D2 D1 D0

ANI 3FH Mask D7 and D6. CNTL SHFT ROW COL

CNTL, Shift keys are
not being used
STA IBUFF Store in R/W memory
POP PSW
POP H
RET

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To display characters, the routine determines whether it is displaying a 4-digit memory
address or a 2-digit data value. Then it sends the control word to read the display RAM.
For example, to display a 4-digit memory address, the control word instructions are as
follows:

MVI A, 90H Control word to write

starting at first RAM Write Display RAM Control Word
location
STA 1900H 1 0 0 A1 A A A A
MVI A, CODE Load seven-segment code

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STA 1800H Output the code

To display a 2-digit data value, the control instructions are as follows:

MVI A, 94H : Control word to display data

STA 1900H

In this example, the control word 94H points to the fifth memory location in the
display RAM; the first four locations are reserved for memory addresses.

5.2.9 Applications Of Microprocessors

INTRODUCTION

Since the advent of the P in 1971, its application domain has been expanding rapidly.
This trend will definitely continue especially in the wake of the fact that new Ps and
Cs with superior performance are now available to the system designer, e.g. Intel’s
80386,80196, Motorola’s MC68030, M68CH11A8, NEC’s 7800 series of
microcontrollers.

The purpose of this chapter is to familiarize the reader with a variety of application areas
of Ps. Obviously, it is not possible to present each application in detail. We have
therefore presented a brief description of several application areas and one application in
detail. The application presented in detail is that of a temperature monitoring system for
which the detailed software and hardware design is also presented.

5.2.10 A Temperature Monitoring System

One of the application areas of Ps is process control. In a typical process control
application, the P continuously monitors one or more process variables and generates
outputs to the electro-mechanical elements which in turn control the process variables.
This kind of control is known as closed loop control. If the P outputs the control
variables to human operators, via displays or line printers, who in turn apply the
necessary control inputs, then the control strategy is known as open loop control. In this
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section we shall present an example to illustrate the use of a P in open loop process
control. To illustrate, we shall use the 8085 as the control P. For simplicity, only one
process variable, namely the temperature at a point, will be monitored and displayed. We
shall present the detailed software and hardware design.

SYSTEM REQUIREMENTS

It is required to design a P-based open loop control system that monitors a process
temperature and displays it on a four-digit seven-segment display. The system should
have the facility to input, from a human operator, the lower and upper limits of the
temperature being monitored. If at any moment these limits are violated, one of the two

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suitable alarms must be set. The alarms in our case are two LED displays. One of these
indicates that the temperature has violated the upper limit (the H1 alarm). The other LED
indicates that the temperature has violated the lower limit (the LO alarm).

OVERALL SYSTEM DESIGN

The complete system can be partitioned into three distinct subsystems:

1. Processor and memory subsystem

2. Input subsystem

3. Output subsystem

We have decided to use the 8085 P as the control processor. We use the 2716A, 2K
byte EPROM, for the program and fixed data storage. For storing stacks and other
variable data, we use the 6116A, 2K byte static RAM. We use the 8255A Programmable
Peripheral Interface, described earlier in Chapter 7, to get the necessary ports for
interfacing various I/O devices. The counters in the 8254 Programmable Interval Timer
chip are used to provide the two timers needed in our application.

THE INPUT SUBSYSTEM

In order to satisfy the design requirements, the P should be able to input the following
variables:

1. temperature, and

2. low and high limits.

The temperature may be converted to an analog voltage by means of a suitable transducer

and this output applied to an ADC. The output of the ADC may be read by the P when

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desired. We assume that successive temperature readings are to be taken

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Figure 5.24: Operator panel for temperature monitoring system.

with a minimum of 50 ms inter-reading gap. A transducer that can be used if the

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temperature being measured is within the range of –55C to +150C, is the Analog
Devices’ AD590. It has a wide power supply range of +4 V to +30 V. It generates a
current output of 1 A/Kelvin. For example, at 25C, the output current is 298 A.

There are several ways in which the low and high limits may be set and read by the P.
We shall use a very simple scheme described below.

Assume that a switch is provided which may be closed by the operator to indicate to the
P whether limit setting is desired or not. Call this as the SET LIMIT switch. Another
switch, called the LO/HI switch, can be used to indicated whether lower or upper limit is

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to be set. Using sixteen LIMIT switches, divided into groups of four each, may set the
limit itself. Thus, the operator using the BCD code may set a four-digit limit.

When the operator desires to change a limit, the following sequence of actions should be
performed:

1. Set a 4-digit limit on the sixteen LIMIT switches. Note that these must be
BCD digits.
2. Set the LO/HI switch to LOW (close it) or HIGH (open it) depending on
which limit is to be set.
3. Close the SET LIMIT switch.

After the processor recognizes the set limit request, it will read the limit from the LIMIT
switches and acknowledge this fact by turning on an LED display named LIMIT SET. At
this point, the SET LIMIT switch may be opened. If it remains closed, the P scans it
again after, approximately, 15s and, if found closed, resets the appropriate limit. The
LED display is turned off approximately 5s after it was turned on.

Fig. 5.24 exhibits the operator panel with all these switches and the output displays. In
this figure, the output produced by the output subsystem is also shown. All switches
shown are of the simple toggle type.

THE OUTPUT SUBSYSTEM

The output subsystem should be able to display the value of the temperature on a 4-digit
7-segment display. When required, the alarms LO or HI must be appropriately set. We
assume that the temperature display is updated when sixteen reading have been
accumulated. The average of these readings is displayed.

As the output is displayed using four digits, the P may display the successive digits one
by one at a rate that would not impair the readability of the display. It would be
sufficient to display the next digit 50 ms after the previous one. Thus, in a total of about
200 ms, all the digits would be displayed once in the cycle. This rate is high enough to
keep the flicker in the display once in the cycle. This rate is high enough to keep the
flicker in the display within tolerance. The advance of using the display in a multiplexed

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mode is that only one digit driver would be required at a slight increase in software
complexity.

After obtaining the average temperature reading, the P should check whether the
temperature is within limits or not. If not, then appropriate alarm lamp should be turned
on, otherwise, any ON lamp must be turned off.

Fig. 5.25 shows a block diagram of the system we plan to design. Fig. 5.26 and Fig. 5.27
show the flow charts embodying the overall algorithm that must be executed by the 8085
in order to achieve the desired design objectives. In the design of these flow charts,

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Fig 5.25: Block diagram of a microprocessor-based temperature monitoring system

it is assumed that timers will be used for interrupting the P to indicate the two
conditions – time to input limits and time to turn off the LIMIT-SET lamp.

HARDWARE DESIGN

Let us begin the detailed hardware design of the system. To begin with, we assume that
we shall not require more than 2K bytes of EPROM and 2 K bytes of RAM. This
decision is difficult to make so early in the design when the software has not been
designed. However, we postpone a discussion on this aspect to the end of this section.

Thus, we require one 2716A and one 6116A. We can now assign addresses to these
chips. As the 8085 jumps to location 0 when it is reset, we must have at least one
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instruction stored at this location. Generally, this instruction is a jump to an initialization
routing for the application. This implies that location 0 must be in EPROM. Thus, we
may assign addresses 0-2047 to the bytes in the 2716A and addresses 2048-4095 to the
bytes in the 6116A static RAM.

To design the address decoding circuitry, we have selected the 11 least significant bits of
the 16-bit address for each memory chip. Bit A11 selects one of the two memory chips.
Fig. 5.28 shows this assignment.

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With this assignment, the chip select signals can be generated using an 74LS138 decoder
as shown in Fig. 5.29. Note that bits A12, A13, A14, and A15 must all be 0 for the
decoder to be enabled. This ensures that each memory byte has a unique address.

INPUT/OUTPUT SUBSYSTEM DESIGN

For data input from the operator panel, the ports available in the 8255A are used.
Similarly, some of the ports are used for data output to LED’s. Table 5.1 shows all the
port assignments for the two 8255A chips used in our design.

We need to generate two timing signals in our system. One of these is a signal, with a
period 0f 15 s, for scanning the SET LIMIT switch. The other signal has a period of 5 s
and is used for turning off the LED display that indicates that the limit set by the operator
has been recognized by the P. We use the Intel 8254 timer chip to generate these two
signals.

The address assignment for different ports and the timer chip appear in Fig. 5.30(a). Fig.
5.30(b) shows how the chip select signals can be generated using one 74LS138. Notice
that the IO/M signal has been used to ensure that when the address on the address bus is
from the memory, only the 74LS138 in Fig. 5.30(b) is enabled, and when it is for a port
or a timer, then only the 74LS138 in Fig. 5.30(b) is enabled.

As the 8254 has not been described earlier, let us examine it before using it in our design.

THE 8254 PROGRAMMABLE INTERVAL TIMER

General description

The 8254 is a 40 pin programmable interval timer from Intel. It has three independent
16-bit counters which are referred to as counter 0, counter 1, and counter 2. Each counter
can be programmed to operate in any one of five different operating modes. The
programming is done by writing a command word into the control word register of the
8254. Each counter can count at a rate that depends on its own input clock. Depending
on which version of the 8254 is used, the counting can be done at a rate as low as DC to
as high as 10 MHz. For example, the 8245-5 can count at a maximum rate of 5 MHz.

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.
Fig 5.26 Temperature monitoring and display algorithm

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Fig 5.27 Flow Chart of subroutine to read limits.

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INPUT AND OUTPUT SIGNALS

Fig. 5.31 shows the input and output signals available in the 8254. The data bus D0-D7 is
used for sending programming information to the 8254 and obtaining status of the
counters. The WR and RD inputs indicate, respectively, a write or a read operation.
When asserted, the CS input select the chip. The A0 and A1 inputs select one of three
counters or the control register in the 8254. Table 5.2 lists the combinations of RD, WR,
A0, A1 and CS signals and the corresponding read/write operations.

The respective counters to count down use the CLK inputs. The rate at which a counter
counts, depends on the corresponding input CLK signal. Counting can be suspended by
negating the GATE input of the counter. The OUT signal depends on the mode in which
a counter has been programmed to operate.

Fig 5.28 Address assignment for EPROM and RAM

MODES OF OPERATION

Though the 8254 provides five different modes of operation for the counters, we shall
describe only mode 0. We shall use mode 0 in our design.
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When programmed to operate in mode 0, a counter generates an interrupt on terminal
count. The entire operation, from loading the counter to the generation of the interrupt,
proceeds as follows:

1. The control word is written into the control register. This should specify that
a counter, say counter 0, is to operate in mode 0. Writing the control word
forces OUT 0 to go low.
2. The initial count is written to the counter. This count can be programmed to
be a 16-bit or an 8-bit value.

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Table 5.1. Port and Timer Assignment

Chip No. Port No. Input or Function

Output

8255A #1 PA0 – PA3 Input Digit 1 limit

PA4 – PA7 Input Digit 2 of limit
PA0 – PA3 Input Digit 3 of limit
PA4 – PA7 Input Digit 4 of limit
PC1 Input LO/HI switch input
PC0 Input SET LIMIT
switch input

8255 A #2 PA0 – PA3 Output One digit, in BCD,

to be displayed
PC0 Output HIGH alarm display
PC1 Output LOW alarm display
PC2 – PC5 Output Cathode of seven-segment
display
PC6 Output LIMIT SET
PB0 Output Blanking input
Of 7448 seven-segment driver

All ports or port pins not mentioned are unused

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Fig 5.29 Generation of chip select signals for memory

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Fig 5.30 (a) Address assignment and (b) chip select signals for I/O ports and counters.

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Table 5.2. Read/Write Operations in 8254

CS RD WR A1 A0 Operation

0 1 0 0 0 Write to counter 0
0 1 0 0 1 Write to counter 1
0 1 0 1 0 Write to counter 2
0 1 0 1 1 Write to control word
0 0 1 0 0 Read from counter 0
0 0 1 0 1 Read from counter 1
0 0 1 1 0 Read from counter 2
0 0 1 1 1 No-operation, data bus tri-stated
1 X X X X No-operation, data bus tri-stated
0 1 1 X X No-operation, data bus tri-stated

3. Count-down begins one clock pulse after the count has been written into the
counter.
4. If GATE 0 is high, then counter 0 counts down. For each CLK 0 pulse,
counter 0 decrements by 1. If GATE 0 is low, countdown is inhibited.
Countdown resumes when GATE 0 goes high.
5. When the counter reaches 0, which is the terminal count, OUT 0 goes high.
OUT 0 remains high until a new count is written or the counter is
reprogrammed with the control word.

The above operation sequence is identical for all the three counters. Note that the counter
does not stop after the count has reached 0. It wraps around to 0FFFFH and continues the
countdown. In some other modes, the counter gets reloaded to the count that was loaded
initially.

Thus mode 0 can be used to interrupt a P. The time delay before an interrupt is
generated after the counter has been loaded, can be controlled by the value loaded into
the counter. Note that a count of 0 leads to the maximum delay. It corresponds to a total
count of 216 CLK pulses. Thus, if the clock period is 320 ns and the counter is loaded
with a count of 0, then OUT will go high 216 x 320 ns = 20.972 ms after the counter was
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PROGRAMMING THE 8254

The control word format for the 8254 appears in Fig. 5.32. As an example of how to set
the control word, assume that we desire to use counter 0 (a) in mode 0, (b) as a binary
counter, and (c) as a 16-bit counter. The control word can be set to: 00 11 00 0. Setting
the RW0 and RW1 bits to 11 implies that counter 0 must be loaded with a 16-bit count.
The count itself is sent to the counter in two steps. First, the least significant byte is sent
followed by the most significant byte.

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Fig 5.31 Signals in the 8254

Writing data to the 8254 can be accomplished using the OUT instruction of the 8085.
Bits A0 and A1 of the port address specified in this instruction will determine the
destination of the data as shown in Table 5.2.

USING THE 8254 IN OUR DESIGN

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We shall use counter 0 of the 8254 for read limit and counter 1 for turning off LIMIT
SET display timing. The OUT 0 output can be connected to the RST 7.5 input of the
8085. Thus, when OUT 0 goes high, implying that counter 0 has reached the terminal
count, the 8085 will be interrupted. Later, we describe how this interrupt is processed.

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Fig 5.32 Control word format for the 8254 timer.

Table 5.3: Memory, Port, and Timer Addresses

Chip No. Type Address

2716A EPROM 0000-07FFH

6116A Static RAM 08FFH-0FFFH
8255A #1 Port A 0
Port B 1
Port C 2
Control word register 3
8255A #2 Port A 4
Port B 5
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Port C
Control word register
6
7
8254 Counter 0 12
Counter 1 13
Control word register 15

The OUT 1 output is connected to the RST 5.5 input of the 8085. Thus when counter 1
reaches the terminal count, the 8085 will be interrupted. Recall that RST 7.5 input is
rising edge sensitive and the RST 5.5 input is high level sensitive. Thus, after OUT 1
goes high, and the RST 5.5 interrupt has been processed, the 8085 will be interrupted

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immediately after the interrupts are enabled unless OUT 1 goes low before the interrupts
are enabled. The software described later takes care of this problem.

INTERFACING THE SWITCHES AND LED’S

Fig. 5.33 shows the design of the I/O subsystem excluding the ADC. The limit switch
positions are input directly as shown in Fig. 8.10. The 1 K resistors are for limiting the
supply current when the switches are closed (note that if these resistors were not present,
the supply VCC would be shorted when the switch is closed). In the open state, a 1 and in
the closed state a 0 is read from the corresponding pins.

Fig 5.33 Port A (input) limit digits (note that all other input ports are to be
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connected as in this figure and therefore are not shown here.).

An N7448 BCD-seven segment Decoder/Driver drives the 7-segment display. The 7448
is used in multiplexed mode. Its outputs a – g are always connected to the anodes of all
the digit segments. The common cathode of each digit is driven separately through port
C pins. Thus, for example, if digit 1 is to be displayed, its cathode should be driven low.
Making transistor T1 conduct by driving its base low can do this. Thus PC0 should be set
to 1 if digit 1 is to be displayed.

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The 7437 NAND gates, used here as buffers by tying the input signal to both the inputs,
provide the required current for driving the 7-segment display. The 7437 has an IOH of –
1.2 mA and an IOL of 48 mA, which is sufficient to drive most LED displays.

The chip selects inputs of the 8255A chips are connected to the 74LS138 decoder outputs
as shown in Fig. 5.11.

Fig 5.34 Seven segment display hardware.

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Fig 5.35 Alarm and LIMIT SET display hardware

ANALOG INPUT

To input the analog signal corresponding to the temperature, we shall use the AD 7820
ADC. The complete interface including the A/D converter and the temperature
transducer is shown in Fig. 5.36.

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Fig 5.36 A/D converter and temperature transducer interface

The AD7820 has been interfaced using I/O mapped I/O. The 74LS138 decoder generates
the chip select signal. The O4 output of the 74LS138 selects the AD7820. See Fig. 5.11
for the decoder circuit. Evidently, there are several addresses that will select the ADC.
The reader can find out all the other addresses and ensure that they do not overlap with
the memory and I/O ports.

The RDY output of the ADC drives the READY input of the 8085. As the conversion
time in the RD-mode is about 1.6 s, it is essential for the RDY signal to be connected to
the 8085. With the circuit shown in Fig. 5.36, any 8085 instruction that can read a byte
from an I/O port can be used to read the digital data from the ADC.

The temperature transducer interface is quite simple. We know that the AD590 generates
1A current per Kelvin. Over the temperature range of this transducer, the generated
current will vary from 218 A to 423A. These numbers can be obtained easily be
noticing that –55C to +150C corresponds to 218 Kelvin to 423 Kelvin.

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A 10 K resistance shown in Fig. 5.36 will force the VIN of the ADC to vary between
approximately 2.18 V to 4.23 V. This corresponds to approximately half the full scale
range of the ADC which is 5 V. If we set the VREF (-) input of the ADC to 2.18 V, then
the ADC will output all zeroes when the input temperature is approximately –55C.
However, for economy of components, we shall not do so.

The least significant bit of the ADC output corresponds to approximately 19 mV. Thus,
an input of 2.18 V will result in approximately.

(2.18/19 mV ~ 01101110B)

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as the digital output of the ADC. Similarly, an input of 4.23 V will result in an
approximate digital output of:

(4.23/19 mV ~ 11100000B)

The BINBCD routine can use this data to transform the digital output of the ADC to the
corresponding temperature reading to be displayed. Note that as we are using an 8-bit
ADC, we need only three digits to display the temperature. However, as we have used
for 7-segment displays, the BINBCD routine must always generate the fourth, or the
highest order digit, to be 0.

That completes the hardware design of the temperature monitoring system. Figure 5.42
gives the complete design for an overview by the reader. We shall now design the
software without which all the hardware designed so far would not work as desired.

SOFTWARE DESIGN

As is evident from the flow charts presented earlier, the complete software may be
partitioned into the following subroutines.

1. INIT – for initializing program variables immediately after system RESET.

2. DISPLAY – for displaying the next digit of the current average value of
temperature. It is called once each time the main loop shown in Fig 8.3 is
executed.
3. UPDATE – for computing the average value of the temperature. It is invoked
after sixteen readings have been accumulated.
4. RLIMITS – for reading new limit values, if desired by the operator. Called
when an interrupt occurs. It reads only one limit at a time, high or low, at 15s
intervals.
5. LAMPOFF – for putting off the lamp that was turned on to indicate that a
limit has been read from the input switches. It is called when an interrupt
occurs or after the lamp has been turned ON. The lamp is turned off 5 s after
it was turned ON.
6. DELAY – for creating a 50 ms delay before the next temperature reading.
7. ATOD – for getting one temperature reading and assigning it to variable
RDNG.
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In addition to these subroutines, several other subroutines are required one for converting
an input

BCD number to equivalent binary and another for converting a binary number (average
temperature) to BCD. We shall refer to these as BCDBIN and BINBCD subroutines,
respectively. The other subroutine requirements will arise as we develop the software.

We shall now design each of the above subroutines and the main program. In order that
these subroutines are readable; we shall use symbolic addresses for various I/O ports and

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devices in the IN, OUT, and other instructions. These symbols can be equated to their
numeric values using the EQU statements at the beginning of the program. All these
statements are given below. These may be referred to while reading the program that
follows.

;*Temperature monitoring program.*

;*Ports, device, and data address equates.*

CR1 EQU 3 ;Control register of 8255 #1

PORTA1 EQU 0 ;Port A of 8255A # 1
PORTB1 EQU 1 ;Port B of 8255A #1
PORTC1 EQU 2 ;Port C of 8255A #1

CR2 EQU 7 ;Control register of 8255 #2

PORTA2 EQU 4 ;Port A of 8255A #2
PORTB2 EQU 5 ;Port B of 8255A #2
PORTC2 EQU 6 ;Port C of 8255A #2

CWR EQU 15 ;Control word register of 8254

CNTR0 EQU 12 ;Counter 0 of 8254
CNTR1 EQU 13 ;Counter 1 of 8254
LCRS EQU 16 ;Address of AD7820

; Address of the list of cathode addresses.

DADDR EQU DIGITS ;First cathode address.

LSADDR EQU DDIGITS ;LSD address.

DATAL EQU RDNG ;Address of the temperature reading.

INITIALIZATION: THE INIT ROUTINE

Several variables and I/O ports are to be initialized before the infinite loop in the main
program begins. We shall first initialize various ports and timers by a subroutine named
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INIT. The variables shall be initialized in the main program using DB and DW
statements.

All ports must be initialized to be in modes specified in Table 5.1. The command words
for 8255A #1 and 8255A #2 are given in Fig. 5.37(a) and (b). The control word for the
two counters inside the 8254 appears in Fig. 5.37(c). Note that in Fig. 5.37(c), altering
the leftmost two bits from 00 to 01 changes the control word for counter 0 to that for
counter 1.

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Fig 5.37 Command word for (a) 8255A#1 (b) 8255A#2 (c) Control word for the 8254

The command words may be assigned the symbols CWR1 and CWR2 for the two 8255A
chips and CCWR0 an CCWR1 for the two counters, respectively. These symbols can be
defined as shown below.
; *Command words for I/O ports and timer*

CWR1 EQU 1 00 11011B ;8255A # command word

CWR2 EQU 1 00 00000B ;8255A # 2 command word

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CCWR0 EQU 00 11 000 1B ;Control word for counter 0

CCWR1 EQU 01 11 000 1B ;Control word for counter 1

; Next two bytes are to turn the LIMIT set lamp on or off.

BLMSET EQU 00000 0 0B ;Bit 6 is 0 to blank the LIMIT SET lamp.

LLMSET EQU 00000 1 0B ;Bit 6 is 1 to light the LIMIT SET lamp.

BHALRM EQU 000000 0B ;Bit 0 is 0 to turn off the H1 alarm

LHALRM EQU 000000 1B ;Bit 0 is 1 to turn on the H1 alarm
BLALRM EQU 000000 0B ;Bit 1 is 0 to turn off the LO alarm
LLALRM EQU 000001 0B ;Bit 1 is 1 to turn on the H1 alarm

INITIALIZING THE TIMERS

The mode bits for both the counters in the 8254 are set to 00 which implies that each
counter will generate a pulse on reaching the terminal count. The counter will continue
counting after reaching the terminal count. In our case, as the initial count is 0, each
counter will begin counting from 0FFFFH after it has reached the terminal count for the
first time. Recall that counter 0 is used for getting the 15s delay between two successive
limit settings. Counter 1 is used for deriving the 5s delay after which the LIMIT SET
lamp is turned off. Counter 1 should be stopped after resetting the lamp.

Counter 0 must be started immediately after all variables have been initialized. Counter 1
should be started immediately after the LIMIT SET lamp is turned ON. Note that the
counters should be programmed first and only then any command issued to them.

STARTING AND STOPPING THE COUNTERS

Immediately after the control word has been writing into the control register, the
corresponding OUT line goes low. This does not affect any 8085 interrupt input. When
the initial count has been written into the counter, the counter starts counting. For
counter 0, this approach is acceptable. It keeps counting down and generates an interrupt
on the RST 7.5 input. After reaching the terminal count, it begins counting again.

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However, we would like to start counter 1 only when the 5s delay is desired. This
implies that once the counter has interrupted the 8085, it should be stopped and started
again only when the LIMIT SET lamp is to be reset. How can we stop the counter and
synchronize it with the software? This can be done by sending only the low byte of the
count to counter 1. When this low byte is received by counter 1, it stops and waits for the
high byte to arrive. The high byte can be sent when the counter needs to be started. This
is the procedure used in the INIT routine described below. We can now write the INIT
subroutine as given below.

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;*Subroutine to initialize I/O ports and the timer.*

;

INIT;

MVI A, CWR1 ;Get 8255A #1command word

OUT CR1
MVI A, CWR2 ;Get 8255A #2 command word
OUT CR2
MVI A, BLMSET ;Get byte to blank the LIMIT SET lamp.
OUT PORTC2 ;Send to port C of 8255 #2
CALL RALARM ;Reset alarms.
CALL STCNTR0 ;Start counter 0.
EI ;Enable interrupts
RET ;End of subroutine.

;*Subroutine to program the 8254 and initialize counters.*

;

STCNTR0:

MVI A, CCWR0 ;Get counter 0 command word.

OUT CWR

; Send count (=0) to counter 0. This will start the counter.

MVI A, O ; Get low byte of initial count.

OUT CNTR0 ; Send low byte to counter 0.
OUT CNTR0 ; Send high byte to counter 0.
RET

; Program counter 1 by sending only the

; control word and the low byte of the count for counter 1.

PRCNTR1:
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MVI A, CCWR1
OUT CWR
UNIVERSITY ; Get counter 1 command word.

; Send only the low byte to counter 1. This will force

; the counter to stop counting and OUT 1 will be
; set to low by the 8254. The counting can be started,
; when necessary, by sending the high byte.

MVI A, 0 ; This is the low byte of the count.

OUT CNTR1 ; Send low byte to counter 1.

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RET ; End of subroutine.

Start counter 1.

STCNTR1;

CALL PRCNTR1 ; Program the counter.

OUT CNTR1 ; Send high byte of count to counter.
; This starts is.
RET

*Subroutine to reset alarm displays.

RALARM:

IN PORTC2 ; Get status of port C of 8255 #2.

ANI 03FH ; Retain current status of all bits and
; set PC0-PC1 to 0.
OUT PORTC2 ; Out to port C to turn off
; the alarm displays
RET ; End of reset alarm routine.

*Subroutine to blank 7-segment display.*

BDSPLY:

MVI A, 01H ; Set LSB to 1

OUT PORTB2 ; Send to blanking input, BI, of 7448.
RET ; End of subroutine.

*Subroutine to unblank the 7-segment display.*

LDSPLY:

MVI A, 00H ; Set LSB to 0.

OUT PORTB2 ; Send to blanking input, BI, of 7448.
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RET UNIVERSITY ; End of subroutine.

DISPLAYING THE TEMPERATURE: THE DISPLAY ROUTINE

As we have already seen, the temperature is displayed digit by digit, using a multiplexing
scheme. Thus, when DISPLAY is called, it should first ascertain the digit that is being
displayed currently and then display the next digit after blanking out the previous one.

The DISPLAY subroutine given below, performs this task by first blanking the currently
ON display by applying a 1 at the BI input of 7448. It then selects the cathode of the next

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digit and sends a 1 to the corresponding port thereby driving the cathode low. However,
the LED’s of this digit would not yet start conducting as the anodes are all at low voltage.
Next, the appropriate BCD digit is output to 7448 and the blanking input removed
thereby displaying the next digit. Finally, the next digit pointer is advanced.

In order to perform the above mentioned tasks, DISPLAY uses auxiliary variables
CADDR, NXTDG, TEMPD, and LSDADDR. DIGITS is a 4-byte array that holds the
addresses of the four cathodes corresponding to the four digits to be displayed. The
contents of this array are 04H, 08H, 10H, and 20H, respectively. These values are the bit
patterns output to port C, corresponding to the digit to be displayed, by driving the
cathode low.

;*Subroutine to display the next*

;*digit on 7-segment display*
;*It uses H, L, B, and A registers.*

DISPLAY:

CALL BDSPLY ; Blank the 7-segment display.

IN PORTC2 ; Get status of port C of 8255 #2
ANI 43H ; Retain status of alarms and LIMIT SET lamp
MOV B, A ; Save in register B.
LHLD CADDR ; Get address of next cathode.
; to be selected
MOV A, M ; Get corresponding port bit to output.
ORA B ; OR in the current port C contents.
OUT PORTC2 ; Drive next digit cathode low.
LHLD TEMPD ; Get digit to be
MOV A, M ; displayed.
OUT PORTA2 ; Send it to 7448.
CALL LDSPLY ; Unblank the display.
LDA NXTDG ; Get next digit number.
INR A ; Increment it.
ANI 03H ; AND it with 3.
JNZ ADDR1 ; If < 4 then update addrs.

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STA NXTDG
LHLD DADDR
UNIVERSITY ; Reset next digit to 0.
; Get first cathode address
SHLD CADDR ; and reset
LHLD LSDADDR ; Get least significant digit address
SHLD TEMPD ; Reset TEMPD
JMP FINIS
ADDR1:LHLD CADDR ; Move to next
INX H ; digit.
SHLD CADDR
LHLD TEMPD

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INX H
SHLD TEMPD
FINIS: RET ; End of display

CADDR is the address of the next displayable element of DIGITS. It is initialized to

point to the first byte of DIGITS. After each digit is displayed, it is incremented to point
to the next one. After all the four digits have been displayed, it is reset to point to the
first byte of DIGITS.

NXTDG indicates the digit number to be displayed next. It assumes values from 0 to 3 in
a round-robin fashion. When NXTDG reaches 4, it is reset to 0. At this time, CADDR
is also reset to point to the first byte of DIGITS. DADDR denotes the address of the first
byte of the DIGITS array.

TEMPD holds the address of the next BCD digit to be displayed. LSDADDR is a
constant that point to the least significant BCD digit. All the variables mentioned above
are initialized in the main program.

UPDATING THE DISPLAY DATA: THE UPDATE ROUTINE

This routine is invoked after 16 temperature readings have been accumulated. It

computes the average of all these readings, checks these against lower and upper limits
and accordingly sets or resets the alarms. It also calls BINBCD to convert the average
reading to 4 BCD digits for display.

;*Subroutine to update display data and reset alarms*

UPDATE:

MVI A, 0FH ; Get 15 in ACC

STA UPCNT ; Reset update count
CALL AVRG ; Compute average temperature
CALL BINBCD ; Convert to 4 BCD digits.
CALL CHECK ; Set/reset alarms if required.
RET ; End of UPDATE.

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;*Subroutine to compute the average of 16 readings.
;*ACCUML and ACCUMH contain, respectively, the low and
;*high byte of this value. The low and high bytes
;*of the average value are stored in AVRGL and AVRGH,
;*respectively.*

AVRG:

LDA ACCUML ; Get low byte

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CALL SHR4 ; Shift ACC right by 4 bits.

MOV B, A ; Save in B
LDA ACCUMH ; Get high byte
CALL SHL4 ; Shift left by 4 bits.
ORA B ; Get low byte of
STA AVRGH ; average
LDA ACCUMH ; Again get high byte
CALL SHR4 ; Shift right by 4 bits.
STA AVRGH ; Get high byte of average
RET ; End of AVRG

;* Subroutine to shift the ACC right by 4 bits.*

SHR4:

RRC
RRC
RRC
RRC
ANI OFH ; Zero high order 4 bits.
RET ; End of SHR4.

;* Subroutine to shift the ACC left by 4 bits.*

SHL4:

RLC
RLC
RLC
RLC
ANI 0F0H ; Zero low order 4 bits.
RET ; End of SHL4.

The CHECK subroutine finds out whether the averaged reading, stored as BCD digits in
a 4-byte array DDIGITS, has crossed the limits. The LOLMT and HILMT arrays contain
the BCD codes of low and high limits respectively. If any limit is crossed, the
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corresponding alarm is set, otherwise only the alarm, that is currently set, is reset. Fig.
5.38 shows the logic used by CHECK in flow chart form. The program appears below.
The reader is invited to design a more structured flow chart and readable program.

;* Subroutine to check whether averaged reading is in or

;* out of range and accordingly reset alarms.*

CHECK:

MVI A, 04H ; Initialize counter

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STA COUNT

; Initialize H-L, D-E and B-C to addresses of MSK of LOLMT,

; HILMT and DDIGITS, respectively. These are symbolically
; denoted by MSDL, MSDH, and MSDT, respectively.

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Fig 5.38 Flow chart for comparing the averaged temperature reading with low and high
limits and accordingly resetting alarms.

LXI H, LOLMT + 3
LXI B, DDIGITS + 3
LXI D, HILMT + 3

BEGIN:
LDAX B ; Get temp digit.
CMP M ; Compare with LOLMT

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JC RHSL ; Go reset HIGH, set LOW.

JNZ HIGH ; Go compare with HIGH.
DCX H

DCX D
LDA COUNT ; Check if over
SUI 01H
STA COUNT ; Save new count.
JNZ BEGIN ; Go compare next digit.
RESET:
CALL RALARM ; Reset both HI and LO.
RET : Return to caller.
HIGH:
XCHG ; Get address of HILMT in H-L.
MVI A, 04H
STA COUNT
LXI B, DDIGITS + 3
LDAX B
HIGH1:
CMP M ; Compare with HILMT digit.
JC RESET ; If less, go reset alarm.
JNZ RLSH ; Go reset LO, set H1 alarm.
DCX H ; Point to next high digit.
DCX B ; Point to next temp digit.
LDA COUNT ; Check if all over.
SUI 1
STA COUNT ; Save new count.
JNZ HIGH1 ; Go compare next digit.
JMP RESET ; Go reset alarms.
; Reset H1 alarm and set LO alarm.

RHSL:
IN PORTC2 ; Get port c of 8255 #2 status.
ANI 0FCH ; Mask off the alarm bits (PC0 – PC1).
ORI 02H ; Set H1 alarm bit to 1(PC0) and LO
; alarm bit to 0(PC1).
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OUT PORTC2
RET
; Send to port C of 8255 #2/
; Return

; Reset LO alarm and set HI alarm

RLSH:
IN PORTC2 ; Get port C of 8255 #w status.
ANI 0FCH ; Mask off the alarm bits.
ORI 01H ; Set H1 alarm bit to 0(PC0) and LO
; alarm bit to 1(PC1).

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OUT PORTC2 ; Send to port C of 8255 #2.

RET ; End of subroutine.

READING LIMITS FROM THE OPERATOR PANEL: THE RLIMITS ROUTINE

As required, the limits are to be read every 15 s. We are using counter 0 to interrupt the
8085 on RST 7.5 every, approximately, 20.972 ms by setting the corresponding count to
0. Thus, to get an interval of 15 s we need to count this interrupt 15/20.972 ~ 715 times.

A 2-byte software counter may be initialized to 715 and decremented by 1 each time the
interrupt occurs. When this counter reaches 0, the limit value could be read. The
program appears below. The software counter SCNTR0 in initialized to 715 before any
interrupt occurs. VALCT0 holds the value to which SCNTR1 should be initialized each
time it reaches 0.

;*Subroutine to read lower/upper limits. Reads once every

;*15 seconds. Locations 3C-2E should contain a JMP RLIMITS
;*instruction to force the 8085 to enter RLIMITS on RST 7.5
;*interrupt.*

RLIMITS:

CALL SAVE ; Save 8085 status.

LHLD SCNTR0 ; Get current counter value
DCD H ; Decrement it.
SHLD SCNTR0 ; Save it
MOV A, H ; Check if 0.
ORA L
CPI 0
JNZ ROVER
LHLK VALCT0 ; Reset SCNTR0 to
SHLD SCNTR0 ; 715
IN PORTC0 ; Get operator’s request.
RRC ; Check if resetting
JC ROVER ; desired.
RRC ; Check if LOW/HIGH
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JC
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HIADDR
; limit should to be reset.
; Go get high limit.

; Get LOLMT address.

LXI H, LOLMT + 3
JMP GETLMT

; Get HILMT address.

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HIADDR: LXI H, HILMT + 3;

GETLMT;
IN PORTA0 ; Get 2 MSD’s of limit.
MOV B, A ; Save them
CALL SHR4 ; Get digit 1.
MOV M, A ; Move to LO/HI limit.
DCX H ; Point to digit 2.
MOV A, B ; Strip next digit
CALL SHL4 ; and store it in LO/HI limit area
CALL SHR4
MOV M, A

;Point to digit 3, strip next digit and store it in LO/HI limit area.

DCX H
IN PORTB0 ; Get 2 least significant digits of the limit.
MOV B, A
CALL SHR4 ; Strip digit 3.
MOV M, A ; and store it.

.;Point to digit 4, strip next digit and store it in LO/HI limit area.

DCX H ; Point to digit 4

MOV A, B ; get digit 4 and
CALL SHL4 ; store it in
CALL SHR4 ; LO/HI limit area
MOV M, A ;
IN PORTC2 ; Get status of port C of 8255 #2
ANI 8FH ; Mask out LIMIT SET display bit (PC6)
ORI 40H ; set LIMIT SET bit to 1.
OUT PORTC2 ; Send to LIMIT SET display.
CALL STCNTR1 ; Start counter 1 to get 5’s delay
ROVER: CALL RESTORE ; Restore 8085 status.
EI ; Enable interrupts.
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RET UNIVERSITY ; End of RLIMITS

; *Subroutine to save and restore 8085 status.*

SAVE: XTHL ; Get return address, that is currently

; on stack top, into H-L and save H-L on stack.
PUSH PSW ; Save PSW.
PUSH B ; Save B-C pair.
PUSH D ; Save D-E pair
RET ; End of SAVE

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RESTORE:
POP H ; Pop return address into H-L.
POP D ; Restore D-E pair.
POP B ; Restore B-C pair.
POP PSW ; Restore PSW.
XTHL ; Get return address on
; stack top and restore H-L pair.
RET ; End of RESTORE

TURNING OFF THE LIMIT SET LAMP: THE LAMPOFF ROUTINE

Immediately after the LIMIT SET indicator is turned ON, counter 1 is also started. This
would generate an interrupt after 20.972 ms on RST 5.5. The lamp should be reset after 5
s which implies that approximately 239 such interrupts should be counted before resetting
the lamp. We get this number as:

5 s/20.972 ms ~ 239

This can be done using the method already described above with the RLIMITS routine.
For this purpose, we use a software counter named SCNTR1. The value to which
SCNTR1 should always be reset is held in VALCT1. The desired routine appears below.

;*Subroutine to turn off limit-set lamp 5 s after it

;* is turned on to indicate that the limits have been set.*

LAMPOFF:
CALL SAVE ; Save 8085 status.
LHLD SCNTR1 ; Get current value of the software counter.
DCX H ; Decrement it.
SHLD SCNTR2 ; Save it
MOV A, H ; If zero then
ORA L
CPI 0 ; turn off
JNZ LMOVER ; the lamp, else return.
LHLD VALCT1 ; Reinitialize software counter.
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SHLD UNIVERSITY
SCNTR1

IN PORTC2 ; Get status of port C of 8255 #2

ANI 8FH ; Mask out LIMIT SET display bit (PC6).
OUT PORTC2 ; Send to port C of 8255 #2
; and turn off the lamp
CALL PRCNTR1 ; This will stop counter 1.
LMOVER:
CALL RESTORE ; Restore 8085 status.
EI ; Enable interrupts.

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RET ; End of LAMPOFF.

ANALOG TO DIGITAL CONVERSION: THE ATOD ROUTINE

Obtaining a temperature sample from the ADC is simple. The ATOD routine given
below does it by merely reading the ADC output. Reading from the ADC will force its
RDY output to go low and will remain so until the conversion is over. The RDY output
forces the 8085 to wail until the conversion is over. Thus, the IN instruction in ATOD
initiates the A-to-D conversion and also reads the digital output. The data obtained is
stored at location RDNG from where the BINBCD routine can pick it up for conversion
to BCD.

;* Subroutine to get an 8-bit temperature reading from the AD7820

;* Hardware handshaking is used.*

ATOD: IN LCRS ; This command starts conversion,

; forces the 8085 to wait until conversion
; is over, and gets the data into ACC.
STA RDNG ; Save reading in memory.

RET ; End of ATOD subroutine

THE DELAY ROUTINE

The DELAY subroutine uses a nested loop to decrement the L and H registers until both
reach zero. Before DELAY is called, both the H and L registers should be initialized to
proper values in order to get a (approximately) 8 ms delay.

;* Subroutine to get desired delay. Registers H and L

;* should be initialized before calling this routine.*

LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
RET
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It can be proved that the delay D caused by this subroutine is given as (approximately)

D = 24 + (L’ – 1) x 14 + (H’ – 1) x [(255 x 14) + 21] (states)

Where H’ and L’ denote the initial values of the H and L registers, respectively, when
DELAY is entered. Assuming a 320 ns clock cycle, the approximately values of H and L
for a 50 ms delay are H = 12, L = 3 (other values are also possible).

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Note that when the DELAY routine is entered, the interrupts are not disabled. Thus, the
interrupts from the counters will increase the delay to more than 8 ms. You may compute
the maximum possible increase as an exercise. In case we decide to disable the interrupts
at the beginning of DELAY, the 15s and 5s delays would be increased since many
counter pulses would then go uncounted. Other criteria may be used to take a suitable
decision (e.g. maximum per cent tolerable error in the delay between successive input
signal sampling instants).

THE MAIN PROGRAM: THE MAIN ROUTINE

The main program defines various constants, initializes ports and devices, and enters an
infinite loop as exhibited in Fig. 5.9. The main program is entered after the 8085 is
RESET. Thus, before calling the INIT subroutine, it initializes the stack pointer, SP, to
the highest address in RAM. From our hardware design, we know this address to be
4095. Recall that the stack grows from high addresses to low addresses. For example,
when INIT is called, its return address will be saved in locations (SP) –1 and (SP)-2
which are bytes 4094 and 4093, respectively.

Before the program can be executed, location 0, 2C and 3C should be filled with JMP
instructions to MAIN, LAMPOFF, and RLIMITS routines, respectively. This will ensure
that when the 8085 is reset, the jump to main program is executed. Also, when the RST
5.5 and RST 7.5 interrupts are recognized by the 8085, it jumps to the appropriate
interrupt processing routine. Note that the RST 0 instruction can be used for a software
reset.

;* Main program for temperature monitoring.*

;* The entire program is stored in EPROM starting at location 40H.
;* Variable data is stored in RAM starting at location 0800H.
;* Initialize constants.*

ORG 800H ; Set the address of the next byte to be 800H.

CADDR: DB DIGITS ; Cathode address reset in display.
DIGITS: DB 04H ; Cathode digit 3.
DB 08H ; Cathode digit 2
DB 10H ; Cathode digit 1
DB 20H ; Cathode digit 0.
NXTDG:
UPCNT:
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DB
DB
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0FH
; Next digit to be displayed
; Update display counter.
ACUML: DB 0 ; Accumulated reading low
ACUMH: DB 0 ; and high bytes
AVRGL: DB 0 ; Average value, low and high
AVRGH: DB 0 ; bytes.
LOLMT: DB 0 ; LSD of low limit
DB 0 ;
DB 0
DB 0 ; MSD of low limit.

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HILMT: DB 9 ; LSD of high limit

DB 9
DB 9
DB 9 ; MSD of high limit.
COUNT: DS 1 ; Counter for check routine.
SCNTR0: DW 715 ; Counter for a delay of 15 s.
VALCT0: DW 715 ; Value to reinitialize SCNTR0
SCNTR1: DB 239 ; Counter for delay of 5 s.
VALCT1: DB 239 ; Value to reinitialize SCNTR1.
RDNG: DB 0 ; ATOD reading
DDGIT: DB 0 ; LSD of BCD digit to be displayed.
DB 0
DB 0
DB 0 ; MSD of BCD digit to be displayed.
TEMPD: DW DDGIT ; Address of next display digit.

;* Begin main program execution.*

;* The program instructions are in the EPROM.*

ORG 40H ; Set the address of the next byte to be 40H.

MAIN:

START: LXI H, 0FFFH ; Initialize stack pointer to

SPHL ; 0FFFH. This is the highest RAM address.
CALL INIT ; Initialize other variables.
MLOOP: LDA UPCNT ; Get update counter.
ANI OFFH ; Check if zero.
JNZ MODFY ; Do not update display
CALL UPDATE ; Update display
JMP DISP ; Go display next digit
MODFY: SUI 01H ; Decrement UPCNT by 1.
STA UPCNT ; Save it
DISP: CALL DISPLAY ; Display next digit.
MVI H, 0CH ; Prepare for 8 ms delay.
MVI L, 03H
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CALL
CALL
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ATOD
; Generate the delay.
; Get next reading.
LDA RDNG ; Get temperature reading into the ACC.
MOV B, A ; Save it in register B.
LDA ACUML ; Get low byte of sum.
ADD B ; Add low byte.
STA ACUML ; Save it in memory.
MOV B, A ; Also get it in register B.
LDA ACUMH ; Get the high byte of sum in ACC.
ADC B ; Add with carry.

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STA ACUMH ; Save it

JMP MLOOP ; Repeat the above process.

;Place jumps to interrupt processing routines.

ORG 2C ; This is the RST 5.5 interrupt branch

address
JMP LAMPOFF
ORG 3CH ; This the RST 7.5 interrupt branch address
JMP RLIMITS
END START ; Begin execution from start

4.2.11 Closed Loop Process Control

In the previous section we developed a system illustrating how Ps can be effectively
used in open loop process control. In this section we shall briefly describe one of the
many P applications in closed loop process control. The specific example chosen is the
control of the growth of synthetic quartz. The control system was developed by Robert
Pettirossi (1977).

THE PROCESS OF GROWING SYNTHETIC QUARTZ

The growth of synthetic quartz takes place inside a long, vertically placed, growing
chamber (autoclave) made of steel. Before the process starts, sodium hydroxide solution
is used to fill the bottom of the autoclave. Small pieces of natural quartz (known as the
nutrient) are mixed with this solution to be dissolved at a later stage. Thin wafers of
quartz (known as seeds) are sliced along the desired crystallographic structure and
suspended at the top of the autoclave.

The growth process begins by turning on two heaters-one at the bottom and the other at
the top. Thus, a two zone temperature system is maintained. The bottom is maintained at
a higher temperature than the top.

The nutrient dissolves in the solution and is carried to the top by convection currents.
The growth of desired crystals begins on seeds after the growth zone (top) becomes

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supersaturated.
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The growth is a pressure, temperature and time dependent process. The growth period is
about 30 days and can be subdivided into three stages-the startup, intermediate, and the
growth cycle. Fig. 5.39 shows the relationship between the top zone temperature (Tt) and
the bottom zone temperature (Tb). This relationship must be maintained for proper
growth.

During the startup period, the rate of temperature rise is critical and must be maintained
taking into account Tb, Tt, and t1. The intermediate period is the one during which the
temperatures move towards stabilization with a difference of t2. During the final growth

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period Tbf, Tft and t2 must be maintained within specified limits. The pressure within the
autoclave should also not exceed the upper limit and not go below a lower limit.

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Fig 5.39 Growth profile of synthetic quartz

In order to meet the demand, a group of 30 independent such chambers need to be

operated. As the control is critical, independent microprocessor based control is
employed for each autoclave.

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Fig 5.40 Control system for growth of synthetic quartz.

MICROPROCESSOR BASED CONTROL SYSTEM HARDWARE

The hardware is centered around an 8080 P. For each autoclave to be controlled, the
following are the inputs from the process, which are converted to digital form using
transducers and ADCs.
1. Top zone temperature (16 bits).
2. Bottom zone temperature (16 bits)
3. Autoclave pressure (8 bits)
The growth is controlled by controlling the power supplied to various heater. When any
of the three values corresponding to temperatures and pressure exceed limits, an alarm is
set. Thus, the P outputs digital data to DACs for controlling the two heaters and
setting/resetting the alarm. An overall block diagram of the complete control system
appears in Fig. 5.40.
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The 8080 require an external clock generator to supply a two phase overlapping clock.
This is unlike the 8085, which generates an internal clock using an externally supplied
crystal. This function is performed by the 8224. Another chip, known as the system
controller, is required to latch the 8-bit status code sent out by the 8080 at the beginning
of every machine cycle. The controller, 8228 chips, latches the code and decodes it to
produce control signals for memory and I/O devices. Recall that all control signals;
IO/M, RD, WR, etc. are generated on chip in 8085.

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SOFTWARE
The software is divided into three distinct modules-startup, intermediate and growth
modules. The startup and growth modules have almost the same logic. It is essentially
loop-20 hours long for startup and about 30 days for growth.

Within the loop, the program first waits for 3 minutes, reads Tb and adjusts power to
bottom heaters. It then adjusts power to the bottom heater to control the rate of rise of
temperature (for startup) or to maintain Tb within limits (for growth). Next, it reads Tt,
checks if Ti (I = 1 for startup, 2 for growth) is too small, too large or within limits. In the
first two cases, the difference is adjusted by applying power to bottom or top heater. Fig.
5.41 shows this loop.

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Fig 5.41 Overall logic of the control algorithm

During the intermediate phase, only Tb is read and adjusted until it reaches the desired
final value Tbf. The successive values are read at 3-minute intervals.

Apart from these three main modules, there are a few other routines for manipulating 16-
bit data approximating Tb and Tt. The complete software requires about 1.2 K bytes of
memory. This is partitioned into 1 K bytes of ROM and 256 bytes of RAM. One
prototype system costs (in 1977) about $400. Thus, to control 30 autoclaves the total cost
would be about $12000. However, the designers also experimented with a centralized

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minicomputer control, the cost of which (including the cost of a redundant mini for high
reliability) is as high as $26000.

Fig 5.42

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5.3 Revision Points

8080A interrupt
The 8080A interrupt process is controlled by the Interrupt Enable flip-flop, which is
internal to the processor and can be set or reset by using software instructions. If the flip-
flop is enabled and the input to the interrupt signal INT (pin 14) goes high, the
microprocessor is interrupted. This is a maskable interrupt and can be disabled. The
8080A has only one interrupt signal; it does not have a nonmaskable interrupt. The 8085
has an interrupt signal called INTR (pin 10), functionally identical with the 8080A
interrupt. However, the 8085 has additional interrupt signals as well.

Alphanumeric Codes
A computer is a binary machine; in order to communicate with the computer in
alphabetic letters and decimal numbers, translation codes are necessary. The commonly
used code known as ASCII, the American Standard Code for Information Interchange.
Another code, called EBCDIC (Extended Binary Coded Decimal Interchange Code), is
widely used in IBM computer. This is an 8-bit code representing 256 combinations;
however, several combinations are not being used.

Transmission Format
A transmission format is concerned with issues such as synchronization, direction of data
flow, speed, errors, and medium of transmission (telephone lines for example). Serial
communication occurs either in synchronous or asynchronous format. In the
asynchronous format, a receiver and a transmitter are synchronized; a block of characters
is transmitted along with the synchronization information.

Simplex and Duplex Transmission

In simplex transmission, data are transmitted in only one direction. A typical example is
the transmission from a microcomputer to a printer. In duplex transmission, data flow in
both directions. However, if the transmission goes one way at a time, it is called half
duplex; if it goes both ways simultaneously, it is called full duplex. Generally,
transmission between two computers or between a computer and a terminal is full duplex.

BAUD
The rate at which the bits are transmitted – bits/second – is called a baud in serial I/O.

MODEM ANNAMALAI
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A modem (Modulator / Demodulator) is a circuit that translates digital data into audio
tone frequencies for transmission over telephone lines and converts audio frequencies
into digital data for reception.

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5.4 Intext Questions

1. Write a brief note on interrupts?
2. Write a brief note on 8155?
3. What does ALE stand for?
4. Write a short note on application area of microprocessors?

5.5 Summary

 These input and output devices are called peripherals or I / Os; memory can be
viewed as a special type of I / O.
 The microprocessor (MPU) communicates with the peripherals in either of
two formats: asynchronous or synchronous.
 Similarly, it transfers data in either of two modes: parallel I / O or serial I / O.
 The 8085 has five interrupt inputs.
 These interrupts are sensitive to different types of triggering.
 Serial communication also can be classified according the direction and
simultaneity of data flow.
 A tri-state buffer is used as an input port to read data from devices such as a
keyboard or data converters.
 The timer can be used to calculate the conversion time.

5.6 Terminal Exercises

1. What is a RST instruction?

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2. What is a Control word?
3. What are the functions performed by a interfacing I/O device?
4. What is TRAP?
5. What is Parity Check?

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5.7 Supplementary Materials

1. Ramesh S. Goankar ,“Microprocessor Architecture & Applications”, Third

Edition , Penram international Publishing (India),1997.
2. Mathur, “ Introduction to Microprocessors”, Third Edition, TMH.

5.8 Assignments
1. Write a brief note on Serial I/O concepts
2. Discuss the applications of microprocessor in detail.

5.9 Suggested Reading/Reference Books/Set Books

1. “Introduction to Microprocessor, Software, Hardware programming “,
L.A.Levanthal.
2. “Fundamentals of Microprocessor”, B.Ram, Dhanapat Rai & Son’s

5.10 Learning Activities

1. Collect information on 8085/8080A Interrupt from internet.
2. Collect information on 8279 KBD/Display interface.

5.11 Keywords

Modem
Extended Binary Coded Decimal Interchange Code (EBCDIC)
American Standard Code for Information Interchange (ASCII)

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Simplex UNIVERSITY
Half duplex
Full duplex
Baud rate.

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