2013 Lecture Ch3
2013 Lecture Ch3
Branch, Call,
and Time Delay
Loop
DECFSZ fileReg, d
0-2
Figure 3-1. Flowchart for the
DECFSZ Instruction
BNZ Branch if not zero
0-5
Maximum Number of Times for
loop
Loop Inside a Loop Nested Loop
Other Conditional Jumps
BZ Branch if Z = 1
BNC Branch If No Carry (CY = 0)
Short Jumps
0-14
Unconditional Branch Instruction
GOTO
0-18
Unconditional Branch Instruction
BRA (Branch)
• A 2-byte instruction.
• The first 5 bits are the opcode.
• The rest lower 11 bits are the relative address of the
target address
0-19
• GOTO to itself using $ sign.
• HERE GOTO HERE
GOTO $
• OVER BRA OVER
BRA $
0-20
CALL Instructions and Stack
• A 4-byte instruction.
• Long call.
0-21
Simplified view of a PIC
microcontroller
22
Figure 3-7. PIC Stack 31 × 21
• A 2-byte instruction.
• Only 11 bits of the 2 bytes are used for the address.
• The target address of RCALL must be within a 2K
range.
0-26
Delay Calculation
0-28
Figure 3-9. Pipeline vs. Non-
pipeline
• Instruction cycles (machine cycles) In PIC18, one
instruction cycle consists of four oscillator periods.
• Brach penalty CPU flushes out the instruction queue.
0-30
Pipeline Activity