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2013 Lecture Ch2 2

Chapter 2 discusses the architecture and assembly language programming for PIC microcontrollers, focusing on the WREG register and various instructions such as MOVLW and ADDLW. It explains the file register structure, including Special Function Registers (SFRs) and General-Purpose Registers (GPRs), as well as the importance of the access bank in memory management. Additionally, it covers assembler directives and the structure of assembly language, emphasizing the differences between machine language and assembly language.

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陳沛如 Pei’s exam questions
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12 views56 pages

2013 Lecture Ch2 2

Chapter 2 discusses the architecture and assembly language programming for PIC microcontrollers, focusing on the WREG register and various instructions such as MOVLW and ADDLW. It explains the file register structure, including Special Function Registers (SFRs) and General-Purpose Registers (GPRs), as well as the importance of the access bank in memory management. Additionally, it covers assembler directives and the structure of assembly language, emphasizing the differences between machine language and assembly language.

Uploaded by

陳沛如 Pei’s exam questions
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 2

PIC
Architecture &
Assembly
Language
Programming
The WREG Register

• WREG  working register


• The vast majority of PIC register are 8-bit
register.

0-2
MOVLW Instruction

• Move an 8-bit literal value into WREG register.


MOVLW K
• The L stands for literal, which means, literally a
number must be used; similar to the immediate
value in other microprocessors.
MOVLW 87H

0-3
ADDLW Instruction

ADDLW K
• ADD a literal value to WREG.
MOVLW 25H
ADDLW 34H
;WREG = 59H

0-4
Figure 2-1. PIC WREG and ALU
Using Literal Value
MOVLW 12H
ADDLW 16H
ADDLW 11H
ADDLW 43H

MOVLW 7F2H
MOVLW 60A5H

0-6
The PIC File Register

• Data memory space vs. Program memory space


• The data memory is also called the file register.
• The file register data RAM has a byte-size width, just
like WREG.
• (a) Special Function Register (SFR)
(b) General-Purpose Register (GPR)
or General-Purpose RAM (GP RAM)

0-7
SFRs

• dedicated to specific functions such as ALU status,


timers, serial communication, I/O ports, ADC, and so
on.
• The more timers we have in a PIC chip, the more SFR
registers we will have.

0-8
GPRs

• A group of RAM locations in the file register that are


used for data storage and scratch pad.
• The space that is not allocated to SFRs typically is
used for general-purpose registers.
• GP RAM vs. EEPROM in PIC chips
• GPRs are used by the CPU for internal data storage.
• EEPROMs are considered as an add-on memory.

0-9
File register size for PIC chips

0-10
Figure 2-2. File Registers of
PIC12, PIC16, and PIC18
File Register and Access Bank

• The PIC18 family can have a maximum of 4096 (4K)


bytes for the file register.
• has the addresses of 000-FFF.
• is divided into 256-byte banks.
• A maximum of 16 banks (16256 = 4096)
• Every PIC18 family member has at least one bank for
the file register.
• This bank is called the access bank.
• The access bank is the default bank when we power up
the PIC18 chip.
0-12
File Register and Access Bank

• The 256 access bank is divided into two equal sections


of 128 bytes.
• The 128 bytes from locations 00H to 7FH are set aside
for general-purpose registers.
• The other 128 bytes from locations F80H to FFFH are
set aside for special function registers.
• A file register of more than 256 bytes will necessitate
bank switching.

0-13
Figure 2-3. File Register for PIC18
Family
Figure 2-4. Special Function
Registers of the PIC18 Family.
MOVWF Instruction

• Move (in reality, copy) the source register of WREG


(W) to a destination in the file register (F).
• Mnemonic instructions.
MOVLW 55H
MOVWF PORTB
MOVWF PORTC
MOVWF 2H
MOVWF 3H
• Notice that you cannot move literal values directly into
the general-purpose RAM locations in the PIC18.
0-16
ADDWF Instruction

• ADDWF fileReg, D
• Add together the contents of WREG and a file register
locations.
• D indicates the destination bit. If D=0, the destination
is WREG. If D=1, then the result will be placed in the
file register.
• The PIC assembler allows us to use the letters W or F
instead of 0 or 1 to indicate the destination.

0-18
Figure 2-5. WREG, fileReg, and
ALU in PIC18
COMF fileReg, d

• Complement the contents of fileReg and places the


result in WREG or fileReg.
• This is a example of “Read-Modify-Write”.

0-21
DECF fileReg, d

• Decrement the contents of fileReg and places the result


in WREG or fileReg.

MOVLW 3
MOVWF 20H
DECF 0x20, F
DECF 0x20, F
DECF 0x20, F

0-22
MOVF fileReg, d

• Is intended to perform MOVFW.


• The only time we let d=‘F’ (to copy data from fileReg
to itself) is when we want to affect the flag bits of the
status register.

0-23
0-24
MOVFF instruction

• Copies data from one location in fileReg to another


location of fileReg.

0-25
PIC18 Status Register

• Also called flag register.


• Five flags are called conditional flags.

• C, there is a carry out. Usually for unsinged number.


• DC, a carry from D3 to D4. (or AC flag)
• Z, zero.
• OV, overflow. Usually for singed number.
• N, negative. Usually for singed number.

0-27
Figure 2-7. Bits of Status Register
Data Format representation

• There are four ways to show hex numbers.


MOVLW 99H
MOVLW 0x99
MOVLW 99
MOVLW h’99’
• Binary numbers
MOVLW B’10011001’

0-33
Data Format representation

• There are two ways to show decimal numbers.


MOVLW D’12’
MOVLW .12
• ASCII character
MOVLW A’2’
MOVLW ’2’

0-34
Assembler Directives

• Instructions tell CPU what to do.


• Directives (pseudo instructions) give directions to the
assembler.
• EQU associates a constant number with a data or an
address label.
COUNT EQU 25H
MOVLW COUNT
• SET and EQU directives are identical. The only
difference is the value assigned by the SET may be
reassigned later.
0-35
Assembler Directives

• ORG  the beginning of the address.


• END  the END of the source (asm) file.
• LIST  the assembler the specific PIC chip for which
the program should be assembled.
LIST P=18F452
• #include  libraries used for compiling.
• Radix  numbering system is hexadecimal or decimal.

0-36
PIC Assembly Programming

• Machine language
• Assembly language
• Assembler, objective code
• Low-level language
• Complier , high-level language

0-37
Structure of Assembly Language

[label] mnemonic [operands] [;comment]

0-38
Figure 2-8. Steps to Create a
Program
Figure 2-9. Program Counter in
PIC18
Figure 2-10. PIC18 On-Chip Program
(code) ROM Address Range
PIC18 Program ROM Space

• The PIC microcontroller wakes


up at memory address 0000
when it is powered up.
• We achieve this by using the
ORG statement in the source
program as shown earlier.
Figure 2-12. Program ROM Width
for the PIC18
Figure 2-13. PIC18 Program ROM
Contents for Program 2-1 List File

• Little endian  The lower byte goes to the low memory


location and the high byte goes to the high memory
address.

• Big endian
Figure 2-14. von Neumann vs.
Harvard Architecture
Instruction Size

• MOVLW

• ADDLW

0-50
Instruction Size

• MOVWF

• MOVFF

0-51
Instruction Size

• GOTO

0-52
RISC Architecture

1. Fixed instruction size


2. A large number of registers
3. A small instruction set
4. 95% instructions are executed with only one clock
cycle
5. Separate buses for data and code (Havard architecture)
6. Hardwire method. (no microinstructions)
7. Load/store architecture

0-53
Figure 2-15. SFR Window in MPLAB
Simulator
Figure 2-16. File Register (Data RAM)
Window in MPLAB Simulator
Figure 2-17. Program (Code)
ROM Window in MPLAB Simulator

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